Power-on reset circuit, chip and display device

Abstract

Embodiments of the present application provide a power-on reset circuit, a chip and a display device. The power-on reset circuit comprises a first control module, a reset control module and an output module connected in sequence, the first control module, the reset control module and the output module are connected with a power supply end, and the conduction state of the reset control module is controlled by the first control module; the first control module is configured to conduct and send a conduction signal to the reset control module when the power supply voltage rises to a set threshold; the reset control module is configured to conduct when receiving the conduction signal and generate a reset control signal according to the power supply voltage and the conduction signal; and the output module is configured to invert the reset control signal to output a power-on reset signal. Therefore, the reset control module and the first control module are basically consistent in the influence of temperature and process factors, thereby being conducive to improving the influence of temperature and process factors on the accuracy of the power-on reset circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular, the present application relates to a power-on reset circuit, chip and display device. BACKGROUND

[0002] The power-on reset (POR) circuit is one of the important circuits of the chip, especially the analog chip, which basically includes the POR circuit. The POR circuit is used to restore the chip to the initial state, and the advantages and disadvantages of the POR circuit directly affect the reliability of the whole system.

[0003] However, the POR circuit is sensitive to process angle, temperature and power voltage, which affects the accuracy of the POR circuit. SUMMARY

[0004] The present application is aimed at the shortcomings of the prior art, and proposes a power-on reset circuit, chip and display device, which can reduce the influence of process and temperature on the power-on reset circuit.

[0005] In a first aspect, an embodiment of the present application provides a power-on reset circuit, which comprises a first control module, a reset control module and an output module connected in sequence, the first control module, the reset control module and the output module are connected with a power supply end respectively, and the conduction state of the reset control module is controlled by the first control module; wherein the first control module is configured to be turned on when the power supply voltage of the power supply end rises to a set threshold value and send a conduction signal to the reset control module;

[0006] The reset control module is configured to be turned on when receiving the conduction signal and generate a reset control signal according to the power supply voltage and the conduction signal;

[0007] The output module is configured to flip the reset control signal to output a power-on reset signal.

[0008] Optionally, the first control module comprises a first P-type MOS tube, a voltage stabilizing device, a first resistor, a second resistor and a third resistor; the source of the first P-type MOS tube is electrically connected with the power supply end, the gate and the drain of the first P-type MOS tube are both electrically connected with the first end of the first resistor, the second end of the first resistor is respectively electrically connected with the first end of the second resistor and the reset control module, the second end of the second resistor is electrically connected with the first end of the third resistor, and the second end of the third resistor is grounded; the voltage stabilizing device is respectively electrically connected with the power supply end and the reset control module.

[0009] Optionally, the reset control module comprises a second P-type MOS tube and a fourth resistor; a gate of the second P-type MOS tube is electrically connected with a second end of the first resistor, a source of the second MOS tube is electrically connected with the power supply end, a drain of the second MOS tube is electrically connected with a first end of the fourth resistor, and a second end of the fourth resistor is grounded.

[0010] Optionally, the output module comprises a Schmitt trigger, a first inverter and a second inverter; an input end of the Schmitt trigger is electrically connected with the first node, an output end of the Schmitt trigger is electrically connected with an input end of the first inverter, an output end of the first inverter is electrically connected with an input end of the second inverter, and an output end of the second inverter outputs the reset signal; an up threshold of the Schmitt trigger is higher than an up threshold of the first inverter, and a down threshold of the Schmitt trigger is lower than a down threshold of the first inverter; the up threshold of the first inverter is the same as an up threshold of the second inverter, and the down threshold of the first inverter is the same as a down threshold of the second inverter.

[0011] Optionally, the output module is further configured to generate a hysteresis control signal according to the power supply voltage and the reset control signal; and the power-on reset circuit further comprises a second control module configured to adjust a hysteresis time of the power-on reset circuit according to the hysteresis control signal.

[0012] Optionally, the second control module comprises a first N-type MOS tube; a gate of the first N-type MOS tube is electrically connected with an output end of the first inverter, a source of the first N-type MOS tube is grounded, a drain of the third MOS tube is electrically connected with a second end of the second resistor, and a voltage of the output end of the first inverter is the hysteresis control signal.

[0013] Optionally, the voltage stabilizing device comprises a voltage stabilizing capacitor, two ends of the voltage stabilizing capacitor are respectively electrically connected with the power supply end and the reset control module.

[0014] Optionally, the voltage stabilizing device comprises a first voltage stabilizing diode; a positive electrode of the first voltage stabilizing diode is electrically connected with the reset control module, and a negative electrode of the voltage stabilizing diode is electrically connected with the power supply end.

[0015] Optionally, the reset control module further comprises a second voltage stabilizing diode; two ends of the second voltage stabilizing diode are respectively electrically connected with the first end and the second end of the fourth resistor.

[0016] Optionally, the first control module further comprises a third P-type MOS tube, a gate and a drain of the third P-type MOS tube are electrically connected with the first end of the first resistor, and a source of the third P-type MOS tube is electrically connected with the drain of the first P-type MOS tube.

[0017] In a second aspect, the embodiments of the present application provide an analog chip, comprising the power-on reset circuit.

[0018] In a third aspect, the embodiments of the present application provide a display device, comprising the analog chip.

[0019] The technical scheme provided by the embodiments of the present application has the beneficial technical effects including:

[0020] The power-on reset circuit, the chip and the display device provided by the embodiments of the present application have the following beneficial technical effects: the conduction of the reset control module is consistent with the conduction of the first control module, so that the reset control module and the first control module are affected by temperature and process factors basically consistently, thereby being beneficial to improving the influence of temperature and process factors on the accuracy of the power-on reset circuit.

[0021] Additional aspects and advantages of the application will be set forth in part in the following description, and in part will become apparent to those skilled in the art from the following description, or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 FIG. 1 is a structural schematic diagram of a power-on reset circuit in the prior art;

[0024] Figure 2 FIG. 2 is a structural schematic diagram of another power-on reset circuit in the prior art;

[0025] Figure 3 FIG. 3 is a structural schematic diagram of a power-on reset circuit provided by the embodiments of the present application;

[0026] Figure 4 FIG. 4 is a specific circuit schematic diagram of the power-on reset circuit provided by the embodiments of the present application;

[0027] Figure 5 FIG. 5 is a structural schematic diagram of another power-on reset circuit provided by the embodiments of the present application;

[0028] Figure 6 FIG. 6 is a specific circuit schematic diagram of another power-on reset circuit provided by the embodiments of the present application;

[0029] Figure 7A specific circuit schematic diagram of another power-on reset circuit provided by an embodiment of the present application is provided.

[0030] Figure 8 A specific circuit schematic diagram of a first control module in a power-on reset circuit provided by an embodiment of the present application is provided.

[0031] Figure 9 For Figure 6 A timing diagram of potentials of nodes and a POR signal in a power-on process corresponding to the power-on reset circuit shown in FIG. 1 is shown in FIG. 2.

[0032] Figure 10 For Figure 6 A POR signal diagram of simulation experimental results of the power-on reset circuit shown in FIG. 1 under different process corners and different temperatures is shown in FIG. 3.

[0033] Figure 11 For Figure 1 A POR signal diagram of simulation experimental results of the power-on reset circuit in the prior art under different process corners and different temperatures is shown in FIG. 4.

[0034] Figure 12 A schematic diagram of a framework structure of a chip provided by an embodiment of the present application is provided.

[0035] Figure 13 A schematic diagram of a framework structure of a display device provided by an embodiment of the present application is provided.

[0036] Reference signs:

[0037] 1 - first control module;

[0038] 2 - reset control module;

[0039] 3 - output module;

[0040] 4 - second control module;

[0041] 100 - chip; 1000 - power-on reset circuit;

[0042] 200 - display panel;

[0043] AVDD - power supply end;

[0044] M1 - first P-type MOS transistor; M2 - second P-type MOS transistor; M3 - first N-type MOS transistor; M4 - third P-type MOS transistor;

[0045] R1 - first resistor; R2 - second resistor; R3 - third resistor; R4 - fourth resistor;

[0046] SMIT - Schmitt trigger; INV1 - first inverter; INV2 - second inverter. DETAILED DESCRIPTION

[0047] The present application is described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar components or components having the same or similar functions are denoted by the same or similar reference numerals throughout. Also, if a detailed description of the known technology is unnecessary for the features of the present application shown, it is omitted. The embodiments described below by reference to the accompanying drawings are exemplary and are for the purpose of explanation of the present application only, and cannot be interpreted as a limitation of the present application.

[0048] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have meanings consistent with meanings in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as such herein.

[0049] Those skilled in the art can understand that, unless otherwise stated, the singular forms "a", "an" and "the" used herein also include the plural forms. It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any single unit and all combinations of the associated listed items.

[0050] The Power On Reset (POR) circuit is one of the important circuits of a chip, especially an analog chip, which basically includes a POR circuit. The POR circuit is used to restore the chip to the starting state, and the quality of the POR circuit directly affects the reliability of the entire system. However, the POR circuit is sensitive to process corners, temperature and power voltage, which affects the accuracy of the POR circuit. Specifically, Figure 1 is a structural schematic diagram of a power-on reset circuit in the prior art. As Figure 1As shown, when the power supply voltage AVDD gradually increases from 0, the voltage difference between A1 point between resistors R2 and R3 and the power supply voltage AVDD gradually increases, until greater than the threshold voltage Vth of M1 (PMOS), M1 is turned on, and then the voltage of A2 point gradually increases. The output signal of the Smit trigger SMIT is related to the voltage value of A2 point and the value of the power supply voltage AVDD, when the voltage of A2 point increases to the flip voltage of SMIT, the output of SMIT is low, and the output is high after passing through the inverter INV1, and the output POR signal is 0 after passing through the inverter INV2. That is, the POR signal first increases with the increase of AVDD, and after the voltage of A2 point increases to the flip voltage of SMIT, the value of the POR signal is 0. Figure 1 The disadvantage of the POR circuit shown is that the POR signal is simultaneously affected by resistors R1, R2, R3 and the threshold voltage of PMOS M1, the flip threshold difference is too large at different processes and different temperatures, and cannot be used for high-precision applications.

[0051] Figure 2 Figure 1 is a structural schematic diagram of another power-on reset circuit in the prior art. As shown in the figure, Figure 2 As shown, first, a reference current i CORE is generated by the reference current generation circuit in the block, and is mirrored to MP2; then a current i MP2 that increases with the increase of AVDD voltage is generated by R2, MN3 and MP3, and is mirrored to MN2; when the MN2 current i MN2 is greater than the MP2 current i MP2 , the POR signal is high, and the subsequent circuit in the chip is started. The disadvantage of the power-on reset circuit is that the circuit structure is complex, the area and power consumption are relatively large, and since the reference current generation circuit also needs to work normally after AVDD reaches a certain voltage, the circuit cannot work when AVDD is low, and this structure cannot work under the condition of low voltage. The POR circuit is also simultaneously affected by the process angles of R2, MP3 and MN3, and the precision is not high.

[0052] The power-on reset circuit, chip and display device provided in the present application aim to solve the above technical problems of the prior art.

[0053] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments.

[0054] Figure 3 Figure 1 is a structural schematic diagram of a power-on reset circuit provided by an embodiment of the present application.

[0055] As shown in the figure, Figure 3As shown, the power-on reset circuit provided in the embodiment includes a first control module 1, a reset control module 2 and an output module 3 connected in sequence, the first control module 1, the reset control module 2 and the output module 3 are connected with a power supply end AVDD respectively; and the on state of the reset control module 2 is controlled by the first control module 1.

[0056] The first control module 1 is configured to be turned on when the power supply voltage AVDD rises to a set threshold value and send a turn-on signal to the reset control module 2; the reset control module 2 is configured to be turned on when receiving the turn-on signal and generate a reset control signal according to the power supply voltage AVDD and the turn-on signal; and the output module 3 is configured to flip the reset control signal to output a power-on reset signal POR.

[0057] It should be noted that, in the embodiment, the power supply end is a port outputting the power supply voltage, and in the embodiment, the power supply end and the power supply voltage are denoted as "AVDD".

[0058] Specifically, the devices in each module in the circuit are affected differently by factors such as temperature and process, which is an important reason for the decrease in the accuracy of the power-on reset circuit. The power-on reset circuit provided in the embodiment has the on state of the reset control module 2 consistent with that of the first control module 1, so the reset control module 2 and the first control module 1 are basically affected by the same factors such as temperature and process, thereby being conducive to improving the influence of factors such as temperature and process on the accuracy of the power-on reset circuit.

[0059] Figure 4 A specific circuit schematic diagram of the power-on reset circuit provided in the embodiment is shown.

[0060] As Figure 4 shown, in the power-on reset circuit provided in the embodiment, the first control module includes a first P-type MOS transistor M1, a voltage stabilizing device, a first resistor R1, a second resistor R2 and a third resistor R3; the source of the first P-type MOS transistor M1 is electrically connected with the power supply end AVDD, the gate and the drain of the first P-type MOS transistor M1 are electrically connected with the first end of the first resistor R1, the second end of the first resistor R1 is electrically connected with the first end of the second resistor R2, the second end of the second resistor R2 is electrically connected with the first end of the third resistor R3, and the second end of the third resistor R3 is grounded; and the voltage stabilizing device is electrically connected with the power supply end AVDD and a first node A1 respectively.

[0061] Specifically, the first control signal output by the first control module is the voltage of the first node A1, when the first P-type MOS tube M1 is off, the voltage of the first node A1 is the ground level GND, when the first P-type MOS tube M1 is on, the voltage of the first node A1 can be determined according to the resistance voltage division principle, in the power-on process of the power-on reset circuit, the change trend of the first node A1 is the same as the change trend of the power supply voltage AVDD.

[0062] It should be noted that the voltage stabilizing device, the first resistor R1, the second resistor R2 and the third resistor R3 all have a certain hysteresis effect, so it is also beneficial to ensure the stability of the first node A1, thereby ensuring the stability of the reset control signal, that is, ensuring the accuracy of the output module 4 flip, thereby ensuring the accuracy of the POR signal.

[0063] As shown in Figure 4 The power-on reset circuit provided by the embodiment includes a reset control module 2, an output module 3 and a first control module 1.

[0064] As shown in Figure 4 The power-on reset circuit provided by the embodiment includes a reset control module 2, an output module 3 and a first control module 1.

[0065] The Schmitt trigger SMIT has a hysteresis effect, so when the power supply voltage AVDD has jitter, especially when the jitter occurs near the flip threshold of the Schmitt trigger SMIT, the "misflip" phenomenon of the power-on reset circuit can be effectively improved. Specifically, misflip refers to the fact that the Schmitt trigger SMIT (or inverter) is misjudged due to jitter of the input signal near the flip threshold, so that the Schmitt trigger SMIT (or inverter) flips at a time when it should not flip, or does not flip at a time when it should flip, thereby affecting the accuracy of the output reset signal POR. The hysteresis makes the Schmitt trigger SMIT have a threshold threshold above and below the flip voltage, which can effectively improve the misflip problem and obtain an accurate reset signal POR.

[0066] Figure 5 A structure diagram of another power-on reset circuit provided by an embodiment of the application is shown. As shown in Figure 5 The power-on reset circuit provided by the embodiment further includes a second control module 4, and the output module 3 is further configured to generate a hysteresis control signal according to the power supply voltage AVDD and the reset control signal; and the second control module 4 is configured to adjust the hysteresis parameter of the power-on reset circuit according to the hysteresis control signal.

[0067] Specifically, the potential at the output end of the first inverter INV1 is the hysteresis control signal, and the hysteresis parameter is mainly reflected in the adjustment of the upper and lower threshold values of the Schmitt inverter SMIT. Therefore, the power-on reset circuit provided by the embodiment can adjust the hysteresis parameter of the power-on reset circuit by adding the second control module 3, which is beneficial to improve the misflip problem of the output module 3.

[0068] Figure 6 A specific circuit diagram of another power-on reset circuit provided by an embodiment of the application is shown. Figure 7 A specific circuit diagram of another power-on reset circuit provided by an embodiment of the application is shown.

[0069] As shown in Figure 6 and Figure 7 In the power-on reset circuit provided by the embodiment, the second control module 3 includes a first N-type MOS tube M3, the gate of the first N-type MOS tube M3 is electrically connected to the output end of the first inverter INV1, the source of the first N-type MOS tube M3 is grounded, the drain of the first N-type MOS tube M3 is electrically connected to the second end of the second resistor R2, and the output end of the first inverter INV1 is the hysteresis control signal.

[0070] Specifically, since the Schmitt trigger SMIT itself has a certain hysteresis effect, and the temperature and process can affect the hysteresis effect, by adjusting the hysteresis time of the entire power-on reset circuit through the second control module M3, the influence of the temperature and process on the hysteresis parameters of the Schmitt trigger SMIT that may cause false flips can be reduced.

[0071] Further, as shown in Figure 6 and Figure 7 , the power-on reset circuit provided by the embodiment can use different devices for the voltage stabilizing device.

[0072] As shown in Figure 6 , in a specific embodiment, the voltage stabilizing device includes a voltage stabilizing capacitor C1, and the two ends of the voltage stabilizing capacitor C1 are respectively electrically connected with the power supply end AVDD and the first node A1. Since the voltage stabilizing capacitor C1 stores charges, when the potential of the first node A1 fluctuates, the voltage stabilizing capacitor C1 can output charges to the first node A1 to maintain the potential of the first node A1 to be relatively stable.

[0073] As shown in Figure 7 , in another specific embodiment, the voltage stabilizing device includes a first voltage stabilizing diode D1, the anode of the first voltage stabilizing diode D1 is electrically connected with the reset control module 2, and the cathode of the first voltage stabilizing diode D1 is electrically connected with the power supply end AVDD. The voltage stabilizing capacitor and the voltage stabilizing diode both have good voltage stabilizing effect, which is conducive to further preventing false flips of the output module 3 and improving the accuracy of the power-on reset circuit.

[0074] As shown in Figure 7 , in the power-on reset circuit provided by the embodiment, the reset control module 2 further includes a second voltage stabilizing diode D2, and the two ends of the second voltage stabilizing diode D2 are respectively electrically connected with the first end and the second end of the fourth resistor R4. The second voltage stabilizing diode D2 can further prevent the voltage fluctuation of the input end of the Schmitt trigger SMIT (i.e. the reset control signal), thereby further improving the accuracy of the power-on reset circuit.

[0075] Figure 8 The specific circuit schematic diagram of the first control module in the power-on reset circuit provided by the embodiment is shown in Figure 8 , in the power-on reset circuit provided by the embodiment, the first control module 1 further includes a third P-type MOS tube M4, the gate and the drain of the third P-type MOS tube M4 are both electrically connected with the first end of the first resistor R1, and the source of the third P-type MOS tube M4 is electrically connected with the drain of the first P-type MOS tube M1. The voltage stabilizing module 1 of the power-on reset circuit provided by the embodiment includes multiple MOS tubes, which can be applied to the power-on reset circuit with high power supply voltage AVDD.

[0076] It should be noted that, although Figure 8The first control module 1 shown only shows the first P-type MOS transistor M1 and the third P-type MOS transistor M4, but in the specific implementation, in order to adapt to a higher power supply voltage value, the first control module 1 can include more MOS transistors.

[0077] After the above detailed description of the power-on reset circuit provided by the application, it can be determined that the power-on reset circuit provided by the embodiment of the application is relatively simple, which is beneficial to the miniaturization of the chip.

[0078] Moreover, the first control signal output by the first control module 1 is mainly determined by the first P-type MOS transistor M1. When the power supply voltage AVDD is greater than the threshold voltage Vth of the first P-type MOS transistor M1, the first P-type MOS transistor M1 is turned on, so that the current starts to flow through the first resistor R1, the second resistor R2 and the third resistor R3, and the potential of the first node A1 starts to rise. At the same time, because the second P-type MOS transistor M2 is also turned on after the first P-type MOS transistor M1 is turned on, that is, the first P-type MOS transistor M1 and the first resistor R1 jointly determine the Vgs voltage of the second P-type MOS transistor M2. Because the Vgs voltage of the first P-type MOS transistor M1 and the Vgs voltage of the second P-type MOS transistor M2 are basically consistent under different power supply voltages and process angles, the second node A2 has good consistency under different process angles, that is, the power-on reset circuit provided by the embodiment has small process response and high accuracy.

[0079] Specifically, the potential of the first node A1 is equal to the potential of the second end of the first resistor R1 and the gate of the second P-type MOS transistor M2. The potential of the second node A2 is the reset control signal, that is, the potential input to the input end of the Schmitt trigger SMIT.

[0080] In order to facilitate the understanding of the working principle of the power-on reset circuit provided by the application, the following describes the working principle of the power-on reset circuit provided by the application in combination with Figure 6 the power-on reset circuit shown in Figure 9 the timing diagram of the potentials of the nodes in the power-on reset circuit and the POR signal in the power-on process and the power supply voltage AVDD.

[0081] As shown in Figure 6 and Figure 9 in the power-on process, the power supply voltage AVDD gradually rises until it is stable. In the power-on process, there are mainly four stages, which are as follows:

[0082] The first stage: the power supply voltage AVDD is greater than V1 and less than V2. At this time, the first P-type MOS transistor M1 and the second P-type MOS transistor M2 are not turned on, the potentials of the first node A1, the second node A2, the fourth node A4 and the fifth node A5 are all 0V, that is, the second control signal input by the input end of the Schmitt trigger SMIT is 0V, which is lower than the flip voltage of the Schmitt trigger SMIT, then the voltage output by the Schmitt trigger SMIT is related to the power supply voltage AVDD, and after the processing of the first inverter INV1 and the second inverter INV2, the POR signal is output, in this stage, the output POR signal is the same as the power supply voltage AVDD. And in this process, the potential of the output end of the first inverter INV1, that is, the third node A3, is always 0.

[0083] The second stage: the power supply voltage AVDD is greater than or equal to V2 and less than V3. When the power supply voltage AVDD reaches V2, the voltage difference between the gate and the source of the first P-type MOS transistor M1 reaches the conduction requirement, so that the voltage of the fourth node A4 is equal to the power supply voltage AVDD, and the voltage of the first node A1 can be obtained through the voltage division principle, specifically, the potential of the first node A1 is equal to R1*AVDD / (R1+R2+R3).

[0084] In the second stage, the potential of the first node A1 after the first P-type MOS transistor M1 is turned on makes the second P-type MOS transistor M2 turned on, and the second node A2 is connected with the power supply end AVDD, that is, the voltage of the second node A2 has the same change trend as the power supply voltage AVDD. The reset control signal (the voltage of the second node A2) input by the input end of the Schmitt trigger SMIT has the same change trend as the power supply voltage AVDD, at this time, the voltage of the reset control signal is still lower than the flip voltage of the Schmitt trigger SMIT, then the voltage output by the Schmitt trigger SMIT is related to the power supply voltage AVDD, and after the processing of the first inverter INV1 and the second inverter INV2, the POR signal is output, in this stage, the output POR signal is the same as the power supply voltage. In this process, the potential of the output end of the first inverter INV1, that is, the third node A3, is always 0.

[0085] Phase 3: The power supply voltage AVDD is greater than or equal to V3 and less than V4. When the power supply voltage AVDD reaches V3, both the first P-type MOSFET M1 and the second P-type MOSFET M2 are turned on. The trend of the change in the first node A1 is the same as the trend of the change in the power supply voltage AVDD. The potential of the second node A2 can be approximated as equal to the power supply voltage AVDD. V3 is the switching voltage of the Schmitt trigger SMIT. Therefore, the voltage output of the Schmitt trigger SMIT is reversed. After being processed by the first inverter INV1, it outputs a high level (i.e., the third node is high). After being processed by the second inverter INV2, it outputs a low level POR signal (usually 0V).

[0086] During this process, the flip-flop of the Schmitt trigger causes the output of the first inverter INV1, i.e., the potential of the third node A3, to be high, thereby turning on the first N-type MOS transistor M3, which in turn short-circuits the third resistor R3, thereby reducing the number of devices in the first control module 1 that affect the hysteresis parameters and thus achieving the purpose of adjusting the hysteresis parameters of the power-on reset circuit.

[0087] It should be noted that in the above three stages, the first capacitor C1 plays a voltage stabilizing role, thereby ensuring that the voltage of the first node A1 remains relatively stable. Furthermore, during these three stages, the POR signal output by the power-on reset circuit causes other circuits in the chip containing the power-on reset circuit to gradually start up.

[0088] In the fourth stage, the power supply voltage AVDD equals V4, the power-on is complete, and the chip returns to its preset state.

[0089] Figure 10 for Figure 6 The POR signal diagram shows the simulation results of the power-on reset circuit under different process angles and temperatures. Figure 11 for Figure 1 The diagram shows the POR signal of the power-on reset circuit in the prior art under different process angles and temperatures.

[0090] Specifically, such as Figure 10 and Figure 11 As shown, the applicants respectively... Figure 1 The power-on reset circuit shown and Figure 4 The power-on reset circuit shown was subjected to simulation experiments at multiple process angles and multiple temperatures.

[0091] Please refer to Figure 10 The horizontal axis represents the power supply voltage AVDD, and the vertical axis represents the voltage value of the POR signal under different power supply voltages. In the initial stage, the POR signal increases as the power supply voltage AVDD increases. When AVDD increases to a certain value, the Schmitt trigger SMIT in the power-on reset circuit begins to flip, and the output POR signal is 0.

[0092] In combination Figure 10 and Figure 11 , the power-on reset circuit and Figure 1 the conventional power-on reset circuit shown in FIG. 1 are simulated under different process corners and temperatures, Figure 10 the number of POR signals generated by the power-on reset circuit provided in the present application is less than Figure 11 the number of POR signals generated by the conventional power-on reset circuit shown in FIG. 1, because the POR signals generated under some different test conditions coincide, which also proves that the level conversion circuit provided in the present application is less affected by process corners and temperature.

[0093] In addition, the range of the flip voltage (POR signal falling point) of the level conversion circuit provided in the present application under different test conditions is obviously smaller than Figure 1 the range of the flip voltage of the conventional level conversion circuit shown in FIG. 2, which also proves that the level conversion circuit provided in the present application is less affected by process corners and temperature.

[0094] Based on the same inventive concept, the embodiment of the present application provides a chip, as shown in FIG. 10, which comprises the power-on reset circuit 1000 in the above-mentioned embodiment, has the beneficial effects of the power-on reset circuit in the above-mentioned embodiment, and details are not repeated here. Figure 12

[0095] Specifically, the structure of the power-on reset circuit 1000 in the chip 100 is relatively simple, which is conducive to the miniaturization of the chip 100. The chip 100 can be used in multiple fields, for example, can be used as a display driving chip.

[0096] Based on the same inventive concept, the embodiment of the present application provides a display device, as shown in FIG. 11, which comprises the chip 100 in the above-mentioned embodiment, has the beneficial effects of the chip 100 in the above-mentioned embodiment, and details are not repeated here. Figure 13

[0097] Specifically, the display device further comprises a display panel 200, and the chip 100 is electrically connected with the display panel 200. The signal generated by the chip 100 is transmitted to the display panel to drive the display panel to display.

[0098] By applying the embodiment of the present application, at least the following beneficial effects can be achieved:

[0099] The power-on reset circuit, chip and display device provided in the embodiment of the present application, the conduction of the reset control module is consistent with the conduction of the first control module, so the temperature and process factors and the like affecting the reset control module and the first control module are basically consistent, thereby being conducive to improving the influence of temperature and process factors and the like on the accuracy of the power-on reset circuit.​​

[0100] The terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or a specific number of the technical features indicated. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0101] The above only describes some embodiments of the present application, and it should be pointed out that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present application.

Claims

1. A power-on reset circuit, characterized in that, It includes a first control module, a reset control module, and an output module connected in sequence, wherein the first control module, the reset control module, and the output module are respectively connected to a power supply terminal; The first control module includes a first P-type MOSFET, a voltage regulator, a first resistor, a second resistor, and a third resistor. The source of the first P-type MOSFET is electrically connected to the power supply terminal. The gate and drain of the first P-type MOSFET are both electrically connected to the first terminal of the first resistor. The second terminal of the first resistor is electrically connected to the first terminal of the second resistor and the reset control module. The second terminal of the second resistor is electrically connected to the first terminal of the third resistor, and the second terminal of the third resistor is grounded. The voltage regulator is electrically connected to both the power supply terminal and the reset control module. The reset control module includes a second P-type MOS transistor and a fourth resistor; the gate of the second P-type MOS transistor is electrically connected to the second terminal of the first resistor, the source of the second P-type MOS transistor is electrically connected to the power supply terminal, the drain of the second P-type MOS transistor is electrically connected to the first terminal of the fourth resistor at a second node, and the second terminal of the fourth resistor is grounded. The output module includes a Schmitt trigger, a first inverter, and a second inverter. The input of the Schmitt trigger is electrically connected to the second node, the output of the Schmitt trigger is electrically connected to the input of the first inverter, the output of the first inverter is electrically connected to the input of the second inverter, and the output of the second inverter outputs a reset signal. The rising threshold of the Schmitt trigger is higher than the rising threshold of the first inverter, and the falling threshold of the Schmitt trigger is lower than the falling threshold of the first inverter. The rising threshold of the first inverter is the same as the rising threshold of the second inverter, and the falling threshold of the first inverter is the same as the falling threshold of the second inverter. Furthermore, the conduction state of the reset control module is controlled by the first control module; wherein, The first control module is configured to turn on and send a turn-on signal to the reset control module when the power supply voltage at the power supply terminal rises to a set threshold. The reset control module is configured to turn on when the turn-on signal is received and to generate a reset control signal based on the power supply voltage and the turn-on signal. The output module is configured to toggle the reset control signal to output a power-on reset signal.

2. The power-on reset circuit according to claim 1, characterized in that, The output module is further configured to generate a hysteresis control signal based on the power supply voltage and the reset control signal; the power-on reset circuit further includes: The second control module is configured to adjust the hysteresis time of the power-on reset circuit according to the hysteresis control signal.

3. The power-on reset circuit according to claim 2, characterized in that, The second control module includes a first N-type MOS transistor, the gate of which is electrically connected to the output terminal of the first inverter, the source of which is grounded, and the drain of which is electrically connected to the second terminal of the second resistor. The voltage at the output terminal of the first inverter is the hysteresis control signal.

4. The power-on reset circuit according to claim 2 or 3, characterized in that, The voltage regulator includes a voltage regulator capacitor, the two ends of which are electrically connected to the power supply terminal and the reset control module, respectively.

5. The power-on reset circuit according to claim 2 or 3, characterized in that, The voltage regulator includes a first Zener diode, the anode of which is electrically connected to the reset control module, and the cathode of which is electrically connected to the power supply terminal.

6. The power-on reset circuit according to claim 1, characterized in that, The reset control module also includes a second Zener diode, the two ends of which are electrically connected to the first and second ends of the fourth resistor, respectively.

7. The power-on reset circuit according to claim 2 or 3, characterized in that, The first control module further includes a third P-type MOS transistor, the gate and drain of which are electrically connected to the first terminal of the first resistor, and the source of which is electrically connected to the drain of the first P-type MOS transistor.

8. A chip, characterized in that, Includes the power-on reset circuit according to any one of claims 1 to 7.

9. A display device, characterized in that, Includes the chip described in claim 8.

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