Condition code and plausibility-driven fault detection in result logic for fast and accurate substring matching

Abstract

Method for detecting faults in a substring search operation, comprising using a processor unit comprising vector registers each having M vector elements, providing an M x M matrix of comparators for a character-by-character comparison of elements of a reference string stored in a first vector register of the vector registers and a target string stored in a second vector register of the vector registers. The vector elements are n-bit elements for encoding characters. A result bit vector is generated using the comparisons performed by the M x M matrix. The result bit vector indicates characters of the target string that match the reference string completely, and indicates characters of the target string that match the reference string partially. Fault detection in the substring search operation is performed by exploiting the result bit vector.

Description

Background Technology

[0001] This invention relates to the field of digital computer systems, and more specifically, to plausibility-driven fault detection in condition codes and result logic for fast and accurate substring matching using processor units for substring searching.

[0002] Numeric text is represented as encoded and stored as binary encoded strings. Widely accepted computer character encoding standards include the American Standard Code for Information Interchange (ASCII) and the Uniform Code Transformation Format (UTF). One of the most common text processing tasks on computers is substring searching or substring matching, which involves identifying the occurrence of a reference string within a larger target string. Summary of the Invention

[0003] Embodiments of the present invention relate to a method for detecting faults in a substring search operation. A non-limiting example of the method includes: using a processor unit comprising vector registers, each having M vector elements, to provide an M×M matrix of comparators for character-by-character comparisons of elements of a reference string stored in a first vector register of the vector registers and a target string stored in a second vector register of the vector registers. The vector elements are n-bit elements used to encode characters. A resulting bit vector is generated using the comparisons performed by the M×M matrix. The resulting bit vector indicates characters in the target string that completely match the reference string, and characters in the target string that partially match the reference string. Fault detection in the substring search operation is performed by utilizing the resulting bit vector.

[0004] Embodiments of the present invention relate to a processor unit for detecting faults in a substring search operation. The processor unit includes a plurality of vector registers, each having M vector elements. The vector elements are n-bit elements used to encode characters. A non-limiting example of the processor includes an M×M matrix of comparators used for character-by-character comparisons of elements in a first register storing a reference string and elements in a second register storing a target string. The M×M matrix is ​​configured to generate bit vectors indicating characters in the target string that fully match the reference string and characters in the target string that partially match the reference string. The processor also includes result generation logic for using the resulting bit vectors to generate an indication of the start and length of a substring of the target string that matches a portion of the reference string. The processor also includes fault detection logic for performing fault detection in the substring search operation by utilizing the resulting bit vectors.

[0005] Embodiments of the present invention relate to a computer program product for detecting faults in a substring search operation. The computer program product includes a computer-readable storage medium having program instructions embodied therein. The program instructions are executable by a processor to cause the processor to perform a method. A non-limiting example of the method includes using a processor unit comprising a vector register, each having M vector elements, to provide an M×M matrix of comparators for character-by-character comparisons of elements of a reference string stored in a first vector register of the vector registers and a target string stored in a second vector register of the vector registers. The vector elements are n-bit elements used to encode characters. A resulting bit vector is generated using the comparisons performed by the M×M matrix. The resulting bit vector indicates characters in the target string that completely match the reference string, and characters in the target string that partially match the reference string. Fault detection in a substring search operation is performed by utilizing the resulting bit vector.

[0006] Additional technical features and benefits are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, refer to the detailed description and accompanying drawings. Attached Figure Description

[0007] The proprietary details described herein are specifically pointed out and clearly claimed in the claims at the end of the specification. The foregoing and other features and advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is an exemplary structure of a processor according to an embodiment of the present invention;

[0009] Figure 2 This is a diagram illustrating the components of a processing unit according to an embodiment of the present invention;

[0010] Figure 3 This is a diagram illustrating the logic for detecting faults by comparing the resulting bit vector with the first row of a comparison matrix according to an embodiment of the present invention;

[0011] Figure 4 This is a diagram illustrating the logic of detecting faults by comparing the resulting bit vector with a zero detection vector associated with the target string according to an embodiment of the present invention;

[0012] Figure 5 This is a diagram illustrating the logic of detecting faults by comparing the reported matching type with the result bit vector and the matchable region according to an embodiment of the present invention;

[0013] Figure 6 This is a diagram illustrating the logic for detecting faults by comparing the resulting bit vector with the element size according to an embodiment of the present invention;

[0014] Figures 7A-7D This is a diagram illustrating the logic for detecting faults by checking the fidelity of condition codes in a report according to an embodiment of the present invention; and

[0015] Figure 8 This is a flowchart of a method for detecting faults in a substring search operation by checking the fidelity of the result bit vector and the reported condition codes, according to an embodiment of the present invention.

[0016] The figures described herein are illustrative. Many variations may be made to the figures or operations described herein without departing from the spirit of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term "coupling" and its variations describe a communication path between two elements and do not imply a direct connection between the elements without any intermediate elements / connections between them. All such variations are considered part of the specification.

[0017] In the accompanying drawings and the following detailed description of the disclosed embodiments, the various elements shown in the drawings are labeled with two or three digits. With a few exceptions, the leftmost digit of each reference numeral corresponds to the figure in which its element is first shown. Detailed Implementation

[0018] As previously mentioned, one of the most common text processing tasks on computers is substring searching or substring matching to identify the presence of a reference string within a larger target string. For example, a target string can be generated based on speech input using a speech transcription process. Typically, the length of the reference string can be specified implicitly (by zero termination) or explicitly through additional operands. Similarly, the target string can be limited by a zero termination of the tokenized end-of-string (EOS). With the ever-increasing pool of information (especially unstructured human-readable information), there is a need for faster extraction of textual information, and therefore a need for faster methods to solve the substring matching problem. Furthermore, additional logic is required to perform plausibility-driven cross-validation on internal signals and intermediate results. Embodiments of this invention provide logic capable of plausibility-driven cross-validation of the results of substring searches and cross-validation of condition codes indicating the type of match detected. Compared to traditional fault detection techniques, the method proposed in this paper focuses primarily on error detection in the results and condition code logic of a SIMD (Single Instruction Multiple Data) substring search engine.

[0019] Vector SIMD engines with dedicated instructions for substring searching allow for the simultaneous comparison of several characters using a single instruction, resulting in a speedup compared to byte-by-byte comparisons. In an exemplary vector SIMD implementation, the vector register has a fixed number of bits (e.g., K bits) to hold a single vector. The vector register may include M vector elements of size n (i.e., each vector element occupies n bits). The width of the register refers to the number of vector elements in the register.

[0020] The number of characters L is less than M. Embodiments of the invention involve searching for a substring of L characters within a target string that may occupy a full vector register (e.g., M×n bits). This string of L characters can be referred to as the reference string.

[0021] The upper triangular portion of the comparator matrix includes the main diagonal and the subsequent upper diagonal. The lower triangular portion of the comparator matrix includes the main diagonal and the subsequent lower diagonal.

[0022] The term "complete match" refers to a substring in the target string that completely matches L characters of the reference string. The term "partial match" refers to a substring in the target string that partially matches one or more characters of the reference string. Using the top diagonal allows you to identify a substring of one or more characters at the end of the target string. Using the bottom diagonal allows you to identify a substring of one or more characters at the beginning of the target string.

[0023] One or more embodiments of the fast and accurate substring matching described herein enable the accurate identification of both complete matches at any position in a target string and partial matches at the end or beginning of the target string. This method eliminates the need for re-evaluation (e.g., substring matching in a short string with currently known instructions might require re-evaluation, which involves additional shifts of operands to search for partial matches). For short strings suitable for use within a vector register, the fast and accurate substring matching method described herein enables the identification of substring matches using a single operation. This eliminates the re-evaluation phase when complete or partial matches occur.

[0024] Many processor designs (especially when targeted at servers or hosts) also need to address and integrate various aspects of RAS (Reliability, Availability, and Serviceability). For example, in such cases, detecting and handling physical failures (permanent, transient, or intermittent) during runtime can be important.

[0025] An error is defined as a deviation from the accuracy or correctness of a fault manifestation. Examples of errors include a memory cell incorrectly acquiring serial data bits due to a delay fault, or an unwanted value being generated due to a missing operator priority.

[0026] Similar to faults, errors can be classified into two types: detected or latent errors. When error detection techniques are applied, an error is referred to as a latent error as long as it is not identified. As an example, an error in a single storage bit of a cache entry caused by the positive charge and kinetic energy of an alpha particle (called a single-event upset (SEU) fault) can be latent or detected. If the processor recognizes the SEU fault, it detects the SEU fault; otherwise, it remains in its latent state. Additionally, latent errors may disappear or be overwritten before they are detected. However, most commonly, many errors propagate and thus generate more errors or pass errors through the system, leading to single or multiple faults. If an SEU occurs in a latch or flip-flop, it can cause a change in state. Because the result of a substring search often affects the control flow (conditions in an if clause), the impact of an SEU can be significant. As a non-limiting example, an error in a database search caused by an SEU could certainly lead to the incorrect allocation or transfer of resources, assets, etc.

[0027] Understandably, traditional fault detection techniques have many limitations in the context of SIMD string search engines. One traditional technique, the resource replication of SIMD architectures, is extremely expensive. Another fault prevention technique (commercial radiation-hardened processors) is also very expensive in terms of required area and computational power. However, other fault detection techniques are suitable for some operations but not others. For example, residual checking techniques are only used for numerical computation, while parity checking is limited to single or odd-bit errors and only protects data, not computation.

[0028] Figure 1 This is an exemplary structure of processor 101. For example, level 1 or multi-level cache 103 is used to buffer memory data to improve processor performance. Cache 103 is a high-speed buffer that holds cache lines of memory data that may be used. Typical cache lines are 64, 128, or 256 bytes of memory data. Cache 103 caches data from higher-level storage (as main memory 105).

[0029] The program counter (instruction counter) 107 tracks the address of the current instruction to be executed. In z / Architecture processors, the program counter is 64 bits and can be truncated to 31 or 24 bits to support previous addressing limitations. The program counter is typically embodied in the computer's Program Status Word (PSW) so that it persists during context switches. Therefore, a program with a program counter value can be interrupted, for example, by the operating system (context switch from program environment to operating system environment). The program counter value is maintained in the program's PSW when the program is inactive, and the operating system's program counter (in the PSW) is used during operating system execution. Typically, the program counter increments by an amount equal to the number of bytes of the current instruction. The program counter 107 is modified, for example, through context switch operations or branch take operations of branch instructions. In a context switch operation, the current program counter value, along with other state information about the executing program (such as condition codes), is saved in the program status word, and a new program counter value is loaded, pointing to the instructions of the new program module to be executed. The branch is executed to perform an operation so that the program can make a decision or loop within the program by loading the result of the branch instruction into the program counter 107.

[0030] Typically, instruction fetching unit 109 is used to represent instruction fetching by processor 101. Fetching unit 109 fetches the "next sequential instruction," the target instruction of a branch take-off instruction, or the first instruction of the program after a context switch. Examples of instruction fetching units typically employ prefetching techniques to speculatively prefetch instructions based on the probability that they might be used. For example, the fetching unit may fetch 16 bytes of instruction, including the next sequential instruction and additional bytes for other sequential instructions.

[0031] The fetched instructions are then executed by processor 101. For example, the fetched instructions(s) are passed to dispatch unit 111 of the fetch unit. Dispatch unit 111 decodes the instructions(s) and forwards information about the decoded instructions(s) to the appropriate units 113, 115, 117. Execution unit 113 can typically receive information about the decoded arithmetic instructions from instruction fetch unit 109 and can perform arithmetic operations on operands according to the opcode of the instructions. Operands are preferably provided to execution unit 113 from memory 105, vector register 119, or from the immediate field of the instruction being executed. When stored, the result of the execution is stored in memory 105, vector register 119, or other machine hardware (such as control registers, PSW registers, etc.).

[0032] like Figure 1As shown, vector registers 119 can have the same size K, where K = M x n, and n is the number of bits used to encode a single character (e.g., n = 8 bits). For example, each vector register 119 can store K bits. M can be the width of the register.

[0033] The data stored in vector register 119 can be processed using parallel vector processing techniques, such as single instruction multiple data (SIMD) hardware, where vector register 119 can hold data for vector processing performed by SIMD instructions.

[0034] For example, a fixed-size chunk, called a word, can be transferred from memory 105 to vector register 119. The number of bits in the word may be equal to or less than the size K of register 119. For example, vector load / store instructions provide the ability to retrieve a word stored in memory 105 and pack it into a sequential vector / stream to be placed in vector register 119. For example, memory 105 may be configured to include a 256-bit memory word. The 256-bit memory word may be divided into K-bit chunks. During processing, each K-bit chunk (containing M characters) is loaded into register 119.

[0035] Figure 2 This is a diagram illustrating components of a processing unit 200 according to one or more embodiments of the present invention. The processing unit 200 may be configured to operate on an entire vector in a single instruction. The processing unit 200 may be... Figure 1 It is part of the execution unit 113.

[0036] Processing unit 200 includes a comparator matrix 214. Comparator matrix 214 may be a hardware comparator matrix. Comparator matrix 214 may be configured to compare individual characters. Comparator matrix 214 includes comparators, such as character equality comparators. In addition to equality comparisons, or as an alternative to equality comparisons, the comparators may be configured to perform combinations of '>' and '<' operators, such as the operation: NOT((r>t)OR(r<t))=(r==t).

[0037] Comparator matrix 214 operates on two operands, a and b. Operand a 202 can be, for example, the reference string to be searched, and operand b 204 can be the target string, checking whether it contains all and / or a portion of operand a 202. The reference string may include L characters, and the target string may include M characters (which may occupy the full vector register 119). The target string and the reference string are compared character by character. Zero-detection logic 212 uses a third operand (operand c 208) to generate a zero-detection vector, and logic 224 applies the zero-detection vector to the result of comparator matrix 214. Operand c (explicit length) 208 can have, for example, five bits 59-63. For example, searching for the reference string "noon" within the target string "abhighnoonoonnoo" with an explicit length of 4 (c=4) returns the result = 0000001001000100. The "1" in the seventh and tenth positions from the left is generated by a complete match, while the "1" in the third position from the right is generated by a partial match.

[0038] The element size control 206, using three bits from 0 to 2, specifies the element size. The element size control 206 specifies the size of the elements in the vector register operand. In one example, the element size control 206 can specify bytes, half-words (e.g., 2 bytes), or words (e.g., 4 bytes). For example, 0 represents a byte; 1 indicates a half-word; and 2 represents a word, also known as a full word. Each element can include encoded data within a stream of UTF-8 (1 byte / character), UTF-16 (2 bytes / character), or UTF-32 (4 bytes / character) code units.

[0039] Since the width of the vector register (M=16) is greater than the number of characters L=4 in the reference string "noon", the vector register storing the reference string can include empty elements. For example, the first 4 characters in reference string 202 can represent the word "noon", while the following 4-12 characters are empty and can be represented by 0x00 in character encoding. The first zero-detection logic 210 and the second zero-detection logic 212 can be configured to generate a first zero-detection vector 211 and a second zero-detection vector 213, respectively. The first zero-detection vector 211 has values ​​indicating empty elements and non-empty elements in the target string, and the second zero-detection vector 213 has values ​​indicating empty elements and non-empty elements in the reference string.

[0040] In one embodiment, the output of comparator matrix 214 may include equality matrix 215. Equality matrix 215 has values ​​indicating the equality relationship between the compared characters. Figure 2As shown, the first zero detection vector 211, the second detection vector 213, and the equality matrix 215 can be input to the corresponding triggers 216a, 216b, and 216c, respectively.

[0041] According to an embodiment of the present invention, the processing unit 200 may further include fault detection logic. The fault detection logic includes a register for storing the expected intermediate result vector 230, a register including a correction mask 228, a register including a target isolation mask 226, and logic for performing an AND operation between corresponding elements of the registers. In one example, the three registers may not be part of the fault detection logic. Using the correction logic 222 to generate the correction mask 228 can implement a simplified method for suppressing indications of partial or complete matches in the expected intermediate result vector 230. Compared to conventional techniques, the processing unit 200 distinguishes between complete and partial matches at the hardware level. This can be achieved by applying the correction mask 228 generated by the correction logic 222 to the expected intermediate result vector 230 (which may include partial matches at the end of string segments). The expected intermediate result vector 230 cannot distinguish between complete and partial matches. For example, if operand b includes operand a and a portion of operand a, then the intermediate result vector 230 includes a bit value at the beginning of the substring of operand b that completely matches operand a and another bit value at another position at the beginning of the substring of operand b that partially matches operand a.

[0042] The fault detection logic may further include a first AND gate 234 for performing an AND operation between the correction mask 228 and the intermediate result vector 230. The output of AND gate 234 can be used as the input of a second AND gate 232. The target isolation mask 226 can be generated using the target isolation logic 220 and can be used as another input of the second AND gate 232. The fault detection logic may further include a third AND gate 236 for performing an AND operation between the intermediate result vector 230 and the target isolation mask 226.

[0043] According to an embodiment of the invention, the result generation logic can be implemented, for example, via an OR tree 238 on the bits of the output of the second AND gate 232. The output of the OR tree 238 provides an indication of a perfect match result 240. As described herein, a perfect match is a substring of L characters of the target string that perfectly matches the target string. The output of the third AND gate 236 is fed to a leading zero counter 242. The leading zero counter 242 returns a result index 244 by determining the number of leading zeros in the result bit vector. The result index 244 indicates the index of the first match. Thus, for example, searching for the reference string "noon" within the target string "Abhighnoonoonnoo" returns a result index value equal to 6 (because the 6th bit of the target string is the first match). The result index 244 can be stored in a flip-flop 246.

[0044] According to an embodiment of the present invention, the result generation logic may further return condition code 250 and result index 244. Exemplary condition codes are shown in the table below:

[0045] condition codes Meaning CC0 No match, no partial match, no end of string (EOS) CC1 No match, no partial match but implying EOS termination CC2 Find exact match CC3 A partial match was found, but no complete match was found.

[0046] In one embodiment, condition code 250 may be generated by condition code generator 248 based on a combination of the following inputs: target isolation mask 226, correction mask 228, and an expected intermediate result indicating a perfect match result 240. In one embodiment, condition code generator 248 may include a decoder. The generated condition code 250 may be stored in a corresponding trigger 252. Figure 2 As shown, SEU faults 218 and 254 can affect any fault detection logic triggers 216a, 216b, and 216c and any result generation logic triggers 246 and 252.

[0047] Figure 3 This is a diagram illustrating the logic for detecting faults by comparing a resulting bit vector with the first row of a comparator matrix according to an embodiment of the present invention. As described herein, comparator matrix 305 may operate on two operands a 202 and b 204. The first row 308 of comparator matrix 305 may include bit values ​​set to 1 at positions where the first character of the reference string matches one of the characters in the target string. Fault detection logic 300 is configured to detect an error when the resulting bit vector 310 indicates a match at a specific position, but the corresponding character in the target string does not match the first character of the reference string at that specific position. Fault detection logic 300 may also generate a zero detection vector 306.

[0048] Comparator matrix 305 is configured to compare the individual characters of each operand 302 and 304. Comparator matrix 305 includes comparators, such as a character-by-character equality comparator. Result bit vector 310 indicates the result of the performed substring search and includes bit values ​​set to 1 at positions where the character sequences of the reference string match those of the target string. Result bit vector 310 can indicate any of a complete match, a partial match, and an overlapping match. Trigger 312 stores result bit vector 310. At some point, for example, due to exposure to radiation including alpha particles or neutrons, trigger 312 may experience SEU event 316. Therefore, the output 318 of trigger 312 may have at least one bit flipped (e.g., the bit at position q6).

[0049] like Figure 3As shown, another flip-flop 314 stores the first row 308 of the comparator matrix 305. The fault detection logic 300 includes an AND gate 320. All bits stored in the flip-flop 314 are inverted and fed into the AND gate 320. Another input to the AND gate 320 is the output 318 of the flip-flop 312. The output of the AND gate 320 is connected to an OR tree 322. It should be noted that the OR tree 322 generates a value of 1 only when the resulting bit vector 318 is not a subset of the first row 308 of the comparator matrix 305. In this case, since the bit at position q6 of the output 318 is set to 1, the value at the corresponding position in the first row 308 is set to 0 (indicating a first character mismatch), which is inverted to 1 at the input of the AND gate 320. Since the second input of the AND gate 320 (the value of the resulting bit vector element q6) is also 1, the OR tree 322 outputs 1, indicating a fault 324. The fault detection logic 300 is configured to check the fidelity of the result bit vector 310 and detect a fault when the result bit vector 310 is different from a subset of the first row 308 of the comparator matrix 305.

[0050] Figure 4 This is a diagram illustrating the logic for detecting faults by comparing a resulting bit vector with a zero-detection vector associated with a target string according to an embodiment of the present invention. According to an embodiment of the present invention, first zero-detection logic 309 processes the information included in operand a 302 to generate a first zero-detection vector 306 associated with a reference string. In the illustrated case, all bits of the first zero-detection vector 306, starting from the fifth position, are set to 1. Second zero-detection logic 404 processes the information included in operand b 304 to generate a second zero-detection vector 406 associated with the target string. In the illustrated case, since the target string included in operand b 304 is implicitly terminated (including the end of string character 402), all bits of the second zero-detection vector 406 are set to 1 starting from the position corresponding to the end of string character 402. Flip-flop 408 stores the second zero-detection vector 406.

[0051] The substring search logic 408 is configured to compare each character of each operand 302 and 304 using a first zero-detection vector 306 and a second zero-detection vector 406. The substring search logic 408 generates a result bit vector 310, which is stored in the trigger 312. At some point, due to exposure to radiation consisting of alpha particles or neutrons, for example, the trigger 312 may experience a SEU event 316. As a result of the occurrence of the SEU event 316, at least one bit of the output 318 of the trigger 312 may be flipped. In the case shown, the last bit of the output 318 is flipped. Note that the flipped bit is outside the end of the target string indicated by the end of string character 402.

[0052] Fault detection logic 400 includes an AND gate 410. The contents of flip-flop 408 are fed into AND gate 410 as one of the inputs. The output 318 affected by SEU includes another input to AND gate 410. Fault detection logic 400 also includes an OR tree 412 for checking the output of AND gate 410. In this case, OR tree 412 produces a value of 1 only if the bit position in the result bit vector indicating a match is higher than the bit position in the zero-detection vector indicating the terminating element (EOS element) of the target string. In this case, since the last bit of the output 318 affected by SEU is set to 1 and the last bit of the second zero-detection vector 406 is set to 1, the value generated by OR tree 412 is 1, indicating fault 414. Fault detection logic 400 is configured to check the plausibility of the result bit vector 310 and detect a fault when the output of the result bit vector 318 indicates a match beyond the implicit or explicit termination of the target string.

[0053] Figure 5 This is a diagram illustrating logic 500 for detecting faults by comparing a resulting bit vector with a matchable region associated with a target string according to an embodiment of the invention. According to an embodiment of the invention, the zero-detection logic processes information included in the operands to generate a zero-detection vector 306 associated with a reference string. In the illustrated case, since the string included in operand a 202 comprises four characters, all bits in the first zero-detection vector 306, starting from the fifth position, are set to 1. According to an embodiment of the invention, logic 500 may further include correction logic 502. Correction logic 502 includes logic for generating a correction mask 228. The correction mask 228 is stored in a flip-flop 510. The correction mask 228 implements a simplified method for suppressing indications of partial or complete matches in the resulting bit vector 310. As mentioned herein, the expected intermediate result 505 cannot be distinguished between a complete match and a partial match. To suppress partial matches from the expected intermediate result 505, correction mask 228 506 can be applied to the expected intermediate result 505, which may include partial matches at the end of string segments. In the case shown, correction mask 228 represents the matchable region. As used herein, the term "matchable region" means the region where a complete match is possible. All bits of the matchable region within correction mask 228 are set to 1 because, in the case shown, the reference string consists of four characters, so the matchable region includes all bits except the last three.

[0054] After applying correction mask 228 506 to the expected intermediate result 505, the resulting bit vector 310 includes only indications of complete matches. Since, in the case shown, the expected intermediate result 505 includes only partial matches indicated by bit s7 set to 1, the applied bit mask 228 sets all bits of the resulting bit vector 310 to 0.

[0055] The resulting bit vector 310 is stored in flip-flop 512. At some point, flip-flop 512 may withstand a SEU event 514. As a result of the occurrence of SEU event 514, at least one bit of the output 516 of flip-flop 512 may be toggled. In the case shown, the third bit from the last output 516 is toggled. Note that the toggled bit is outside the matchable region.

[0056] Fault detection logic 500 includes an AND gate 524. The contents of flip-flop 510 are fed into the AND gate 524 as one of the inputs. The output 516 affected by the SEU includes another input to the AND gate 524. Fault detection logic 500 also includes a first OR tree 526 on the bits of the output of the AND gate 524. The OR tree 526 generates a value of 1 only when the match of the bit position indicating the result bit vector is within the matchable region. In this case, since the output of the AND gate 524 is 0, the value generated by the OR tree 526 is also 0.

[0057] like Figure 5 As shown, the fault detection logic 500 also includes a second OR tree 518 on the bits of the output 516 of the flip-flop 512. Since bit 5 of the output 516 of the flip-flop 512 is set to 1, the output of the second OR tree 518 is also 1. This output includes a perfect match indicator 522. The perfect match indicator 522 is fed to another AND gate 528. The output of the first OR tree 526 is inverted and used as another input to the AND gate 528. The output of the AND gate 528 indicates a fault 530. The fault detection logic 500 is configured to check the plausibility of the output 516 of the flip-flop 512 and detect a fault when the output indicates a perfect match, while all bits in the matching region within the output 516 of the flip-flop 512 are set to 0.

[0058] Figure 6 This diagram illustrates misalignment detection logic 600 according to an embodiment of the present invention, which includes logic for detecting a fault when the resulting bit vector is not aligned with the element size. For illustrative purposes only, it is assumed that the characters are encoded using a UTF-16 encoding mechanism, a non-ASCII transparent byte serialization encoding mechanism that can be big-endian (BE) or little-endian (LE), and thus defines the order of bytes in the encoding mechanism. Each character is encoded using 2 bytes. In this example, only the third byte of the exemplary resulting bit vector 310 is set to 1, and all other bytes are set to 0. A trigger 601 stores the resulting bit vector 310. At some point, the trigger 601 may withstand an SEU event 603. If at least one byte other than the first byte of each element is set to 1, a misalignment occurs in the resulting bit vector 310.

[0059] To detect this misalignment between the resulting bit vector 310 and its corresponding element size, misalignment detection logic 600 includes circuit elements for detecting element misalignment with an element size of at least a word or half-word. Misalignment detection logic 600 is configured to process the output 605 of flip-flop 601 storing the resulting bit vector 310. To process the output 605 of flip-flop 601 with half-word elements 604, misalignment detection logic 600 includes a first OR tree 608 on the corresponding second byte of each half-word. It is expected that only the first byte of each word will have a value of 1. The output of the first OR tree 608 is connected to the input of AND gate 614. Another input of AND gate 614 is an element size indicator 616. The element size indicator 616 includes a value indicating that each element of the resulting bit vector has a size of 2 bytes. The output of AND gate 614 indicates whether any misalignment exists with respect to the elements of the resulting bit vector 310 when each element has a half-word size. In this case, since the second byte of the first half-word element 604 is incorrectly set to 1, the output of OR tree 608 is 1. Therefore, AND gate 614 also produces 1, indicating the misalignment 618 of the resulting bit vector 310 with half-word elements.

[0060] The misalignment detection logic 600 may further include circuit elements for processing the output 605 of the flip-flop 601 storing the result bit vector 310 when each element of the vector 605 is a word (4 bytes). The misalignment detection logic 600 includes a second OR tree 606 on the second to fourth bytes of each word. The output of the second OR tree 606 is connected to the input of a second AND gate 610. Another input of the second AND gate 610 receives an element size indicator 612. The element size indicator 612 includes a value indicating that each element of the result bit vector 310 is 4 bytes long. The output of the second AND gate 610 indicates whether there is any misalignment with respect to the elements of the result bit vector 310 when each element has the size of a word. In this case, since the second and third bytes of the first word 602 are both set to 1, the output of the second OR tree 606 is 1. Therefore, the second AND gate 610 also produces 1, indicating a misalignment 620 in the result bit vector 310 with word elements. If at least one of AND gates 610 and 614 produces 1, then OR gate 622 compares the outputs of the corresponding AND gates 610 and 614 to indicate the corresponding misalignment error 624.

[0061] Figures 7A-7DThis is a diagram illustrating the logic for detecting faults by checking the plausibility of condition codes in a report according to an embodiment of the invention. According to an embodiment of the invention, the result generation logic can generate one of the condition codes and a result index indicating the index of the first match. Thus, for example, searching for the reference string "noon" within the target string "Abhighnoonoonnoo" returns a result index value equal to 6 (because the 6th character of the target string is the first match). For illustrative purposes only, exemplary values ​​of the condition codes are repeated here: CC0: no complete match, no partial match, and no EOS detected; CC1: no complete match, no partial match, but an implicit EOS termination was detected; CC2: a complete match found; CC3: a partial match found, but no complete match found.

[0062] Figure 7A The diagram illustrates logic 700 for detecting errors by comparing the reported condition code CC0 706 with the result index 702 and the zero detection vector 406 to check the plausibility of the reported condition code CC0 706. The value of condition code CC0 706 is stored in trigger 708. At some point, trigger 708 can withstand an SEU event 710. As a result of the occurrence of SEU event 710, the output 712 of trigger 708 can be toggled. In the case shown, a toggled value of 1 indicates no complete match, no partial match, and no EOS detected.

[0063] like Figure 7A As shown, the fault detection logic 700 also includes an OR gate 704 for processing the values ​​of the zero detection vector 406 and the result index 702 associated with the target string. When the vector size is a power of 2, it is sufficient to check the most significant bit (MSB) of the result index. If a match is found, the bit will be 0; if no match is found, the bit will be 1. The MSB of the result index 702 is fed into the OR gate 704, where the value of the MSB of the result index 702 is inverted. In this case, the value of the MSB of the result index 702 is inverted to 1, and the output of the OR gate 704 is 1. The second input of the OR gate 704 is connected to the least significant bit (LSB) of the zero detection vector 406. When an EOS is detected, this LSB is set to 1. Therefore, in both cases where a match is found or an EOS is detected, the output of the OR gate 704 is 1, and the output of the OR gate 704 is connected to one input of the AND gate 714. The output 712 of the SEU-affected flip-flop 708 is used as the other input of the AND gate 714. The output of the AND gate 714 indicates a fault 716. Fault detection logic 700 is configured to check the plausibility of CC0 condition code 706 in the report, and detects a fault when CC0 code is reported, regardless of whether the result generation logic detects a match or EOS.

[0064] Figure 7BThe logic 717 is shown to detect errors by comparing the condition code of the report with the result index 702 and the zero detection vector 406 to check the plausibility of the CC1 condition code 718 of the report. The value of the condition code CC1 718 is stored in a trigger 709. At some point, the trigger 709 can withstand a SEU event 711. As a result of the SEU event 711, the output 720 of the trigger 709 may be toggled. In the case shown, the toggled value 1 indicates that no complete match was detected, no partial match was detected, but an explicit EOS termination was detected.

[0065] like Figure 7B As shown, the fault detection logic 717 also includes an OR gate 724 for processing the values ​​of the zero detection vector 406 and the result index 702 associated with the target string. When the vector size is a power of 2, it is sufficient to check the most significant bit (MSB) of the result index. If a match is found, the bit will be 0; if no match is found, the bit will be 1. These MSBs of the result index 702 are fed to the OR gate 724, where they are inverted. In this case, the value of the MSB of the result index 702 is inverted to 1, and the output of the OR gate 724 is 1. The second inverted input of the OR gate 724 is connected to the least significant bit (LSB) of the zero detection vector 406. When no EOS is detected, this LSB is set to 0. Therefore, in both cases where a match is found or no EOS is detected, the output of the OR gate 724 is 1. The output of the OR gate 724 is connected to one input of the AND gate 726. The output 720 of the SEU-affected flip-flop 709 is used as the other input of the AND gate 726. The output of the AND gate 726 indicates a fault 728. Fault detection logic 717 is configured to check the plausibility of the reported CC1 condition code 718 and detect a fault when a CC1 code is reported, regardless of whether the result generation logic detects a match or not an EOS.

[0066] Figure 7C The diagram illustrates logic 729 for detecting errors by comparing the reported condition code CC2 732 with the result index 702 and the match type indicator. The value of condition code CC2 732 is stored in trigger 713. At some point, trigger 713 may experience a SEU event 715. As a result of the SEU event 715, the output 734 of trigger 713 may be toggled. In the case shown, the toggled value 1 indicates a perfect match was detected.

[0067] like Figure 7CAs shown, the fault detection logic 729 also includes an OR gate 736 for processing the values ​​of the match indicator 730 and the result index 702. In this embodiment, a match indicator with a value of 1 indicates that a complete match has been detected. The values ​​of the MSB of the result index 702 and the match indicator 730 are fed into the OR gate 736, where the value of the match indicator 730 is inverted. In this case, since both inputs have non-zero values, the output of the OR gate 736 is 1. The output of the OR gate 736 is connected to one input of the AND gate 738. The output 734 of the SEU-affected flip-flop 713 is used as the other input of the AND gate 738. The output of the AND gate 738 indicates a fault 740. The fault detection logic 729 is configured to check the plausibility of the reported CC2 condition code 732 and detect a fault when the CC2 code is reported, regardless of whether the result generation logic detects only a partial match or a non-match.

[0068] Figure 7D The logic 741 is shown to check the plausibility of a report's condition code to detect errors by comparing the report's CC3 condition code 742 with the result index 702 and the match type indicator. The value of condition code CC3 742 is stored in trigger 719. At some point, trigger 719 can withstand a SEU event 721. As a result of the occurring SEU event 721, the output 744 of trigger 719 may be toggled. In the case shown, the toggled value 1 indicates that a partial match was detected instead of a complete match.

[0069] like Figure 7D As shown, the fault detection logic 741 also includes an OR gate 746 to process the values ​​of the MSB of the match indicator 730 and the result index 702. In this embodiment, a match indicator with a value of 1 indicates that a perfect match has been detected. The values ​​of the MSB of the result index 702 and the match indicator 730 are fed into the OR gate 746. In this case, since both inputs have non-zero values, the output of the OR gate 746 is 1. The output of the OR gate 746 is connected to one input of the AND gate 748. The output 744 of the SEU-affected flip-flop 719 is used as the other input of the AND gate 748. The output of the AND gate 748 indicates a fault 750. The fault detection logic 741 is configured to check the plausibility of the reported CC3 condition code 742 and detect a fault when the CC3 code is reported, regardless of whether the result generation logic detects a perfect match or a mismatch.

[0070] Figure 8 This is a flowchart of a method 800 for detecting faults in a substring search operation according to an embodiment of the present invention, which uses a processor unit 200, each including a vector register having M vector elements. Each vector element is an n-bit element used to encode a character. The case L < M indicates that a substring search of L characters is performed.

[0071] In box 802, a reference string can be loaded into a first register of register 119, a target string can be loaded into a second register of register 119, and a comparison matrix 214 can be provided. The comparison matrix 214 can be used to check whether the target string includes all and / or only a part of the reference string.

[0072] In box 804, a resulting bit vector is generated. The resulting bit vector includes a bit value at a position marking the beginning of a substring of the target string that fully matches the string, and another bit value at a position marking the beginning of a substring of the target string that partially matches the string. The resulting bit vector may include indications of both partial and full matches occurring at the end of the target string. To generate the resulting bit vector, an expected intermediate result (which cannot distinguish between full and partial matches) can be combined with a correction mask that masks L-1 bits higher to suppress partial matches from the resulting bit vector.

[0073] In box 806, the result index for the first match is generated. In one embodiment, the result index is derived from the generated result bit vector. For example, searching for the reference string "noon" within the target string "abhighnoonoonnoo" returns a result index value equal to 6 (because the 6th bit of the target string is the first match).

[0074] In block 808, condition codes are generated. In one embodiment, condition codes may be generated by condition code generator 248. Figure 2 The condition code generator (shown in the diagram) is generated based on a combination of the following inputs: a target isolation mask 226, a correction mask 228, and an expected intermediate result based on an indication of a perfect match result 240. In one embodiment, the condition code generator 248 may include a decoder. The generated condition code 250 may be stored in a corresponding trigger 252.

[0075] In block 810, fault detection is performed by determining the plausibility of the resulting bit vector using fault detection logic 300, 400, 500 and misalignment detection logic 600 described herein. According to an embodiment of the invention, fault detection logic 300 is configured to check the plausibility of the resulting bit vector and detect a fault when the starting subset of the resulting bit vector differs from the subset of the first row of the comparator matrix. Additionally, fault detection logic 400 is configured to check the plausibility of the resulting bit vector and detect a fault when the output of the resulting bit vector indicates a match at a position beyond the implicit termination of the target string. Furthermore, fault detection logic 500 is configured to check the plausibility of the resulting bit vector and detect an error when the output of the resulting bit vector indicates a perfect match, while all bits in the matchable region within the resulting bit vector are set to 0. Misalignment detection logic 600 is configured to detect misalignment when the resulting bit vector is not aligned with the element size.

[0076] In block 812, fault detection is performed by determining the plausibility of condition codes using fault detection logic 700, 717, 729, and 741 described herein. According to embodiments of the invention, fault detection logic 700 is configured to check the plausibility of reported CC0 condition codes and detect a fault when a CC0 code is reported, regardless of whether the result generation logic detects a match or an EOS. Fault detection logic 717 is configured to check the plausibility of reported CC1 condition codes and detect a fault when a CC1 code is reported, regardless of whether the result generation logic detects a match or an EOS. Fault detection logic 729 is configured to check the plausibility of reported CC2 condition codes and detect a fault when a CC2 code is reported, regardless of whether the result generation logic detects a partial match or a non-match. Fault detection logic 741 is configured to check the plausibility of reported CC3 condition codes and detect a fault when a CC3 code is reported, regardless of whether the result generation logic detects a complete match or a non-match.

[0077] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0078] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0079] Computer-readable storage media can be tangible devices capable of retaining and storing instructions used by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CDROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0080] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0081] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(e.g., Smalltalk, C++, etc.) and conventional procedural programming languages ​​(e.g., the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information from the computer-readable program instructions.

[0082] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0083] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0084] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments of the invention may be devised without departing from the scope thereof. Various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are illustrated in the following description and drawings. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limiting in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. Furthermore, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process with additional steps or functionality not described in detail herein.

[0085] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such compositions, mixtures, processes, methods, articles, or apparatus.

[0086] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" can be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" can be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0087] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include a degree of error associated with a measurement of a specific quantity based on the equipment available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0088] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand them.

[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions mentioned in the blocks may not occur in the order indicated in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

Claims

1. A method for detecting faults in a substring search operation, the method comprising: A processor unit comprising vector registers, each having M vector elements, is used to provide an M×M matrix of comparators for comparing, character by character, elements of a reference string stored in a first vector register and elements of a target string stored in a second vector register, wherein the vector elements are n-bit elements used to encode characters. A result bit vector is generated using comparisons performed by the M×M matrix, the result bit vector indicating characters in the target string that completely match the reference string and characters in the target string that partially match the reference string; and Fault detection in the substring search operation is performed by utilizing the resulting bit vector.

2. The method according to claim 1, wherein, Generating the result bit vector further includes generating an index of the result bit vector based on the result bit vector for identifying a first match of the reference string within the target string, and generating a condition code based on the result bit vector indicating the type of the detected match.

3. The method according to claim 2, wherein, Performing the fault detection further includes comparing the resulting bit vector with the first row of the M×M matrix, and indicating an error if the resulting bit vector is different from a subset of the first row of the M×M matrix.

4. The method of claim 2, further comprising generating a zero-detection vector having values ​​indicating the terminating element of the target string, and comparing the resulting bit vector with the zero-detection vector, wherein, Performing the fault detection further includes indicating an error if the position of the bit indicating the matching bit in the result bit vector is higher than the position of the bit indicating the terminating element of the target string in the zero detection vector.

5. The method of claim 2, further comprising determining a matchable region within the target string, and comparing the resulting bit vector with the matchable region, wherein, Performing the fault detection further includes indicating an error when the condition code indicates a complete match and all bits of the matchable region within the target string are set to 0.

6. The method according to claim 2, wherein, Performing the fault detection further includes indicating an error in the event that the resulting bit vector and vector elements are not aligned.

7. The method according to claim 6, wherein, Misalignment is detected when at least one byte, which is different from the first byte of the vector element of the resulting bit vector, is set to 1.

8. The method of claim 2, further comprising generating a zero-detection vector having values ​​indicating the terminating element of the target string, comparing the condition code with the generated index, and comparing the condition code with the zero-detection vector, wherein, Performing the fault detection further includes (a) indicating an error if the condition code indicates (1) no complete string match, (2) no partial match, and (3) no terminating element is detected, or (b) indicating an error if the index generated by (1) indicates the first match or if the zero detection vector of (2) has a bit value set to 1 indicating the terminating element of the target string.

9. The method according to claim 8, wherein, Performing the fault detection further includes (a) indicating an error when the condition code indicates that no complete string match was detected and no partial match was detected and indicates that the terminating element has been detected, or (b) indicating an error when the resulting index indicates that all bits of the first match or the zero detection vector are set to 0 to indicate that the terminating element of the target string has not been detected.

10. The method of claim 8, further comprising determining a matching type based on the resulting bit vector, comparing the condition code with the generated index, and comparing the condition code with the determined matching type, wherein, Performing the fault detection further includes indicating an error if (a) the condition code indicates that a full string match is detected, or (b) the index generated in (1) indicates that no match is detected, or (2) the resulting bit vector indicates that a partial match is detected.

11. The method according to claim 10, wherein, Performing the fault detection further includes indicating an error if (a) the condition code indicates that a partial match was detected but no complete string match was detected, or (b) the index generated in (1) indicates that no match was detected, or (2) the result bit vector indicates that a complete match was detected.

12. A processor unit for detecting faults in a substring search operation, the processor unit comprising: Multiple vector registers, each vector register having M vector elements, where each vector element is an n-bit element used to encode a character; The comparator is an M×M matrix used to perform character-by-character comparisons between the elements of the first register storing the reference string and the elements of the second register storing the target string in the plurality of vector registers. The result generation logic generates a result bit vector indicating characters in the target string that completely match the reference string and characters in the target string that partially match the reference string; and Fault detection logic is used to perform fault detection in the substring search operation by utilizing the resulting bit vector.

13. The processor unit according to claim 12, wherein, Generating the result bit vector further includes generating an index of the result bit vector based on the result bit vector for identifying a first match of the reference string within the target string, and generating a condition code based on the result bit vector indicating the type of the detected match.

14. The processor unit according to claim 13, wherein, Performing the fault detection further includes comparing the resulting bit vector with the first row of the M×M matrix, and indicating an error if the resulting bit vector is different from a subset of the first row of the M×M matrix.

15. The processor unit of claim 13, further comprising zero-detection logic for generating a zero-detection vector having a value indicating the terminating element of the target string, wherein, Performing the fault detection further includes indicating an error if the position of the bit indicating the matching bit in the result bit vector is higher than the position of the bit indicating the terminating element of the target string in the zero detection vector.

16. The processor unit according to claim 13, wherein, The fault detection logic determines a matchable region within the target string and compares the resulting bit vector with the matchable region. Furthermore, performing the fault detection includes indicating an error if the condition code indicates a complete match and all bits of the matchable region within the target string are set to 0.

17. The processor unit according to claim 13, wherein, Performing fault detection further includes indicating an error in the event that the resulting bit vector and vector elements are not aligned.

18. The processor unit according to claim 17, wherein, Misalignment is detected when at least one byte, which is different from the first byte of the vector element of the resulting bit vector, is set to 1.

19. The processor unit of claim 13, further comprising zero-detection logic for generating a zero-detection vector having a value indicating the terminating element of the target string, wherein, Performing the fault detection further includes (a) indicating an error if the condition code indicates that a complete string match, a partial match, or a terminating element was not detected, or (b) indicating an error if the index generated in (1) indicates the first match, or (2) the zero detection vector has a bit value set to 1 indicating the terminating element of the target string.

20. A computer program product for detecting faults in a substring search operation, the computer program product comprising program instructions executable by a processor to cause the processor to perform a method comprising: A processor unit comprising vector registers, each having M vector elements, is used to provide an M×M matrix for a comparator, used to perform a character-by-character comparison between elements of a reference string stored in a first vector register and elements of a target string stored in a second vector register. Vector elements are n-bit elements used to encode characters; The comparisons performed by the M×M matrix are used to produce a result bit vector, which indicates characters in the target string that completely match the reference string and characters in the target string that partially match the reference string. as well as Fault detection in the substring search operation is performed by utilizing the resulting bit vector.

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