Memory with System ECC

Abstract

A method and apparatus for a system error correction code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host when performing a computing function, and is configured to provide an error correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

Description

[0001] Claiming priority under 35 U.S.C. § 119

[0002] This patent application claims priority to U.S. Non - Provisional Application No. 16 / 944,110, titled "MEMORY WITH SYSTEM ECC", filed on July 30, 2020, and claims priority to U.S. Provisional Application Serial No. 62 / 894,625, titled "MEMORY WITH SYSTEM ECC", filed on August 30, 2019, the entire contents of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present disclosure generally relates to methods and apparatuses for memories with enhanced error detection and / or correction schemes, and more particularly to memories using a system error - detection code (ECC). Background Art

[0004] A computing device (e.g., a laptop computer, a mobile phone, etc.) may include one or more processors to perform various computing functions, such as telephone, wireless data access, and camera / video functions, etc. A memory is an important component of the computing device. The processor may be coupled to the memory to perform the above - mentioned computing functions. For example, the processor may extract instructions from the memory to perform computing functions and / or store temporary data in the memory for processing these computing functions, etc. Summary of the Invention

[0005] This summary identifies features of some example aspects and is not an exclusive or exhaustive description of the disclosed subject matter. Additional features and aspects are described when reading the following detailed description and viewing the drawings that form a part thereof, and will become apparent to those skilled in the art.

[0006] An apparatus according to at least one embodiment includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to: when performing a computing function, provide the data stored in the memory array to the host, and is configured to: provide an error - correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

[0007] Another apparatus according to at least one embodiment includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to: receive data from the host when performing a computing function, store the data in the memory array, and receive an ECC associated with the data from the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

[0008] Another device according to at least one embodiment includes a memory configured to communicate with a host. The memory includes a memory array configured to store data and an ECC associated with the data. The memory is configured to: provide the data when performing a computing function, and provide the ECC stored in the memory array to the host via a read ECC signal connection. The read ECC signal connection is configured to: in a write operation, provide a data mask from the host to the memory.

[0009] Another device according to at least one embodiment includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to: receive data from the host when performing a computing function, receive an ECC associated with the data from the host via a write ECC signal connection, and store the data and the ECC in the memory array. The write ECC signal connection is configured to: in a read operation, provide a data strobe to the host.

[0010] Another device according to at least one embodiment includes a host configured to communicate with a memory. The host is further configured to: receive data from the memory when performing a computing function, and receive an ECC associated with the data from the memory via a read ECC signal connection. The data and the ECC are stored in the memory array of the memory. The read ECC signal connection is configured to: in a write operation, provide a data mask from the host to the memory.

[0011] Another device according to at least one embodiment includes a host configured to communicate with a memory. The host is further configured to: provide data to the memory when performing a computing function, and provide an ECC associated with the data to the memory array of the memory via a write ECC signal connection. The write ECC signal connection is configured to: in a read operation, provide a data strobe to the host.

[0012] A method for operating an ECC function is presented. The method includes: when performing a computing function, providing, by the memory, data stored in the memory array of the memory to the host. The method further includes: providing, by the memory, an error correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

[0013] Another method for the ECC function of an operating system is proposed. The method includes: when performing a computing function, the memory receives data from the host. The method further includes: the memory stores the data into a memory array of the memory. The method further includes: the memory receives ECC associated with the data from the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

[0014] Another method for the ECC function of an operating system is proposed. The method includes: when performing a computing function, the memory provides data stored in a memory array of the memory to the host. The method further includes: when performing a computing function, the memory provides ECC associated with the data and stored in the memory array to the host via a read ECC signal connection. The read ECC signal connection is configured to: in a write operation, provide a data mask from the host to the memory.

[0015] Another method for the ECC function of an operating system is proposed. The method includes: when performing a computing function, the host receives data from the memory. The method further includes: the host receives ECC associated with the data from the memory via a read ECC signal connection. The data and the ECC are stored in a memory array of the memory. The read ECC signal connection is configured to: in a write operation, provide a data mask from the host to the memory.

[0016] Another method for the ECC function of an operating system is proposed. The method includes: when performing a computing function, the host provides data to the memory. The method further includes: the host provides ECC associated with the data to a memory array of the memory via a write ECC signal connection. The write ECC signal connection is configured to: in a read operation, provide a data strobe to the host. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Aspects of the apparatus and method will now be presented in the detailed description by way of example and not limitation with reference to the accompanying drawings, in which:

[0018] Figure 1 An apparatus is illustrated that includes a host, a memory, and a channel coupling the host and the memory.

[0019] Figure 2 An illustration shows Figure 1 another representation of an apparatus having a host, a memory, and a channel.

[0020] Figure 3 An illustration shows Figure 1 another embodiment of an apparatus according to certain aspects of the present disclosure.

[0021] Figure 4Illustrates the waveform of the system ECC function of the device in a write operation according to certain aspects of the present disclosure Figure 3 of the device

[0022] Figure 5 Illustrates the waveform of another system ECC function of the device in a write operation according to certain aspects of the present disclosure Figure 3 of the device

[0023] Figure 6 Illustrates the waveform of the system ECC function of the device in a read operation according to certain aspects of the present disclosure Figure 3 of the device

[0024] Figure 7 Illustrates the waveform of another system ECC function of the device in a read operation according to certain aspects of the present disclosure Figure 3 of the device

[0025] Figure 8 Illustrates the data structure of another embodiment of the device according to certain aspects of the present disclosure Figure 3 of the device

[0026] Figure 9 Illustrates an embodiment of the mode register of the device according to certain aspects of the present disclosure Figure 3 of the device

[0027] Figure 10 Illustrates a method for operating the system ECC function of the device according to certain aspects of the present disclosure Figure 3 of the device

[0028] Figure 11 Illustrates another method for operating the system ECC function of the device according to certain aspects of the present disclosure Figure 3 of the device

[0029] Figure 12 Illustrates another method for operating the system ECC function of the device according to certain aspects of the present disclosure Figure 3 of the device

[0030] Figure 13 Illustrates another method for operating the system ECC function of the device according to certain aspects of the present disclosure Figure 3 of the device

[0031] Figure 14 Illustrates another method for operating the system ECC function of the device according to certain aspects of the present disclosure Figure 3 of the device

[0032] Figure 15 Illustrates another method for operating the system ECC function of the device according to certain aspects of the present disclosure Figure 3Another method for the system ECC function of the device. Detailed implementation

[0033] The detailed description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details for providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0034] As used herein, the verb "couple" in various tenses of the term "coupled to" may mean that element A is directly connected to element B, or that other elements may be connected between elements A and B (i.e., element A is indirectly connected to element B) to operate certain intended functions. In the case of electrical components, the term "coupled to" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and B (and any components electrically connected therebetween). In some examples, the term "coupled to" means the transfer of electrical energy between elements A and B to operate certain intended functions.

[0035] In some examples, the term "electrically connected" means having current or being configured to have current flow between elements A and B. For example, in addition to wires, traces, or other conductive materials and components, elements A and B may also be connected via resistors, transistors, or inductors. Additionally, for radio frequency functions, elements A and B may be "electrically connected" via capacitors.

[0036] The terms "first", "second", "third", etc. are employed for ease of reference and may not have a substantial meaning. Similarly, for ease of reference, names of components / modules may be employed and may not limit the components / modules. For example, such non-restrictive names may include "Read ECC" signal connection and "Write ECC" signal connection. The modules and components presented in this disclosure may be implemented in hardware, software, or a combination of hardware and software. In some examples, the modules and components presented in this disclosure may be implemented only in hardware.

[0037] The term "bus system" may stipulate that elements coupled to the "bus system" may exchange information directly or indirectly between them. In this way, the "bus system" may encompass multiple physical connections as well as intermediate levels such as buffers, latches, registers, etc. Modules may be implemented in hardware, software, or a combination of hardware and software.

[0038] The term error correction code (ECC or ECCs) in the present disclosure may refer to an error detection, error correction, or error detection and correction code. ECC is not limited to a specific type of coding. In some examples, ECC may include Hamming codes and / or parity codes.

[0039] The memory in the present disclosure may be embedded within a processor on a semiconductor die or be part of a different semiconductor die. The memory may be of various types. For example, the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc.

[0040] In the present disclosure, methods and apparatuses are presented by way of non-limiting examples of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, an LPDDR memory operating according to the LPDDR specification promulgated by the Joint Electron Device Engineering Council (JEDEC). One such LPDDR specification may be LPDDR5.

[0041] As the demand for computing devices to perform more functions at an increasing speed grows, the errors in the data stored in the memory may also increase. As the amount of data stored in the memory and transferred between blocks increases, the errors may increase. An example of an error correction code (ECC) for a link between a host and a memory is provided in U.S. Patent No. 10,331,517, which has been assigned to the assignee of the present application, and the entire content thereof is hereby expressly incorporated by reference. A solution for improving error detection / correction when accessing the memory without overburdening the host or the memory is beneficial for improving system performance.

[0042] In addition to the link ECC provided in U.S. Patent No. 10,331,517, other ECC schemes may also be utilized. For example, within the memory, the memory may utilize an array ECC that detects and / or corrects errors within the memory. A host coupled to the memory may separately utilize a different memory for ECC at the system level (system ECC). In some examples, an end-to-end system ECC may be implemented in the host by adding a large density on-chip SRAM to store online ECC parity bits for certain data to enhance overall data reliability. However, in terms of the overall system cost, such a high density on-chip SRAM is very expensive, and the high density SRAM is vulnerable to soft errors associated with SRAM cells.

[0043] In the present disclosure, system ECC parity bits are generated inside the host and transmitted between the host and the memory device via RDQS_t (in a write operation) and DM (in a read operation). The system parity bits can be stored together with the given data into the DRAM cell array, so that ECC protection provides a unified and consistent way to reduce the overall system cost by removing the on-chip SRAM and achieve better performance without the need for a separate memory link ECC.

[0044] The present disclosure thus provides a simplified and effective ECC scheme to implement system ECC by sharing some resources of the link ECC. In this way, the overall system cost can be reduced and the performance can be improved.

[0045] Figure 1 FIG. illustrates an apparatus 100 that includes a host 110, a memory 150, and a channel 190 that couples the host 110 and the memory 150. The apparatus 100 can be, for example, a device among the following: a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop, a mobile phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, or an augmented reality (AR) system, etc. The host 110 can include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). The host 110 can be configured to: when performing a computing function, be coupled to and communicate with the memory 150 (e.g., memory 150-1 to 150-4) via the channel 190 (e.g., channels 190-1 to 190-4), where the computing function can be one of data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc. For example, the memory 150 can store instructions or data for the host to perform the above computing functions.

[0046] The host 110 may include a memory controller 130, and the memory controller 130 may include controller PHY modules 134-1 to 134-4. Each of the controller PHY modules 134-1 to 134-4 may be coupled to a corresponding memory among memories 150-1 to 150-4 via a corresponding channel 190-1. For ease of reference, reads and writes are referenced from the perspective of the host 110. For example, in a read operation, the host 110 may receive stored data from the memory 150 via the channel 190. In a write operation, the host 110 may provide data to be written to the memory 150 via the channel 190 for storage. The memory controller 130 may be configured to control various aspects of communication to and from the memory 150, such as the logical layer. The controller PHY module 134 may be configured to control the electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) of the signals provided or received on the channel 190.

[0047] In some examples, the memory 150 may be LPDDR DRAM (e.g., LPDDR5). The host 110, the memory 150, and / or the channel 190 may operate according to the LPDDR (e.g., LPDDR5) specification. In some examples, each channel in the channel 190 may include 16 bits of data (e.g., 16 DQs). In some examples, each channel in the channel 190 may operate on 32 bits of data. In Figure 1 which, four channels are shown. In some examples, the device 100 may include 8 or 16 channels.

[0048] The channel 190 is shown in Figure 2 greater specificity. Figure 2 Illustrated is another representation of the device with the host 110, the memory 150, and the channel 190 having Figure 1 The channel 190 may include a data clock (e.g., WCK) used when providing data to the corresponding memory 150 and a read data strobe (e.g., RDQS) used when receiving data from the corresponding memory 150, on a per-byte basis. The channel 190 may also include data mask (e.g., DM, sometimes referred to as DMI to indicate the various functions performed by the signal connection) signaling, which is used to mask a portion of the data in a write operation. The channel 190 may also include command and address (e.g., CA) and an associated CA clock to provide commands (e.g., read or write commands) to the corresponding memory 150.

[0049] The host 110 may include at least one processor 120, and the at least one processor 120 may include a CPU 122, a GPU 123, and / or an NPU 124. The host 110 may further include a memory controller 130 having a controller PHY module 134. When performing various computing functions, the memory controller 130 may be coupled to the at least one processor 120 via a bus system 115. The host 110 may be configured to perform multiple ECC functions. To support the system ECC function, the host 110 may include a system ECC memory 137. The memory controller 130 may be coupled to the system ECC memory 137 via a bus system 116. The memory controller 130 may further include a system ECC decoder 131 and a system ECC encoder 132. The controller PHY module 134 may include a link ECC decoder 135 and a link ECC encoder 136.

[0050] The apparatus 100 may implement a system ECC function to detect / correct errors that occur during the execution of computing functions (e.g., by operating with the at least one processor 120). The system ECC function may be applicable to applications with low fault tolerance, such as automotive applications. In some examples, the system ECC encoder 132 may generate a system ECC for a data block. The memory controller 130 may send the data block together with the system ECC to other modules, such as the at least one processor 120 and / or the memory 150. For example, the system ECC may be sent to the memory 150, and the memory 150 may store the system ECC in the same manner as the data and does not perform an ECC function based on the system ECC. In some examples, the memory controller 130 may receive a data block and an associated system ECC from, for example, the at least one processor 120 and / or the memory 150. Then the memory controller 130 may use the system ECC to detect / correct errors in the data block.

[0051] The host 110 is coupled to the memory 150 via a channel 190, and the channel 190 is illustrated for data bytes DQ[0:7]. The channel 190 and the signaling between the host 110 and the memory 150 can be implemented according to the JEDEC DRAM specification (e.g., LPDDR5). As illustrated, the channel 190 includes signal connections for DQ, a read data strobe (RDQS), a data mask (DM), a data clock (WCK), command and address (CA), and a command and address clock (CK). The host 110 can use the read data strobe RDQS to strobe (e.g., clock) data in a read operation to receive data on DQ. The memory 150 can use the data mask DM to mask a portion of the data to prevent writing during a write operation. The memory 150 can use the data clock WCK to sample the data on DQ for a write operation. The memory 150 can use the command and address clock CK to clock (e.g., receive) CA. The signal connections for each signaling can include pins at the host 110, pins at the memory 150, and one or more conductive traces that electrically connect the pins.

[0052] The memory 150 can include a memory I / O module 160 (e.g., PHY layer), and the memory I / O module 160 is configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on the memory. For example, the memory I / O module 160 can be configured to capture (e.g., sample) data, commands, and addresses from the host 110 via the channel 190 and output data to the host 110 via the channel 190. The memory I / O module 160 can include a memory link ECC decoder 161 and a memory link ECC encoder 162.

[0053] The memory 150 can further include a memory array 175, and the memory array 175 can include a plurality of memory cells (e.g., DRAM memory cells) that store data (e.g., generally information). The host 110 can read data stored in the memory array 175 via the channel 190 and write data to the memory array 175. In addition, the memory array 175 can be configured to store ECC, such as array ECC, which is associated with the stored data. For example, a data block (e.g., word) can be associated with the array ECC via a shared address. For example, reading (or writing) the shared address at the memory array 175 can read out (or write) the data block at that address and the array ECC associated with the data block.

[0054] The memory 150 may also include an array ECC decoder 171 and an array ECC encoder 172 to support the array ECC function. The array ECC decoder 171 may be coupled to the memory I / O module 160 via node 163 and to the memory array 175 via node 173. The array ECC encoder 172 may be coupled to the memory I / O module 160 via node 164 and to the memory array 175 via node 174. In some examples, the array ECC function may detect / correct errors that occur in the data stored in the memory array 175. As semiconductor processes advance, memory cells are pushed to their physical limits, and errors in stored data may occur even when the data is not being accessed. Thus, the array ECC function may be implemented to detect and / or correct those errors in storage. In some examples, the host 110 may not access or even be aware of the array function.

[0055] In some examples, the array ECC function may be encoded (by the array ECC encoder 172) and decoded (by the array ECC decoder 171) within the memory 150. In a write operation, write data (e.g., received from the host 110 via channel 190) may be provided to the array ECC encoder 172 via node 163. The array ECC encoder 172 may generate an array ECC based on the write data. The write data and the associated array ECC may be written to the memory array 175 via node 173. The write data and the associated array ECC may be stored in the memory array 175 and share a common address. Thus, the write data and the associated array ECC may be accessed (read or written) via the shared common address.

[0056] In a read operation, the data stored in the memory array 175 and the associated array ECC may be provided to the array ECC decoder 171 via node 174. The array ECC decoder 171 may use the array ECC to detect / correct the data. The corrected data may be provided to the memory I / O module 160 as read data via node 164. The memory I / O module 160 may provide the read data to the host 110 via channel 190. Thus, the array function may be transparent to the host 110.

[0057] In addition, the device 100 may include a link ECC function to detect / correct errors caused by data transmission in the channel 190. For example, in a write operation, the link ECC encoder 136 may generate a link ECC associated with a data block (e.g., write data) to be written into the memory 150. The host 110 may provide the write data to the memory 150 via a DQ signal connection, and provide the link ECC to the memory 150 via a read data strobe RDQS signal connection. At the memory 150, the memory link ECC decoder 161 may use the link ECC to detect / correct errors in the write data. When the link ECC function is resolved at the memory I / O module 160, the link ECC may not be stored in the memory array 175.

[0058] In a read operation, the memory link ECC encoder 162 may receive data (e.g., read data) stored in the memory array 175 and generate a link ECC associated with the read data (e.g., via the node 174, the array ECC decoder 171, and the node 164). The memory I / O module 160 may provide the read data to the host 110 via the signal connection of DQ and provide the link ECC to the host 110 via the signal connection of the data mask DM. At the host 110, the link ECC decoder 135 may use the link ECC to detect / correct errors in the read data.

[0059] As described above, the device 100 can operate multiple layers of ECC functions, and each scheme can be operated independently of other schemes. This multi-layer scheme causes inefficiency. Certain aspects of the present disclosure provide a system ECC function that shares a signal connection with the link ECC function. In this way, system complexity is reduced and therefore system cost is reduced.

[0060] Figure 3 The present invention illustrates some aspects of the present invention. Figure 1 Another embodiment of the device 100. Figure 3 , the device 100_s is shown to have various functional blocks and is configured to support novel system ECC functions. The device 100_s may include a host 110_s, which is configured to be coupled to and communicate with a memory 150_s via a channel 190_s when performing various computing functions, such as one of data processing, data communication, graphic display, camera, AR or VR rendering, image processing, neural processing, etc. For example, the memory 150_s may store instructions or data for the host to perform the above-mentioned computing functions.

[0061] The host 110_s may include at least one processor 120, and the at least one processor 120 may include a CPU 122, a GPU 123, and / or an NPU 124 (see Figure 2 ). The host 110_s may further include a memory controller 130_s having a controller PHY module 134_s. When performing various computing functions, the memory controller 130_s may be coupled to the at least one processor 120 via a bus system 115. The controller PHY module 134_s may be configured to control the electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) of signals provided or received on the channel 190_s.

[0062] The host 110_s may be configured to: implement a system ECC function using the memory 150_s via the channel 190_s. For example, via a signal connection of a data mask DM and / or a read data strobe RDQS for data on the channel 190_s. For the system ECC function, the memory controller 130_s may include a system ECC decoder 131 and a system ECC encoder 132. When performing a computing function, the system ECC encoder 132 of the memory controller 130_s may generate a system ECC code for a data block and provide the data block and the system ECC code to the at least one processor 120 via the bus system 115. The memory controller 130_s may receive a data block and an associated system ECC code from the at least one processor 120 via the bus system 115. The system ECC decoder 131 may use the system ECC code to detect and / or correct one or more errors in the data block.

[0063] The memory 150_s may be configured to support the system ECC function. Since the device 100_s uses the memory 150_s for the system ECC function, a system ECC memory 137 ( Figure 2 ) is not required. The memory 150_s may include a memory array 175_s configured to store data, array ECC, and system ECC. For example, a data block may share the same address with the array ECC and / or the system ECC. The data block and the array ECC or the system ECC may be accessed (read or written) using the same address. The memory 150_s may further include a mode register 179 configured to indicate (e.g., to the host 110_s) that the memory 150_s is configured to support the system ECC function.

[0064] Device 100_s is also configured to implement system ECC functionality using memory 150_s. In some examples, the system ECC functionality may support end-to-end ECC functionality. For example, the system ECC functionality may be implemented for data from at least one processor 120 to memory 150_s and / or data from memory 150_s to at least one processor 120. In some examples, host 110_s may provide or receive system ECC codes from memory 150_s via a signal connection of channel 190_s (a signal connection shared with the link ECC functionality).

[0065] Device 100_s may support ECC functionality and link ECC functionality (e.g., at different times or different operations). Memory I / O module 160 may optionally include a memory link ECC decoder 161 and a memory link ECC encoder 162 (see Figure 2 ). Controller PHY module 134_s may optionally include a link ECC decoder 135 and a link ECC encoder 136. The link ECC functionality may use the data mask DM signal connection to transfer link ECC from memory 150_s to host 110_s during a read operation and use the read strobe RDQS_t signal connection to transfer link ECC from host 110_s to memory 150_s during a read operation.

[0066] Figure 4 illustrates a waveform of the system ECC functionality of device 100_s according to certain aspects of the present disclosure Figure 3 during a write operation. The command and address clock CK may be a differential signal having CK_t and CK_c signal connections. The data clock WCK may be a differential signal having WCK0_t and WCK0_c signal connections. The read data strobe RDQS may be a differential signal having RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), a CAS command may be provided by host 110_s for a write operation to memory 150_s. At T1, a write command may be provided by host 110_s to memory 150_s.

[0067] After a write latency (WL) in a time period, host 110_s may switch data clocks WCK0_t and WCK0_c on the DQ signal connection to provide timing to memory 150_s for receiving data for writing. At Tc0 - Tc2, memory 150_s may serially receive 16 - bit data on each of the DQ[0:7] signal connections, timed by data clocks WCK0_t and WCK0_c. Memory 150_s may serially receive a 16 - bit data mask DM0 (e.g., based on data clocks WCK0_t and WCK0_c) to mask certain portions of the data received from the write operation. In some examples, 16 bytes of data and a 16 - bit data mask DM0 may be received by memory 150_s, where each bit of the data mask DM0 masks a corresponding byte of the received data.

[0068] At Tc0 - Tc2, memory 150_s may receive, e.g., 16 - bit ECC on the RDQS_t signal connection based on data clocks WCK0_t and WCK0_c. In a read operation, the RDQS_t signal connection may be configured to provide a read data strobe (RDQS) from memory 150_s to host 110_s. In some examples, the ECC received by memory 150_s may be a link ECC. Refer to Figure 3 , memory link ECC decoder 161 may utilize the received 16 - bit ECC to detect and / or correct errors in the received 16 - byte data. As a link ECC, the received 16 - bit ECC may not be stored in memory array 175_s (see Figure 3 ).

[0069] In some examples, the received ECC may be a system ECC. Device 100_s may be configured to operate link ECC functions and system ECC functions at different times / configurations via a shared signal connection (e.g., data mask DM and / or read data strobe RDQS). Additionally, device 100_s may also be configured to perform an array ECC function. Refer to Figure 3 , memory 150_s may be configured to provide 16 bytes of data and 16 - bit system ECC to array ECC encoder 172 via node 163. Array ECC encoder 172 may be configured to: generate an array ECC based on the 16 - byte data and / or 16 - bit system ECC, and provide the data, system ECC, and array ECC to memory array 175_s for storage (via node 173). Memory array 175_s may be configured to store (e.g., write) the received data, received system ECC, and array ECC from array ECC encoder 172.

[0070] Figure 5illustrates the waveform of another system ECC function of the device 100_s according to certain aspects of the present disclosure Figure 3 during a write operation. In some examples, different ECC encoding / decoding protocols may require fewer bits of ECC for 16-byte data during a write operation. In this example, 12-bit ECC is provided to the memory 150_s via the signal connection of the read data strobe RDQS_t. Additionally, the host 110_s may be configured to provide 4-bit additional data information of the data on the signal connection of the read data strobe RDQS_t during a write operation. For example, the additional data information may indicate the data type for writing or using the information (e.g., data attributes, cacheable or non-cacheable, etc.).

[0071] Figure 6 illustrates the waveform of the system ECC function of the device 100_s according to certain aspects of the present disclosure Figure 3 during a read operation. The command and address clock CK may be a differential signal having CK_t and CK_c signal connections. The data clock WCK may be a differential signal having WCK0_t and WCK0_c signal connections. The read data strobe RDQS may be a differential signal having RDQS_t and RDQS_c signal connections. The data mask is labeled as DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), a CAS command may be provided by the host 110_s for a read operation of the memory 150_s. At T1, a read command may be provided by the host 110_s to the memory 150_s.

[0072] After a period of read latency (RL), the memory 150_s may switch the read data strobe RDQS on the DQ signal connection to provide timing to the host 110_s to receive data for the read operation. At Tc0 - Tc2, the host 110_s may serially receive 16-bit data on each of the DQ[0:7] signal connections and is timed by the read data strobe signals RDQS_t and RDQS_c. Thus, in this example, 16-byte data is received by host_110.

[0073] At Tc0 - Tc2, the host 110_s may receive, for example, 16-bit ECC on the data mask DM0 signal connection based on the read data strobe RDQS_t and RDQS_c (e.g., timed by them). During a write operation, the DM signal connection may be configured to provide a data mask from the host 110_s to the memory 150_s. In some examples, the ECC received by the host 110_s may be link ECC. Refer to Figure 3, the memory link ECC encoder 162 may generate a 16-bit link ECC based on 16 bytes of data stored in the memory array 175_s (and provided to the host 110_s in a read operation). As the link ECC, the 16-bit ECC may not be stored in the memory array 175_s (see Figure 3 ).

[0074] In some examples, the ECC received by the host 110_s may be a system ECC. The device 100 may be configured to operate the link ECC and the system ECC at different times / configurations via a shared signal connection (eg, data mask DM and / or read data strobe RDQS). Figure 3 , the memory 150_s may be configured to provide 16 bytes of data, associated array ECC, and associated system ECC (all stored in the memory array 175_s) to the array ECC decoder 171 via the node 174. The array ECC decoder 171 may be configured to detect / correct errors in the 16 bytes of data and / or the system ECC based on the array ECC. The array ECC decoder 171 may be configured to output the corrected 16 bytes of data and / or the system ECC to the memory I / O module 160 and the host 110_s in a read operation.

[0075] Figure 7 The present disclosure illustrates certain aspects of the Figure 3 Another system ECC function of the device 100_s is in a waveform in a read operation. In some examples, different ECC encoding / decoding protocols may require fewer bits in a read operation for 16 bytes of data output by the memory 150_s. In this example, the 12-bit ECC is provided to the host 110_s via the signal connection of the data mask DM. In addition, the memory 150_s can be configured to provide 4 bits of additional data information on the signal connection of the data mask DM0. For example, the additional data information can indicate the type of data (e.g., cacheable or non-cacheable) used to write or use information. For example, additional information can be provided by the host 110_s and associated with the data in a read operation and stored in the memory 150_s before the read operation.

[0076] In some examples, the additional information may include additional ECC information. The additional ECC information may be based on, for example, the array ECC or information about the array ECC. For example, the additional ECC information may indicate the number of times data in a read operation has been corrected by the array ECC or include errors that have not been corrected by the array ECC. In some examples, the host_110 may utilize the additional ECC information and the system ECC to further detect / correct errors in the data received in the read operation, rather than using the system ECC alone.

[0077] Figure 8 The present invention illustrates some aspects of the present invention. Figure 3 In some examples, channel 190_s may be x16 (two bytes of DQ; for clarity, Figure 3 Only the lower byte of DQ is shown). Figure 8 The read / write of burst length 16 is illustrated. Therefore, a total of 32 bytes of data are read or written in the figure. A corresponding data mask DM (DM0 and DM1) and a read data strobe RDQS_t (RDQS0_t and RDQS1_t) can be provided for each byte of DQ. For example, a data mask DM0 can be provided for DQ[0:7], and a data mask DM1 can be provided for DQ[8:15] to mask certain parts of the write data in a write operation. A read data strobe RDQS0_t can be provided for DQ[0:7], and a read data strobe RDQS1_t can be provided for DQ[8:15] to provide timing for reading data in a read operation.

[0078] In some examples, the system ECC functions may be implemented and / or distributed on byte boundaries to improve floorplanning in the memory 150_s. For example, in some ECC functions, 12 bits of ECC may be sufficient to read or write 32 bytes of data. The 12 bits of ECC may be conveyed by the data masks DM0 and DM1 (provided by the memory 150_s to the host 110_s) in a read operation and by the read data strobes RDQS0_t and RDQS1_t (provided by the host 110_s to the memory 150_s) in a write operation. Figure 8 As shown in FIG. 1 , for each byte of data read or written, 6 bits of ECC may be transmitted in the first 6 cycles of the burst. For the remaining 10 cycles, data masks DM0 and DM1 and / or read data select signals RDQS0_t and RDQS1_t may be utilized to transmit additional information, such as additional ECC information and / or additional data information (see FIG. 1 ). Figure 5 and Figure 7 ).

[0079] Figure 9 The present invention illustrates some aspects of the present invention. Figure 3An embodiment of the mode register 179 of the apparatus 100_s. As illustrated at 910, the mode register 179 may include an 8-bit operand OP[7:0], where OP[7:4] may be reserved. OP[3:0] may indicate system ECC support and configuration (SESC). As illustrated at 920, the mode register 179 may be read-only. For example, the memory 150_s (e.g., by its manufacturer) may set the mode register 179 regarding SESC independently of the host 110_s. The host 110_s may be configured to read the mode register 179 to learn, for example, whether the memory 150_s supports system ECC, the size of the system ECC, and / or additional information transmitted in the system ECC (see Figure 5 and Figure 7 ). However, the host 110_s may not write to the mode register 179.

[0080] For example, the mode register 179 may indicate whether system ECC is supported. For example, OP[3:0] at 0000 may indicate that system ECC is not supported. OP[3:0] may also indicate the size of the system ECC and the size of the additional information (e.g., based on the number per DQ and / or the number per burst length). For example, OP[3:0] at 0010 may indicate 24-bit ECC and 8-bit additional information per x16 channel and a burst length (BL) of 16. The additional information may be additional data information and / or additional ECC information. For example, the additional ECC information may be array ECC decoding information (AED). For example, AED may be the array ECC of the read or written data and / or its system ECC. In some examples, AED may be information related to the array ECC function, such as the number of times the read or written data has been corrected by the array ECC function or whether the read or correct data includes an error that has not been corrected by the array ECC function.

[0081] Figure 10 Illustrated is a method for operating the system ECC function of the apparatus 100_s according to certain aspects of the present disclosure. For example, Figure 3 the operation of Figure 10 may be implemented by the apparatus 100 or 100_s presented by Figure 1 and Figures 3 - 9 . The arrows indicate certain relationships between the operations, but not necessarily the order. At 1010, when performing a computing function, data stored in the memory array of the memory is provided by the memory to the host. At 1020, an error correction code (ECC) associated with the data is provided by the memory to the host, where the ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

[0082] For example, device 100_s may include a memory 150_s configured to communicate with a host 110_s. The memory 150_s may include a memory array 175_s configured to store data (e.g., read data provided to the host 110_s or write data received from the host 110_s). The memory 150_s may be configured to: provide the data stored in the memory array 175_s to the host 110_s when performing various computing functions, and be configured to: provide an error correction code (ECC) associated with the data to the host 110_s. The ECC may not be stored in the memory array in a first configuration of the memory 150_s (e.g., the memory 150_s is configured for link ECC function) and may be stored in the memory array 175_s in a second configuration of the memory (e.g., the memory 150_s is configured for system ECC function).

[0083] The first and second configurations of the memory 150_s may be based on at least one mode register 179 of the memory 150_s, and the at least one mode register is separately accessible from the memory array 175_s. For example, the at least one mode register 179 may indicate that the memory 150_s supports or enables the second configuration (e.g., system ECC function). In addition, the at least one mode register 179 is separately accessible from the memory array 175_s. For example, the at least one mode register 179 may be read (or written) by a mode register read (or mode register write) command that is not shared with commands for reading or writing the memory array 175_s.

[0084] The memory 150_s may also be configured to: for the first and second configurations, provide ECC (e.g., link ECC or system ECC) to the host 110_s via a read ECC signal connection. For example, the read ECC signal connection may include a data mask DM configured to provide a data mask from the host 110_s to the memory 150_s during a write operation. In some examples, the first configuration may include a link ECC function, and the second configuration includes a system ECC function.

[0085] The at least one mode register 179 may be configured to: indicate that the second configuration is enabled (see Figure 9)。For example, the memory 150_s may configure at least one mode register 179 to indicate that system ECC is enabled / supported. The at least one mode register 179 may also be configured (e.g., by the memory 150_s) to indicate the size of ECC in the second configuration. The at least one mode register 179 may also be configurable to: indicate that the memory 150_s provides additional data information or additional ECC information associated with data (read data or write data) via a read ECC signal connection.

[0086] The additional ECC information may be based on array ECC (the array ECC may be stored in the memory array 175_s; see Figure 3 )。The memory 150_s may also be configured to generate array ECC based on data (e.g., read data) before storing the data in the memory array 175_s (e.g., via the array ECC encoder 172). The memory 150_s may also be configured to detect or correct errors in data (e.g., read data) stored in the memory array 175_s based on the array ECC (e.g., via the array ECC decoder 171). In some examples, the at least one mode register 179 may be readable by the host 110_s but not writable by the host 110_s (see Figure 9 )。

[0087] Figure 11 Illustrates another method for operating the system ECC function of the device 100_s according to certain aspects of the present disclosure. For example, Figure 3 The device 100_s may be implemented by the device 100 or 100_s presented by Figure 11 and Figure 1 and Figures 3 - 9 The arrows indicate certain relationships between operations, but not necessarily an order relationship. At 1110, data is received by the memory from the host while performing a computing function. At 1120, the data is stored by the memory into the memory array. At 1130, the ECC associated with the data from the host is received by the memory, and the ECC is not stored in the memory array in the first configuration of the memory and is stored in the memory array in the second configuration of the memory.

[0088] For example, the memory 150_s may be configured to: receive data (e.g., write data) from the host 110_s during the execution of a computing function, store or write the data into the memory array, and receive ECC (e.g., link ECC or system ECC) from the host 110_s. The memory may also be configured to receive ECC from the host 110_s via a write ECC signal connection (e.g., read data strobe RDQS) for a first configuration (e.g., a configuration for supporting or implementing a link ECC function) and a second configuration (e.g., a configuration for supporting or implementing a system ECC function). The write ECC signal connection may also be configured to provide a data strobe from the memory 150_s to the host 110_s during a read operation.

[0089] The at least one mode register 179 of the apparatus as claimed in claim 14 may also be capable of being configured to indicate the size of the ECC in the second configuration. The at least one mode register 179 may also be capable of being configured to indicate that the memory 150_s provides additional ECC information associated with data (e.g., read data) via a read ECC signal connection (e.g., data mask DM) during a read operation or receives additional data information associated with data (e.g., write data) via a write ECC signal connection (e.g., read data strobe RDQS) during a write operation.

[0090] The additional ECC information provided by the memory 150_s may be based on array ECC. The array ECC may be stored in the memory array 175_s. The memory 150_s may also be configured to generate the array ECC based on data (e.g., received write data) before storing the data in the memory array 175_s and to detect or correct errors in the data (e.g., read data) stored in the memory array based on the array ECC. In some examples, the at least one mode register 179 may be readable by the host 110_s but not writable by the host 110_s.

[0091] For example, the memory 150_s may be configured to communicate with the host 110_s. The memory 150_s may include a memory array 175_s configured to store data. The memory 150 may also be configured to: receive data (e.g., write data) from the host 110_s during the execution of a computing function, write the data into the memory array 175_s, and receive ECC associated with the data from the host 110_s (e.g., link ECC or system ECC). The ECC may not be stored in the memory array 175_s in a first configuration of the memory 150_s (e.g., a configuration for supporting or implementing the link ECC function), and may be stored in the memory array 175_s in a second configuration of the memory 150_s (e.g., a configuration for supporting or implementing the system ECC function). The first configuration and the second configuration may be based on at least one mode register 179 of the memory 150_s, and the at least one mode register 179 may be separately accessible from the memory array 175_s.

[0092] The memory 150_s may also be configured to: for the first configuration and the second configuration, receive ECC from the host 110_s via a write ECC signal connection (e.g., read data strobe RDQS). The write ECC signal connection may be configured to: in a read operation, provide a data strobe from the memory 150_s to the host 110_s. The first configuration may include link ECC. The second configuration may include system ECC.

[0093] The at least one mode register 179 may be configurable to: indicate that the second configuration is enabled (see Figure 9 ). The at least one mode register may be configurable to: indicate the size of the ECC. The at least one mode register 179 may be readable by the host 110_s but not writable by the host 110_s. The at least one mode register may also be configurable to: indicate that the memory 150_s receives additional data information associated with the data via the write ECC signal connection.

[0094] Figure 12 Illustrated is another method for operating the system ECC function of the apparatus 100_s in accordance with certain aspects of the present disclosure. For example, Figure 3 the operation of Figure 12 may be performed by Figure 1 and Figures 3 - 9The presented apparatus 100 or 100_s is implemented. The arrows indicate certain relationships between operations, but not necessarily an order relationship. At 1210, when performing a computing function, data stored in the memory array of the memory is provided by the memory to the host. At 1220, when performing a computing function, ECC associated with the data and stored in the memory array is provided by the memory to the host via a read ECC signal connection. The read ECC signal connection is configured to provide a data mask from the host to the memory in a write operation.

[0095] For example, the memory 150_s may include a memory array 175_s configured to store data and ECC associated with the data. When performing a computing function, the memory 150_s may be configured to provide the data (e.g., read data) and ECC stored in the memory array 175_s to the host 110_s via a read ECC signal connection (e.g., data mask DM). The read ECC signal connection may be configured to provide a data mask from the host 110_s to the memory 150_s in a write operation. At least one mode register 179 may be configurable to: indicate enabling the provision of ECC stored in the memory 150_s to the host 110_s via the read ECC signal connection. At least one mode register 179 may also be configurable to: indicate that the memory 150_s provides additional ECC information via the read ECC signal connection.

[0096] Figure 13 Another method for operating the system ECC function of the apparatus 100_s according to certain aspects of the present disclosure is illustrated. For example, Figure 3 the operation may be implemented by Figure 13 and Figure 1 and Figures 3 - 9 the presented apparatus 100 or 100_s. The arrows indicate certain relationships between operations, but not necessarily an order relationship. At 1310, the memory receives data from the host when performing a computing function. At 1320, the ECC associated with the data is received from the host via a write ECC signal connection. At 1330, the data and ECC are stored into the memory array of the memory, and the write ECC signal connection is configured to provide a data strobe to the host in a read operation.

[0097] For example, when performing a computing function, the memory 150_s may also be configured to receive data (e.g., write data) and ECC from the host 110_s via a write ECC signal connection (e.g., read data strobe RDQS) and store the data and ECC in the memory array 175_s. The write ECC signal connection may be configured to provide a data strobe from the memory 150_s to the host 110_s in a read operation. At least one mode register may also be configurable to instruct the memory 150_s to provide additional ECC or data information associated with the data via the read ECC signal connection in a read operation or to receive additional ECC or data information associated with the data via the write ECC signal connection in a write operation.

[0098] Figure 14 illustratively illustrates a method for operating a Figure 3 Another method of the system ECC function of the device 100_s. For example, Figure 14 The operation can be done by Figure 1 and Figures 3 - 9 The presented apparatus 100 or 100_s is implemented. Arrows indicate certain relationships between operations, but not necessarily sequential relationships. At 1410, data from a memory is received by a host while performing a computing function. At 1420, an ECC associated with the data is received from the memory by the host via a read ECC signal connection, and the data and the ECC are stored in a memory array of the memory. The read ECC signal connection is configured to provide a data mask from the host to the memory in a write operation.

[0099] For example, the host 110_s may be configured to communicate with the memory 150_s. The host 110_s may also be configured to receive data from the memory 150_s when performing a computing function and receive an ECC associated with the data from the memory 150_s via a read ECC signal connection (data mask DM). For example, in a system ECC function, the ECC associated with the data may be provided in advance by the host 110_s together with the data and stored in the memory array 175_s. The data and the associated ECC may share a common address in the memory array 175_s. In a link ECC function, the ECC associated with the data may be provided by the memory link ECC encoder 162 ( Figure 3 ) is generated based on the data stored in the memory array 175_s. The data and ECC are stored in the memory array 175_s of the memory 150_s. The read ECC signal connection can be configured to provide a data mask from the host 110_s to the memory 150_s in a write operation.

[0100] The host 110_s may also be configured to read from at least one mode register 179 in the memory 150_s. The at least one mode register 179 may be separately accessible from the memory array 175_s and may be configurable to indicate that the memory 150_s is enabled to provide ECC stored in the memory array 175_s via a read ECC signal connection. The at least one mode register 179 may also be configurable to indicate the size of the ECC. The host 110 may also be configured to: provide data and provide ECC to the memory 150_s via a write ECC signal connection (e.g., read data strobe RDQS) when performing a computing function. The write ECC signal connection may be configured to: provide a data strobe from the memory 150_s to the host 110_s during a read operation.

[0101] Figure 15 Illustrated is another method for operating Figure 3 the device 100_s to run a system ECC function in accordance with certain aspects of the present disclosure. For example, Figure 15 the operation may be implemented by Figure 1 and Figures 3 - 9 the device 100 or 100_s presented. The arrows indicate certain relationships between the operations but not necessarily an order relationship. At 1510, when performing a computing function, data is provided by the host to the memory. At 1520, the ECC associated with the data is provided by the host to the memory array of the memory via a write ECC signal connection, and the write ECC signal connection is configured to: provide a data strobe to the host during a read operation.

[0102] For example, the host 110_s may also be configured to: via a write ECC signal connection (e.g., read data strobe RDQS), provide data (e.g., write data) and provide the ECC associated with the data to the memory array 175_s of the memory 150_s when performing a computing function. For example, in a link ECC function, the ECC may be generated by a link ECC encoder 136( Figure 3 ) based on the data. In a system ECC function, the ECC may be generated by a system ECC encoder 132( Figure 3 ) based on the data. The write ECC signal connection may be configured to: provide a data strobe to the host during a read operation.

[0103] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, where the elements recited in the singular are not intended to mean "one and only one" but rather "one or more" unless specifically stated otherwise. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or better than other aspects. Unless otherwise expressly stated, the term "some" means one or more. Combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "any combination of A, B, C, or thereof" include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "at least one of A, B, or C," and "any combination of A, B, C, or thereof" may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described herein that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public, whether or not such disclosure is expressly recited in the claims. The words "module," "mechanism," "element," "apparatus," etc. do not substitute for the word "means." Thus, no claim element is to be construed as a means-plus-function unless the element expressly recites the phrase "means for."

Claims

1. An apparatus, comprising: a memory configured to communicate with a host, wherein the memory includes a memory array configured to store data, the memory is configured to: provide the data stored in the memory array to the host when performing a computing function, and is configured to: provide an error correction code (ECC) associated with the data to the host, the error correction code (ECC) is not stored in the memory array in a first configuration of the memory, and is stored in the memory array in a second configuration of the memory, and wherein the first configuration includes a link ECC function, and the second configuration includes a system ECC function.

2. The apparatus according to claim 1, wherein the first configuration and the second configuration are based on at least one mode register of the memory, and the at least one mode register can be accessed separately from the memory array.

3. The apparatus according to claim 2, wherein the memory is further configured to: provide the error correction code (ECC) to the host via a read ECC signal connection for the first configuration and the second configuration.

4. The apparatus according to claim 3, wherein the read ECC signal connection is further configured to: provide a data mask from the host to the memory during a write operation.

5. The apparatus according to claim 4, wherein the at least one mode register can be configured to: indicate that the second configuration is enabled.

6. The apparatus according to claim 5, wherein the at least one mode register can be configured to: indicate the size of the error correction code (ECC) in the second configuration.

7. The apparatus according to claim 6, wherein the at least one mode register can further be configured to: indicate that the memory provides additional ECC information associated with the data via the read ECC signal connection.

8. The apparatus according to claim 7, wherein the additional ECC information is based on array ECC, the array ECC is stored in the memory array, the memory is further configured to: generate the array ECC based on the data before storing the data in the memory array, and detect or correct errors in the data stored in the memory array based on the array ECC.

9. The apparatus according to claim 5, wherein the at least one mode register can be read by the host but cannot be written by the host.

10. The apparatus according to claim 5, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, wherein the device includes the memory, the host, and the read ECC signal connection.

11. The apparatus according to claim 5, wherein the memory is further configured to: receive the data from the host when performing a computing function, store the data in the memory array, and receive the error correction code (ECC) from the host.

12. The apparatus according to claim 11, wherein the memory is further configured to receive the error correction code (ECC) from the host via a write ECC signal connection for the first configuration and the second configuration.

13. The apparatus according to claim 12, wherein the write ECC signal connection is further configured to provide a data strobe from the memory to the host during a read operation.

14. The apparatus according to claim 13, wherein the at least one mode register is configurable to indicate the size of the error correction code (ECC) in the second configuration.

15. The apparatus according to claim 14, wherein the at least one mode register is further configurable to indicate that the memory provides additional ECC information associated with the data via the read ECC signal connection during the read operation, or receives additional data information associated with the data via the write ECC signal connection during the write operation.

16. The apparatus according to claim 15, the additional ECC information provided by the memory is based on array ECC, the array ECC is stored in the memory array, the memory is further configured to generate the array ECC based on the data before storing the data in the memory array, and to detect or correct errors in the data stored in the memory array based on the array ECC.

17. The apparatus according to claim 14, wherein the at least one mode register can be read by the host but cannot be written by the host.

18. The apparatus according to claim 14, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, the device including the memory, the host, the read ECC signal connection, and the write ECC signal connection.

19. An apparatus, comprising: a memory configured to communicate with a host, the memory including a memory array configured to store data, the memory being configured to: receive data from the host during performance of a computing function, store the data in the memory array, and receive an error correction code (ECC) associated with the data from the host, the error correction code (ECC) not being stored in the memory array in a first configuration of the memory and being stored in the memory array in a second configuration of the memory, and wherein the first configuration includes a link ECC function and the second configuration includes a system ECC function.

20. The apparatus according to claim 19, wherein the first configuration and the second configuration are based on at least one mode register of the memory, and the at least one mode register and the memory array can be accessed separately.

21. The apparatus according to claim 20, wherein the memory is further configured to receive the error correction code (ECC) from the host via a write ECC signal connection for the first configuration and the second configuration.

22. The apparatus according to claim 21, wherein the write ECC signal connection is further configured to provide a data strobe from the memory to the host during a read operation.

23. The apparatus according to claim 22, wherein the at least one mode register is configurable to indicate that the second configuration is enabled.

24. The apparatus according to claim 23, wherein the at least one mode register is configurable to indicate the size of the error correction code (ECC).

25. The apparatus according to claim 23, wherein the at least one mode register is readable by the host but not writable by the host.

26. The apparatus according to claim 23, wherein the at least one mode register is further configurable to indicate that the memory receives additional data information associated with the data via the write ECC signal connection.

27. The apparatus according to claim 23, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, wherein the device includes the memory, the host, and the write ECC signal connection.

28. An apparatus, comprising: a memory configured to communicate with a host, the memory including a memory array configured to store data and an error correction code (ECC) associated with the data, the memory being configured to provide the data and, via a read ECC signal connection, provide the error correction code (ECC) stored in the memory array to the host when performing a computing function, the read ECC signal connection being configured to provide a data mask from the host to the memory during a write operation, and wherein the error correction code (ECC) is a system ECC.

29. The apparatus according to claim 28, wherein the memory further includes at least one mode register, the at least one mode register and the memory array being separately accessible, and the at least one mode register being configurable to indicate enabling the provision of the error correction code (ECC) stored in the memory to the host via the read ECC signal connection.

30. The apparatus according to claim 29, wherein the at least one mode register is further configurable to indicate the size of the error correction code (ECC).

31. The apparatus according to claim 29, wherein the at least one mode register is further configurable to indicate that the memory provides additional ECC information via the read ECC signal connection.

32. The apparatus according to claim 31, wherein the additional ECC information provided by the memory is based on an array ECC, the array ECC being stored in the memory array, the memory being further configured to generate the array ECC based on the data before storing the data in the memory array and to detect or correct errors in the data stored in the memory array based on the array ECC.

33. The apparatus according to claim 29, wherein the at least one mode register is readable by the host but not writable by the host.

34. The apparatus according to claim 29, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, wherein the device includes the memory, the host, and the read ECC signal connection.

35. The apparatus according to claim 29, the memory is further configured to: receive the data and the error correction code (ECC) from the host via a write ECC signal connection during execution of a computing function, and store the data and the error correction code (ECC) in the memory array, the write ECC signal connection is configured to: provide a data strobe from the memory to the host during a read operation.

36. The apparatus according to claim 35, wherein the at least one mode register is further configurable to: instruct the memory to provide additional ECC information associated with the data via the read ECC signal connection during the read operation, or receive additional data information associated with the data via the write ECC signal connection during the write operation.

37. The apparatus according to claim 36, the additional ECC information provided by the memory is based on array ECC, the array ECC is stored in the memory array, the memory is further configured to: generate the array ECC based on the data before storing the data in the memory array, and detect or correct errors in the data stored in the memory array based on the array ECC.

38. The apparatus according to claim 35, wherein the at least one mode register is readable by the host but not writable by the host.

39. The apparatus according to claim 35, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, wherein the device includes the memory, the host, the read ECC signal connection, and the write ECC signal connection.

40. An apparatus, comprising: a memory configured to communicate with a host, the memory includes a memory array configured to store data, the memory is configured to: receive data from the host during execution of a computing function, receive an error correction code (ECC) associated with the data from the host via a write ECC signal connection, and store the data and the error correction code (ECC) in the memory array, the write ECC signal connection is configured to: provide a data strobe to the host during a read operation, and wherein the error correction code (ECC) is a system ECC.

41. The apparatus according to claim 40, the memory further includes at least one mode register, The at least one mode register and the memory array can be accessed separately, and the at least one mode register can be configured to indicate enabling receipt of the error correction code (ECC) via the write ECC signal connection and writing the error correction code (ECC) into the memory array.

42. The apparatus according to claim 41, wherein the at least one mode register can further be configured to indicate the size of the error correction code (ECC).

43. The apparatus according to claim 41, wherein the at least one mode register can further be configured to: indicate that the memory receives additional data information associated with the data via the write ECC signal connection.

44. The apparatus according to claim 41, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, wherein the device includes the memory, the host, and the write ECC signal connection.

45. The apparatus according to claim 40, wherein the memory is an LPDDR5 memory.

46. The apparatus according to claim 40, wherein the error correction code (ECC) includes parity bits.

47. An apparatus, comprising: a host configured to communicate with a memory, the host is further configured to: receive data from the memory when performing a computing function, and receive an error correction code (ECC) associated with the data from the memory via a read ECC signal connection, the data and the error correction code (ECC) are stored in a memory array of the memory, the read ECC signal connection is configured to: in a write operation, provide a data mask from the host to the memory, and wherein the error correction code (ECC) is a systematic ECC.

48. The apparatus according to claim 47, the host is further configured to: read from at least one mode register in the memory, the at least one mode register and the memory array can be accessed separately, and the at least one mode register can be configured to: indicate that the memory is enabled to provide the error correction code (ECC) stored in the memory array via the read ECC signal connection.

49. The apparatus according to claim 48, wherein the at least one mode register can further be configured to: indicate the size of the error correction code (ECC).

50. The apparatus according to claim 48, wherein the at least one mode register can further be configured to: indicate that the host receives additional ECC information from the memory via the read ECC signal connection.

51. The apparatus according to claim 50, the additional ECC information provided by the memory is based on an array ECC, the array ECC is stored in the memory array, the memory is further configured to: generate the array ECC based on the data before storing the data in the memory array, and detect or correct errors in the data stored in the memory array based on the array ECC.

52. The apparatus according to claim 48, wherein the at least one mode register is readable by the host but not writable by the host.

53. The apparatus according to claim 48, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, wherein the device includes the host, the memory, and the read ECC signal connection.

54. The apparatus according to claim 48, wherein the host is further configured to: provide the data and the error correction code (ECC) to the memory via a write ECC signal connection when performing a computing function, wherein the write ECC signal connection is configured to: provide a data strobe from the memory to the host during a read operation.

55. The apparatus according to claim 54, wherein the at least one mode register is configurable to indicate the size of the error correction code (ECC).

56. The apparatus according to claim 54, wherein the at least one mode register is further configurable to indicate that the host receives additional ECC information associated with the data via the read ECC signal connection during the read operation, or provides additional data information associated with the data via the write ECC signal connection during the write operation.

57. The apparatus according to claim 54, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, wherein the device includes the memory, the host, the read ECC signal connection, and the write ECC signal connection.

58. An apparatus, comprising: a host configured to communicate with a memory, wherein the host is further configured to: provide data to the memory when performing a computing function, and for a first configuration and a second configuration, provide an error correction code (ECC) associated with the data to a memory array of the memory via a write ECC signal connection, wherein the write ECC signal connection is configured to: provide a data strobe to the host during a read operation, and wherein the first configuration includes a link ECC function and the second configuration includes a system ECC function.

59. The apparatus according to claim 58, wherein the host is further configured to: read from at least one mode register in the memory, wherein the at least one mode register and the memory array are separately accessible, and the at least one mode register is configurable to indicate that the memory is configured to receive the error correction code (ECC) via the write ECC signal connection for the memory array of the memory.

60. The apparatus according to claim 59, wherein the at least one mode register is further configurable to indicate the size of the error correction code (ECC).

61. The apparatus according to claim 59, wherein the at least one mode register is further configurable to indicate that the host provides additional data information associated with the data via the write ECC signal connection.

62. The apparatus according to claim 58, further comprising a device selected from one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, The device includes the memory, the host, and the write ECC signal connection.

63. A method for operating an ECC function, comprising: When performing a computing function, providing, by the memory, data stored in a memory array of the memory to the host; And Providing, by the memory, an error correction code (ECC) associated with the data to the host, the error correction code (ECC) not being stored in the memory array in a first configuration of the memory and being stored in the memory array in a second configuration of the memory, and Wherein the first configuration includes a link ECC function, and the second configuration includes a system ECC function.

64. A method for operating an ECC function, comprising: When performing a computing function, receiving, by the memory, data from the host; Storing, by the memory, the data into a memory array of the memory; And Receiving, by the memory, an error correction code (ECC) associated with the data from the host, the error correction code (ECC) not being stored in the memory array in a first configuration of the memory and being stored in the memory array in a second configuration of the memory, and Wherein the first configuration includes a link ECC function, and the second configuration includes a system ECC function.

65. A method for operating an ECC function, comprising: When performing a computing function, providing, by the memory, data stored in a memory array of the memory to the host; When performing a computing function, providing, by the memory, to the host an error correction code (ECC) associated with the data and stored in the memory array via a read ECC signal connection, the read ECC signal connection being configured to: in a write operation, provide a data mask from the host to the memory, and Wherein the error correction code (ECC) is a system ECC.

66. A method for operating an ECC function, comprising: When performing a computing function, receiving, by the memory, data from the host; Receiving, by the memory, from the host an error correction code (ECC) associated with the data via a write ECC signal connection; Storing the data and the error correction code (ECC) into a memory array of the memory, the write ECC signal connection being configured to: in a read operation, provide a data strobe to the host, and Wherein the error correction code (ECC) is a system ECC.

67. A method for operating an ECC function, comprising: When performing a computing function, receiving, by the host, data from the memory; And Receiving, by the host, from the memory an error correction code (ECC) associated with the data via a read ECC signal connection, the data and the error correction code (ECC) being stored in a memory array of the memory, The read ECC signal connection is configured to: in a write operation, provide a data mask from the host to the memory, and wherein the error correction code (ECC) is a system ECC.

68. A method for operating an ECC function, comprising: when performing a computing function, providing data from a host to a memory; and for a first configuration and a second configuration, providing, by the host via a write ECC signal connection, ECC associated with the data to a memory array of the memory, the write ECC signal connection being configured to: in a read operation, provide a data strobe to the host, and wherein the first configuration includes a link ECC function and the second configuration includes a system ECC function.

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