Thermally induced bow reduction in semiconductor structures

Abstract

A monolithic microwave integrated circuit (MMIC) structure having a thermally conductive substrate; a semiconductor layer disposed on a first portion of an upper surface of the substrate; an active mesa-shaped semiconductor device layer disposed on the semiconductor layer; and a passive electrical device disposed directly on a second portion of the upper surface of the substrate.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor structures, and more particularly to semiconductor structures with reduced thermally induced bowing. Background Technology

[0002] As is known in the art, when two mismatched materials in a structure are bonded / grown together, the different material properties (such as the coefficient of thermal expansion (CTE)) cause the structure to bow (bend). This bowing leads to difficulties in wafer fabrication, which manifests as reduced performance and yield of semiconductor devices. A structure for fabricating high-power monolithic microwave integrated circuits (MMICs) uses a substrate material with high thermal conductivity (such as diamond (with a thermal conductivity of 1000-2000) or silicon carbide (SiC) (with a thermal conductivity of 120 W / (m·K), for example, due to its high thermal conductivity) and a semiconductor material (such as III-N group, for example, gallium nitride (GaN)), which is formed on or bonded to the entire upper surface of the substrate. Active devices such as FETs (field-effect transistors) are fabricated on the semiconductor material (as mesa-shaped semiconductor structures resting on a portion of the GaN material), as well as passive devices (such as matching networks, passive components such as capacitors and resistors) and interconnect transmission lines, which are also resting on portions of GaN. However, the direct growth of diamond on GaN or its bonding at high temperatures results in a coefficient of thermal expansion (CTE). For a 100 mm wafer, the CTE causes a per-wafer bowing of >1 mm. This bowing leads to difficulties in wafer fabrication, resulting in reduced performance and yield of semiconductor devices.

[0003] Several papers and publications have addressed this bowing problem, including: J. Thompson, G. Tepolt, L. Racz, A. Mueller, T. Langdo, D. Gauthier, B. Smith, and Draper Laboratory's "Embedded Package Wafer Bow Elimination Techniques", http: / / ieeexplore.ieee.org / stamp / stamp.jsp? tp=&arnumber=5898491; PauloKi, QuanzhongJiang, WangN.Wang, and DuncanW.E.Allsopp"Stress Engineering During the Fabrication of InGaN / GaN Vertical LightEmitting Diodes for Reducing the Quantum Confined Stark Effect",http: / / ieeexplore.ieee.org / document / 7728035 / ;NgaP.Pham,MaartenRosmeulen,GeorgeBryce,DenizS.Tezcan,B.Majeed,HarisOsmanv,Imec,Kapeldreef75,B-3001Leuven,Belgium"Wafer bow of substrate transfer process for GaNLED on Si 8inch"http: / / ieeexplore.ieee.org / stamp / stamp.jsp? arnumber=6507078.

[0004] Figure 1 shows a structure using a high thermal conductivity substrate (e.g., diamond or silicon carbide (SiC)). Active devices (e.g., HEMT FETs (High Electron Transfer Rate Field-Effect Transistors)) are formed on a portion of the upper surface of the substrate, while passive devices (e.g., resistors) are formed on another portion of the upper surface. The resistors and FETs are electrically interconnected via electrical interconnects. It should be understood that passive devices can be inductors, capacitors, etc., while electrical interconnects can be power dividers, power combiners, couplers, such as hybrid couplers, quadrature couplers, phase shifters, input matching networks, output matching networks, etc. It should be noted that a semiconductor layer (here, for example, gallium nitride (GaN)) is disposed over the entire upper portion of the high thermal conductivity substrate. A portion of this semiconductor layer is a mesa-shaped semiconductor structure providing the active region for the active device (here, the FET), while the remaining portion of the semiconductor layer forms the passive devices and electrical interconnect portions. As shown, a dielectric passivation layer, such as silicon nitride, is formed on this structure. Summary of the Invention

[0005] According to this disclosure, a monolithic microwave integrated circuit (MMIC) structure is provided, comprising: a thermally conductive substrate; a semiconductor layer disposed on a first portion of the upper surface of the substrate; an active semiconductor device layer disposed on the semiconductor layer; and passive electrical devices disposed directly on a second portion of the upper surface of the substrate. In one embodiment, the active devices are mesa-shaped (layered) structures.

[0006] In one embodiment, a semiconductor structure is provided, comprising: a thermally conductive substrate; an active device including: a mesa structure disposed on a layer on an upper surface of the substrate; and a passive device disposed on the upper surface of the substrate, the bottom of the passive device being directly disposed on the upper surface of the substrate.

[0007] In one embodiment, the semiconductor structure includes an electrical interconnect that interconnects active and passive devices, wherein the bottom surface of the electrical interconnect is disposed directly on the upper surface of the substrate.

[0008] In one embodiment, a method for forming a semiconductor structure is provided, comprising: providing a diamond substrate, wherein a III-V semiconductor epitaxial layer is located on and in direct contact with an upper surface of the diamond substrate; determining a first location on the upper surface of the diamond substrate for forming an active semiconductor device and a second location on the upper surface of the diamond substrate for forming a passive device; removing a portion of the III-V semiconductor epitaxial layer having the determined second location, while leaving the III-V semiconductor epitaxial layer on the upper surface of the diamond substrate at the determined first location; and forming an active device directly on the III-V semiconductor epitaxial layer at the determined first location and forming a passive device directly at the second location.

[0009] In one embodiment, a method for forming a semiconductor structure is provided, comprising: designing a schematic diagram of a micro-microelectronic device (MMIC) circuit having active semiconductor devices, passive devices, and electrical interconnects connecting the active devices to the passive devices; generating a mask set based on the schematic diagram circuit of the MMIC design using any conventional mask generation software program for fabricating the designed MMIC circuit, the mask set having: a series of masks for forming active semiconductor devices on active regions of a III-V group semiconductor epitaxial layer directly bonded to or formed on a thermally conductive substrate; a second series of masks for forming passive devices on passive regions, the passive devices being directly located on and in direct contact with the substrate outside the active regions; and a third series of masks for forming electrical interconnects having a first end located on an electrical contact of an active semiconductor device, a second end located on an electrical contact region of a passive device, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect portion being in the active region. The process involves: providing a wafer comprising: a thermally conductive substrate; and a III-V group semiconductor epitaxial layer directly bonded to or grown on the upper surface of the thermally conductive substrate; forming a semiconductor mesa structure using a first series of masks, at which active devices are formed on a portion of the epitaxial layer; etching away a portion of the epitaxial layer outside the mesa structure; forming active semiconductor devices on the mesa structure of the III-V group semiconductor epitaxial layer; forming passive devices on passive regions using a second series of masks, the passive devices being directly located on and in direct contact with the substrate outside the active regions; and forming electrical interconnects using a third series of masks, the electrical interconnects having a first end located on an electrical contact of an active semiconductor device, a second end located on an electrical contact region of a passive device, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect portion being directly located on and in direct contact with the substrate outside the active regions, and being directly located on the substrate.

[0010] In one embodiment, the substrate is diamond or silicon carbide (SiC).

[0011] The inventors have recognized that, with such an arrangement, early in the wafer fabrication process, once the locations for forming heat-generating active devices on the epitaxial layer (e.g., GaN / AlGaN) are determined, a portion of the epitaxial layer can be removed from the upper surface of the substrate for passive devices and electrical interconnects, where the operation of the passive devices and electrical interconnects does not require the epitaxial layer. By removing most of the GaN / AlGaN surface, and noting that most of the surface is used for passive devices and electrical interconnects, primarily leaving the diamond or SiC substrate, this surface is highly smooth and will support the fabrication of monolithic features such as transmission lines and passive devices. Most importantly, the removal of a large area of ​​epitaxial layer reduces the overall stress and bowing of the wafer, restoring the properties of the diamond or SiC substrate, rather than acting as a composite material affected by the epitaxial layer. Therefore, a semiconductor fabrication process and composite wafer substrate are provided in which most of the epitaxial material from the heat-generating active device region is etched away, thereby supporting minimal coverage for active device and MMIC operation. Therefore, the epitaxial layer is left only in the critical regions; the active device regions that generate heat, to reduce the heating effect that causes wafer bowing across the entire composite substrate, while still providing a functional MMIC transistor circuit.

[0012] Details of one or more embodiments of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the description, the drawings, and the claims. Attached Figure Description

[0013] Figure 1 is a simplified cross-sectional schematic diagram of a portion of an MMIC according to the prior art, the MMIC having active devices electrically connected to passive devices;

[0014] Figure 2 yes Figure 5 A simplified cross-sectional schematic diagram of a portion of an MMIC having active devices electrically connected to passive devices according to this disclosure;

[0015] Figure 3A-3S It is used to form Figure 2 A simplified cross-sectional schematic diagram of the MMIC process at each stage of its manufacturing.

[0016] Figure 4 It is a process flow diagram that shows the manufacturing process according to this disclosure. Figure 2 The steps of MMIC; and

[0017] Figure 5 This is a simplified schematic diagram of the top plan view of a chip on which an MMIC is formed, according to the present disclosure;

[0018] The same reference numerals in each figure indicate the same element. Detailed Implementation

[0019] Now for reference Figure 2 The figure shows an MMIC 10 formed on a single-crystal or crystalline thermally conductive substrate 12 (here, for example, diamond or SiC). The MMIC 10 includes a heat-generating active device (here, for example, a HEMT FET 14) and a passive device 16 (here, for example, a resistor), which are electrically interconnected via an electrical interconnect 18. In this embodiment, the HEMT FET 14 is a mesa-shaped semiconductor structure 19, having a lower epitaxial III-N group layer 20 (here, GaN) on the upper surface 11 of the diamond substrate 12, and an upper epitaxial layer 22 (here, AlGaN) on the upper epitaxial layer 20. As shown, the FET (field-effect transistor) 14 has a dielectric passivation layer 29 (here, for example, SiN). x The passive device 16 is formed on the outer surfaces of the lower epitaxial III-N layer 20 and the upper epitaxial layer 22. Source and drain contacts 24 and 26 form ohmic contacts with the epitaxial AlGaN layer 22, as shown in the figure. Source and drain electrodes 28 and 30 are formed on the source and drain contacts, respectively, as shown in the figure. Gate electrode 32 forms a Schottky contact with the epitaxial AlGaN layer 22 to control carrier flow between source contacts 24 and drain contacts 26. It should be noted that the bottom of the passive device 16 is disposed on and in direct contact with the upper surface 11 of the substrate 12. It should also be noted that, as shown in the figure, a gap (GAP) exists between the edge 19E of the mesa-shaped semiconductor structure 19 and the edge 16E of the passive device 16. Furthermore, a portion of the bottom of the electrical interconnect 18 is disposed on and in direct contact with the upper surface 11 of the thermally conductive substrate 12.

[0020] Now for reference Figures 3A to 3S The formation is shown Figure 2 The process of MMIC 10. Therefore, in providing substrate 12, lower semiconductor layer 20 and upper semiconductor layer 22 ( Figure 3A After that, a mask 34 is formed on a portion of the upper surface of the AlGaN layer 22. Figure 3B This portion is on the surface 11 of the substrate 12, where a mesa-shaped semiconductor structure 19 will be formed. Figure 2 Then the surface is exposed to a suitable etchant, removing only the upper exposed portion of the lower GaN semiconductor layer 22 and the upper portion of the lower semiconductor layer 20, as shown. Figure 3C As shown. In Figure 3D The structure after removing mask 34 is shown; it should be noted that the entire upper surface 11 of substrate 12 is covered by the unetched portion of the lower GaN layer 20.

[0021] Now for reference Figure 3E The active device to be formed in the mesa-shaped semiconductor structure 19 (here, FET 14) Figure 2 A mask 40 is formed on the substrate 12. As shown, the entire exposed portion (unmasked portion) of the un-etched portion of the lower GaN semiconductor layer 20 is etched away down to the upper surface 11 of the substrate 12. The mask 40 is then removed to produce... Figure 3F The structure shown.

[0022] Reference Figure 3G ,exist Figure 3G A mask 42 is formed on the structure shown, which has a window or opening 44 to expose portions of the upper AlGaN semiconductor layer 22 for forming ohmic contacts 24, 26 for forming the source and drain, respectively, as shown in the figure.

[0023] like Figure 3H As shown, after removing the mask 42, the surface of the structure is covered with SiNx passivation material 29.

[0024] Reference Figure 3I A mask 44 is formed on a portion of the deposited passivation material 29, on which an active device (here, FET 14) is to be formed in the mesa-shaped semiconductor structure 19. Figure 2 On the part of )). For example Figure 3J As shown, the entire exposed portion (unmasked portion) of the passivation layer (19) is etched away down to the upper surface 11 of the substrate 12. It should also be noted that the passivation layer 29 can also be masked for later use on layers on which passive structures are formed.

[0025] Then remove mask 44, leaving... Figure 3K The structure shown; it should be noted that the upper surface of the thermally conductive substrate 12 is on the mesa-shaped semiconductor structure 19 where the active device (here, FET 14) is to be formed. Figure 2 Exposed outside of the part ))

[0026] Now for reference Figure 3L In the passivation material 29, the gate contact 32 to be formed ( Figure 2 A new mask 46 with a window or opening 47 is formed on the part of the mask.

[0027] Now for reference Figure 3M ,like Figure 3M As shown, the mask 46 ( Figure 3L The structure is exposed in a suitable etchant to expose a portion of the surface of the AlGaN layer 22 where the gate contact 32 to be formed is located.

[0028] Now for reference Figure 3NA mask 48 with an opening is deposited structurally, at which the gate metal 32 will form a Schottky contact with the AlGaN layer 22. Next, the gate metal 32 is deposited on the mask 48 and deposited through the opening onto the Schottky contact 32 to be formed on the AlGaN layer 22. Figure 2 The portion of the gate metal 32 is processed to form this Schottky gate contact 32. The mask 48 is removed, thereby removing the portion of the gate metal 32 thereon, thus forming... Figure 3O The Schottky gate contact 32 is shown.

[0029] Now for reference Figure 3P A mask 50 is structurally formed with a window or opening 23, which is located on the portion of the passivation material 29 above the source and drain contacts 24 and 26, respectively; source and drain electrodes 28 and 30 ( Figure 2 ) will be formed respectively on this part of the structure. By with Figure 3M and Figure 3N In a similar process, the source and drain contacts 24 and 26 are exposed and then masked to deposit the source and drain electrode metals.

[0030] Now for reference Figure 3Q As shown in the figure, the source and drain electrode metals are deposited onto the source and drain contacts 24 and 26 respectively through windows. The mask is then lifted to remove the portion of the metal that was not used for the source and drain electrodes.

[0031] Reference Figure 3R A mask 52 is structurally formed, the mask 52 having a window 53 to expose the passive device 16 to be formed (a resistor in this example). Figure 2 The passive device 16 is formed by depositing resistive material (e.g., tantalum nitride (TaN)) through window 53, as shown in the figure. It should be noted that, as shown, the passive device 16 is formed directly on and in direct contact with the thermally conductive substrate 12. It should also be noted that, as an alternative to forming directly on top of the substrate 12, the passive device 16 can also be formed on top of the passivation layer 29. Furthermore, active devices (here, FET 14) are formed on the mesa-shaped semiconductor structure 19. Figure 2 The above reference exists between the edge of the part and the edge of the passive device. Figure 2 The gap described.

[0032] Now for reference Figure 3S , Figure 3RThe mask 52 is removed and replaced with a new mask 54 having a window 55 that exposes the drain contact 30 and extends to one end 53 of the passive device 16, as shown. Metal for the electrical interconnect 18 is deposited through this window, thereby connecting the drain contact 30 and the passive device 16. The mask 54 is then removed, resulting in… Figure 2 The MMIC 10 shown.

[0033] Now for reference Figure 4 This shows the method for manufacturing with Figure 2 The simplified flowchart of the MMIC shown above, and the above-mentioned... Figure 3A-3S The relevant steps are as follows. Therefore, an MMIC circuit schematic is designed (step 401), the circuit having active semiconductor devices and passive devices, and electrical interconnects for electrically interconnecting the active semiconductor devices and passive devices. Based on the MMIC circuit schematic, a mask set for fabricating the designed MMIC circuit is generated using any conventional mask generation software program. The first mask set has: a series of masks for forming active semiconductor devices on the active region of a III-V semiconductor epitaxial layer, the III-V semiconductor epitaxial layer being directly bonded to or formed on a thermally conductive substrate; a second series of masks for forming passive devices on the passive region, the passive devices being directly located on and in direct contact with the substrate outside the active region; and a third series of masks for forming electrical interconnects having a first end located on the electrical contacts of the active semiconductor devices, a second end located on the electrical contact region of the passive devices, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect portion being directly located on and in direct contact with the substrate outside the active region (step 402). A wafer comprising: a thermally conductive substrate 12; and a component directly bonded to the thermally conductive substrate ( Figure 5A) The upper surface of the epitaxial layer 22 of a III-V semiconductor grown on the upper surface (step 403). A semiconductor mesa structure 19 is formed using a first series of masks 34, 40, 42, 44, 46, and 48, at which an active device 14 is formed on a portion of the epitaxial layer 22; the portion of the epitaxial layer 22 outside the mesa structure 19 is etched away; the active semiconductor device 14 is formed on the mesa structure of the III-V semiconductor epitaxial layer 22 (step 404). A passive device is formed on a passive region using a second series of masks, which is located directly on and in direct contact with the substrate outside the active region (step 405). Using a third series of masks, an electrical interconnect 18 is formed having a first end located on an electrical contact of an active semiconductor device, a second end located on an electrical contact region of a passive device 16, and a portion of the electrical interconnect 18 disposed between the first end and the second end, which is located directly on and in direct contact with the substrate outside the active region and is located directly on the substrate 12 (step 406).

[0034] Now for reference Figure 5 The figure shows a simplified planar diagram of a chip with an MMIC 10 already formed. The MMIC 10 includes multiple HEMT FETs (as shown in Figure 2), multiple passive devices (here, resistors, capacitors, and inductors), and electrical interconnects (here, microwave transmission lines, such as microstrips or coplanar waveguides (CPWs)). As shown in Figure 3, the HEMT FET in this embodiment has a lower epitaxial layer 20 (here, GaN) on the upper surface 13 of a diamond substrate 12, and an upper epitaxial layer 22 (here, AlGaN, as referenced above) on the lower epitaxial upper epitaxial layer 20. Figure 2 The FET 14a has a mesa structure 18. A 2DEG channel (trench) 24, indicated by dashed lines, is formed on the upper part of the lower epitaxial layer 20. The FET 14a has a dielectric passivation layer 29 (here, for example, SiN). x ), as mentioned above Figure 2 and Figure 3A-3S The formation is described above. It can be seen that the only region on the upper surface 11 of the substrate 12 with the epitaxial III-N group layer 20 is the mesa structure 19; more specifically, the aforementioned only region on the upper surface 11 of the substrate 12 is the active device 14. Therefore, the mesa structures 19 are separated from each other by the exposed portions of the upper surface 11 of the substrate 12.

[0035] Therefore, refer to Figure 5 It should be noted that the FET is occupied by the mesa structure 19, while a large portion of the upper surface of the substrate is not used to form the epitaxial III-N group layer 20 for passive devices and electrical interconnects.

[0036] It should now be understood that the monolithic microwave integrated circuit (MMIC) structure according to this disclosure includes: a thermally conductive substrate; a semiconductor layer disposed on a first portion of the upper surface of the substrate; active semiconductor devices disposed on the semiconductor layer; and passive electrical devices disposed directly on a second portion of the upper surface of the substrate. The MMIC structure may independently or in combination include one or more of the following features: wherein the active devices are mesa-shaped structures; wherein the semiconductor structure includes: electrical interconnects interconnecting the active devices and passive devices, and wherein the bottom surface of the electrical interconnects is directly disposed on the upper surface of the substrate; or includes: electrical interconnects interconnecting the active devices and passive devices, and wherein the electrical interconnects are directly disposed on the substrate and indirectly contact the substrate.

[0037] It should now be understood that the semiconductor structure according to this disclosure includes: a thermally conductive substrate; an active device including: a mesa structure disposed on a layer on the upper surface of the substrate; and a passive device disposed on the upper surface of the substrate, the bottom of which is directly disposed on the upper surface of the substrate.

[0038] It should now also be understood that the method for forming a semiconductor structure according to this disclosure includes: providing a substrate having a III-V semiconductor epitaxial layer located on and in direct contact with an upper surface of a diamond substrate; determining a first location on the upper surface of the substrate for forming an active semiconductor device and a second location on the upper surface of the substrate for forming a passive device; removing a portion of the III-V semiconductor epitaxial layer having the determined second location while leaving the III-V semiconductor epitaxial layer on the upper surface of the substrate at the determined first location; and forming an active device directly on the III-V semiconductor epitaxial layer at the determined first location and forming a passive device directly at the second location.

[0039] It should now be understood that the method for forming a semiconductor structure according to this disclosure includes: designing a schematic diagram of an MMIC circuit having active semiconductor devices, passive devices, and electrical interconnects connecting the active devices to the passive devices; using a mask set from any conventional mask generation software program to fabricate the designed MMIC circuit, the mask set having: a series of masks for forming active semiconductor devices on active regions of a III-V group semiconductor epitaxial layer directly bonded to or formed on a thermally conductive substrate; a second series of masks for forming passive devices on passive regions, the passive devices being directly located on and in direct contact with the substrate outside the active regions; and a third series of masks for forming electrical interconnects having a first end located on an electrical contact of an active semiconductor device, a second end located on an electrical contact region of a passive device, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect having a first end located on an electrical contact of an active semiconductor device, a second end located on an electrical contact region of a passive device, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect having a first end located on an electrical contact of an active semiconductor device, a second end located on an electrical contact region of a passive device, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect having a first end located on an electrical contact of an active semiconductor device, the ... of an active semiconductor device, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect having a first end located on an electrical contact of an active semiconductor device, the second end located on an electrical contact region of a passive semiconductor An interconnect portion is located directly on and in direct contact with a substrate outside of an active region; a wafer is provided, comprising: a thermally conductive substrate; and a III-V semiconductor epitaxial layer directly bonded to or grown on the upper surface of the thermally conductive substrate; a semiconductor mesa structure is formed using a first series of masks, wherein an active device is formed on a portion of the epitaxial layer; the epitaxial layer portion outside the mesa structure is etched away; an active semiconductor device is formed on the mesa structure of the III-V semiconductor epitaxial layer; a passive device is formed on a passive region using a second series of masks, the passive device being located directly on and in direct contact with the substrate outside of the active region; and an electrical interconnect is formed using a third series of masks, the electrical interconnect having a first end located on an electrical contact of an active semiconductor device, a second end located on an electrical contact region of a passive device, and an electrical interconnect portion disposed between the first end and the second end, the electrical interconnect portion being located directly on and in direct contact with the substrate outside of the active region, and being located directly on the substrate. The method may include, independently or in combination, one or more of the following features: wherein the substrate is diamond or silicon carbide (SiC), or includes forming electrical interconnects that interconnect active and passive devices, and wherein the electrical interconnects are formed on the substrate and are in indirect contact with the substrate.

[0040] Some embodiments of this disclosure have been described. However, it is understood that various modifications can be made without departing from the spirit and scope of this disclosure. For example, the MMC circuit can be... Figure 2 The differences are shown. Furthermore, passive devices can be formed after active devices are formed. Therefore, other embodiments are also within the scope of the following claims.

Claims

1. A monolithic microwave integrated circuit structure comprising: a thermally conductive substrate composed of diamond or SiC; an active semiconductor device disposed directly on the thermally conductive substrate, the active semiconductor device comprising: a lower epitaxial semiconductor layer composed of GaN disposed on a first portion of an upper surface of the thermally conductive substrate; an upper epitaxial semiconductor layer composed of AlGaN disposed on the lower epitaxial semiconductor layer; and a passivation layer composed of SiNx formed on an outer surface of the lower epitaxial semiconductor layer and an outer surface of the upper epitaxial semiconductor layer; a passive electrical device disposed directly on a second portion of the upper surface of the thermally conductive substrate; and an electrical interconnect disposed in a gap between the passive electrical device and an edge of the active semiconductor device, the electrical interconnect disposed directly on the thermally conductive substrate.

2. The monolithic microwave integrated circuit structure of claim 1, wherein, The active semiconductor device is a mesa structure.

3. The monolithic microwave integrated circuit structure of claim 1, wherein, The electrical interconnect interconnects the active semiconductor device and the passive electrical device, and wherein a bottom surface of the electrical interconnect is disposed directly on the upper surface of the thermally conductive substrate.

4. A semiconductor structure comprising: a thermally conductive substrate composed of diamond or SiC; an active device comprising a mesa structure disposed on an upper surface of the substrate, the active device comprising: a lower epitaxial semiconductor layer composed of GaN disposed on a first portion of an upper surface of the substrate; an upper epitaxial semiconductor layer composed of AlGaN disposed on the lower epitaxial semiconductor layer; and a passivation layer composed of SiNx formed on an outer surface of the lower epitaxial semiconductor layer and an outer surface of the upper epitaxial semiconductor layer; a passive device disposed on the upper surface of the substrate, a bottom of the passive device disposed directly on the upper surface of the substrate; and an electrical interconnect disposed in a gap between the passive device and an edge of the active device, the electrical interconnect disposed directly on the substrate.

5. The semiconductor structure of claim 4, wherein, The electrical interconnect interconnects the active device and the passive device.

6. A method for forming a semiconductor structure comprising: providing a thermally conductive substrate composed of diamond or SiC, the thermally conductive substrate having a III-V semiconductor epitaxial layer on and in direct contact with an upper surface of the thermally conductive substrate, wherein the III-V semiconductor epitaxial layer comprises: a lower epitaxial semiconductor layer disposed on the thermally conductive substrate; and an upper epitaxial semiconductor layer disposed on the lower epitaxial semiconductor layer; determining a first location on the upper surface of the thermally conductive substrate for forming an active semiconductor device and a second location on the upper surface of the thermally conductive substrate for forming a passive device; removing a portion of the III-V semiconductor epitaxial layer having the determined second location, thereby leaving the III-V semiconductor epitaxial layer on the upper surface of the thermally conductive substrate at the determined first location; and forming the active semiconductor device on the determined first location and the passive device on the determined second location. forming the active semiconductor devices directly on the III-V semiconductor epitaxial layer at defined first locations; forming the passive devices directly on the thermally conductive substrate at defined second locations; and forming an electrical interconnect in a gap between an edge of one of the passive devices and an edge of one of the active semiconductor devices, the electrical interconnect being formed on and in contact with the thermally conductive substrate; wherein forming the active semiconductor devices includes forming a passivation layer comprised of SiNx on outer surfaces of the lower epitaxial semiconductor layer and the upper epitaxial semiconductor layer.

7. A method for forming a semiconductor structure, comprising: designing a circuit schematic for a monolithic microwave integrated circuit, the circuit schematic having active semiconductor devices, passive devices, and electrical interconnects interconnecting the active semiconductor devices and the passive devices; generating a mask set for fabricating the monolithic microwave integrated circuit from the circuit schematic, the mask set having: a first series of masks for forming the active semiconductor devices on active regions of a III-V semiconductor epitaxial layer bonded directly to or formed on a thermally conductive substrate, wherein the thermally conductive substrate is comprised of diamond or SiC; a second series of masks for forming the passive devices on passive regions on the thermally conductive substrate outside of the active regions, the passive devices directly contacting the thermally conductive substrate outside of the active regions; a third series of masks for forming the electrical interconnects having first end portions on electrical contacts of the active semiconductor devices, second end portions on electrical contact regions of the passive devices, and portions of the electrical interconnects disposed between the first and second end portions and directly on and in contact with the thermally conductive substrate outside of the active regions; providing a wafer including the thermally conductive substrate and the III-V semiconductor epitaxial layer bonded directly to or formed on an upper surface of the thermally conductive substrate, the III-V semiconductor epitaxial layer including a lower epitaxial semiconductor layer disposed on the thermally conductive substrate and an upper epitaxial semiconductor layer disposed on the lower epitaxial semiconductor layer; using the first series of masks, forming a semiconductor mesa structure, wherein the active devices are formed on portions of the III-V semiconductor epitaxial layer, etching away portions of the III-V semiconductor epitaxial layer outside of the mesa structure, and forming the active semiconductor devices on the mesa structure; using the second series of masks, forming the passive devices on the passive regions on the thermally conductive substrate outside of the active regions, the passive devices directly contacting the thermally conductive substrate outside of the active regions; and using the third series of masks, forming the electrical interconnects having first end portions on electrical contacts of the active semiconductor devices, second end portions on electrical contact regions of the passive devices, and portions of the electrical interconnects disposed between the first and second end portions and directly on and in contact with the thermally conductive substrate outside of the active regions. using the third mask series, forming the electrical interconnect having a first end portion on an electrical contact of the active semiconductor device, a second end portion on an electrical contact area of the passive device, and a portion of the electrical interconnect disposed between the first and second end portions and directly on and in direct contact with the thermally conductive substrate outside the active region, wherein forming the active semiconductor device includes forming a passivation layer comprised of SiNx on an outer surface of the lower epitaxial semiconductor layer and an outer surface of the upper epitaxial semiconductor layer.

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