Solid-state imaging device and imaging apparatus having combined dynamic vision sensor function and imaging function

Abstract

An imaging device includes a plurality of unit pixels or a plurality of pixels, each pixel separated from all other unit pixels by an isolation structure. Each unit pixel includes a photoelectric conversion cell, a pixel imaging signal readout circuit, and an address event detection readout circuit. A first transfer transistor selectively connects the photoelectric conversion cell to the pixel imaging signal readout circuit, and a second transfer transistor selectively connects the photoelectric conversion cell to the address event detection readout circuit. The photoelectric conversion cell, the pixel imaging signal readout circuit, the address event detection readout circuit, the first transfer transistor, and the second transfer transistor of a given pixel are all positioned within a pixel area defined by the isolation structure. The isolation structure can be in the form of a full-thickness dielectric trench isolation structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an imaging apparatus having a dynamic vision sensor capability and an imaging capability. BACKGROUND

[0002] In related art, a synchronous type solid-state imaging device that captures image data in synchronization with a synchronization signal such as a vertical synchronization signal has been used in imaging apparatuses and the like. In a typical synchronous type solid-state imaging device, it is difficult to acquire image data within each cycle of the synchronization signal (for example, within every 1 / 60 second), and thus it is difficult to cope with cases requiring relatively high-speed processing, such as in fields requiring high-speed (for example, real-time) processing, such as autonomous vehicles and robots, and the like. In this regard, a non-synchronous type solid-state imaging device has been proposed in which a detection circuit is provided for each pixel to detect, in real time, a case where the amount of light reception exceeds a threshold value as an address event. The non-synchronous type solid-state imaging device that detects an address event for each pixel is also referred to as a dynamic vision sensor (DVS). SUMMARY

[0003] PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] A sensor having a combination of a DVS and a conventional frame-based imaging can be implemented using various methods. These include devices featuring time-based readout using additional photodiodes, known as asynchronous time-based image sensor (ATIS) systems. However, since ATIS systems require two photodiodes per pixel in order to provide both an image sensor signal and a DVS signal, their resolution and image quality can be degraded compared to arrangements that do not require additional photodiodes. Other devices feature pixels that use a common photodiode to provide both an image sensor signal and a dynamic vision sensor (DVS) event signal, known as dynamic and active pixel vision sensor (DAVIS) systems. However, DAVIS systems can suffer from interference between the imaging function and the event detection function, as these functions are not well isolated. Additionally, difficulties in readout of the DVS signal and the active image sensor signal can degrade the dynamic range of the DAVIS sensor.

[0005] Accordingly, the present disclosure provides a solid-state imaging device and an imaging apparatus that are capable of providing an imaging function and an event detection function, and have improved light-receiving efficiency compared to other configurations.

[0006] SOLUTION TO THE PROBLEM

[0007] According to embodiments and aspects of the present disclosure, there is provided an imaging device comprising a plurality of photoelectric conversion regions or a plurality of pixels arranged in a pixel array. Each pixel comprises: a single photoelectric conversion region; a first readout circuit selectively connected to the photoelectric conversion region by a first transfer gate or a first transfer transistor; and a second readout circuit selectively connected to the photoelectric conversion region by a second transfer gate or a second transfer transistor. Further, the photoelectric conversion region, the first readout circuit, the first transfer transistor, the second readout circuit, and the second transfer transistor of any one pixel in the pixel array are separated from the photoelectric conversion region, the first readout circuit, the first transfer transistor, the second readout circuit, and the second transfer transistor of any adjacent pixel in the pixel array by an isolation structure. The isolation structure can comprise a dielectric structure. The dielectric structure can be provided as a full thickness back trench isolation (RFTI) structure or a full thickness front trench isolation (FFTI) structure. According to at least some embodiments of the present disclosure, the isolation structure encloses each pixel in the pixel array. Thus, a relatively large photosensitive area can be achieved by using a single photoelectric conversion region for both image sensor function and event detection function in each pixel. In addition, the isolation between adjacent pixels is provided by the isolation structure formed between adjacent pixels.

[0008] According to further embodiments and aspects of the present disclosure, in each pixel, some or all components of the first readout circuit can be formed on or towards a first side of the photoelectric conversion region of the pixel, and some or all components of the second readout circuit can be formed on or towards a second side of the photoelectric conversion region of the pixel. According to still further embodiments of the present disclosure, in each pixel, the first transfer transistor can be formed on a first side of the photoelectric conversion region of the pixel, and the second transfer transistor can be formed on a second side of the photoelectric conversion region of the pixel.

[0009] According to still further embodiments and aspects of the present disclosure, the first transfer transistor of a pixel can be provided as a first one of an N-type device and a P-type device, and the second transfer transistor of the pixel can be provided as a second one of the N-type device and the P-type device. If the transfer gates have different compositions (i.e., the first transfer transistor is N-type and the second transfer transistor is P-type, or the first transfer transistor is P-type and the second transfer transistor is N-type), the carriers used for imaging and the carriers used for event-based detection will be different, allowing simultaneous use of imaging mode and DVS detection mode. Thus, in such a configuration, both imaging mode and DVS mode can be simultaneously used from a single pixel. In addition, enhanced isolation between imaging signal and DVS signal can be provided.

[0010] The present disclosure can provide an imaging device having dynamic visual sensing capability and imaging capability and capable of improving light-receiving efficiency. In addition, the present disclosure can provide an imaging device having improved pixel isolation. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram illustrating a schematic configuration example of an imaging device according to an embodiment of the present disclosure.

[0012] Figure 2 is a view illustrating a layer stack structure example of a solid-state imaging device according to an embodiment of the present disclosure.

[0013] Figure 3 is a block diagram illustrating a functional configuration example of a solid-state imaging device according to an embodiment of the present disclosure.

[0014] Figure 4A is a schematic view illustrating an array example of unit pixels in a case where a Bayer array is employed in a color filter array according to an embodiment of the present disclosure.

[0015] Figure 4B is a cross section of the array of unit pixels of Figure 4A

[0016] Figure 5 is a circuit diagram illustrating a schematic configuration example of a unit pixel according to an embodiment of the present disclosure.

[0017] Figure 6 is a block diagram illustrating a schematic configuration example of an address event detection unit according to an embodiment of the present disclosure.

[0018] Figure 7 is a circuit diagram illustrating a schematic configuration example of a subtracter and quantizer according to an embodiment of the present disclosure.

[0019] Figure 8 is a block diagram illustrating a schematic configuration example of a column ADC according to an embodiment of the present disclosure.

[0020] Figure 9 is a timing chart illustrating an example of operation of a solid-state imaging device according to an embodiment of the present disclosure.

[0021] Figure 10 is a flowchart illustrating an example of operation of a solid-state imaging device according to an embodiment of the present disclosure.

[0022] Figure 11 is a plan view of a pixel configuration according to a first example embodiment of the present disclosure.

[0023] Figure 12 ​is a plan view of a portion of a pixel array including groups of pixels constructed as in the first example embodiment.

[0024] Figure 13 is a plan view of a pixel configuration according to a second example embodiment of the present disclosure.

[0025] Figure 14 is a plan view of a portion of a pixel array including groups of pixels constructed as in the second example embodiment.

[0026] Figure 15 is a plan view of a pixel configuration according to a third example embodiment of the present disclosure.

[0027] Figure 16 is a plan view of a portion of a pixel array including groups of pixels constructed as in the third example embodiment.

[0028] Figure 17 is a plan view of a pixel configuration according to a fourth example embodiment of the present disclosure.

[0029] Figure 18 is a plan view of a portion of a pixel array including groups of pixels constructed as in the fourth example embodiment.

[0030] Figure 19 is a plan view of a pixel configuration according to a fifth example embodiment of the present disclosure.

[0031] Figure 20 is a plan view of a portion of a pixel array including groups of pixels constructed as in the fifth example embodiment.

[0032] Figure 21 is a plan view of a pixel configuration according to a sixth example embodiment of the present disclosure.

[0033] Figure 22 is a plan view of a portion of a pixel array including groups of pixels constructed as in the sixth example embodiment.

[0034] Figure 23 is a plan view of a pixel configuration according to a seventh example embodiment of the present disclosure.

[0035] Figure 24 is a plan view of a portion of a pixel array including groups of pixels constructed as in the seventh example embodiment.

[0036] Figure 25 is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0037] Figure 26 is a view illustrating an example of mounting positions of a vehicle exterior information detection unit and an imaging unit. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. Further, in the following embodiments, the same reference numerals are assigned to the same parts, and redundant descriptions thereof will be omitted.

[0039] A typical dynamic vision sensor (DVS) employs a so-called event-driven driving method in which the presence or absence of address event ignition is detected for each unit pixel, and a pixel signal is read out from the unit pixel in which the address event ignition is detected.

[0040] Further, the unit pixel in the present specification indicates a minimum unit of a pixel or a unit pixel including one photoelectric conversion element (also referred to as a "light receiving element"), and can correspond to each dot in image data read out from an image sensor as an example. In addition, the address event indicates an event that occurs for each address assignable to each of a plurality of unit pixels arranged in a two-dimensional lattice shape. The event detection sensor asynchronously responds to an intensity change. The intensity change is associated with a change in photo current, and if such a change exceeds a constant threshold, it can be detected as an event.

[0041] Figure 1 is a block diagram illustrating a schematic configuration example of an imaging device according to at least some embodiments of the present disclosure. As shown, for example, the imaging device 100 includes an imaging lens 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. The imaging device 100 can be provided as a camera mounted in an industrial robot, a vehicle-mounted camera, or a part thereof, or as a part of or in connection with other devices or instruments, as an example. Figure 1

[0042] The imaging lens 110 can include an optical system that guides (for example, converges) incident light and images an image of the incident light on a light-receiving surface of the solid-state imaging device 200 (also simply referred to as the imaging device 200 herein). The light-receiving surface is a surface of a substrate on which a photoelectric conversion element in the solid-state imaging device 200 is arranged. The solid-state imaging device 200 photoelectrically converts incident light to generate image data. In addition, the solid-state imaging device 200 can perform predetermined signal processing such as noise removal and white balance adjustment on the generated image data. The result obtained by the signal processing and a detection signal indicating the presence or absence of address event ignition are output to the recording unit 120 through a signal line 209. Further, a method of generating the detection signal indicating the presence or absence of address event ignition will be described later.

[0043] ​The recording unit 120 is constituted by, for example, a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like, and records data input from the solid-state imaging device 200.

[0044] The control unit 130 is constituted by, for example, a central processing unit (CPU) or the like, and outputs various instructions through a signal line 139 to control each unit such as the solid-state imaging device 200 in the imaging apparatus 100.

[0045] Next, a configuration example of the solid-state imaging device 200 will be described in detail with reference to the drawings.

[0046] Figure 2 is a view illustrating a layer structure example of the solid-state imaging device 200 according to at least some embodiments of the present disclosure. As Figure 2 indicated, the solid-state imaging device 200 can have a structure in which a light-receiving chip 201 and a logic chip 202 are vertically stacked. In the joining of the light-receiving chip 201 and the logic chip 202, for example, a so-called direct joining in which joining surfaces of the chips are planarized and the chips are stacked with an electronic interatomic force can be used. However, it is not limited thereto, and for example, a so-called Cu-Cu joining that bonds Cu (copper) electrode pads formed on the joining surfaces and bump joining, or the like can also be used.

[0047] In addition, for example, the light-receiving chip 201 and the logic chip 202 are electrically connected to each other through a connection portion such as a through-silicon via (TSV) that penetrates the semiconductor substrate. In the connection using the TSV, for example, a so-called double TSV method in which two TSVs including a TSV formed in the light-receiving chip 201 and a TSV formed from the light-receiving chip 201 to the logic chip 202 are connected to each other on the outer surface of the chip and a so-called shared TSV method in which the light-receiving chip 201 and the logic chip 202 are connected with a TSV that penetrates both chips, or the like can be employed.

[0048] However, in the case where the Cu-Cu joining or the bump joining is used in the joining of the light-receiving chip 201 and the logic chip 202, both the light-receiving chip 201 and the logic chip 202 are electrically connected to each other through a Cu-Cu joint or a bump joint.

[0049] Figure 3 is a block diagram illustrating a functional configuration example of the solid-state imaging device according to at least some embodiments of the present disclosure. As Figure 3 indicated, the solid-state imaging device 200 includes a drive circuit 211, a signal processing unit 212, an arbiter 213, a column ADC 220, and a pixel array unit 300.

[0050] A plurality of unit cells or unit pixels 310 (hereinafter simply referred to as pixels 310) are arranged in a two-dimensional lattice shape in the pixel array unit 300. Details of the unit pixels 310 will be described later. For example, each unit pixel 310 includes a photoelectric conversion element such as a photodiode and a circuit (hereinafter referred to as a pixel circuit) that generates a pixel signal having a voltage value corresponding to the amount of charge generated in the photoelectric conversion element. Further, as discussed in more detail herein, the pixel circuit can include a first or imaging signal generation circuit and a second or address event detection readout circuit. Here, each photoelectric conversion element is associated with a pixel circuit provided only for that photoelectric conversion element. That is, the pixel circuit is not shared by a plurality of photoelectric conversion elements.

[0051] The plurality of unit pixels 310 are arranged in a two-dimensional lattice shape in the pixel array unit 300. The plurality of unit pixels 310 can be grouped into a plurality of pixel blocks or groups, each including a predetermined number of unit pixels. Hereinafter, a set of unit pixels arranged along a horizontal direction will be referred to as a "row" and a set of unit pixels arranged along a direction orthogonal to the row will be referred to as a "column".

[0052] Each unit pixel 310 generates a charge corresponding to the amount of light received in the respective photoelectric conversion element. In addition, the unit pixel 310 can be operated to detect the presence or absence of an address event trigger based on whether the value of a current (hereinafter referred to as a photocurrent) generated by the charge generated in the photoelectric conversion element or the amount of change thereof exceeds a predetermined threshold. In addition, when an address event is triggered, a request for reading out a pixel signal having a voltage value corresponding to the amount of light reception of the photoelectric conversion element is output to the arbitrator 213.

[0053] The drive circuit 211 drives each unit pixel 310 and allows each unit pixel 310 to output a pixel signal to the column ADC 220.

[0054] The arbitrator 213 arbitrates the requests from the unit pixels 310 and transmits a predetermined response to the requesting unit pixel 310 based on the arbitration result. The unit pixel 310 that receives the response supplies a detection signal (hereinafter simply referred to as an "address event detection signal") indicating the presence or absence of an address event trigger to the drive circuit 211 and the signal processing unit 212.

[0055] The column ADC 220 converts the analog pixel signal from each column of unit pixels 310 into a digital signal. In addition, the column ADC 220 supplies the digital signal generated by the conversion to the signal processing unit 212.

[0056] The signal processing unit 212 performs predetermined signal processing, such as correlated double sampling (CDS: correlated double sampling) processing (noise removal) and white balance adjustment, on the digital signal transmitted from the column ADC 220. In addition, the signal processing unit 212 supplies the signal processing result and the address event detection signal to the recording unit 120 through the signal line 209.

[0057] The unit pixels 310 within the pixel array unit 300 can be arranged in pixel groups 314. For example, in the case of a Bayer array, the unit pixels 310 are arranged in the pixel groups 314 in a 2 x 2 pixel group. Figure 3 In the illustrated configuration, the pixel array unit 300 is composed of the pixel groups 314 including a set of the unit pixels 310 that receive wavelength components required for reconstructing a color. For example, in the case of reconstructing a color based on RGB three primary colors, in the pixel array unit 300, the unit pixels 310 that receive red (R) light, the unit pixels 310 that receive green (G) light, and the unit pixels 310 that receive blue (B) light are arranged in the groups 314 according to a predetermined color filter array.

[0058] Examples of the color filter array configuration include various arrays or pixel groups such as: a Bayer array of 2 x 2 pixels; a color filter array of 3 x 3 pixels employed in an X-Trans (registered trademark) CMOS sensor (hereinafter also referred to as an "X-Trans (registered trademark) type array"); a Quadra array of 4 x 4 pixels (also referred to as a "Quadra array"); and a color filter of 4 x 4 pixels that combines a white RGB color filter to a Bayer array (hereinafter also referred to as a "white RGB array"). Here, in the following description, a case in which a Bayer array is employed as the color filter array will be exemplified.

[0059] Figure 4A is a schematic diagram illustrating an array example of the unit pixels 310 in a case in which the pixel groups 314 having an arrangement of the unit pixels 310 and the associated color filters are employed in the color filter array configured to form a plurality of basic patterns 310A. As Figure 4A As illustrated, in a case in which the Bayer array is employed as the color filter array configuration, in the pixel array unit 300, a basic pattern 310A including a total of four unit pixels 310 of 2 x 2 pixels is repeatedly arranged along the column direction and the row direction. For example, the basic pattern 310A is composed of a unit pixel 310R including a color filter 401 of red (R), a unit pixel 310Gr including a color filter 401 of green (Gr), a unit pixel 310Gb including a color filter 401 of green (Gb), and a unit pixel 310B including a color filter 401 of blue (B).

[0060] Figure 4BIt depicts the section intercepted along line A-A' Figure 4A A cross-section of an example of unit pixel 310 is shown. As illustrated, unit pixel 310 is formed in substrate 402, which can be included as part of light receiving chip 201. Additionally, and as discussed further elsewhere herein, each unit pixel is defined by an isolation structure 1208. The isolation structure 1208 may be in the form of a full-thickness dielectric trench (RFTI) structure or group of structures extending from light incident surface 403 through the entire thickness of substrate 402 to the opposing surface 404 of substrate 402. Furthermore, each unit pixel can be associated with an on-chip lens 476. Alternatively or additionally, RFTI structures or groups of structures can be provided for isolation between adjacent unit pixels.

[0061] Next, we will explain an example of constructing a unit pixel of 310. Figure 5 This is a circuit diagram illustrating a schematic construction example of a unit pixel 310 according to at least some embodiments of the present disclosure. Figure 5 As shown, for example, a unit pixel 310 includes a pixel imaging signal generation unit (or readout circuit) 320, a light receiving unit 330, and an address event detection unit (or readout circuit) 400. According to at least one exemplary embodiment, the readout circuit 400 is configured to control the readout circuit 320 based on the charge generated by the photoelectric conversion element (or photoelectric conversion region) 333. Furthermore, Figure 5 The logic circuit 210 in the example includes, for example Figure 3 The logic circuits of the drive circuit 211, signal processing unit 212 and arbitrator 213 are included.

[0062] For example, the light receiving unit 330 includes a first or imaging transmission transistor or gate (first transistor) 331, a second or address event detection transmission transistor or gate (second transistor) 332, and a photoelectric conversion element 333. A first transmission signal TG1 transmitted from the driving circuit 211 is selectively supplied to the gate of the first transmission transistor 331 of the light receiving unit 330, and a second transmission signal TG2 transmitted from the driving circuit 211 is selectively supplied to the gate of the second transmission transistor 332. The output of the first transmission transistor 331 of the light receiving unit 330 is connected to the pixel imaging signal generation unit 320, and the output of the second transmission transistor 332 is connected to the address event detection unit 400.

[0063] For example, the pixel imaging signal generation unit 320 includes a reset transistor (third transistor) 321, an amplification transistor (fourth transistor) 322, a selection transistor (fifth transistor) 323, and a floating diffusion layer (FD) 324.

[0064] According to at least some embodiments of the present disclosure, for example, the first transfer transistor 331 and the second transfer transistor 332 of the light-receiving unit 330 are configured by using N-type metal-oxide-semiconductor (MOS) transistors (hereinafter, simply referred to as "NMOS transistors"). Similarly, for example, the reset transistor 321, the amplification transistor 322, and the selection transistor 323 of the pixel imaging signal generation unit 320 are each configured by using NMOS transistors.

[0065] For example, the address event detection unit 400 includes a current-voltage conversion unit 410 and a subtracter 430. However, the address event detection unit 400 is also provided with a buffer, a quantizer, and a transfer unit. In the following description, details of the address event detection unit 400 will be described by using Figure 6

[0066] In the illustrated configuration, the photoelectric conversion element 333 of the light-receiving unit 330 photoelectrically converts incident light to generate a charge. The first transfer transistor 331 transfers the charge generated in the photoelectric conversion element 333 to the floating diffusion layer 324 in accordance with a first transfer signal TG1. The second transfer transistor 332 supplies an electric signal (photoelectric current) based on the charge generated in the photoelectric conversion element 333 to the address event detection unit 400 in accordance with a second transfer signal TG2.

[0067] The floating diffusion layer 324 accumulates the charge transferred from the photoelectric conversion element 333 via the first transfer transistor 331. The reset transistor 321 discharges (initializes) the charge accumulated in the floating diffusion layer 324 in accordance with a reset signal transferred from the drive circuit 211. The amplification transistor 322 allows a pixel signal having a voltage value corresponding to a charge amount of the charge accumulated in the floating diffusion layer 324 to appear in the vertical signal line VSL. The selection transistor 323 switches the connection between the amplification transistor 322 and the vertical signal line VSL in accordance with a selection signal SEL transferred from the drive circuit 211. Further, the analog pixel signal appearing in the vertical signal line VSL is read out by the column ADC 220, and is converted into a digital pixel signal.

[0068] When the control unit 130 gives an instruction of the start of the address event detection, the drive circuit 211 in the logic circuit 210 outputs a control signal for setting the second transfer transistor 332 of the light-receiving unit 330 in the pixel array unit 300 to an on state. With this arrangement, the photoelectric current generated in the photoelectric conversion element 333 of the light-receiving unit 330 is supplied to the address event detection unit 400 of each unit pixel 310 via the second transfer transistor 332.

[0069] ​When an address event trigger is detected based on the photocurrent from the light-receiving unit 330, the address event detection unit 400 of each unit pixel 310 outputs a request to the arbitrator 213. In response to this, the arbitrator 213 arbitrates the requests transmitted from each unit pixel 310 and transmits a predetermined response to the unit pixel 310 that made the request based on the arbitration result. The unit pixel 310 that received the response supplies a detection signal (hereinafter referred to as an "address event detection signal") indicating the presence or absence of an address event trigger to the drive circuit 211 and the signal processing unit 212 in the logic circuit 210.

[0070] The drive circuit 211 sets the second transfer transistor 332 in the unit pixel 310 that is a supply source of the address event detection signal to an off state. With this arrangement, the supply of the photocurrent from the light-receiving unit 330 to the address event detection unit 400 of the unit pixel 310 is stopped.

[0071] Next, the drive circuit 211 sets the first transfer transistor 331 in the light-receiving unit 330 of the unit pixel 310 to an on state by the first transfer signal TG1. With this arrangement, the charge generated in the photoelectric conversion element 333 of the light-receiving unit 330 is transferred to the floating diffusion layer 324 via the first transfer transistor 331. In addition, a pixel signal having a voltage value corresponding to the amount of charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL connected to the selection transistor 323 of the pixel imaging signal generation unit 320.

[0072] As described above, in the solid-state imaging device 200, the pixel signal SIG is output from the unit pixel 310 that detected the address event trigger to the column ADC 220.

[0073] Further, for example, the light-receiving unit 330, the pixel imaging signal generation unit 320, and two logarithmic (LG) transistors (sixth and seventh transistors) 411 and 414 and two amplification transistors (eighth and ninth transistors) 412 and 413 in the current-voltage conversion unit 410 of the address event detection unit 400 are provided in, for example, the light-receiving chip 201 as shown in FIG. 2, and the other components can be provided in, for example, the logic chip 202 that is bonded with the light-receiving chip 201 by Cu-Cu bonding. Therefore, in the following description, the configuration provided in the light-receiving chip 201 is referred to as an "upper layer circuit" in the unit pixel 310. Figure 2

[0074] Figure 6 is a block diagram illustrating a schematic configuration example of the address event detection unit 400 according to at least some embodiments of the present disclosure. As Figure 6 ​As shown, the address event detection unit 400 includes a current-to-voltage conversion unit 410, a buffer 420, a subtractor 430, a quantizer 440, and a transmission unit 450.

[0075] The current-to-voltage conversion unit 410 converts the photocurrent from the light receiving unit 330 into a voltage signal that is logarithmic in nature, and supplies the voltage signal generated by the conversion to the buffer 420.

[0076] The buffer 420 corrects the voltage signal transmitted from the current-to-voltage conversion unit 410 and outputs the corrected voltage signal to the subtractor 430.

[0077] Subtractor 430 reduces the voltage level of the voltage signal transmitted from buffer 420 according to the row drive signal transmitted from drive circuit 211, and supplies the reduced voltage signal to quantizer 440.

[0078] The quantizer 440 quantizes the voltage signal transmitted from the subtractor 430 into a digital signal, and outputs the digital signal generated by quantization as a detection signal to the transmission unit 450.

[0079] The transmission unit 450 transmits the detection signal from the quantizer 440 to the signal processing unit 212, etc. For example, when an address event is detected, the transmission unit 450 supplies the arbitrator 213 with a request to transmit the address event detection signal from the transmission unit 450 to the drive circuit 211 and the signal processing unit 212. Furthermore, when the transmission unit 450 receives a response from the arbitrator 213 regarding this request, the transmission unit 450 supplies the detection signal to the drive circuit 211 and the signal processing unit 212.

[0080] For example, Figure 6 The current-to-voltage conversion unit 410 in the illustrated configuration includes, as shown in the figure Figure 5 The diagram shows two LG transistors 411 and 414, two amplifying transistors 412 and 413, and a constant current circuit 415.

[0081] For example, the source of LG transistor 411 and the gate of amplifying transistor 413 are connected to the drain of the second transmission transistor 332 of the light receiving unit 330. Additionally, for example, the drain of LG transistor 411 is connected to the source of LG transistor 414 and the gate of amplifying transistor 412. For example, the drain of LG transistor 414 is connected to the power supply terminal VDD.

[0082] In addition, for example, the source of the amplification transistor 413 is grounded, and the drain thereof is connected to the gate of the LG transistor 411 and the source of the amplification transistor 412. For example, the drain of the amplification transistor 412 is connected to the power supply terminal VDD through a constant current circuit 415. For example, the constant current circuit 415 is constituted by a load MOS transistor such as a P-type MOS transistor.

[0083] In this connection relationship, a ring source follower circuit is constructed. With this arrangement, the photoelectric current from the light-receiving unit 330 is converted into a voltage signal corresponding to the logarithmic value of the charge amount thereof. In addition, the LG transistors 411 and 414 and the amplification transistors 412 and 413 can each be constituted by, for example, an NMOS transistor.

[0084] Figure 7 is a circuit diagram illustrating a schematic configuration example of a subtracter and a quantizer according to at least some embodiments of the present disclosure. As Figure 7 shown, the subtracter 430 includes capacitors 431 and 433, an inverter 432, and a switch 434. In addition, the quantizer 440 includes a comparator 441.

[0085] One end of the capacitor 431 is connected to the output terminal of the buffer 420, and the other end is connected to the input terminal of the inverter 432. The capacitor 433 is connected in parallel to the inverter 432. The switch 434 opens or closes the route connecting both ends of the capacitor 433, in accordance with a row drive signal.

[0086] The inverter 432 inverts the voltage signal input through the capacitor 431. The inverter 432 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 441.

[0087] When the switch 434 is on, the voltage signal Vinit is input to the buffer 420 side of the capacitor 431. In addition, the opposite side becomes a virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, when the capacity of the capacitor 431 is set to C1, the potential Qinit accumulated in the capacitor 431 is represented by the following expression (1). On the other hand, both ends of the capacitor 433 are short-circuited, and thus the accumulated charge thereof becomes zero.

[0088] Qinit = C1 x Vinit (1)

[0089] Next, when considering a case where the switch 434 is off, and the voltage on the buffer 420 side of the capacitor 431 changes to Vafter, the charge Qafter accumulated in the capacitor 431 is represented by the following expression (2).

[0090] Qafter = C1 x Vafter (2)

[0091] On the other hand, when the output voltage is set to Vout, the charge Q2 accumulated in the capacitor 433 is represented by the following expression (3).

[0092] Q2 = -C2 x Vout (3)

[0093] At this time, the total charge amount of the capacitors 431 and 433 does not change, and thus the following expression (4) holds.

[0094] Qinit = Qafter + Q2 (4)

[0095] When expression (1) to expression (3) are substituted into expression (4), the following expression (5) is obtained.

[0096] Vout = -(C1 / C2) x (Vafter - Vinit) (5)

[0097] Expression (5) represents a subtraction operation of the voltage signal, and the gain of the subtraction result becomes C1 / C2. In general, it is desirable to maximize (or alternatively, increase) the gain, and thus it is preferable to design so that C1 becomes large and C2 becomes small. On the other hand, when C2 is too small, kTC noise increases, and thus there is a concern that the noise characteristic deteriorates. Therefore, the reduction of the capacity of C2 is limited to a range in which noise can be allowed. In addition, since the address event detection unit 400 including the subtracter 430 is mounted for each unit pixel 310, there is a limitation on the area in terms of the capacities C1 and C2. The values of the capacities C1 and C2 are determined in consideration of the limitation.

[0098] The comparator 441 compares the voltage signal transmitted from the subtracter 430 with a predetermined threshold voltage Vth applied to the inverting input terminal (-). The comparator 441 outputs a signal indicating the comparison result to the transmission unit 450 as a detection signal.

[0099] In addition, when the conversion gain of the current-voltage conversion unit 410 is set to CG log and the gain of the buffer 420 is set to "1", the gain A of the address event detection unit 400 as a whole is represented by the following expression (6).

[0100] [Math. 1]

[0101]

[0102] In expression (6), i photo_ n represents the photo current of the nth unit pixel 310, and the unit is, for example, ampere (A). N represents the number of unit pixels 310 in the pixel block, and is "1" in the present embodiment.

[0103] Figure 8is a block diagram illustrating a schematic configuration example of a column ADC according to at least some embodiments of the present disclosure. The column ADC 220 includes a plurality of ADCs 230 provided for each column of the unit pixels 310.

[0104] Each of the ADCs 230 converts an analog pixel signal appearing in the vertical signal line VSL into a digital signal. For example, the pixel signal is converted into a digital signal having a bit length greater than that of the detection signal. For example, when the detection signal is set to two bits, the pixel signal is converted into a digital signal of three bits or more (16 bits, etc.). The ADC 230 supplies the generated digital signal to the signal processing unit 212.

[0105] Next, the operation of the solid-state imaging device 200 according to at least some embodiments of the present disclosure will be described in detail with reference to the drawings.

[0106] First, an example of the operation of the solid-state imaging device 200 will be described by using a timing chart. Figure 9 is a timing chart illustrating an example of the operation of the solid-state imaging device according to the first embodiment.

[0107] As Figure 9 indicated, at timing TO, when the control unit 130 gives an instruction of the start of address event detection, the drive circuit 211 raises the second transfer signal TG2 applied to the gates of the second transfer transistors 332 of all the light-receiving units 330 in the pixel array unit 300 to the high level. With this arrangement, the plurality of second transfer transistors 332 of all the light-receiving units 330 enter the on state, and a photoelectric current based on the electric charge generated in the photoelectric conversion element 333 of each light-receiving unit 330 is supplied from each light-receiving unit 330 to each of the plurality of address event detection units 400.

[0108] In addition, the first transfer signal TG1 applied to the gates of the first transfer transistors 331 in each light-receiving unit 330 is maintained at the low level throughout the period in which the second transfer signal TG2 is at the high level. Thus, the plurality of transfer transistors 331 in all the light-receiving units 330 are in the off state in this period.

[0109] Next, it will be assumed that the address event detection unit 400 of an arbitrary unit pixel 310 detects an address event trigger in the period in which the second transfer signal TG2 is at the high level. In this case, the address event detection unit 400 that detected the address event trigger transmits a request to the arbiter 213. In response to this, the arbiter 213 arbitrates the request, and returns a response to the request to the address event detection unit 400 that made the request.

[0110] For example, in the period from timing T1 to timing T2, the address event detection unit 400 that received the response raises the detection signal input to the drive circuit 211 and the signal processing unit 212 to the high level. Further, in the present specification, it is assumed that the detection signal is a 1-bit signal.

[0111] The drive circuit 211 that input the high-level detection signal from the address event detection unit 400 at timing T1 lowers all the second transfer signals TG2 to the low level at the subsequent timing T2. With this arrangement, the supply of the photoelectric current from all the light-receiving units 330 of the pixel array unit 300 to the address event detection unit 400 is stopped.

[0112] In addition, at timing T2, the drive circuit 211 raises the selection signal SEL applied to the gate of the selection transistor 323 in the pixel imaging signal generation unit 320 of the unit pixel 310 in which the address event trigger is detected (hereinafter referred to as "readout target unit pixel") to the high level, and raises the reset signal RST applied to the gate of the reset transistor 321 of the same pixel imaging signal generation unit 320 to the high level for a constant pulse period, thereby discharging (initializing) the charge accumulated in the floating diffusion layer 324 of the pixel imaging signal generation unit 320. In this way, the voltage appearing in the vertical signal line VSL in the state where the floating diffusion layer 324 is initialized is read out as a reset level pixel signal (hereinafter simply referred to as "reset level") by the ADC 230 connected to the vertical signal line VSL in the column ADC 220, and is converted into a digital signal.

[0113] Next, at timing T3 after the reset level is read out, the drive circuit 211 applies the first transfer signal TG1 of the constant pulse period to the gate of the first transfer transistor 331 of the light-receiving unit 330 in the readout target unit pixel 310. With this arrangement, the charge generated in the photoelectric conversion element 333 of the light-receiving unit 330 is transferred to the floating diffusion layer 324 in the pixel imaging signal generation unit 320, and the voltage corresponding to the charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL. In this way, this voltage appearing in the vertical signal line VSL is read out as a signal level pixel signal (hereinafter simply referred to as "signal level") of the light-receiving unit 330 by the ADC 230 connected to the vertical signal line VSL in the column ADC 220, and is converted into a digital value.

[0114] The signal processing unit 212 implements CDS processing in which the difference between the reset level and the signal level read out as described above is obtained as a net pixel signal corresponding to the amount of light reception of the photoelectric conversion element 333.

[0115] Next, at timing T4, the drive circuit 211 lowers the selection signal SEL applied to the gate of the selection transistor 323 in the pixel imaging signal generation readout circuit 320 of the readout target unit pixel 310 to a low level, and raises the second transfer signal TG2 applied to the gate of the second transfer transistor 332 in all the light-receiving units 330 in the pixel array unit 300 to a high level. With this arrangement, address event triggered detection in all the light-receiving units 330 in the pixel array unit 300 is restarted.

[0116] Next, an example of the operation of the solid-state imaging device 200 will be described using a flowchart. Figure 10 is a flowchart illustrating an example of the operation of a solid-state imaging device according to at least some embodiments of the present disclosure. This operation is started, for example, when a predetermined application program for detecting address events is implemented.

[0117] As shown in Figure 10 In this operation, first, each unit pixel 310 in the pixel array unit 300 detects the presence or absence of an address event trigger (step S901). In addition, the drive circuit 211 determines whether an address event trigger is detected in any of the unit pixels 310 (step S902).

[0118] In a case where an address event trigger is not detected (NO in step S902), the operation proceeds to step S904. On the other hand, in a case where an address event trigger is detected (YES in step S902), the drive circuit 211 implements readout of a pixel signal for the unit pixel 310 in which the address event trigger is detected (step S903), and proceeds to step S904.

[0119] In step S904, it is determined whether to terminate the operation. In a case where the operation is not terminated (NO in step S904), the operation returns to step S901, and the subsequent operation is repeated. On the other hand, in a case where the operation is terminated (YES in step S904), the operation is terminated.

[0120] Figure 11 is a plan view of a pixel configuration according to the first exemplary embodiment of the present disclosure, Figure 12 is a plan view of a portion of a pixel array including a group of pixels configured as in the first exemplary embodiment. More specifically, Figure 11is a top view illustrating a schematic configuration example of a unit pixel 310 according to a first exemplary embodiment. In this example, the photoelectric conversion element 333 of the unit pixel 310 has a hexagonal shape. According to further embodiments of the present disclosure, the photoelectric conversion element 333 can have any other shape, including but not limited to a rectangular, an elliptical, or a circular shape. Also in this example, the circuit elements associated with the pixel imaging signal generation unit or readout circuit 320 are positioned on a first side of the center line C of the photoelectric conversion element 333, while the circuit elements associated with the address event detection unit or readout circuit 400 are positioned on a second side of the center line C of the photoelectric conversion element 333. The components of the unit pixel 310 are placed within a pixel area 311, which in this example has a rectangular shape, although other shapes are possible, and the pixel area 311 is delimited by the isolation structure 1208.

[0121] In this first exemplary embodiment, the circuit elements of the pixel imaging signal generation readout circuit 320 of the unit pixel 310 positioned within the pixel area 311 include a reset transistor 321, a floating diffusion layer 324, an amplification transistor 322, and a selection transistor 323. The circuit elements of the address event detection readout circuit 400 of the unit pixel 310 positioned within the pixel area 311 include a first logarithmic transistor 411 and a second logarithmic transistor 414, as well as a first amplification transistor 412 and a second amplification transistor 413. The pixel imaging signal generation readout circuit 320 is connected to the photoelectric conversion element 333 through a first transfer transistor 331, while the address event detection readout circuit 400 is connected to the photoelectric conversion element 333 through a second transfer transistor 332. The first transfer transistor 331 and the second transfer transistor 332 are also positioned within the pixel area 311.

[0122] Also in this exemplary embodiment, the first transfer transistor 331 is formed along a portion of one side of the hexagonal photoelectric conversion element 333. Further, the first transfer transistor 331 is formed on the first side of the center line C of the photoelectric conversion element 333. The second transfer transistor 332 is formed along a portion of another side of the hexagonal photoelectric conversion element 333. Further, the second transfer transistor 332 is formed on the second side of the center line C of the photoelectric conversion element 333. As shown, the side or facet of the photoelectric conversion element 333 in which the first transfer transistor 331 is formed can be separated from the side or facet in which the second transfer transistor 332 is formed by another side or facet of the photoelectric conversion element 333. However, it should be understood that for a hexagonal photoelectric conversion element 333, the minimum separation of the transfer transistors 331 and 332 is any number of facets between 0 and 3 facets. According to yet another embodiment of the present disclosure, the first transfer transistor 331 and the second transfer transistor 332 can be formed on the same side or the same facet of the photoelectric conversion element 333. Figure 11 ​

[0123] Figure 12 is a plan view of a portion of a pixel array including a group 314 of unit pixels 310 constructed according to the first exemplary embodiment, respectively. More specifically, the group 314 of unit pixels 310 includes a 2x2 subarray of first unit pixels 310 (unit pixels 310.1), second unit pixels 310 (unit pixels 310.2), third unit pixels 310 (unit pixels 310.3), and fourth unit pixels 310 (unit pixels 310.4). According to at least some embodiments of the present disclosure, the group 314 of unit pixels 310 can be constructed as a group 314 of pixels constructed in a pattern 310A including a collection of unit pixels 310 that receive different wavelength components. As shown, there is no sharing of circuit elements shown as included in each individual unit pixel 310. Instead, isolation structures 1208 disposed around each unit pixel region 311 separate the unit pixels 310 from one another. As shown, when unit pixels 310 are grouped into a group 314, isolation structures between adjacent unit pixels 310 can be shared such that an isolation structure 1208 defining one side of a first unit pixel (e.g., unit pixel 310.1) can also define one side of an adjacent unit pixel (e.g., unit pixel 310.2). According to embodiments of the present disclosure, the isolation structures 1208 can be in the form of full thickness dielectric trench isolation or simply a full thickness trench isolation (RFTI) structure. Figure 12

[0124] Figure 13 is a plan view of a portion of a pixel array including a group of pixels constructed as in the second exemplary embodiment. More specifically, Figure 14 is a plan view of a portion of a pixel array including a group of pixels constructed as in the second exemplary embodiment. More specifically, Figure 13 is a plan view illustrating an example of a schematic construction of a unit pixel 310 according to the second exemplary embodiment. In this example, the opto-electric conversion element 333 of the unit pixel 310 has a generally rectangular shape. However, according to further embodiments of the present disclosure, the opto-electric conversion element 333 can have any other shape, including but not limited to a hexagonal, an elliptical, or a circular shape. Also in this example, all of the circuit elements associated with the address event detection unit or readout circuit 400 are positioned adjacent to one side (the top side in Figure 13 ) of the opto-electric conversion element 333, while some of the circuit elements associated with the pixel imaging signal generation unit or readout circuit 320 are positioned adjacent to the top side of the opto-electric conversion element 333, other components of the pixel imaging signal generation readout circuit 320 are positioned adjacent to the opposite side (the bottom side in Figure 13 ​The bottom side) adjacent. As used herein, terms such as "top" and "bottom" are used to illustrate the relative position of components in the figures and are not intended to necessarily imply the absolute position of the components. The components of the unit pixel 310 are positioned within a pixel area 311 bounded by the isolation structure 1208. In this example, the pixel area 311 has a rectangular shape, however other shapes are possible.

[0125] In this second example embodiment, the circuit elements of the pixel imaging signal generation readout circuit 320 for the unit pixel 310 positioned within the pixel area 311 include a reset transistor 321, a floating diffusion layer 324, an amplification transistor 322, and a selection transistor 323. The circuit elements of the address event detection readout circuit 400 for the unit pixel 310 positioned within the pixel area 311 include a first logarithmic transistor 411 and a second logarithmic transistor 414, and a first amplification transistor 412 and a second amplification transistor 413. The pixel imaging signal generation readout circuit 320 is connected to the photoelectric conversion element 333 through a first transfer transistor 331, while the address event detection readout circuit 400 is connected to the photoelectric conversion element 333 through a second transfer transistor 332. The first transfer transistor 331 and the second transfer transistor 332 are also positioned within the pixel area 311.

[0126] The first transfer transistor 331 in the second example embodiment is formed at a position corresponding to a first portion or corner of the photoelectric conversion element 333 formed by a first side (top side in Figure 13 and a second side (right side in Figure 13 of the photoelectric conversion element 333. The second transfer transistor 332 is formed at a position corresponding to a second portion or corner of the photoelectric conversion element 333 formed by the first side and a third side (left side in Figure 13 of the photoelectric conversion element 333.

[0127] Figure 14 is a plan view of a portion of a pixel array unit 300 including a group 314 of unit pixels 310 constructed in accordance with the second example embodiment, respectively. More specifically, the unit pixels 310 of the pixel group 314 include a 2x2 subarray of a first unit pixel 310 (unit pixel 310.1), a second unit pixel 310 (unit pixel 310.2), a third unit pixel 310 (unit pixel 310.3), and a fourth unit pixel 310 (unit pixel 310.4). In accordance with at least some embodiments of the present disclosure, the group 314 of unit pixels 310 can be constructed as a pixel group 314 constructed in a pattern 310A that includes a collection of unit pixels 310 that receive different wavelength components. As Figure 14As shown, there is no sharing of circuit elements shown as included in each individual unit pixel 310. Instead, isolation structures 1208 disposed around each unit pixel region 311 separate the unit pixels 310 from one another. As shown, when the unit pixels 310 are grouped into a group 314, the isolation structures between adjacent unit pixels 310 can be shared such that the isolation structures 1208 that define one side of a first unit pixel (e.g., unit pixel 310.1) can also define one side of an adjacent unit pixel (e.g., unit pixel 310.2). According to embodiments of the present disclosure, the isolation structures 1208 can be in the form of a full thickness dielectric trench isolation or a simple full thickness trench isolation (RFTI) structure.

[0128] Figure 15 is a plan view of a pixel configuration according to a third exemplary embodiment of the present disclosure, Figure 16 is a plan view of a portion of a pixel array including groups of pixels configured as in the third exemplary embodiment. More specifically, Figure 15 is a top view illustrating an exemplary configuration of a unit pixel 310 according to the third exemplary embodiment. As in the second embodiment, the photoelectric conversion element 333 of the unit pixel 310 in this third embodiment has a generally rectangular shape, although other shapes are possible. However, in this third exemplary configuration, the arrangement of the components of the unit pixel 310 differs from that of the second embodiment. This alternative configuration can simplify the wiring required to interconnect the various circuit elements of the unit pixel 310. Specifically, in this third exemplary embodiment, the circuit elements associated with the pixel imaging signal generation unit or readout circuit 320 are positioned adjacent to one side of the photoelectric conversion element 333 (the top side in Figure 15 ). The first pair of logarithmic transistors 411 of the address event detection unit or readout circuit 400 are positioned on the same side of the photoelectric conversion element as the circuit elements of the pixel imaging signal generation readout circuit 320. The amplification transistors 412 and 413 of the address event detection readout circuit 400 are positioned adjacent to the other, opposite side of the photoelectric conversion element 333 (the bottom side in Figure 15 ). The second pair of logarithmic transistors 414 of the address event detection readout circuit 400 are positioned adjacent to one side of the photoelectric conversion element 333 (the left side in Figure 15 ). The components of the unit pixel 310 are placed within the pixel region 311 bounded by the isolation structures 1208. In this example, the pixel region 311 has a rectangular shape, although other shapes are possible.

[0129] In this third embodiment, the circuit elements of the pixel-imaging signal generation readout circuit 320 for the unit pixel 310 positioned within the pixel region 311 include a reset transistor 321, a floating diffusion 324, an amplification transistor 322, and a selection transistor 323. The circuit elements of the address-event detection readout circuit 400 for the unit pixel 310 positioned within the pixel region 311 include a first logarithmic transistor 411 and a second logarithmic transistor 414, and a first amplification transistor 412 and a second amplification transistor 413. The pixel-imaging signal generation readout circuit 320 is connected to the photoelectric conversion element 333 through a first transfer transistor 331, while the address-event detection readout circuit 400 is connected to the photoelectric conversion element 333 through a second transfer transistor 332. The first transfer transistor 331 and the second transfer transistor 332 are also positioned within the pixel region 311.

[0130] In this third exemplary embodiment, the first transfer transistor 331 is formed at a position corresponding to a first portion or corner of the photoelectric conversion element 333 formed by a first side (top side in Figure 15 Figure 15 the second side (right side in Figure 15 ).

[0131] Figure 16 is a plan view of a portion of a pixel array unit 300 including a group 314 of unit pixels 310 constructed in accordance with the third exemplary embodiment, respectively. More specifically, the unit pixels 310 of the pixel group 314 include a 2x2 subarray of a first unit pixel 310 (unit pixel 310.1), a second unit pixel 310 (unit pixel 310.2), a third unit pixel 310 (unit pixel 310.3), and a fourth unit pixel 310 (unit pixel 310.4). According to at least some embodiments of the present disclosure, the group 314 of unit pixels 310 can be constructed as a pixel group 314 constructed in a pattern 310A including a collection of unit pixels 310 that receive different wavelength components. As Figure 16 ​As shown, there is no sharing of circuit elements shown as included in each individual unit pixel 310. Instead, isolation structures 1208 disposed around each unit pixel region 311 separate the unit pixels 310 from one another. As shown, when the unit pixels 310 are grouped into a group 314, the isolation structures between adjacent unit pixels 310 can be shared such that the isolation structures 1208 that define one side of a first unit pixel (e.g., unit pixel 310.1) can also define one side of an adjacent unit pixel (e.g., unit pixel 310.2). According to embodiments of the present disclosure, the isolation structures 1208 can be in the form of a full thickness dielectric trench isolation or a simple full thickness trench isolation (RFTI) structure.

[0132] Figure 17 is a plan view of a pixel configuration according to a fourth exemplary embodiment of the present disclosure, Figure 18 is a plan view of a portion of a pixel array including groups of pixels configured as in the fourth exemplary embodiment. More specifically, Figure 17 is a top view illustrating an exemplary configuration of a unit pixel 310 according to the fourth exemplary embodiment. As in the second and third embodiments, the photoelectric conversion element 333 of the unit pixel 310 in this fourth embodiment has a generally rectangular shape, although other shapes are possible. However, the circuit elements of the address event detection readout circuit 400 of this fourth exemplary configuration include two transistors, whereas the first, second, and third exemplary embodiments feature an address event detection readout circuit 400 that includes four transistors. The two-transistor configuration allows for a larger area for the photoelectric conversion element 333 within a given pixel region 311 compared to the embodiments incorporating the four-transistor address event detection readout circuit 400. However, the gain of the two-transistor arrangement can be less than the four-transistor configuration. In this fourth exemplary embodiment, all of the circuit elements associated with the address event detection readout circuit 400 are positioned adjacent to one side of the photoelectric conversion element 333 (the top side in Figure 17 , whereas some of the circuit elements associated with the pixel imaging signal generation readout circuit 320 are positioned adjacent to the top side of the photoelectric conversion element 333, and other components of the pixel imaging signal generation readout circuit 320 are positioned adjacent to the opposite side of the photoelectric conversion element 333 (the bottom side in Figure 17 . The components of the unit pixel 310 are positioned within the pixel region 311 as bounded by the isolation structures 1208. In this example, the pixel region 311 has a rectangular shape, although other shapes are possible.

[0133] In this fourth embodiment, the circuit elements of the pixel-imaging signal generation readout circuit 320 for the unit pixel 310 positioned within the pixel region 311 include a reset transistor 321, a floating diffusion 324, an amplification transistor 322, and a selection transistor 323. The circuit elements of the address-event detection readout circuit 400 for the unit pixel 310 positioned within the pixel region 311 include a first logarithmic transistor 411 and a first amplification transistor 413. The pixel-imaging signal generation readout circuit 320 is connected to the photoelectric conversion element 333 through a first transfer transistor 331, while the address-event detection readout circuit 400 is connected to the photoelectric conversion element 333 through a second transfer transistor 332. The first transfer transistor 331 and the second transfer transistor 332 are also positioned within the pixel region 311.

[0134] In this fourth exemplary embodiment, the first transfer transistor 331 is formed at a position corresponding to a first portion or corner of the photoelectric conversion element 333 formed by a first side (top side in Figure 17 Figure 17 In this fourth exemplary embodiment, the first transfer transistor 331 is formed at a position corresponding to a first portion or corner of the photoelectric conversion element 333 formed by a first side (top side in Figure 17

[0135] Figure 18 is a plan view of a portion of a pixel array unit 300 including a group 314 of unit pixels 310 constructed in accordance with the fourth exemplary embodiment, respectively. More specifically, the unit pixels 310 of the pixel group 314 include a 2x2 subarray of a first unit pixel 310 (unit pixel 310.1), a second unit pixel 310 (unit pixel 310.2), a third unit pixel 310 (unit pixel 310.3), and a fourth unit pixel 310 (unit pixel 310.4). According to at least some embodiments of the present disclosure, the group 314 of unit pixels 310 can be constructed as a pixel group 314 constructed in a pattern 310A that includes a collection of unit pixels 310 that receive different wavelength components. As Figure 18 ​​As shown, there is no sharing of circuit elements shown as included in each individual unit pixel 310. Instead, isolation structures 1208 disposed around each unit pixel region 311 separate the unit pixels 310 from one another. As shown, when the unit pixels 310 are grouped into a group 314, the isolation structures between adjacent unit pixels 310 can be shared such that an isolation structure 1208 defining a side of a first unit pixel (e.g., unit pixel 310.1) can also define a side of an adjacent unit pixel (e.g., unit pixel 310.2). According to embodiments of the present disclosure, the isolation structures 1208 can be in the form of a full thickness dielectric trench isolation or a simple full thickness trench isolation (RFTI) structure.

[0136] Figure 19 is a plan view of a pixel configuration according to a fifth exemplary embodiment of the present disclosure, Figure 20 is a plan view of a portion of a pixel array including groups of pixels configured as in the fifth exemplary embodiment. More specifically, Figure 19 is a top view illustrating an exemplary configuration of a unit pixel 310 according to the fifth exemplary embodiment. As in the second, third, and fourth embodiments, the photoelectric conversion element 333 of the unit pixel 310 in this fifth embodiment has a generally rectangular shape, although other shapes are possible. As in the fourth example, the circuit elements of the address event detection readout circuit 400 of this fifth exemplary configuration include two transistors. In this fifth exemplary embodiment, all of the circuit elements associated with the pixel imaging signal generation readout circuit 320 are positioned adjacent to the top side of the photoelectric conversion element 333, while all of the circuit elements associated with the address event detection readout circuit 400 are positioned adjacent to the opposite or bottom side of the photoelectric conversion element 333. The components of the unit pixel 310 are positioned within a pixel region 311 bounded by isolation structures 1208. In this example, the pixel region 311 has a rectangular shape, although other shapes are possible.

[0137] In this fifth embodiment, the circuit elements of the pixel imaging signal generation readout circuit 320 of the unit pixel 310 positioned within the pixel region 311 include a reset transistor 321, a floating diffusion 324, an amplification transistor 322, and a selection transistor 323. The circuit elements of the address event detection readout circuit 400 of the unit pixel 310 positioned within the pixel region 311 include a first logarithmic transistor 411 and a first amplification transistor 413. The pixel imaging signal generation readout circuit 320 is connected to the photoelectric conversion element 333 by a first transfer transistor 331, while the address event detection readout circuit 400 is connected to the photoelectric conversion element 333 by a second transfer transistor 332. The first transfer transistor 331 and the second transfer transistor 332 are also positioned within the pixel region 311.

[0138] In this fifth exemplary embodiment, the first transfer transistor 331 is formed at a position corresponding to a first portion or corner of the photoelectric conversion element 333 formed by a first side (top side in Figure 19 ) and a second side (right side in Figure 19 ) of the photoelectric conversion element 333. The second transfer transistor 332 is formed at a position corresponding to a second portion or corner of the photoelectric conversion element 333 formed by a third side (left side in Figure 19 ) and a fourth side (bottom side in Figure 19 ) of the photoelectric conversion element 333.

[0139] Figure 20 is a plan view of a portion of a pixel array unit 300 including a group 314 of unit pixels 310 constructed in accordance with the fifth exemplary embodiment, respectively. More specifically, the unit pixels 310 of the group 314 include a 2x2 subarray of a first unit pixel 310 (unit pixel 310.1), a second unit pixel 310 (unit pixel 310.2), a third unit pixel 310 (unit pixel 310.3), and a fourth unit pixel 310 (unit pixel 310.4). In accordance with at least some embodiments of the present disclosure, the group 314 of unit pixels 310 can be constructed as a group 314 of pixels constructed in a pattern 310A including a collection of unit pixels 310 that receive different wavelength components. As shown, there is no sharing of circuit elements shown as included in each individual unit pixel 310. Instead, isolation structures 1208 disposed around each unit pixel region 311 separate the unit pixels 310 from one another. Also as shown, when the unit pixels 310 are grouped into a group 314, the isolation structures between adjacent unit pixels 310 can be shared such that an isolation structure 1208 defining a side of a first unit pixel (e.g., unit pixel 310.1) can also define a side of an adjacent unit pixel (e.g., unit pixel 310.2). In accordance with embodiments of the present disclosure, the isolation structures 1208 can be in the form of a full thickness dielectric trench isolation or a simple full thickness trench isolation (RFTI) structure. Figure 20

[0140] Figure 21 is a plan view of a pixel configuration in accordance with a sixth exemplary embodiment of the present disclosure, Figure 22 is a plan view of a portion of a pixel array including a group of pixels constructed as in the sixth exemplary embodiment. More specifically, Figure 21 ​is a top view illustrating a schematic configuration example of a unit pixel 310 according to a sixth exemplary embodiment. As in the second, third, fourth, and fifth embodiments, the photoelectric conversion element 333 of the unit pixel 310 in this sixth embodiment has a substantially rectangular shape, although other shapes are also possible. As in the fourth and fifth examples, the circuit elements of the address event detection readout circuit 400 of this sixth exemplary configuration include two transistors. In this sixth exemplary embodiment, all of the circuit elements associated with the address event detection readout circuit 400 are positioned adjacent to the left side of the photoelectric conversion element 333, while the circuit elements associated with the pixel imaging signal generation readout circuit 320 are positioned adjacent to the right and bottom sides of the photoelectric conversion element 333. The components of the unit pixel 310 are positioned within a pixel region 311 bounded by the isolation structure 1208. In this example, the pixel region 311 has a rectangular shape, although other shapes are also possible.

[0141] In this sixth embodiment, the circuit elements of the pixel imaging signal generation readout circuit 320 of the unit pixel 310 positioned within the pixel region 311 include a reset transistor 321, a floating diffusion layer 324, an amplification transistor 322, and a selection transistor 323. The circuit elements of the address event detection readout circuit 400 of the unit pixel 310 positioned within the pixel region 311 include a first logarithmic transistor 411 and a first amplification transistor 413. The pixel imaging signal generation readout circuit 320 is connected to the photoelectric conversion element 333 through a first transfer transistor 331, while the address event detection readout circuit 400 is connected to the photoelectric conversion element 333 through a second transfer transistor 332. The first transfer transistor 331 and the second transfer transistor 332 are also positioned within the pixel region 311.

[0142] In this sixth exemplary embodiment, the first transfer transistor 331 is positioned along a portion of one side of the photoelectric conversion element 333 (the right side in Figure 21 ). The second transfer transistor 332 is positioned along a portion of the other side of the photoelectric conversion element 333 (the left side in Figure 21 ).

[0143] Figure 22is a plan view of a portion of a pixel array including groups 314 of unit pixels 310 constructed according to the sixth example embodiment, respectively. More specifically, the group 314 of unit pixels 310 includes a 2x2 subarray of first unit pixels 310 (unit pixels 310.1), second unit pixels 310 (unit pixels 310.2), third unit pixels 310 (unit pixels 310.3), and fourth unit pixels 310 (unit pixels 310.4). According to at least some embodiments of the present disclosure, the group 314 of unit pixels 310 can be constructed as a group 314 of pixels constructed in a pattern 310A including a collection of unit pixels 310 that receive different wavelength components. As shown, Figure 22 there is no sharing of circuit elements shown as included in each individual unit pixel 310. Instead, isolation structures 1208 disposed around each unit pixel region 311 separate the unit pixels 310 from one another. Also as shown, when unit pixels 310 are grouped into groups 314, isolation structures between adjacent unit pixels 310 can be shared such that an isolation structure 1208 defining one side of a first unit pixel (e.g., unit pixel 310.1) can also define one side of an adjacent unit pixel (e.g., unit pixel 310.2). According to embodiments of the present disclosure, the isolation structures 1208 can be in the form of full thickness dielectric trench isolation or simply a full thickness trench isolation (RFTI) structure.

[0144] Figure 23 is a plan view of a pixel construction according to a seventh example embodiment of the present disclosure, Figure 24 is a plan view of a portion of a pixel array including groups of pixels constructed as in the seventh example embodiment. More specifically, Figure 23 is a top view illustrating an example of a schematic construction of a unit pixel 310 according to the seventh example embodiment. In this example, the opto-electric conversion element 333 of the unit pixel 310 has a generally rectangular shape. However, according to further embodiments of the present disclosure, the opto-electric conversion element 333 can have any other shape including, but not limited to, a hexagonal, an elliptical, or a circular shape. Also in this example, all of the circuit elements associated with the address event detection unit or readout circuit 400 are positioned adjacent to one side (the top side in Figure 23 ) of the opto-electric conversion element 333, while some of the circuit elements associated with the pixel imaging signal generation unit or readout circuit 320 are positioned adjacent to the top side of the opto-electric conversion element 333, other components of the pixel imaging signal generation readout circuit 320 are positioned adjacent to the opposite side (the bottom side in Figure 23 ) of the opto-electric conversion element 333. The components of the unit pixel 310 are placed within a pixel region 311 bounded by isolation structures 1208. In this example, the pixel region 311 has a rectangular shape, however other shapes are possible.

[0145] In this seventh exemplary embodiment, the circuit elements of the pixel-imaging-signal-generating readout circuit 320 of the unit pixel 310 positioned within the pixel region 311 include a reset transistor 321, a floating diffusion layer 324, an amplification transistor 322, and a selection transistor 323. The circuit elements of the address-event-detection readout circuit 400 of the unit pixel 310 positioned within the pixel region 311 include a first logarithmic transistor 411 and a second logarithmic transistor 414, and a first amplification transistor 412 and a second amplification transistor 413. The pixel-imaging-signal-generating readout circuit 320 is connected to the photoelectric conversion element 333 through a first transfer transistor 331, while the address-event-detection readout circuit 400 is connected to the photoelectric conversion element 333 through a second transfer transistor 332. The first transfer transistor 331 and the second transfer transistor 332 are also positioned within the pixel region 311.

[0146] The first transfer transistor 331 in the seventh exemplary embodiment is formed at a position corresponding to a first portion or a corner of the photoelectric conversion element 333 formed by a first side (top side in Figure 23 ) and a second side (right side in Figure 23 ) of the photoelectric conversion element 333. In addition, the first transfer transistor 331 is a P-type MOS transistor. The second transfer transistor 332 is formed at a position corresponding to a second portion or a corner of the photoelectric conversion element 333 formed by a first side and a third side (left side in Figure 23The second transfer transistor 332 is an N-type MOS transistor. The transfer gate of the first transfer transistor 331 can be electrically connected to the transfer gate of the second transfer transistor 332 through a joint signal line 2301. This configuration allows the first and second transfer transistors 331, 332 to be operated by a single signal line. More specifically, in response to a first signal provided by the joint signal line 2301, a first one of the first and second transfer transistors 331, 332 can be placed in an on state, while a second one of the first and second transfer transistors 331, 332 can be placed in an off state. Conversely, in response to a second signal provided by the joint signal line 2301, the first one of the first and second transfer transistors 331, 332 can be placed in an off state, while the second one of the first and second transfer transistors 331, 332 can be placed in an on state. The unit pixel 310 as configured in this seventh exemplary embodiment can provide increased switching speed between the event detection mode and the imaging mode. According to further embodiments of the present disclosure, by providing separate signal lines to the first and second transfer transistors 331, 332, the imaging mode and the DVS mode can be used simultaneously. As will be appreciated by those skilled in the art upon considering the present disclosure, in alternative configurations, the first transfer transistor 331 can be an N-type MOS transistor, while the second transfer transistor 332 can be a P-type MOS transistor. Further, as will be appreciated from the present disclosure, the overall layout of the unit pixel 310 in this seventh exemplary embodiment is similar to the second exemplary embodiment, except for the different composition of the first and second transfer transistors 331, 332. However, according to further embodiments of the present disclosure, other embodiments including the first and third through sixth exemplary embodiments can also feature one N-type transfer transistor 331 or 332 and one P-type transfer transistor 331 or 332 to achieve the advantage of simultaneous operation in the imaging mode and the DVS mode or to enhance the switching speed between the above-mentioned modes. As will be appreciated by those skilled in the art upon considering the present disclosure, in the case where the transfer transistor 331 or 332 is of a particular type, the type of the other associated readout transistor should be changed to match the type and thus address the carriers read by the transfer transistor 331 or 332.

[0147] Figure 24is a plan view of a portion of a pixel array unit 300 that includes a group 314 of unit pixels 310 constructed in accordance with the seventh example embodiment, respectively. More specifically, the unit pixels 310 of the pixel group 314 include a 2x2 subarray of first unit pixels 310 (unit pixels 310.1), second unit pixels 310 (unit pixels 310.2), third unit pixels 310 (unit pixels 310.3), and fourth unit pixels 310 (unit pixels 310.4). According to at least some embodiments of the present disclosure, the group 314 of unit pixels 310 can be constructed as a pixel group 314 constructed in a pattern 310A that includes a collection of unit pixels 310 that receive different wavelength components. As shown, there is no sharing of circuit elements shown as included in each individual unit pixel 310. Instead, isolation structures 1208 disposed around each unit pixel region 311 separate the unit pixels 310 from one another. As shown, when the unit pixels 310 are grouped into the group 314, the isolation structures between adjacent unit pixels 310 can be shared such that the isolation structures 1208 that define one side of a first unit pixel (e.g., unit pixel 310.1) can also define one side of an adjacent unit pixel (e.g., unit pixel 310.2). According to embodiments of the present disclosure, the isolation structures 1208 can be in the form of a full thickness dielectric trench isolation or a simple full thickness trench isolation (RFTI) structure. Figure 24

[0148] In an imaging mode, the first transfer transistor 331 associated with the photoelectric conversion element 333 of one or more unit pixels 310 within the pixel array unit 300 is placed in a conductive state (e.g., an on state) to operably connect the photoelectric conversion element 333 to the floating diffusion layer 324 of the pixel imaging signal generation readout circuit 320. In an event detection or dynamic vision sensor (DVS) mode, the second transfer transistor 332 associated with the photoelectric conversion element 333 of one or more unit pixels is placed in a conductive state to operably connect the selected photoelectric conversion element 333 to the address event detection readout circuit 400.

[0149] In at least some modes of operation, the second transfer transistor 332 of the selected unit pixel 310 remains open (e.g., in a cutoff state) during imaging operations, and the first transfer transistor 331 remains open during event detection mode. As can be further appreciated by those skilled in the art after considering the present disclosure, the turning on of the first transfer transistor 331, the turning off of the second transfer transistor 332, and the operation of the pixel imaging signal generation readout circuit 320 can be triggered by the address event detection readout circuit 400 detecting an event.

[0150] ​In at least some other operation modes, particularly in the case where the first transfer transistor 331 is configured as a P-type MOS transistor and the second transfer transistor 332 is configured as an N-type MOS transistor, it is possible to simultaneously supply hole carriers to the pixel imaging signal generation readout circuit 320 and to supply electrons to the address event detection readout circuit 400. Alternatively, in the case where the first transfer transistor 331 is configured as an N-type MOS transistor and the second transfer transistor 332 is configured as a P-type MOS transistor, it is possible to simultaneously supply electrons to the pixel imaging signal generation readout circuit 320 and to supply hole carriers to the address event detection readout circuit 400. According to yet another operation mode, particularly in the case where the signal line 2301 is set to electrically connect the first transfer transistor 331 and the second transfer transistor 332, a first one of the first transfer transistor 331 and the second transfer transistor 332 is configured as a P-type MOS transistor, and a second one of the first transfer transistor 331 and the second transfer transistor 332 is configured as an N-type MOS transistor, it is possible to perform switching between the imaging mode and the DVS mode at high speed using a single switching signal supplied to the first transfer transistor 331 and the second transfer transistor 332.

[0151] Accordingly, the embodiments of the present disclosure provide the unit pixel 310 of the imaging device 100 capable of performing the event detection operation and the imaging operation. Furthermore, because the circuit elements of any one unit pixel 310 are separated from the circuit elements of any other unit pixel 310, it is possible to achieve an improvement in image quality compared to a configuration in which such separation between the unit pixels 310 is not provided.

[0152] According to the embodiments of the present disclosure, the isolation structure 1208 can be in the form of an RFTI structure. The isolation structure 1208 extends through an entire thickness of the substrate 402 of the light-receiving chip 201 in which the photodiode 333 of the unit pixel 310 is formed. That is, according to at least some embodiments of the present disclosure, the isolation structure 1208 extends from at least a first light-incident surface 403 of the substrate 402 of the light-receiving chip 201 to a second non-light-incident surface 404 of the substrate 402 of the light-receiving chip 201. Accordingly, it is possible to achieve excellent isolation between adjacent unit pixels.

[0153] Figure 25 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure is applicable.

[0154] The vehicle control system 12000 includes a plurality of electronic control units connected to each other through a communication network 12001. In the vehicle control system 12000, the plurality of electronic control units are connected to each other through the communication network 12001, and the plurality of electronic control units share information and cooperate with each other. Figure 25In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and a comprehensive control unit 12050. In addition, as a functional configuration of the comprehensive control unit 12050, a microcomputer 12051, a sound image output unit 12052, and a vehicle-mounted network I / F (interface) 12053 are illustrated in the drawing.

[0155] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generation device, such as an internal combustion engine and a drive motor, for generating a drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to wheels, a steering mechanism for adjusting a steering angle of the vehicle, and a brake device for generating a brake force of the vehicle, and the like.

[0156] The body system control unit 12020 controls the operation of various devices mounted to the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, and various lamps such as a headlamp, a tail lamp, a brake lamp, a blinker, and a fog lamp. In this case, an electric wave transmitted from a portable device that substitutes for a key or a signal of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input of the electric wave or the signal, and controls a door lock device, a power window device, and a lamp, and the like of the vehicle.

[0157] The vehicle exterior information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 can perform an object detection process or a distance detection process of a person, a vehicle, an obstacle, a sign, or a character on a road, and the like, on the basis of the received image.

[0158] The imaging unit 12031 is a light sensor that receives light and outputs an electric signal corresponding to the amount of light received. The imaging unit 12031 can output the electric signal as an image or ranging information. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared rays. Furthermore, the imaging unit 12031 can include a solid-state imaging device 200 incorporating a pixel array unit 300 according to an embodiment of the present disclosure, the pixel array unit 300 having a unit pixel 310 configured to be isolated from other unit pixels 310 within the pixel array unit 300.

[0159] The vehicle interior information detection unit 12040 detects vehicle interior information. For example, a driver state detection unit 12041 that detects a driver state is connected to the vehicle interior information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that images the driver, and the vehicle interior information detection unit 12040 can calculate the degree of fatigue of the driver or the degree of concentration of the driver, or can determine whether the driver is dozing based on detection information input from the driver state detection unit 12041.

[0160] The microcomputer 12051 calculates a control target value of a driving force generation device, a steering mechanism, or a braking device based on vehicle exterior information or interior information acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing functions of an advanced driver assistance system (ADAS: advanced driver assistance system) including collision avoidance or impact mitigation of the vehicle, following travel based on an inter-vehicle distance, vehicle constant speed travel, vehicle collision warning, and vehicle lane departure warning, and the like.

[0161] In addition, the microcomputer 12051 can perform cooperative control for automatic driving or the like in which the vehicle autonomously travels without depending on the operation of the driver, by controlling the driving force generation device, the steering mechanism, the braking device, and the like based on information in the vicinity of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040.

[0162] The microcomputer 12051 can output a control command to the body system control unit 12020 based on vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control to realize glare protection such as switching a high beam to a low beam, by controlling a headlamp in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0163] The sound image output unit 12052 transmits an output signal of at least one of a sound and an image to an output device that is capable of visually or aurally notifying a passenger in the vehicle or outside the vehicle of information. In Figure 25 In the example, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified. The display unit 12062 can include at least one of a vehicle-mounted display and a head-up display, for example.

[0164] Figure 26 is a view that illustrates an example of a mounting position of the imaging unit 12031.

[0165] In Figure 26 In the example, as the imaging unit 12031, an imaging unit 12101, 12102, 12103, 12104, and 12105 are provided.

[0166] The imaging units 12101, 12102, 12103, 12104, and 12105 are mounted at positions such as a front nose, a side mirror, a rear bumper, a rear door, and an upper side of a windshield in a cabin of the vehicle 12100, for example. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper side of the windshield in the cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirror mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the rear door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper side of the windshield in the cabin can be mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, and the like.

[0167] Further, Figure 26 An example of a photographing range of the imaging units 12101 to 12104 is illustrated. A photographing range 12111 represents a photographing range of the imaging unit 12101 provided in the front nose, photographing ranges 12112 and 12113 respectively represent photographing ranges of the imaging units 12102 and 12103 provided in the side mirror, and a photographing range 12114 represents a photographing range of the imaging unit 12104 provided in the rear bumper or the rear door. When a plurality of image data captured by the imaging units 12101 to 12104 are superimposed on each other, for example, a bird's-eye view image when the vehicle 12100 is viewed from above can be obtained.

[0168] At least one of the imaging units 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 can be a stereo camera including a plurality of imaging elements, or can be an imaging element including pixels for phase difference detection.

[0169] For example, the microcomputer 12051 can obtain distances between respective three-dimensional objects in the imaging ranges 12111 to 12114 and changes in the distances over time (relative to the speed of the vehicle 12100) on the basis of the distance information obtained from the imaging units 12101 to 12104, to extract, as a preceding vehicle, a three-dimensional object that is closest among the three-dimensional objects, in particular, on a travel path of the vehicle 12100, and that travels in an approximately same direction as a direction in which the vehicle 12100 travels at a predetermined speed (e.g., 0 km / h or more). In addition, the microcomputer 12051 can be able to set a vehicle-to-vehicle distance to be maintained ahead of a preceding vehicle in advance, to perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up acceleration control), and the like. As described above, cooperative control for automatic driving and the like in which a vehicle autonomously travels without depending on an operation of a driver can be performed.

[0170] For example, the microcomputer 12051 can extract three-dimensional object data related to three-dimensional objects by classifying a plurality of three-dimensional object data into two-wheeled vehicle data, standard vehicle data, large vehicle data, pedestrian data, and other three-dimensional object data such as a utility pole on the basis of distance information obtained from the imaging units 12101 to 12104, and can use the three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 discriminates obstacles in the periphery of the vehicle 12100 as obstacles that a driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 is difficult to visually recognize. In addition, the microcomputer 12051 determines a collision risk indicating a degree of danger of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and a collision is likely to occur, the microcomputer 12051 can assist driving by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062 or by performing forced deceleration or evasive steering via the drive system control unit 12010, to avoid the collision.

[0171] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 is able to recognize a pedestrian by judging whether or not a pedestrian is present in an image captured by the imaging units 12101 to 12104. For example, pedestrian recognition is performed by extracting a specific point in an image captured by the imaging units 12101 to 12104 that are infrared cameras, and performing pattern matching processing on a series of specific points that represent the outline of an object to judge whether or not the object is a pedestrian. When the microcomputer 12051 judges that a pedestrian is present on an image captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the sound image output unit 12052 controls the display unit 12062 to superimpose and display a quadrangular outline for emphasis on the recognized pedestrian. In addition, the sound image output unit 12052 can control the display unit 12062 to display an icon or the like that represents a pedestrian at a desired position.

[0172] In the foregoing, an explanation has been given of an example of a vehicle control system to which the technology according to the present disclosure is applicable. The technology according to the present disclosure is applicable to the imaging unit 12031 and the driver state detection unit 12041 and the like in the above-described configuration.

[0173] In the foregoing, an embodiment of the present disclosure has been explained, but the technical scope of the present disclosure is not limited to the above-described embodiment, but various modifications can be made without departing from the scope of the present disclosure. In addition, the constituent elements in other embodiments and modification examples can be appropriately combined.

[0174] In addition, the effects in the embodiments described in this specification are merely illustrative and there can be other effects without being limited.

[0175] Furthermore, the present technology can adopt the following configuration.

[0176] (1) An imaging device comprising:

[0177] a pixel array unit, wherein the pixel array unit comprises:

[0178] a plurality of pixels; and

[0179] an isolation structure, wherein each pixel of the plurality of pixels is separated from one or more neighboring pixels of the plurality of pixels by the isolation structure, and wherein each

[0180] a pixel comprises:

[0181] a photoelectric conversion region;

[0182] a first transfer transistor;

[0183] a second transfer transistor;

[0184] a first readout circuit selectively coupled to the photoelectric conversion region through the first transfer transistor; and

[0185] a second readout circuit selectively coupled to the photoelectric conversion region through the second transfer transistor.

[0186] (2) The imaging device of (1), wherein the second readout circuit is an address event detection readout circuit.

[0187] (3) The imaging device of (1) or (2), wherein the first readout circuit is an imaging signal generation readout circuit.

[0188] (4) The imaging device of any one of (1) to (3), wherein the pixel array unit includes a plurality of pixel groups, wherein each pixel of a first pixel group of the plurality of pixel groups is isolated from other pixels in the first pixel group.

[0189] (5) The imaging device of any one of (1) to (4), wherein the isolation structure is a dielectric structure.

[0190] (6) The imaging device of (5), wherein the dielectric structure surrounds each of the pixels within the first pixel group.

[0191] (7) The imaging device of (6), wherein the dielectric structure is a full-thickness dielectric trench.

[0192] (8) The imaging device of any one of (1) to (7), wherein the first readout circuit includes a floating diffusion, an amplification transistor, a selection transistor, and a reset transistor.

[0193] (9) The imaging device of any one of (1) to (8), wherein the second readout circuit includes a current-to-voltage conversion unit and a subtractor.

[0194] (10) The imaging device of any one of (1) to (8), wherein the second readout circuit includes a first logarithmic transistor and a first amplification transistor.

[0195] (11) The imaging device of any one of (1) to (8), wherein the second readout circuit includes a first logarithmic transistor, a second logarithmic transistor, a first amplification transistor, and a second amplification transistor.

[0196] (12) The imaging device of any of (1) to (11), wherein the first transfer gate of the first transfer transistor is a first of an N-type transfer gate and a P-type transfer gate, and wherein the second transfer gate of the second transfer transistor is a second of the N-type transfer gate and the P-type transfer gate.

[0197] (13) The imaging device of (12), wherein the photoelectric conversion region of at least a first pixel included in the plurality of pixels is selectively connected to the first readout circuit and the second readout circuit simultaneously.

[0198] (14) The imaging device of (12), further comprising:

[0199] a joint signal line, wherein the joint signal line electrically connects the first transfer gate to the second transfer gate.

[0200] (15) The imaging device of any of (1) to (14), wherein, for each pixel, all components of the first readout circuit are formed in a first half of the pixel, and all components of the second readout circuit are formed in a second half of the pixel.

[0201] (16) The imaging device of any of (1) to (15), wherein the photoelectric conversion region includes a plurality of sides in plan view, wherein a first transfer gate is positioned along a first side of the photoelectric conversion region, and wherein a second transfer gate is positioned along a second side of the photoelectric conversion region.

[0202] (17) The imaging device of (4), wherein each pixel group further includes a first unit pixel, a second unit pixel, a third unit pixel, and a fourth unit pixel, and wherein the first unit pixel, the second unit pixel, the third unit pixel, and the fourth unit pixel are arranged in a 2x2 array.

[0203] (18) The imaging device of any of (1) to (17), wherein the isolation structure defines a pixel region for each of the pixels, and wherein circuit elements of each pixel are separated from circuit elements of any adjacent pixel in the pixel array unit by the isolation structure.

[0204] (19) The imaging device of any of (1) to (18), wherein the isolation structure is entirely a full-thickness trench isolation structure.

[0205] (20) An electronic device comprising:

[0206] an imaging lens; and

[0207] A solid-state imaging device, the solid-state imaging device comprising:

[0208] a pixel array unit, wherein the pixel array unit includes:

[0209] a plurality of pixels; and

[0210] an isolation structure, wherein each pixel of the plurality of pixels is separated from one or more adjacent pixels of the plurality of pixels by the isolation structure, and wherein each pixel includes:

[0211] a photoelectric conversion region;

[0212] a first transfer transistor;

[0213] a second transfer transistor;

[0214] a first readout circuit selectively coupled to the photoelectric conversion region through the first transfer transistor; and

[0215] a second readout circuit selectively coupled to the photoelectric conversion region through the second transfer transistor; and

[0216] a control unit, wherein the control unit controls an operation of the solid-state imaging device.

[0217] It will be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations can occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. An imaging device comprising: A pixel array unit, wherein the pixel array unit comprises: Multiple pixels; and An isolation structure, wherein each of the plurality of pixels is separated from one or more neighboring pixels of the plurality of pixels by the isolation structure, and wherein each pixel includes: Photoelectric conversion region; First transmission transistor; Second transmission transistor; A first readout circuit, which is selectively coupled to the photoelectric conversion region via the first transfer transistor; and The second readout circuit is selectively coupled to the photoelectric conversion region via the second transmission transistor. In the planar view, for each pixel, all components of the first readout circuit are formed in the first half of the pixel, and the first logarithmic transistor and the first amplifying transistor of the second readout circuit are formed in the second half of the pixel. The second readout circuit is an address event detection readout circuit, and The first readout circuit is an imaging signal generation and readout circuit.

2. The imaging apparatus as claimed in claim 1, wherein, The pixel array unit includes multiple pixel groups, wherein each pixel of the first pixel group is isolated from the other pixels in the first pixel group.

3. The imaging apparatus as claimed in claim 2, wherein, The isolation structure is a dielectric structure.

4. The imaging apparatus as claimed in claim 3, wherein, The dielectric structure surrounds each of the pixels within the first pixel group.

5. The imaging apparatus as claimed in claim 4, wherein, The dielectric structure is a full-thickness dielectric trench.

6. The imaging apparatus as claimed in claim 1, wherein, The first readout circuit includes a floating diffusion layer, an amplifying transistor, a selection transistor, and a reset transistor.

7. The imaging apparatus of claim 6, wherein, The second readout circuit includes a current-to-voltage conversion unit and a subtractor. The current-to-voltage conversion unit includes the first logarithmic transistor and the first amplifying transistor.

8. The imaging apparatus of claim 6, wherein, The second readout circuit further includes a second logarithmic transistor and a second amplifying transistor, and the second logarithmic transistor and the second amplifying transistor are formed in the second half of the pixel.

9. The imaging apparatus as claimed in claim 1, wherein, The first transmission gate of the first transmission transistor is a first of an N-type transmission gate and a P-type transmission gate, and the second transmission gate of the second transmission transistor is a second of the N-type transmission gate and the P-type transmission gate.

10. The imaging apparatus of claim 9, wherein, The photoelectric conversion region of at least the first pixel included in the plurality of pixels is selectively connected simultaneously to both the first readout circuit and the second readout circuit.

11. The imaging apparatus of claim 9, further comprising: A combined signal line, wherein the combined signal line electrically connects the first transmission gate to the second transmission gate.

12. The imaging apparatus of claim 1, wherein, The photoelectric conversion region includes multiple sides in the plan view, wherein a first transmission gate is positioned along a first side of the photoelectric conversion region, and wherein a second transmission gate is positioned along a second side of the photoelectric conversion region.

13. The imaging apparatus of claim 2, wherein, Each pixel group also includes a first unit pixel, a second unit pixel, a third unit pixel, and a fourth unit pixel, wherein the first unit pixel, the second unit pixel, the third unit pixel, and the fourth unit pixel are arranged in a 2×2 array.

14. The imaging apparatus of claim 1, wherein, The isolation structure defines a pixel region for each pixel, and wherein the circuit elements of each pixel are separated from the circuit elements of any neighboring pixels in the pixel array unit by the isolation structure.

15. The imaging apparatus according to any one of claims 1 to 14, wherein, The isolation structure is a full-thickness trench isolation structure.

16. An electronic device comprising: Imaging lens; and Solid-state imaging device, the solid-state imaging device comprising: A pixel array unit, wherein the pixel array unit comprises: Multiple pixels; and An isolation structure, wherein each of the plurality of pixels is separated from one or more neighboring pixels of the plurality of pixels by the isolation structure, and wherein each pixel includes: Photoelectric conversion region; First transmission transistor; Second transmission transistor; A first readout circuit, which is selectively coupled to the photoelectric conversion region via the first transfer transistor; and A second readout circuit is selectively coupled to the photoelectric conversion region via the second transfer transistor; and A control unit, wherein the control unit controls the operation of the solid-state imaging device. In the planar view, for each pixel, all components of the first readout circuit are formed in the first half of the pixel, and the first logarithmic transistor and the first amplifying transistor of the second readout circuit are formed in the second half of the pixel. The second readout circuit is an address event detection readout circuit, and The first readout circuit is an imaging signal generation and readout circuit.

Images