Instruction management method, memory storage device and memory control circuit unit

Abstract

The present invention provides an instruction management method, a memory storage device, and a memory control circuit unit. The method includes: obtaining multiple instructions from a memory of a host system; storing the multiple instructions in a first buffer of the memory storage device; in response to a first instruction and a second instruction in the first buffer meeting a pairing condition, placing the first instruction and the second instruction in the first buffer into a first instruction queue of the memory storage device; and continuously executing the first instruction and the second instruction in the first instruction queue, thereby improving the operational stability of the memory storage device.

Description

Technical Field

[0001] The present invention relates to a memory control technology, and in particular to an instruction management method, a memory storage device and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have experienced rapid growth in recent years, leading to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideal for integration into various portable electronic devices, due to their non-volatility, power efficiency, compact size, and lack of mechanical structure.

[0003] In a host memory buffering (HMB) architecture, a memory storage device utilizes the host system's memory as a buffer for the memory storage device and can actively access the host system's memory for data. However, in practice, the cache space available for temporarily storing instructions in the memory storage device is limited. This can cause problems with subsequent operations of the memory storage device due to the limited instruction cache space. Summary of the Invention

[0004] In view of this, the present invention provides an instruction management method, a memory storage device, and a memory control circuit unit, which can improve the operation stability of the memory storage device.

[0005] An exemplary embodiment of the present invention provides a command management method for a memory storage device. The memory storage device is connected to a host system. The command management method includes: obtaining a plurality of commands from a memory of the host system; storing the plurality of commands in a first buffer of the memory storage device; in response to a first command and a second command in the first buffer meeting a pairing condition, placing the first command and the second command in the first buffer into a first command queue of the memory storage device; and sequentially executing the first command and the second command in the first command queue.

[0006] In an exemplary embodiment of the present invention, the instruction management method further includes: in response to the presence of the first instruction in the first buffer and the absence of the second instruction, obtaining the second instruction from the memory of the host system; storing the second instruction in a second buffer of the memory storage device; and placing the first instruction in the first buffer and the second instruction in the second buffer into the first instruction queue.

[0007] In an exemplary embodiment of the present invention, the first instruction is obtained from a specific instruction queue in the memory, and the step of obtaining the second instruction from the memory of the host system includes: forcing the next instruction to be read from the specific instruction queue in the memory to obtain the second instruction.

[0008] In an exemplary embodiment of the present invention, the command management method further includes: configuring a plurality of command queues in the memory storage device, wherein the plurality of command queues include the first command queue and at least one second command queue.

[0009] In an exemplary embodiment of the present invention, the instruction management method further includes: placing a third instruction in the first buffer that does not meet the pairing condition into the at least one second instruction queue; and executing the third instruction in the at least one second instruction queue.

[0010] In an exemplary embodiment of the present invention, the instruction management method further includes: scanning the plurality of instructions in the first buffer to identify at least one of the first instruction and the second instruction that meets the pairing condition.

[0011] In an exemplary embodiment of the present invention, the step of scanning the plurality of instructions in the first buffer includes: after identifying the first instruction in the first buffer that meets the pairing condition, searching for the second instruction that meets the pairing condition from the remaining instructions in the first buffer.

[0012] An exemplary embodiment of the present invention further provides a memory storage device comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit includes a buffer memory. The memory control circuit unit is configured to: obtain a plurality of instructions from a memory of the host system; store the plurality of instructions in a first buffer of the buffer memory; in response to a first instruction and a second instruction in the first buffer meeting a pairing condition, place the first instruction and the second instruction in the first buffer into a first instruction queue of the buffer memory; and continuously execute the first instruction and the second instruction in the first instruction queue.

[0013] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: obtain the second instruction from the memory of the host system in response to the presence of the first instruction and the absence of the second instruction in the first buffer; store the second instruction in a second buffer of the buffer memory; and place the first instruction in the first buffer and the second instruction in the second buffer into the first instruction queue.

[0014] In an exemplary embodiment of the present invention, the first instruction is obtained from a specific instruction queue in the memory, and the operation of obtaining the second instruction from the memory of the host system includes: forcing the next instruction to be read from the specific instruction queue in the memory to obtain the second instruction.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: configure a plurality of instruction queues in the buffer memory, wherein the plurality of instruction queues include the first instruction queue and at least one second instruction queue.

[0016] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: place a third instruction in the first buffer that does not meet the pairing condition into the at least one second instruction queue; and execute the third instruction in the at least one second instruction queue.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to scan the plurality of instructions in the first buffer to identify at least one of the first instruction and the second instruction that meets the pairing condition.

[0018] In an exemplary embodiment of the present invention, the operation of scanning the plurality of instructions in the first buffer includes: after identifying the first instruction in the first buffer that meets the pairing condition, searching for the second instruction that meets the pairing condition from the remaining instructions in the first buffer.

[0019] An exemplary embodiment of the present invention further provides a memory control circuit unit comprising a host interface, a memory interface, a buffer memory, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to a rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the buffer memory. The memory management circuit is configured to: obtain a plurality of instructions from a memory of the host system; store the plurality of instructions in a first buffer of the buffer memory; in response to a first instruction and a second instruction in the first buffer meeting a pairing condition, place the first instruction and the second instruction in the first buffer into a first instruction queue of the buffer memory; and sequentially execute the first instruction and the second instruction in the first instruction queue.

[0020] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: in response to the presence of the first instruction in the first buffer and the absence of the second instruction, obtain the second instruction from the memory of the host system; store the second instruction in a second buffer of the buffer memory; and place the first instruction in the first buffer and the second instruction in the second buffer into the first instruction queue.

[0021] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: configure a plurality of instruction queues in the buffer memory, wherein the plurality of instruction queues include the first instruction queue and at least one second instruction queue.

[0022] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: place a third instruction in the first buffer that does not meet the pairing condition into the at least one second instruction queue; and execute the third instruction in the at least one second instruction queue.

[0023] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: scan the plurality of instructions in the first buffer to identify at least one of the first instruction and the second instruction that meets the pairing condition.

[0024] In an exemplary embodiment of the present invention, the operation of scanning the plurality of instructions in the first buffer includes: after identifying the first instruction in the first buffer that meets the pairing condition, searching for the second instruction that meets the pairing condition from the remaining instructions in the first buffer.

[0025] Based on the above, after obtaining multiple instructions from the host system's memory, these instructions may be stored in a first buffer of the memory storage device. In response to a first instruction and a second instruction in the first buffer that meet a pairing condition, the first and second instructions in the first buffer may be placed in a first instruction queue of the memory storage device to ensure that the first and second instructions that meet the pairing condition can be executed continuously. This improves the operational stability of the memory storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0033] Figure 8 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0034] Figure 9 is a schematic diagram showing the sequential placement of a first instruction and a second instruction into a first instruction queue according to an exemplary embodiment of the present invention;

[0035] Figure 10 is a schematic diagram showing the sequential placement of a first instruction and a second instruction into a first instruction queue according to an exemplary embodiment of the present invention;

[0036] Figure 11 is a schematic diagram showing placing a third instruction into a second instruction queue according to an exemplary embodiment of the present invention;

[0037] Figure 12 is a flow chart of an instruction management method according to an exemplary embodiment of the present invention;

[0038] Figure 13 is a flow chart of an instruction management method according to an exemplary embodiment of the present invention;

[0039] Figure 14 FIG. 1 is a flow chart of an instruction management method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0040] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0041] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to the memory storage device or read data from the memory storage device.

[0042] Figure 1 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0043] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 may be connected to a system bus 110 .

[0044] In one exemplary embodiment, the host system 11 may be connected to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 may be connected to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I / O device 12 or receive input signals from the I / O device 12 via the system bus 110.

[0045] In one exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless method.

[0046] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a display 209, and a speaker 210, via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0047] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can each include Figure 3 The memory storage device 30 and the host system 31 are connected.

[0048] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3, the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0049] Figure 4 FIG is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0050] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In one exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0051] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions from the host system 11.

[0052] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which each cell can store one bit), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which each cell can store two bits), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which each cell can store three bits), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which each cell can store four bits), other flash memory modules, or other memory modules with similar characteristics.

[0053] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining the one or more bits stored in the memory cell.

[0054] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than two bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0055] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit may be a physical page or a physical sector. If a physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area includes 32 physical sectors, and the size of each physical sector is 512 bytes (bytes). However, in other exemplary embodiments, the data bit area may include 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erase. That is, each physical erase unit contains the minimum number of storage cells to be erased together. For example, a physical erase unit is a physical block.

[0056] Figure 5 FIG is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0057] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 is in operation, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0058] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 includes a microprocessor unit (not shown) and a read-only memory (ROM) (not shown), and these control instructions are burned into the ROM. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0059] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in the form of program code in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data). In addition, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). In particular, the read-only memory includes a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the RAM of the memory management circuit 51. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.

[0060] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 43 to write data to the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0061] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0062] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and corresponding command sequences for instructing various memory operations (e.g., changing a read voltage level or performing a garbage collection operation). These command sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0063] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0064] The error checking and correction circuit (also known as a decoding circuit module) 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure data accuracy. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates an error correcting code (ECC) and / or an error detecting code (EDC) corresponding to the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it also reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0065] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10 .

[0066] In one exemplary embodiment, the memory control circuit unit 42 further includes a detection circuit 57. The detection circuit 57 is connected to the memory management circuit 51 and can be used to analyze the type of at least one instruction received from the host system 11. For example, the detection circuit 57 may include a hardware circuit such as a microprocessor or microcontroller independent of the memory management circuit 51. In one exemplary embodiment, the detection circuit 57 may also be implemented as a hardware circuit within the memory management circuit 51, or executed by the memory management circuit 51 in the form of software or firmware.

[0067] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0068] Figure 6 FIG is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602 .

[0069] In one exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In one exemplary embodiment, a physical unit may also be composed of multiple consecutive or discontinuous physical addresses. In one exemplary embodiment, a physical unit may also be referred to as a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units.

[0070] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1) to 610(B) in the idle area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In one exemplary embodiment, the idle area 602 is also called a free pool.

[0071] The memory management circuit 51 can configure logical units 612(0)-612(C) to map physical units 610(0)-610(A) in the storage area 601. In one exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple consecutive or non-consecutive logical addresses.

[0072] Note that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it indicates that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, it indicates that the data currently stored in the physical unit is invalid data.

[0073] The memory management circuit 51 may record management data describing the mapping relationship between logical units and physical units (also known as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 based on the information in the logical-to-physical mapping table.

[0074] Figure 7 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 7Both the host system 11 and the memory storage device 10 support host memory buffering (HMB) technology. Under the HMB architecture, the host system 11 can provide internal memory 112 to the memory storage device 10. It should be noted that the present invention does not limit the total number, capacity, or type of memory in the memory 112.

[0075] The memory management circuit 51 can establish a connection between the memory storage device 10 and the host system 11. For example, the memory management circuit 51 can perform a handshake operation with the host system 11 to establish the connection. After the connection is established, the memory management circuit 51 can access the memory 112 (e.g., store data in the memory 112 or read data from the memory 112) and communicate with the host system 11 via the connection. In one exemplary embodiment, the connection between the memory storage device 10 and the host system 11 complies with the Non-Volatile Memory Express (NVMe) specification.

[0076] The memory management circuit 51 may receive a request from the host system 11. This request is used to inquire whether the memory storage device 10 supports host memory caching. The memory management circuit 51 may provide a response to the host system 11 based on the request. This response may inform the host system 11 whether the memory storage device 10 supports host memory caching.

[0077] If the memory storage device 10 supports host memory caching, the host system 11 may enable memory 112 for access by the memory storage device 10 based on this response. If the memory storage device 10 does not support host memory caching, the host system 11 may not enable memory 112. In one exemplary embodiment, if the memory storage device 10 supports host memory caching, the response may also inform the host system 11 of parameters related to host memory caching, such as the memory space required for host memory caching. The host system 11 may configure the memory 112 based on this response.

[0078] When the host system 11 wishes to perform an access operation on the memory storage device 10 (e.g., reading data from or writing data to the memory storage device 10), the processor 111 (e.g., a CPU) of the host system 11 may execute one or more processing routines to generate one or more instructions (also referred to as operation instructions) to be provided to the memory storage device. The processor 111 may place the prepared instructions in a command queue 711. The total number of command queues 711 may be one or more. The processor 111 may then transmit a notification to the memory storage device 10 (step S701). In one exemplary embodiment, the operation of step S701 is also referred to as a ring. In one exemplary embodiment, under the NVM express interface standard, after the notification is issued, the host system 11's active behavior with respect to the memory storage device 10 ends.

[0079] The memory management circuit 51 may receive this notification and actively read one or more instructions corresponding to the notification from the instruction queue 711 (step S702). For example, the obtained instructions may be cached in the instruction queue 721 of the memory storage device 10. Based on the instructions in the instruction queue 721, the memory management circuit 51 may perform corresponding access operations. For example, based on a read instruction, the memory management circuit 51 may perform a data read operation on the rewritable non-volatile memory module 43 and transfer the obtained read data from the data buffer 722 to the host system 11 (step S703). For example, the read data may be stored in the data buffer 712 of the host system 11. Alternatively, based on a write instruction, the memory management circuit 51 may actively read the write data from the data buffer 712 of the host system 11 and cache it in the data buffer 722 of the memory storage device 10 (step S703). Then, the memory management circuit 51 may perform a data write operation on the rewritable non-volatile memory module 43 to write the write data buffered in the data buffer 722 into the rewritable non-volatile memory module 43 .

[0080] Upon completion of an access operation, the memory management circuit 51 may generate a completion message, which may be cached in a completion queue 723 within the memory storage device 10. This completion message is used to notify the host system 11 that the access operation corresponding to a particular instruction has completed. This completion message is then transmitted to the host system 11 and cached in the completion queue 713 of the host system 11 (step S704). Based on the data in the completion queue 713, the host system 11 can determine that the memory access operation corresponding to the particular operation instruction has completed.

[0081] It should be noted that in Figure 7 In the exemplary embodiment, the instruction queue 711, the data cache 712, and the completion queue 713 are located in the memory 112 of the host system 11, and the instruction queue 721, the data cache 722, and the completion queue 723 are located in the buffer memory 55 of the memory storage device 10. However, in another exemplary embodiment, any of the instruction queue 711, the data cache 712, and the completion queue 713 may be located in other storage media of the host system 11, and / or any of the instruction queue 721, the data cache 722, and the completion queue 723 may be located in other storage media of the memory storage device 10 (e.g., the rewritable non-volatile memory module 43).

[0082] Figure 8 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 8 In one exemplary embodiment, the host system 11 may include a memory 80. For example, the memory 80 may include Figure 7 The host system 11 may configure the instruction queues 801(0) to 801(D) in the memory 80. For example, the instruction queues 801(0) to 801(D) may include Figure 7 Instruction queue 711.

[0083] In one exemplary embodiment, the memory management circuit 51 may configure a buffer (also referred to as a first buffer) 81, a buffer (also referred to as a second buffer) 82, a multiplexer 83, and instruction queues 841 (0) to 841 (3) in the memory storage device 10. For example, the buffer 81, the buffer 82, and the instruction queues 841 (0) to 841 (3) may be configured at Figure 7 The multiplexer 83 can be set in the form of hardware, software or firmware. Figure 4 In the memory control circuit unit 42. In addition, the total number of instruction queues 841 (0) to 841 (3) may be more or less, and the present invention is not limited thereto.

[0084] In one exemplary embodiment, the memory management circuit 51 may obtain a plurality of instructions from the memory 80 of the host system 11 via the host interface 52. For example, at least one of the plurality of instructions may be obtained from the instruction queue 801(i). The memory management circuit 51 may store the obtained instructions in the buffer 81. Based on the type of an instruction (also referred to as a target instruction) in the buffer 81, the multiplexer 83 may transfer the target instruction in the buffer 81 to one of the instruction queues 841(0)-841(3) (i.e., the target instruction queue), so that the target instruction waits in the target instruction queue to be executed by the memory management circuit 51.

[0085] In one exemplary embodiment, the memory management circuit 51 may place the instructions that meet the pairing condition in the buffer 81 into the instruction queue 841 (3) continuously. The instruction queue 841 (3) is also referred to as the first instruction queue. For example, the instructions that meet the pairing condition may be grouped into two, one of which is referred to as the first instruction and the other as the second instruction. The first instruction and the second instruction are paired with each other. In one exemplary embodiment, the instructions that meet the pairing condition (i.e., the first instruction and the second instruction that are paired with each other) are standardized as needing to be executed continuously. In addition, in one exemplary embodiment, the instructions that meet the same pairing condition may also include more instructions, for example, three instructions, and these three paired instructions are standardized as needing to be executed continuously.

[0086] In one exemplary embodiment, the detection circuit 57 may scan multiple instructions in the buffer 81 to identify instructions in the buffer 81 that meet the pairing condition (e.g., the first instruction and / or the second instruction). Then, the detection circuit 57 may control the multiplexer 83 to successively place the multiple paired instructions (e.g., the first instruction and the second instruction) into the instruction queue 841 (3). Thereafter, the memory management circuit 51 may successively execute the instructions in the instruction queue 841 (3) that meet the pairing condition (i.e., the first instruction and the second instruction) and perform the operations corresponding to the instructions.

[0087] Figure 9 is a schematic diagram showing the sequential placement of the first instruction and the second instruction into the first instruction queue according to an exemplary embodiment of the present invention. Figure 9 In one exemplary embodiment, it is assumed that there are instructions CMD(1) (i.e., the first instruction) and CMD(2) (i.e., the second instruction) in the buffer 81 at the same time. Instructions CMD(1) and CMD(2) meet the pairing condition. That is, instructions CMD(1) and CMD(2) are instructions that are regulated to be executed continuously. In one exemplary embodiment, if instructions CMD(1) and CMD(2) are not executed continuously (for example, a certain instruction is executed between instructions CMD(1) and CMD(2)), it may cause the memory storage device 10 to perform unexpected behavior or malfunction.

[0088] In one exemplary embodiment, the detection circuit 57 may scan the buffer 81. After detecting the instruction CMD(1), the detection circuit 57 may search for the instruction CMD(2) that meets the same pairing condition from the remaining instructions in the buffer 81. In response to the instructions CMD(1) and CMD(2) in the buffer 81, the detection circuit 57 may control the multiplexer 83 to place the instructions CMD(1) and CMD(2) in the buffer 81 into the instruction queue 841(3) successively. Thereafter, the memory management circuit 51 may execute the instructions CMD(1) and CMD(2) in the instruction queue 841(3) successively. In this way, it is ensured that the instructions CMD(1) and CMD(2) will be executed successively.

[0089] Please return Figure 8 In one exemplary embodiment, in response to the presence of the first instruction and the absence of the second instruction in the buffer 81 (i.e., only a portion of the instructions that meet the pairing condition exists in the buffer 81), the memory management circuit 51 may obtain the second instruction from the memory 80 of the host system 11. For example, assuming that the first instruction is obtained from the instruction queue 801 (i) in the memory 80, the memory management circuit 51 may force the next instruction to be read from the same instruction queue 801 (i) to obtain the second instruction. The memory management circuit 51 may store the forcedly read second instruction in the buffer 82. Then, the memory management circuit 51 may successively place the first instruction in the buffer 81 and the second instruction in the buffer 82 into the instruction queue 841 (3).

[0090] Figure 10 is a schematic diagram showing the sequential placement of the first instruction and the second instruction into the first instruction queue according to an exemplary embodiment of the present invention. Figure 10 , assuming that the detection circuit 57 detects that there is instruction CMD (1) in the buffer 81 but there is no instruction CMD (2) that meets the same pairing condition. In response to the instruction CMD (1) coming from the instruction queue 801 (i) in the host system 11, the detection circuit 57 can force the next instruction to be read from the instruction queue 801 (i) via the host interface 52 to obtain the instruction CMD (2). The instruction CMD (2) can be stored in the buffer 82. Then, the detection circuit 57 can control the multiplexer 83 to put the instruction CMD (1) in the buffer 81 and the instruction CMD (2) in the buffer 82 into the instruction queue 841 (3) continuously. In this way, it can also be ensured that the instructions CMD (1) and CMD (2) in the instruction queue 841 (3) can be executed continuously.

[0091] Please return Figure 8In one exemplary embodiment, the memory management circuit 51 may place the instruction in the buffer 81 that does not meet the matching condition (also referred to as the third instruction) into one of the instruction queues 841(0)-841(2). The instruction queues 841(0)-841(2) are also referred to as the second instruction queue. Thereafter, the memory management circuit 51 may execute the instruction in the instruction queues 841(0)-841(2) (i.e., the third instruction).

[0092] Figure 11 FIG is a schematic diagram showing placing the third instruction into the second instruction queue according to an exemplary embodiment of the present invention. Figure 11 For the instruction CMD(3) (i.e., the third instruction) in the buffer 81 that does not meet the matching conditions, the detection circuit 57 can control the multiplexer 83 to place the instruction CMD(3) into one of the instruction queues 841(0) to 841(2), such as the instruction queue 841(1), to wait for execution.

[0093] In one exemplary embodiment, the first instruction queue (e.g. Figures 8 to 11 The instruction queue 841 (3) is dedicated to storing instructions that meet the pairing conditions (such as the first instruction and the second instruction). On the other hand, the second instruction queue (such as Figures 8 to 11 The instruction queues 841(0) to 841(2)) are dedicated to storing instructions that do not meet the pairing conditions (such as the third instruction).

[0094] In one exemplary embodiment, instruction queues 841(0)-841(2) can also be used to store different types of instructions. For example, instruction queue 841(0) can be dedicated to storing write instructions, instruction queue 841(2) can be dedicated to storing read instructions, and / or instruction queue 841(3) can be dedicated to storing erase instructions. In one exemplary embodiment, the total number of instruction queues 841(0)-841(2) can also be greater to store more types of instructions.

[0095] In one exemplary embodiment, instructions that meet the pairing condition (i.e., the first instruction and the second instruction) must be executed consecutively. That is, no other instructions can be executed during the execution of the first and second instructions. Furthermore, in response to the failure of execution of one of the instructions that meet the pairing condition (i.e., the first instruction), another of the instructions that meet the pairing condition (i.e., the second instruction) will be aborted (i.e., not executed).

[0096] In one exemplary embodiment, the instructions that meet the pairing condition (i.e., the first instruction and the second instruction) may include a fused operation (FUSE) instruction. The fused operation instruction may include a comparison instruction and a write instruction. In particular, in the fused operation instruction, the write instruction must be executed immediately after the comparison instruction. For example, based on the comparison instruction in the fused operation instruction, the memory management circuit 51 may determine whether specific data exists in the rewritable non-volatile memory module 43. This specific data may be stored in a specific logical unit. If the specific data exists, the memory management circuit 51 may proceed to execute the write instruction in the fused operation instruction. Based on this write instruction, the memory management circuit 51 may update the specific data. However, if the specific data does not exist, the memory management circuit 51 may not execute the write instruction.

[0097] Through the above mechanism, regardless of whether there are instructions that meet the matching conditions in the current buffer 81, the instructions that meet the matching conditions can be continuously placed in the same instruction queue to be executed continuously. This can reduce the probability of the memory storage device 10 not continuously executing specific instructions and causing unexpected behavior or malfunction.

[0098] Figure 12 is a flow chart of an instruction management method according to an exemplary embodiment of the present invention. Figure 12 In step S1201, a plurality of instructions are obtained from the memory of the host system. In step S1202, the plurality of instructions are stored in a first buffer of the memory storage device. In step S1203, it is determined whether a first instruction that meets the pairing condition exists in the first buffer. If a first instruction that meets the pairing condition exists in the first buffer, in step S1204, it is determined whether a second instruction that meets the pairing condition exists in the first buffer. If both a first instruction and a second instruction that meet the pairing condition exist in the first buffer, in step S1205, in response to the first instruction and the second instruction that meet the pairing condition in the first buffer, the first instruction and the second instruction in the first buffer are placed in a first instruction queue of the memory storage device. In step S1206, the first instruction and the second instruction in the first instruction queue are executed continuously.

[0099] Figure 13 is a flow chart of an instruction management method according to an exemplary embodiment of the present invention. Figure 13 , continued by Figure 12In an exemplary embodiment, if step S1204 determines no (i.e., a first instruction meeting the pairing condition exists in the first buffer but the second instruction does not), then in step S1301, the second instruction is obtained from the host system's memory. In step S1302, the second instruction is stored in the second buffer of the memory storage device. In step S1303, the first instruction in the first buffer and the second instruction in the second buffer are placed in the first instruction queue. In step S1304, the first instruction and the second instruction in the first instruction queue are executed sequentially.

[0100] Figure 14 is a flow chart of an instruction management method according to an exemplary embodiment of the present invention. Figure 14 , continued by Figure 12 In an exemplary embodiment, if the determination in step S1203 is negative, then in step S1401, for the third instruction in the first buffer that does not meet the pairing condition, the third instruction in the first buffer that does not meet the pairing condition is placed in the second instruction queue of the memory storage device. In step S1402, the third instruction in the second instruction queue is executed.

[0101] However, Figures 12 to 14 The steps have been described in detail above and will not be repeated here. Figures 12 to 14 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figures 12 to 14 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0102] In summary, by centrally placing instructions that need to be executed consecutively (e.g., a first instruction and a second instruction that meet a pairing condition) into a specific instruction queue, it is possible to ensure that these instructions can be executed consecutively. Furthermore, by forcibly fetching the next instruction from a specific instruction queue in the host system, instructions missing from the buffer of the memory storage device (e.g., a second instruction that meets the pairing condition) can be directly obtained. This reduces the probability of unexpected behavior or malfunction caused by the memory storage device 10 not executing specific instructions consecutively, and / or improves the operational stability of the memory storage device.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for instruction management, characterized in that: For use in a memory storage device, wherein the memory storage device is connected to a host system, and the instruction management method comprises: obtaining a plurality of instructions from a memory of the host system; storing the plurality of instructions in a first buffer of the memory storage device; In response to a first instruction and a second instruction in the first buffer meeting a pairing condition, placing the first instruction and the second instruction in the first buffer into a first instruction queue of the memory storage device; In response to the first instruction existing in the first buffer and the second instruction not existing in the first buffer, obtaining the second instruction from the memory of the host system; storing the second instruction in a second buffer of the memory storage device; placing the first instruction in the first buffer and the second instruction in the second buffer into the first instruction queue; and The first instruction and the second instruction in the first instruction queue are executed continuously.

2. The instruction management method according to claim 1 , wherein the first instruction is obtained from a specific instruction queue in the memory, and the step of obtaining the second instruction from the memory of the host system comprises: The next instruction is forced to be read from the specific instruction queue in the memory to obtain the second instruction.

3. The instruction management method according to claim 1, further comprising: configuring a plurality of instruction queues in the memory storage device, The plurality of command queues include the first command queue and at least one second command queue.

4. The instruction management method according to claim 3, further comprising: placing a third instruction in the first buffer that does not meet the pairing condition into the at least one second instruction queue; as well as The third instruction in the at least one second instruction queue is executed.

5. The instruction management method according to claim 1, further comprising: The plurality of instructions in the first buffer are scanned to identify at least one of the first instruction and the second instruction that meets the pairing condition.

6. The instruction management method according to claim 5, wherein the step of scanning the plurality of instructions in the first buffer comprises: After identifying the first instruction in the first buffer that meets the pairing condition, searching for the second instruction that meets the pairing condition from the remaining instructions in the first buffer.

7. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module; The memory control circuit unit includes a buffer memory, and the memory control circuit unit is configured to: obtaining a plurality of instructions from a memory of the host system; storing the plurality of instructions in a first buffer of the buffer memory; In response to a first instruction and a second instruction in the first buffer meeting a pairing condition, placing the first instruction and the second instruction in the first buffer into a first instruction queue of the buffer memory; In response to the first instruction existing in the first buffer and the second instruction not existing in the first buffer, obtaining the second instruction from the memory of the host system; storing the second instruction in a second buffer of the buffer memory; placing the first instruction in the first buffer and the second instruction in the second buffer into the first instruction queue; as well as The first instruction and the second instruction in the first instruction queue are executed continuously.

8. The memory storage device of claim 7 , wherein the first instruction is obtained from a specific instruction queue in the memory, and the operation of obtaining the second instruction from the memory of the host system comprises: The next instruction is forced to be read from the specific instruction queue in the memory to obtain the second instruction.

9. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to: configuring a plurality of instruction queues in the buffer memory, The plurality of command queues include the first command queue and at least one second command queue.

10. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: placing a third instruction in the first buffer that does not meet the pairing condition into the at least one second instruction queue; and The third instruction in the at least one second instruction queue is executed.

11. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to: The plurality of instructions in the first buffer are scanned to identify at least one of the first instruction and the second instruction that meets the pairing condition.

12. The memory storage device of claim 11 , wherein scanning the plurality of instructions in the first buffer comprises: After identifying the first instruction in the first buffer that meets the pairing condition, searching for the second instruction that meets the pairing condition from the remaining instructions in the first buffer.

13. A memory control circuit unit, characterized in that: include: A host interface for connecting to a host system; A memory interface for connecting to a rewritable non-volatile memory module; Buffer memory; as well as a memory management circuit connected to the host interface, the memory interface and the buffer memory, The memory management circuit is used to: obtaining a plurality of instructions from a memory of the host system; storing the plurality of instructions in a first buffer of the buffer memory; In response to a first instruction and a second instruction in the first buffer meeting a pairing condition, placing the first instruction and the second instruction in the first buffer into a first instruction queue of the buffer memory; In response to the first instruction existing in the first buffer and the second instruction not existing in the first buffer, obtaining the second instruction from the memory of the host system; storing the second instruction in a second buffer of the buffer memory; placing the first instruction in the first buffer and the second instruction in the second buffer into the first instruction queue; as well as The first instruction and the second instruction in the first instruction queue are executed continuously.

14. The memory control circuit unit according to claim 13 , wherein the first instruction is obtained from a specific instruction queue in the memory, and the operation of obtaining the second instruction from the memory of the host system comprises: The next instruction is forced to be read from the specific instruction queue in the memory to obtain the second instruction.

15. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to: configuring a plurality of instruction queues in the buffer memory, The plurality of command queues include the first command queue and at least one second command queue.

16. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: placing a third instruction in the first buffer that does not meet the pairing condition into the at least one second instruction queue; and The third instruction in the at least one second instruction queue is executed.

17. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to: The plurality of instructions in the first buffer are scanned to identify at least one of the first instruction and the second instruction that meets the pairing condition.

18. The memory control circuit unit according to claim 17, wherein the operation of scanning the plurality of instructions in the first buffer comprises: After identifying the first instruction in the first buffer that meets the pairing condition, searching for the second instruction that meets the pairing condition from the remaining instructions in the first buffer.

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