Storage device and method of operating the same

Abstract

The present invention relates to a storage device and an operating method thereof, the storage device can include a memory device including a temperature sensor, and a memory controller obtaining temperature information sensed by the temperature sensor at a temperature management period from the memory device, performing a performance limiting operation that limits a performance of the memory device according to the temperature information, calculating the temperature management period by using the temperature information, and updating the temperature management period by using history information about a performance history of the performance limiting operation.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0134660, filed on October 16, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to an electronic device, and more particularly to a storage device and a method of operating the same. Background Technology

[0004] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that store data only when power is supplied and lose the stored data when the power supply is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are memory devices whose data is not lost even when the power supply is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] Various embodiments of this disclosure provide a storage device for performing improved temperature management operations and a method of operating the storage device.

[0008] According to one aspect of this disclosure, a storage device is provided, comprising: a memory device including a temperature sensor; and a memory controller configured to acquire temperature information sensed by the temperature sensor in each temperature management cycle from the memory device, perform a performance limiting operation to limit the performance of the memory device based on the temperature information, calculate a temperature management cycle using the temperature information, and update the temperature management cycle using historical information about the performance history of the performance limiting operation.

[0009] According to another aspect of this disclosure, a method for operating a storage device is provided, the storage device including a temperature sensor, the method comprising: acquiring temperature information sensed by the temperature sensor in each temperature management cycle; performing a performance limiting operation to limit the performance of the storage device based on the temperature information; calculating a minimum cycle and a maximum cycle of the temperature management cycle using the temperature information; and updating the temperature management cycle using historical information about the performance limiting operation, the minimum cycle, and the maximum cycle.

[0010] According to another aspect of this disclosure, a storage device is provided, comprising: a memory device including a temperature sensor; and a memory controller configured to: perform a temperature management operation, the temperature management operation including a temperature acquisition operation for acquiring temperature information sensed by the temperature sensor from the memory device, and a performance limiting operation for limiting the performance of the memory device based on the temperature information, wherein the memory controller: calculates a temperature change per unit time based on prior temperature information regarding a first temperature management operation performed prior to the temperature management operation and time information regarding the first temperature management operation; calculates a first execution time and a second execution time for a second temperature management operation to be performed after the temperature management operation based on the temperature change per unit time; and determines a final execution time of the second temperature management operation by using the temperature information, the cumulative number of times the performance limiting operation has been performed, the first execution time, and the second execution time. Attached Figure Description

[0011] Various embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of these embodiments to those skilled in the art.

[0012] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, there may be only one element between the two elements, or there may be one or more intermediate elements. The same reference numerals always refer to the same element.

[0013] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0015] Figure 3 This is a block diagram illustrating a temperature sensor according to an embodiment of the present disclosure.

[0016] Figure 4This is a diagram illustrating various temperature management operations according to embodiments of the present disclosure.

[0017] Figure 5 This is a diagram illustrating temperature management operation according to an embodiment of the present disclosure.

[0018] Figure 6 This is a block diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0019] Figure 7 This is a diagram illustrating multiple temperature ranges according to embodiments of the present disclosure.

[0020] Figure 8 This is a flowchart illustrating an operation method of a storage device according to an embodiment of the present disclosure.

[0021] Figure 9 This is a block diagram illustrating a memory controller according to another embodiment of the present disclosure.

[0022] Figure 10 This is a diagram illustrating a storage block according to an embodiment of the present disclosure.

[0023] Figure 11 This is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0024] Figure 12 This is a diagram illustrating a solid-state drive (SSD) according to an embodiment of the present disclosure.

[0025] Figure 13 This is a diagram illustrating a user system according to an embodiment of the present disclosure. Detailed Implementation

[0026] The specific structural or functional descriptions disclosed herein are merely illustrative and intended to describe embodiments according to this disclosure. Embodiments according to this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0027] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The storage device 1000 may include a memory device 100 and a memory controller 200.

[0029] Storage device 1000 can be a device for storing data under the control of host 2000 such as: mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, display device, tablet PC, or in-vehicle infotainment system.

[0030] Depending on the host interface, which serves as the communication scheme with the host 2000, the storage device 1000 can be manufactured as any of various types of storage devices. For example, the storage device 1000 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro MMC (micro-MMC), secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0031] The storage device 1000 can be implemented as any of a variety of package types. For example, the storage device 1000 can be implemented as any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0032] The memory device 100 can store data or use the stored data. The memory device 100 operates under the control of the memory controller 200. Moreover, the memory device 100 may include a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array, the memory cell array including a plurality of memory cells for storing data.

[0033] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0034] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells, and a memory block may include multiple pages. A page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0035] The memory device 100 can be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is NAND Flash Memory is described.

[0036] Memory device 100 may receive commands and addresses from memory controller 200. Memory device 100 may access a region in the memory cell array selected by the received address. When memory device 100 accesses the selected region, this indicates that memory device 100 performs an operation corresponding to the received command on the selected region. For example, memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. A programming operation may be an operation in which memory device 100 records data in the region selected by the address. A read operation may be an operation in which memory device 100 reads data from the region selected by the address. An erase operation may be an operation in which memory device 100 erases data stored in the region selected by the address.

[0037] According to embodiments of this disclosure, the memory device 100 may include a temperature sensor 140. Furthermore, the memory device 100 may, in response to a temperature information request received from the memory controller 200 in each temperature management cycle, transmit temperature information sensed by the temperature sensor 140 to the memory controller 200. The temperature information may be a code (CODE) corresponding to the temperature sensed by the temperature sensor 140. Specifically, the temperature sensor 140 may be implemented as a digital temperature sensing circuit to convert the sensed temperature into a code (CODE) as a digital signal, and then output the code (CODE). That is, the temperature sensor 140 may output a code corresponding to the temperature and transmit the output code to the memory device 100 or the memory controller 200.

[0038] Furthermore, the temperature sensor 140 can sense the temperature of the memory device 100 or the storage device 1000 in response to a command (e.g., a temperature information request) transmitted from the memory device 100 or the memory controller 200, and output temperature information corresponding to the sensed temperature. Optionally, the temperature sensor 140 can perform the following operations: sense the temperature of the memory device 100 or the storage device 1000 and output temperature information according to a constant time, regardless of the command transmitted from the memory device 100 or the memory controller 200. Specifically, the temperature sensor 140 can perform the operation of sensing temperature and outputting temperature information according to a constant period, and the memory device 100 can store the temperature information output from the temperature sensor 140. When the memory device 100 receives a temperature information request from the memory controller 200, the memory device 100 can transmit the stored temperature information to the memory controller 200.

[0039] The memory controller 200 can control all operations of the storage device 1000. When power is supplied to the storage device 1000, the memory controller 200 can run firmware (FW). The FW may include a host interface layer (HIL) that receives requests from or outputs responses to the host 2000, a flash translation layer (FTL) that manages the operation between the interface of the host 2000 and the interface of the storage device 100, and a flash interface layer (FIL) that provides commands to or receives responses from the storage device 100.

[0040] The memory controller 200 can receive data and logical addresses (LA) from the host 2000 and translate the LA into physical addresses (PA), where PA represents the address of a memory cell containing data to be stored in the memory device 100. LA can be a logical block address (LBA), and PA can be a physical block address (PBA).

[0041] The memory controller 200 can respond to requests from the host 2000 to control the memory device 100 to perform programming operations, read operations, erase operations, etc. During programming operations, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and PBAs to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0042] The memory controller 200 can control the memory device 100 to autonomously perform programming, reading, or erasing operations, regardless of any requests from the host 2000. For example, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations for background operations such as wear leveling, garbage collection, or read recycling.

[0043] The host 2000 can communicate with the storage device 1000 using at least one of the following communication interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0044] Furthermore, despite Figure 1 The illustration shows a case where the temperature sensor 140 is included in the memory device 100, but this is merely an embodiment of the present disclosure, and the temperature sensor 140 may be implemented in the form of attaching the temperature sensor 140 to the outside of the memory device or implementing the temperature sensor 140 as a separate electronic device.

[0045] Figure 2 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0046] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, control logic 130, and a temperature sensor 140.

[0047] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to row decoder 121 via row lines RL. Row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLn. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In an embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include multiple pages.

[0048] Each of the memory cells included in the memory cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0049] The peripheral circuit 120 can be configured to perform programming, reading, or erasing operations on selected regions in the memory cell array 110 under the control of the control logic 130. In other words, the peripheral circuit 120 can drive the memory cell array 110 under the control of the control logic 130. For example, the peripheral circuit 120 can apply various operating voltages to or release the applied voltages to the row lines RL and bit lines BL1 to BLn under the control of the control logic 130.

[0050] Specifically, the peripheral circuit 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0051] The row decoder 121 can be connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In an embodiment, the word lines may include ordinary word lines and dummy word lines. In an embodiment, the row line RL may further include pipe select lines.

[0052] The row decoder 121 operates under the control of the control logic 130. The row decoder 121 receives the row address RADD from the control logic 130. Specifically, the row decoder 121 decodes the row address RADD. The row decoder 121 selects at least one memory block from BLK1 to BLKz based on the decoded address. Furthermore, the row decoder 121 selects at least one word line within the selected memory block based on the decoded address to apply the voltage generated by the voltage generator 122 to that at least one word line WL.

[0053] For example, in a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and apply a programming pass voltage with a level lower than the programming voltage to the unselected word line. In a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and apply a verification pass voltage with a level higher than the verification voltage to the unselected word line. In a reading operation, the line decoder 121 can apply a reading voltage to the selected word line and apply a reading pass voltage with a level higher than the reading voltage to the unselected word line.

[0054] In this embodiment, the erase operation of the memory device 100 can be performed on a block-by-block basis. During the erase operation, the row decoder 121 can select a memory block based on the decoded address. During the erase operation, the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0055] Voltage generator 122 can operate under the control of control logic 130. Specifically, voltage generator 122 can generate multiple voltages under the control of control logic 130 by using the external power supply voltage supplied to memory device 100. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., under the control of control logic 130. That is, voltage generator 122 can generate various operating voltages Vop used in programming operations, read operations, and erase operations in response to the operation signal OPSIG.

[0056] In this embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the operating voltage of memory cell array 110.

[0057] In this embodiment, voltage generator 122 can generate multiple voltages using either an external power supply voltage or an internal power supply voltage. For example, voltage generator 122 may include multiple pump capacitors for receiving internal power supply voltages, and generate multiple voltages by selectively activating the multiple pump capacitors under the control of control logic 130. Additionally, the multiple generated voltages can be supplied to memory cell array 110 via line decoder 121.

[0058] Page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn may be connected to memory cell array 110 via first to nth bit lines BL1 to BLn, respectively. Furthermore, the first to nth bit lines BL1 to BLn may operate under the control of control logic 130. Specifically, the first to nth bit lines BL1 to BLn may operate in response to the page buffer control signal PBSIGNALS. For example, during a read operation or a verification operation, the first to nth page buffers PB1 to PBn may temporarily store data received via the first to nth bit lines BL1 to BLn, or sense the voltage or current of the bit lines BL1 to BLn.

[0059] Specifically, during programming, when a programming voltage is applied to the selected word line, the first to nth page buffers PB1 to PBn can transmit data DATA received through the input / output circuit 125 to the selected memory cell via the first to nth bit lines BL1 to BLn. The memory cell in the selected page can be programmed according to the transmitted data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained.

[0060] During the programming verification operation, the first to nth page buffers PB1 to PBn can read page data from the selected memory cell through the first to nth bit lines BL1 to BLn.

[0061] During the read operation, under the control of the column decoder 124, the first to nth page buffers PB1 to PBn can read data DATA from the memory cell in the selected page through the first to nth bit lines BL1 to BLn, and output the read data DATA to the input / output circuit 125.

[0062] During the erase operation, the first to nth page buffers PB1 to PBn can make the first to nth bit lines BL1 to BLn float.

[0063] The column decoder 124 can communicate data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can communicate data with the first to nth page buffers PB1 to PBn via the data lines DL, or with the input / output circuitry 125 via the column lines CL.

[0064] The input / output circuit 125 can transmit the command CMD and address ADD received from the memory controller 200 to the control logic 130, or exchange data DATA with the column decoder 124.

[0065] In a read or verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit VRYBIT signal and output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0066] Control logic 130 can control peripheral circuitry 120 by outputting operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit VRYBIT in response to commands CMD and address ADDR. Furthermore, control logic 130 can determine whether the verification operation has passed or failed in response to signals PASS or FAIL. Moreover, control logic 130 can control page buffer group 123 to temporarily store verification information, including the pass signal PASS or the failure signal FAIL, in page buffer group 123. Specifically, control logic 130 can determine the programming state of a memory cell in response to signals PASS or FAIL. For example, when the memory cell operates as a three-level cell (TLC), control logic 130 can determine whether the programming state of the memory cell is erase state E or one of the first programming states P1 to the seventh programming states P7.

[0067] According to embodiments of this disclosure, control logic 130 can control the operation of temperature sensor 140 in response to a temperature information request received from memory controller 200. Temperature sensor 140 can output temperature information TEMP corresponding to the sensed temperature in response to a temperature sensor control signal DTSSIG provided from control logic 130. The temperature sensor control signal DTSSIG can be transmitted to temperature sensor 140 in each predetermined cycle. For example, the temperature sensor control signal DTSSIG can be generated in each temperature management cycle of memory controller 200 for transmission to temperature sensor 140.

[0068] Furthermore, despite Figure 2 The diagram shows the temperature sensor 140 located inside the memory device 100, but the temperature sensor 140 can also be implemented with the temperature sensor 140 located outside the memory device 100. (Refer to...) Figure 3 The configuration and operation of temperature sensor 140 are described in detail.

[0069] Figure 3 This is a block diagram illustrating a temperature sensor according to an embodiment of the present disclosure.

[0070] Reference Figure 3 The temperature sensor 140 may include a temperature voltage generator 141 and a temperature code generator 143. The temperature sensor 140 may output temperature information TEMP corresponding to the sensed temperature in response to a temperature sensor control signal DTSSIG. The temperature sensor control signal DTSSIG may be generated in each predetermined cycle.

[0071] Temperature voltage generator 141 can generate a temperature voltage and a reference voltage in response to a received temperature sensor control signal DTSSIG. Specifically, by using a signal from... Figure 2 The voltage generator 122 shown receives the voltage, and the temperature voltage generator 141 can generate a temperature voltage VCTAT and a reference voltage VREF, wherein the temperature voltage VCTAT has a voltage level determined according to the temperature, and the reference voltage VREF has a constant level regardless of temperature changes.

[0072] Specifically, the temperature voltage VCTAT generated by the temperature voltage generator 141 is a voltage corresponding to temperature, and can be a voltage whose level increases or decreases according to temperature changes. The temperature voltage generator 141 may include a transistor whose threshold voltage changes according to temperature or a resistor whose resistance value changes according to temperature. Moreover, the temperature voltage generator 141 can generate the temperature voltage VCTAT by using a transistor whose threshold voltage changes according to temperature or a resistor whose resistance value changes according to temperature.

[0073] The reference voltage VREF generated by the temperature voltage generator 141 can be a voltage with a constant voltage level regardless of temperature changes. Specifically, the reference voltage VREF can include VREF+ as a relatively high voltage and VREF- as a relatively low voltage. Furthermore, the temperature voltage generator 141 can be implemented in the form of a bandgap voltage generation circuit or a Widlar voltage generation circuit, which ensures that the voltage has a constant potential regardless of temperature changes.

[0074] The temperature code generator 143 can generate a code CODE based on the temperature voltage VCTAT and reference voltage VREF received from the temperature voltage generator 141. The temperature voltage VCTAT and reference voltage VREF can have analog values ​​corresponding to the temperature of the memory device 100, and the code CODE can have a digital value corresponding to the temperature information. That is, the temperature code generator 143 can be implemented as an analog-to-digital converter (ADC) that converts the temperature voltage VCTAT and reference voltage VREF, which are analog signals, into a code CODE, which is a digital signal.

[0075] As the bit depth increases, code can be implemented at a higher resolution. Resolution can refer to the difference between the actual internal temperature and the temperature represented by the generated code. For example, at a lower resolution, a code might be represented as 0 when the actual internal temperature is 5°C, but as 1 when the actual internal temperature is 10°C. Conversely, at a higher resolution, a code might be represented as 0 when the actual internal temperature is 5°C, but as 5 when the actual internal temperature is 10°C. In other words, because the difference between the output codes at the same temperature difference becomes larger with higher resolution, the difference between the actual internal temperature and the temperature represented by the generated code becomes smaller, and the actual internal temperature corresponding to the code can be accurately represented.

[0076] Figure 4 This is a diagram illustrating various temperature management operations according to embodiments of the present disclosure.

[0077] Reference Figure 4 The diagram illustrates the (n-1)th temperature management operation S410, the nth temperature management operation S420, and the (n+1)th temperature management operation S430. The temperature management operation can be an operation that manages the internal temperature of the storage device 1000. Specifically, when the storage device 1000 performs internal operations, the number of internal operations may increase. Moreover, when the internal operations of the storage device 1000 become excessive, the components of the storage device 1000 may be damaged, and the operation of the storage device 1000 is likely to deteriorate. Therefore, the temperature management operation can be an operation that manages the internal temperature of the storage device 1000 to prevent damage and deterioration that may occur when the internal temperature of the storage device 1000 becomes too high.

[0078] Storage device 1000 can perform temperature management operations, which include a temperature acquisition operation to obtain temperature information sensed by temperature sensor 140 and a performance limiting operation to limit the performance of storage device 1000 based on the acquired temperature information. That is, the performance limiting operation can be an operation that limits the internal operations of storage device 1000 when the internal temperature of storage device 1000 becomes too high, thereby reducing the internal temperature of storage device 1000. For example, storage device 1000 can control the total current flowing into storage device 1000 by suspending all or part of the operations performed in storage device 1000. Storage device 1000 controls the total current to prevent the internal temperature of storage device 1000 from becoming excessively hot. Optionally, storage device 1000 can reduce the processing speed of internal operations (e.g., the number of clock cycles per unit time) to prevent the internal temperature of storage device 1000 from becoming excessively hot.

[0079] However, frequent execution of temperature management operations can lead to unnecessary power waste, and the performance overhead of the storage device 1000 can be reduced due to the execution of temperature management operations. According to embodiments of this disclosure, the storage device 1000 can perform effective temperature management operations based on improved temperature management operations.

[0080] In this specification, for ease of description, the memory controller 200 performs a temperature management operation on the memory device 100. However, the temperature management operation can be equivalently applied to situations where the temperature of the memory controller 200 or the memory device 1000 overheats to a predetermined throttling temperature or higher.

[0081] Reference Figure 4 The storage device 1000 can perform temperature management operations according to a temperature management cycle. For example, the storage device 1000 can perform the (n-1)th temperature management operation S410 and the nth temperature management operation S420 after a time amount Δt corresponding to the temperature management cycle. Furthermore, the storage device 1000 can update the temperature management cycle using the time amount Δt and temperature information Δ℃, where the temperature information Δ℃ represents the temperature change sensed by the temperature sensor 140 of the storage device during that time amount. That is, according to embodiments of this disclosure, the storage device 1000 can determine the time point for starting the (n+1)th temperature management operation S430 based on the result obtained by performing the nth temperature management operation S420. For example, the storage device 1000 can determine the time point for starting the (n+1)th temperature management operation S430 by using the time amount Δt and temperature information Δ℃ obtained from the temperature sensor 140 in the nth temperature management operation S420.

[0082] According to another embodiment of this disclosure, the temperature management operation may include a temperature acquisition operation and a performance limiting operation, wherein in the temperature acquisition operation, temperature information sensed by the temperature sensor 140 is acquired from the memory device 100, and the performance limiting operation limits the performance of the memory device 100 based on the acquired temperature information and a time amount Δt. The memory controller 200 may calculate the temperature change per unit time based on the temperature information measured in the (n-1)th temperature management operation performed prior to the nth temperature management operation. Specifically, the memory controller 200 may calculate the temperature change (e.g., temperature information Δ°C) by comparing the temperature information sensed in the (n-1)th temperature management operation with the temperature information sensed in the nth temperature management operation. Moreover, the memory controller 200 may calculate the time change (e.g., the time amount Δt corresponding to the temperature management cycle) by comparing the time point at which the (n-1)th temperature management operation begins with the time point at which the nth temperature management operation begins. The memory controller 200 can calculate the temperature change Δ℃ and time change Δt by comparing the (n-1)th temperature management operation with the nth temperature management operation, and calculate the temperature change per unit time based on the temperature change Δ℃ and time change Δt. Furthermore, the memory device 200 can calculate the first and second time points for starting the (n+1)th temperature management operation based on the temperature change per unit time, where the (n+1)th temperature management operation will be executed after the nth temperature management operation. The memory controller 200 can determine the final time point for starting the (n+1)th temperature management operation by using the temperature information sensed during the nth temperature management operation, the cumulative number of performance limiting operations executed after power is applied to the memory device 1000 and before the (n-1)th temperature management operation, and the first and second time points.

[0083] In various embodiments, the memory controller 200 can generate corrected temperature information using temperature information, and can perform the above-described operations using the corrected temperature information. The corrected temperature information can be temperature information obtained by processing the temperature information according to various methods. Optionally, the memory controller 200 may further include another temperature sensor separate from the temperature sensor 140 included in the memory device 100. The memory controller 200 can calculate the corrected temperature information using this other temperature sensor separate from the temperature sensor 140 included in the memory device 100. For example, the memory controller 200 can calculate the corrected temperature information by calculating the arithmetic mean of the temperature information received from the temperature sensor 140 included in the memory device 100 and the temperature information from another temperature sensor separate from the temperature sensor 140.

[0084] Figure 5This is a diagram illustrating temperature management operation according to an embodiment of the present disclosure.

[0085] Reference Figure 5 The diagram illustrates the execution of the nth temperature management operation S420 by the memory device 100 and the memory controller 200. The nth temperature management operation S420 may include an operation (S510) in which the memory controller 200 requests temperature information from the memory device 100. Specifically, the memory controller 200 may request temperature information from the memory device 100, which includes the temperature sensor 140, in each temperature management cycle.

[0086] Additionally, the memory device 100 can perform a temperature information sensing operation (S520) in response to a temperature information request received from the memory controller 200. Specifically, the memory device 100 can control the temperature sensor 140 included in the memory device 100 and perform a temperature information sensing operation by using the temperature sensor 140.

[0087] Furthermore, the memory device 100 can transmit temperature information obtained from the temperature sensor 140 (S530), and the memory controller 200 can perform a performance limiting operation to limit the performance of the memory device 100 based on the temperature information (S540). The performance limiting operation may be an operation that limits the internal operation of the memory device 1000 when the internal temperature of the memory device 1000 becomes too high, so as to reduce the internal temperature of the memory device 1000.

[0088] Additionally, the memory controller 200 can update the temperature management cycle using temperature information (S550). Specifically, the memory controller 200 can calculate the minimum and maximum cycles of the temperature management cycle using temperature information and a reference temperature management cycle, and update the temperature management cycle using historical information about the performance limiting operation performed after power is applied to the storage device 1000, the minimum and maximum cycles. (Refer to...) Figure 6 and Figure 7 Provide a detailed description of the temperature management cycle update.

[0089] Figure 6 This is a block diagram illustrating a memory controller according to an embodiment of the present disclosure. Figure 7 This is a diagram illustrating multiple temperature ranges according to embodiments of the present disclosure.

[0090] Reference Figure 6 The memory controller 200 may include a cycle calculator 210, a cycle determiner 220, a cycle updater 230, a temperature information storage device 240, and a historical information storage device 250.

[0091] The cycle calculator 210 can be a component for calculating the minimum and maximum cycles of a temperature management cycle. Specifically, the cycle calculator 210 can calculate the temperature change per unit time using temperature information and a reference temperature management cycle, and calculate the minimum and maximum cycles using the temperature change per unit time and an initial or predetermined temperature management cycle. The initial temperature management cycle can be the reference temperature management cycle. Moreover, the cycle calculator 210 can calculate the minimum and maximum cycles according to the following Equation 1.

[0092] Equation 1

[0093] MIN_SEC=X*(T*(1÷DT))

[0094] MAX_SEC=Y*(T*(1÷DT))

[0095] T can be the reference temperature management period, DT can be the temperature change per unit time within each temperature management period, MIN_SEC can be the minimum period, MAX_SEC can be the maximum period, X can be any constant, and Y can be any constant greater than X. The unit of T can be [s], the unit of DT can be [℃ / s], the units of MIN_SEC and MAX_SEC can both be [s], and the units of X and Y can both be [℃ / s].

[0096] When the temperature change per unit time increases, the period calculator 210 can increase the minimum period and the maximum period, and when the temperature change per unit time decreases, the period calculator 210 can decrease the minimum period and the maximum period.

[0097] The cycle determiner 220 can be a component used to determine the current temperature response cycle and historical response cycles. The current temperature response cycle can be a cycle determined based on temperature information received from the temperature sensor 140. That is, the current temperature response cycle can be a cycle obtained by reflecting the current temperature state of the memory device 100.

[0098] The period determiner 220 can determine the current temperature response period based on the temperature information, choosing any one of the minimum period, the maximum period, or the arithmetic mean of the minimum and maximum periods. Specifically, the period determiner 220 can determine the current temperature response period based on whether the temperature of the memory device 100 corresponding to the temperature information falls within one of multiple temperature ranges.

[0099] Reference Figure 7The diagram illustrates multiple temperature ranges. A first range may be a temperature range above a first temperature (e.g., 10°C) and below or equal to a second temperature (e.g., 40°C). A second range may be one or more of a temperature range above 0°C and below or equal to the first temperature (e.g., 10°C), and a temperature range above the second temperature (e.g., 40°C) and below or equal to a third temperature (e.g., 78°C). A third range may be one or more of a temperature range below or equal to 0°C and a temperature range above the third temperature (e.g., 78°C).

[0100] When the temperature of the memory device 100 corresponding to the temperature information falls within a first range, the period determiner 220 can determine the maximum period as the current temperature response period. When the temperature of the memory device 100 corresponding to the temperature information falls within a second range, the period determiner 220 can determine the arithmetic mean of the minimum and maximum periods as the current temperature response period. When the temperature of the memory device 100 corresponding to the temperature information falls within a third range, the period determiner 220 can determine the minimum period as the current temperature response period.

[0101] The cycle determiner 220 can determine the historical response cycle based on the number of times a performance limiting operation has been performed since power was applied to the storage device 1000. When the temperature of the storage device 100, corresponding to temperature information, falls within a certain range... Figure 7 When the third temperature range is shown, the memory controller 200 can perform a performance limiting operation that restricts the performance of the memory device 100. For example, when the temperature of the memory device 100 corresponding to the temperature information is higher than the third temperature, the memory controller 200 can perform a performance limiting operation. Furthermore, the memory controller 200 can store the number of times the performance limiting operation has been performed since power was applied to the memory device 1000 in the historical information storage device 250.

[0102] The cycle determiner 220 can determine the historical response cycle according to the following Table 1.

[0103] Table 1

[0104]

[0105] When the accumulated number of cycles falls within a first range, the cycle determiner 220 can determine the maximum cycle as the historical response cycle. When the accumulated number of cycles falls within a second range, the cycle determiner 220 can determine the arithmetic mean of the minimum and maximum cycles as the historical response cycle. When the accumulated number of cycles falls within a third range, the cycle determiner 220 can determine the minimum cycle as the historical response cycle. The cycle updater 230 can be a component used to update the temperature management cycle by using the current temperature response cycle and the historical response cycle. Specifically, the cycle updater 230 can update the temperature management cycle by using the arithmetic mean of the current temperature response cycle and the historical response cycle determined by the cycle determiner 220. For example, when the current temperature response cycle is the minimum cycle and the historical response cycle is the maximum cycle, the cycle updater 230 can update the temperature management cycle to the value of (minimum cycle + maximum cycle) / 2.

[0106] Furthermore, the memory controller 200 according to embodiments of this disclosure may include a temperature information storage device 240 and a history information storage device 250. The temperature information storage device 240 may be a component for receiving temperature information sensed by the temperature sensor 140 from the memory device 100 and storing the received temperature information, and the history information storage device 250 may be a component for storing the cumulative number of times a performance limiting operation has been performed since power was applied to the memory device 1000.

[0107] Figure 8 This is a flowchart illustrating an operation method of a storage device according to an embodiment of the present disclosure.

[0108] Reference Figure 8 The diagram illustrates an operation method for a storage device including a temperature sensor. The storage device 1000 can acquire temperature information sensed by the temperature sensor during each temperature management cycle (S810). The temperature information can be a code corresponding to the temperature sensed by the temperature sensor 140. The storage device 1000 can map the code and temperature according to resolution, and as the bit depth increases, the code can be implemented at a higher resolution.

[0109] Furthermore, the storage device 1000 can perform a performance limiting operation (S820) to limit the performance of the storage device 1000 based on temperature information. The performance limiting operation can be an operation that restricts internal operations of the storage device to reduce the internal temperature of the storage device 1000. The storage device 1000 can control the total current flowing into the storage device 1000 by suspending all or part of the operations performed within the storage device 1000. The storage device 1000 controls the total current to prevent the internal temperature of the storage device 1000 from becoming excessively hot. Optionally, the storage device 1000 can reduce the processing speed of internal operations (e.g., the number of clock cycles per unit time) to prevent the internal temperature of the storage device 1000 from becoming excessively hot.

[0110] Furthermore, the storage device 1000 can calculate the minimum and maximum periods of the temperature management cycle using temperature information and a reference temperature management cycle (S830). Specifically, the storage device 1000 can calculate the minimum and maximum periods using the temperature change per unit time and the reference temperature management cycle. The storage device 1000 can determine the minimum and maximum periods such that when the temperature change per unit time increases, the minimum and maximum periods increase, and when the temperature change per unit time decreases, the minimum and maximum periods decrease.

[0111] According to embodiments of this disclosure, the storage device 1000 can determine the current temperature response period based on whether the temperature of the storage device 100 corresponding to temperature information falls within one of a first range, a second range, and a third range. The first range can be a temperature range higher than a first temperature and lower than or equal to a second temperature. The second range can be one or more of a temperature range higher than 0°C and lower than or equal to the first temperature, and a temperature range higher than the second temperature and lower than or equal to the third temperature. The third range can be one or more of a temperature range lower than or equal to 0°C and a temperature range higher than the third temperature.

[0112] When the temperature of the memory device 100 corresponding to the temperature information falls within a first range, the memory device 1000 can determine the maximum period as the current temperature response period. When the temperature of the memory device 100 corresponding to the temperature information falls within a second range, the memory device 1000 can determine the arithmetic mean of the minimum period and the maximum period as the current temperature response period. When the temperature of the memory device 100 corresponding to the temperature information falls within a third range, the memory device 1000 can determine the minimum period as the current temperature response period.

[0113] According to embodiments of this disclosure, the storage device 1000 can store temperature information and the number of times a performance limiting operation has been performed since power was applied to the storage device 1000. Furthermore, the storage device 1000 can update the temperature management cycle (S840) using historical information about the performance limiting operation, the minimum cycle, and the maximum cycle. According to embodiments of this disclosure, the storage device 1000 can determine a current temperature response cycle determined by one of the minimum cycle, the maximum cycle, and the arithmetic mean of the minimum and maximum cycles, and determine a historical response cycle based on the number of times a performance limiting operation has been performed since power was applied to the storage device 1000. Furthermore, the storage device 1000 can update the temperature management cycle using the current temperature response cycle and the historical response cycle.

[0114] Figure 9 This is a block diagram illustrating a memory controller according to another embodiment of the present disclosure.

[0115] Reference Figure 9 The memory controller 1300 may include a processor 1310, RAM 1320 and ECC circuit 1330, ROM 1360, host interface 1370, flash memory interface 1380 and temperature sensor 140. Figure 9 The memory controller 1300 shown can be Figure 1 or Figure 6 Another embodiment of the memory controller 200 shown.

[0116] Processor 1310 can communicate with host 2000 via host interface 1370 and perform logical operations to control the operation of memory controller 1300. For example, processor 1310 can load programming commands, data files, data structures, etc., based on requests received from host 2000 or external devices, and perform various operations or generate commands and addresses. For example, processor 1310 can generate various commands required for programming operations, read operations, erase operations, pause operations, and parameter setting operations.

[0117] Furthermore, processor 1310 can perform the functions of a Flash Translation Layer (FTL). Processor 250 can use the FTL to translate logical block addresses (LBAs) provided by host 2000 into physical block addresses (PBAs). The FTL can receive input LBAs and translate them into PBAs using a mapping table. Depending on the mapping unit, there are several address mapping methods for the FTL. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0118] Furthermore, the processor 1310 can generate commands without any request from the host 2000. For example, the processor 1310 can generate commands for background operations such as wear leveling operations for the memory device 100 and garbage collection operations for the memory device 100.

[0119] RAM 1320 can be used as a buffer memory, working memory, or cache memory for processor 1310. Furthermore, RAM 1320 can store code and commands executed by processor 1310. RAM 1320 can store data processed by processor 1310. Moreover, RAM 1320 can be implemented as static RAM (SRAM) or dynamic RAM (DRAM).

[0120] The ECC circuit 1330 can detect and correct errors during programming or reading operations. Specifically, the ECC circuit 1330 can perform error correction operations based on error correction codes (ECC). Furthermore, the ECC circuit 1330 can perform ECC encoding based on data to be written to the memory device 100. The ECC-encoded data can be transferred to the memory device 100 via the flash memory interface 1380. Moreover, the ECC circuit 1330 can perform ECC decoding on data received from the memory device 100 via the flash memory interface 1380.

[0121] ROM 1360 can be used as a storage unit for storing various information necessary for the operation of memory controller 1300. Specifically, ROM 1360 may include a mapping table, and physical-to-logical address information and logical-to-physical address information can be stored in the mapping table. Moreover, ROM 1360 can be controlled by processor 1310.

[0122] The host interface 1370 may include protocols for exchanging data between the host 2000 and the memory controller 1300. Specifically, the host interface 1370 may communicate with the host 2000 via at least one of the following interface protocols: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Electronic Integrated Drive (IDE) protocol, and proprietary protocols.

[0123] The flash memory interface 1380 can communicate with the memory device 100 under the control of the processor 1310 using a communication protocol. Specifically, the flash memory interface 1380 can communicate commands, addresses, and data with the memory device 100 through channels. For example, the flash memory interface 1380 may include a NAND interface.

[0124] According to another embodiment of this disclosure, the memory controller 1300 may include a temperature sensor 140. Figure 9 The temperature sensor 140 shown may include, with Figure 2 or Figure 3 The temperature sensor 140 described herein has the same configuration and performs the same function as... Figure 2 or Figure 3 The temperature sensor 140 described herein has the same function. Specifically, the temperature sensor 140 can be disposed inside the memory controller 1300 to sense the temperature information of the memory controller 1300 under the control of the processor 1310. Moreover, in addition to the memory controller 1300, the temperature sensor 140 can also be disposed inside the memory device 1000 to obtain accurate temperature information of the memory device 1000. For example, the memory controller 1300 can obtain accurate temperature information by comparing the temperature information received from the temperature sensor 140 disposed inside the memory controller 1300 with the temperature information received from the temperature sensor 140 disposed in the memory device 100, and so on.

[0125] Figure 10 This is a diagram illustrating a storage block according to an embodiment of the present disclosure.

[0126] Reference Figure 10 , showed Figure 2 The diagram shows one of the memory blocks, BLKi. Within BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, BLKi can include multiple strings (ST) connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to the strings ST individually, and the source line SL can be connected collectively to the strings ST. The strings ST can be configured identically to each other; therefore, a string ST connected to the first bit line BL1 will be described in detail as an example.

[0127] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells F1 to F16, and a drain selection transistor DST. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and a string ST may include a greater number of memory cells than the number of memory cells F1 to F16 shown in the figures.

[0128] The source of the source select transistor (SST) can be connected to the source line SL, and the drain of the drain select transistor (DST) can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistors SST and the drain select transistors DST. The gates of the source select transistors SST included in different string STs can be connected to the source select line SSL, and the gates of the drain select transistors DST included in different string STs can be connected to the drain select line DSL. The gates of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word lines from different string STs can be called a physical page PPG. Therefore, a physical page PPG corresponding to the number of word lines WL1 to WL16 can be included in the memory block BLKi.

[0129] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0130] An SLC can store one bit of data. One physical page (PPG) of an SLC can store one logical page (LPG) of data. An LPG of data can include a number of data bits corresponding to the number of cells included in a physical page (PPG).

[0131] MLC, TLC, and QLC can store two or more bits of data. A physical page (PPG) can store two or more LPGs of data.

[0132] Figure 11 This is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0133] Reference Figure 11 The memory card system 3000 includes a memory controller 3100, a memory device 3200, and a connector 3300.

[0134] The memory controller 3100 can be connected to the memory device 3200. The memory controller 3100 can access the memory device 3200. For example, the memory controller 3100 can control read operations, write operations, erase operations, and background operations on the memory device 3200. The memory controller 3100 can provide an interface between the memory device 3200 and the host computer. Furthermore, the memory controller 3100 can drive the firmware used to control the memory device 3200.

[0135] For example, memory controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error corrector 233.

[0136] The memory controller 3100 can communicate with external devices via connector 3300. The memory controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. The memory controller 3100 can communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0137] The memory device 3200 can be implemented using various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0138] The memory controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 3100 and memory device 3200 can form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC and eMMC), SD cards (SD, mini SD, micro SD and SDHC), and universal flash memory (UFS).

[0139] Figure 12 This is a diagram illustrating a solid-state drive (SSD) according to an embodiment of the present disclosure.

[0140] Reference Figure 12 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals SIG with the host 4100 through a signal connector 4001 and receives power PWR through a power connector 4002. The SSD 4200 includes an SSD controller 4210, multiple flash memories 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0141] In this embodiment, the SSD controller 4210 can be used as a reference. Figure 1 or Figure 6 The memory controller 200 is described. The SSD controller 4210 can control multiple flash memories 4221 to 422n in response to a signal SIG received from the host 4100. The signal SIG can be a signal based on the interface between the host 4100 and the SSD 4200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0142] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive and charge power PWR from host 4100. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power to SSD 4200. Auxiliary power supply 4230 can be located inside SSD 4200 or externally to SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and provide auxiliary power to SSD 4200.

[0143] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple flash memories 4221 to 422n, or temporarily store metadata (e.g., mapping tables) of flash memories 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0144] Figure 13 This is a diagram illustrating a user system according to an embodiment of the present disclosure.

[0145] Reference Figure 13 The user system 5000 includes an application processor 5100, a memory module 5200, a network module 5300, a storage module 5400, and a user interface 5500.

[0146] Application processor 5100 can drive components, operating system (OS), user programs, etc., included in user system 5000. Application processor 5100 may include controllers for controlling components, interfaces, graphics engines, etc., included in user system 5000. Application processor 5100 can be configured as a system-on-a-chip (SoC).

[0147] Memory module 5200 can be used as main memory, working memory, buffer memory, or cache memory of user system 5000. Memory module 5200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. Application processor 5100 and memory module 5200 can be configured as a single semiconductor package by being packaged based on a PoP (PoP) architecture.

[0148] Network module 5300 can communicate with external devices. Network module 5300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Network module 5300 can be included in application processor 5100.

[0149] Storage module 5400 can store data. For example, storage module 5400 can store data received from application processor 5100. Optionally, storage module 5400 can transfer the stored data to application processor 5100. Storage module 5400 can be implemented using a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. Storage module 5400 can be configured as a memory card of user system 5000 or a removable drive of an external drive.

[0150] The storage module 5400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be used in conjunction with a reference. Figure 1 or Figure 2 The memory device described operates in the same manner. The memory module 4400 can be compared with the referenced... Figure 1 The storage device 1000 described operates in the same manner.

[0151] User interface 5500 may include interfaces for inputting data or commands to application processor 5100 or outputting data to external devices. User interface 5500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touchscreens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 5500 may include user output interfaces such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, and monitors.

[0152] According to this disclosure, a storage device that performs improved temperature management operations and a method of operating the storage device can be provided.

[0153] While this disclosure has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0154] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the described order, and the steps may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0155] Various embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations can exist within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0156] The embodiments described above are intended to illustrate, not limit, the invention. Various alternatives and equivalents are possible. The invention is not limited to the embodiments described herein. The invention is also not limited to any particular type of storage device. Any additions, reductions, or modifications that are apparent from this disclosure are intended to fall within the scope of the appended claims.

Claims

1. A storage device, comprising: Memory device, including a temperature sensor; and Memory controller: Perform a temperature acquisition operation to obtain temperature information sensed by the temperature sensor during the temperature management cycle. The minimum and maximum cycles are calculated based on the temperature information and the reference temperature management cycle. Based on historical information regarding the number of performance-limiting operations, the temperature management cycle is updated using at least one selected from the minimum and maximum cycles to limit the operational performance of the memory device. The temperature acquisition operation is performed according to the updated temperature management cycle.

2. The storage device according to claim 1, wherein the memory controller comprises: The cycle calculator calculates the minimum cycle and the maximum cycle by using the temperature change per unit time within each temperature management cycle and the reference temperature management cycle; Period Determiner: Based on the temperature information, one of the minimum period, the maximum period, and the arithmetic mean of the minimum period and the maximum period is determined as the current temperature response period, and The historical response period is determined based on the number of times the performance limiting operation is performed after power is applied to the storage device; as well as The cycle updater updates the temperature management cycle by using the current temperature response cycle, the historical response cycle, the minimum cycle, and the maximum cycle.

3. The storage device according to claim 2, wherein when the temperature change per unit time increases, the period calculator increases the minimum period and the maximum period.

4. The storage device of claim 2, wherein when the temperature change per unit time decreases, the period calculator decreases the minimum period and the maximum period.

5. The storage device according to claim 2, The cycle determiner determines the current temperature response cycle based on whether the temperature of the memory device corresponding to the temperature information falls within one of a first range, a second range, and a third range. The first range is a temperature range that is higher than a first temperature and lower than or equal to a second temperature. The second range is one or more of a temperature range above 0°C and below or equal to the first temperature and a temperature range above the second temperature and below or equal to the third temperature. The third range is one or more of a temperature range below or equal to 0°C and a temperature range above the third temperature.

6. The storage device according to claim 5, wherein when the temperature of the storage device corresponding to the temperature information is within the first range, the period determiner determines the maximum period as the current temperature response period.

7. The storage device according to claim 5, wherein when the temperature of the storage device corresponding to the temperature information is within the second range, the period determiner determines the arithmetic mean of the minimum period and the maximum period as the current temperature response period.

8. The storage device according to claim 5, wherein when the temperature of the storage device corresponding to the temperature information falls within the third range, the period determiner determines the minimum period as the current temperature response period.

9. The storage device of claim 2, wherein the memory controller further comprises: A temperature information storage device for storing the temperature information; as well as A historical information storage device that stores the number of times the performance limiting operation has been performed since power was applied to the storage device.

10. The storage device of claim 2, wherein the cycle updater updates the temperature management cycle by using the arithmetic mean of the current temperature response cycle and the historical response cycles.

11. The storage device of claim 1, wherein when the temperature of the storage device corresponding to the temperature information is higher than a third temperature, the storage controller performs the performance limiting operation that limits the performance of the storage device.

12. A method of operating a storage device, the storage device including a temperature sensor, the method comprising: Perform a temperature acquisition operation to obtain temperature information sensed by the temperature sensor during the temperature management cycle; The minimum and maximum cycles are calculated based on the temperature information and the reference temperature management cycle. Based on historical information regarding the number of performance-limiting operations, the temperature management cycle is updated using at least one selected from the minimum and maximum cycles. The temperature acquisition operation is performed according to the updated temperature management cycle.

13. The method of claim 12, wherein the minimum period and the maximum period are calculated by using the temperature change per unit time within each temperature management cycle and the reference temperature management cycle.

14. The method of claim 13, further comprising: Based on the temperature information, one of the minimum period, the maximum period, and the arithmetic mean of the minimum period and the maximum period is determined as the current temperature response period; and The historical response period is determined based on the number of times the performance limiting operation is performed after power is applied to the storage device.

15. The method of claim 14, wherein the temperature management cycle is updated by using the current temperature response cycle and the historical response cycle.

16. The method of claim 13, wherein the calculation comprises: As the temperature change per unit time increases, the minimum period and the maximum period are increased, and When the temperature change per unit time decreases, the minimum period and the maximum period are reduced.

17. The method according to claim 14, The current temperature response period is determined based on whether the temperature of the memory device corresponding to the temperature information falls within one of a first range, a second range, and a third range. The first range is a temperature range that is higher than a first temperature and lower than or equal to a second temperature. The second range is one or more of a temperature range above 0°C and below or equal to the first temperature and a temperature range above the second temperature and below or equal to the third temperature. The third range is one or more of a temperature range below or equal to 0°C and a temperature range above the third temperature.

18. The method according to claim 17, Wherein, when the temperature of the memory device corresponding to the temperature information falls within the first range, the maximum period is determined as the current temperature response period. Wherein, when the temperature of the memory device corresponding to the temperature information falls within the second range, the arithmetic mean of the minimum period and the maximum period is determined as the current temperature response period, and When the temperature of the memory device corresponding to the temperature information falls within the third range, the minimum period is determined as the current temperature response period.

19. The method of claim 12, further comprising storing the temperature information and the number of times the performance limiting operation is performed after power is applied to the storage device.

20. A storage device, comprising: Memory device, including a temperature sensor; and Memory controller: Perform a temperature management operation, the temperature management operation including a temperature acquisition operation to obtain temperature information sensed by the temperature sensor from the memory device, and a performance limiting operation to limit the performance of the memory device based on the temperature information; The temperature change per unit time is calculated based on the temperature information regarding the temperature management operation, the previous temperature information regarding the first temperature management operation performed before the temperature management operation, and the amount of time between the start time of the temperature management operation and the start time of the first temperature management operation. Based on the temperature change per unit time, calculate the first and second time points at which the second temperature management operation to be executed after the first temperature management operation will begin; and The final time point for starting the second temperature management operation is determined by using the temperature information, the cumulative number of times the performance limiting operation is performed, the first time point, and the second time point.

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