Apparatus and method for reading data from a memory cell

Abstract

Embodiments of the present disclosure relate to apparatuses and methods of reading data from memory cells. An integrated circuit includes a memory array. The memory array includes a plurality of bit lines. The bit lines are each coupled to a respective local I / O circuit. All of the local I / O circuits are coupled to a global I / O circuit. Each local I / O circuit includes a first sense stage for reading data from a memory cell. The global I / O circuit includes a second sense stage for reading data from a memory cell.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit memory cells. More specifically, this disclosure relates to read operations of memory cells. Background Technology

[0002] Integrated circuits typically include arrays of memory cells. For many integrated circuits, performing memory read and write operations at higher speeds is beneficial because it impacts the performance of the system-on-a-chip (SoC). However, factors such as parasitic capacitances in the bit lines can limit the speed of memory read and write operations. Efforts to reduce the negative effects of parasitic capacitances often result in other drawbacks. Summary of the Invention

[0003] In one or more embodiments, this disclosure provides an integrated circuit including a multi-port memory cell configured to store data values. The integrated circuit includes a plurality of bit lines, each bit line being coupled to the multi-port memory cell. The integrated circuit includes a plurality of local I / O circuits, each local I / O circuit being coupled to a corresponding bit line and including a first sensing level configured to sense data values ​​from the bit line when the bit line is selected for a read operation. The integrated circuit includes global I / O circuitry coupled to each local I / O circuit. The global I / O circuitry includes global bit lines that can be selectively coupled to receive data values ​​from local I / O circuitry coupled to the bit line selected for a read operation. The global I / O circuitry includes a second sensing level including evaluation circuitry configured to sense data values ​​on the global bit lines.

[0004] In one or more embodiments, the integrated circuit includes a memory array and a plurality of local I / O circuits. The memory array has a plurality of memory cell libraries. Each local I / O circuit is coupled to a corresponding memory cell library and includes a first sensing level configured to sense a data value from the corresponding memory cell library when the memory cell library is selected for a read operation. The integrated circuit includes global I / O circuitry coupled to each local I / O circuit. The global I / O circuitry includes global bit lines that can be selectively coupled to receive data values ​​from the local I / O circuitry coupled to the memory cell library selected for the read operation. The global I / O circuitry includes a second sensing level that includes evaluation circuitry configured to sense the data values ​​on the global bit lines.

[0005] In one or more embodiments, the method includes: storing a data value in a memory cell; selecting the memory cell for a read operation; and outputting the data value to a bit line coupled to the memory cell. The method also includes: sensing the data value from the bit line using local I / O circuitry coupled to the bit line; providing the data value from the local I / O circuitry to global I / O circuitry by selectively enabling the local I / O circuitry; and sensing the data value using the global I / O circuitry and outputting the data value from the global I / O circuitry. Attached Figure Description

[0006] Figure 1 It is a block diagram of an integrated circuit including a memory array according to one or more embodiments.

[0007] Figure 2 It is a block diagram of a memory array including multi-port memory cells according to one or more embodiments.

[0008] Figure 3 It is a block diagram of a memory array in a library configuration according to one or more embodiments.

[0009] Figure 4 This is a schematic diagram of a memory read circuit device for an integrated circuit according to one or more embodiments.

[0010] Figure 5 It is a timing diagram of signals associated with memory read operations according to one or more embodiments.

[0011] Figure 6 This is a schematic diagram of a memory read circuit device for an integrated circuit according to one or more embodiments.

[0012] Figure 7 This is a flowchart of a method for reading data from a memory cell of an integrated circuit, according to one embodiment. Detailed Implementation

[0013] Figure 1 This is a block diagram of an integrated circuit 100 according to one or more embodiments. The integrated circuit 100 includes a memory array 102. The memory array 102 may include a plurality of memory cells 104. For simplicity, Figure 1 Only a single memory cell 104 is shown in the diagram. The integrated circuit 100 also includes local I / O (LIO) circuitry 106 and global I / O (GIO) circuitry 108. As will be described in more detail below, the LIO circuitry 106 and GIO circuitry 108 are configured to enable fast read operations on the memory cell 104 while reducing the area used compared to conventional I / O circuits.

[0014] In some embodiments, memory cell 104 is a multi-port memory cell. A multi-port memory cell is a memory cell that can output data to multiple ports. In one example, integrated circuit 100 includes a multi-core processor (not shown). Each core of the processor can read data from the same memory cell. Therefore, the memory cell can be connected to a separate bit line for each core. This is an example of a multi-port memory cell.

[0015] The integrated circuit 100 includes a group 120 of four bit lines BL1-BL4. Each of the four bit lines BL1-BL4 is used to read data from memory cell 104 to one of four separate ports. Additionally, the integrated circuit 100 includes a group 122 of four word lines WL1-WL4. By selecting one bit line from BL1-BL4 and one sub-line from word lines WL1-WL4, data can be read from memory cell 104 to one of the ports. For example, if data is read from memory cell 104 to the first port, bit line BL1 and word line WL1 are selected.

[0016] In some embodiments, the integrated circuit includes a corresponding LIO circuit 106 for each bit line. Figure 1 In the example, there are four bit lines. Therefore, there are four LIO circuits 106. Each LIO circuit 106 is identical to each other. Each LIO circuit 106 includes a first sensing stage 110. When a bit line is selected for a read operation of memory cell 104, the first sensing stage 110 performs a first sensing operation on the corresponding bit line.

[0017] Each LIO circuit 106 is coupled to a corresponding GIO circuit 108. When a read operation is performed on one of the bit lines, the corresponding LIO circuit 106 senses the data on the bit line and transmits the sensed data value or its logical complement to the corresponding GIO circuit 108. The GIO circuit 108 then senses the data value provided from the LIO circuit 106 and outputs the data value to the corresponding output ports OUT1-OUT4.

[0018] Each GIO circuit 108 includes a second sensing stage 114 and a latch 116. The second sensing stage 114 senses a data value received from the LIO circuit 106. The second sensing stage 114 provides the data value to the latch 116. The latch 116 latches the output OUT of the GIO circuit 108 at the data value sensed by the second sensing stage 114. In this way, the GIO circuit 108 receives and outputs data values ​​from the LIO circuit 106. Receiving data values ​​from the LIO circuit 106 may include the logical complement of the received data value.

[0019] Integrated circuit 100 may include a large number of LIO circuits 106. In the case of multi-port memory cells, multiple LIO circuits 106 may be present for each column of memory cells in memory cell array 102. If each memory cell has four ports, then each column of memory cells in memory array 102 may have four LIO circuits 106. Furthermore, in some cases, as will be discussed below... Figure 3 To explain in more detail, memory array 102 may include multiple memory cell libraries to reduce parasitic capacitance between bit lines. The library configuration divides each column of memory cells into two or more groups of bit lines. The first half of the column may have a first set of bit lines. The second half of the column may have a second set of bit lines. Integrated circuits may include LIO circuitry 106 for each bit line of the two sets. Therefore, a large number of LIO circuits 106 may be present for the memory array library configuration.

[0020] One possible solution for reading data from memory cells in a multi-port or banked configuration is to include complex logic circuitry in each LIO circuit that senses data from the corresponding bit line. However, this solution results in a large area usage of the integrated circuit. This is because each LIO circuit would include complex logic circuitry to sense data from the corresponding bit line. If there are a large number of ports, banks, or both, the area consumed by the LIO circuits 106 together becomes very large.

[0021] Embodiments of this disclosure overcome the area loss drawbacks of other solutions by providing sensing stages in both the LIO circuit 106 and the GIO circuit 108. Specifically, each of the LIO circuits 106 includes a first sensing stage 110, which is very simple and consumes little area. The GIO circuit 108 includes a more complex second sensing stage 114.

[0022] For example, regarding Figure 3 In more detail, LIO circuit 106 and GIO circuit 108 can also be used in a sharded memory array configuration. Therefore, the integrated circuit 100 including LIO circuit 106 and GIO circuit 108 (as described in...) Figure 1 (As described in the following figures) It provides reliable multi-port or sharded memory sensing while consuming less area compared to other solutions.

[0023] Figure 2 This is a block diagram of a portion of a memory array 102 of an integrated circuit 200 according to one embodiment. Specifically, Figure 2The diagram illustrates a single column of memory cells. The column comprises four memory cells 104a-104d. In practice, each column may contain more than four memory cells. The memory array 102 includes bit line groups 120. In this case, the memory array 102 is a multi-port memory array, such that each column of memory cells has multiple bit lines. For each row of memory cells, the memory array 102 includes corresponding word line groups 122a-122d.

[0024] For each bit line, integrated circuit 200 includes information about... Figure 1 The corresponding LIO circuit 106 is described. Figure 2 The LIO circuit 106 can be used with Figure 1 Those shown are essentially the same, including the first sensing stage 110. Integrated circuit Figure 200 also includes multiple GIO circuits 108. Figure 2 The GIO circuit 108 can be used with Figure 1 The GIO circuit 108 is basically the same, including the second sensing level 114. Bit lines 120, word lines 122a-122d, LIO circuit 106 and GIO circuit 108 cooperate to perform read operations from memory cells 104a-104d.

[0025] Figure 3 This is a block diagram of a portion of a memory array 102 of an integrated circuit 300 according to one embodiment. Figure 3 In this configuration, the memory array is in a partitioned configuration. In this partitioned configuration, the memory array 102 is divided into two libraries or subarrays of memory cells.

[0026] As previously mentioned, when each column of memory cells includes a large number of memory cells, one or more bit lines (in a multi-port configuration) of a column of memory cells can become very long. The length of the bit lines results in very large parasitic capacitances between the bit lines. In one example, the memory cell array may include 512 rows of memory cells. Therefore, each column of memory cells will include 512 memory cells. To reduce the length of the bit lines, the memory array 102 is divided into two or more libraries. In a library configuration, half of the memory cells in each column are in a first library 103a, and the other half are in a second library 103b. As a result, the length of the bit lines is halved compared to a non-library configuration. This significantly reduces the parasitic capacitances between the bit lines. Furthermore, each library 103a, 103b may include a large number of columns of memory cells. More than two memory cell libraries may exist without departing from the scope of this disclosure.

[0027] exist Figure 3In the example, the first set of bit lines 120a is coupled to memory cells 104a and 104b of the first memory cell library 103a. The second set of bit lines 120b is coupled to memory cells 104c and 104d of the second memory cell library 103b. In practice, there may be more than two memory cells in each column of each memory cell library. For example, there may be 256 or more memory cells in each column of each memory cell library.

[0028] The first group of bit lines 120a includes bit lines 121a, 123a, 125a, and 127a. The second group of bit lines 120b includes bit lines 121b, 123b, 125b, and 127b. The partitioned memory array causes a single bit line to be split into two. For example, if the memory array were not partitioned, bit lines 121a and 121b would be consecutive single bit lines. Because the memory array is partitioned, the bit lines can be considered segmented bit lines. Bit lines 121a and 121b are single segmented bit lines. Bit lines 123a and 123b are single segmented bit lines. Bit lines 125a and 125b are single segmented bit lines. Bit lines 127a and 127b are single segmented bit lines. Each bit line from group 120a is coupled to a corresponding LIO circuit 106. Each bit line from group 120b is coupled to the corresponding LIO circuit 106.

[0029] A single GIO circuit 108 is associated with each segment bit line. Therefore, the LIO circuits coupled to bit lines 121a and 121b are coupled to a single GIO circuit 108. Two LIO circuits 108 coupled to bit lines 123a and 123b are coupled to a single GIO circuit 108. An LIO circuit 106 coupled to bit lines 125a and 125b is coupled to a single GIO circuit 108. An LIO circuit 106 coupled to bit lines 127a and 127b is coupled to a single GIO circuit 108.

[0030] from Figure 3 As can be seen in the example, the number of LIO circuits 106 can become very large for a multi-port memory cell library array. Additionally, a large number of memory cell columns can exist in each memory cell library, further increasing the number of LIO circuits 106. Therefore, since GIO circuits 108 are fewer than LIO circuits 106, moving more complex sensing circuitry from LIO circuits 106 to GIO circuits 108 provides a more efficient and efficient sensing solution for... Figure 1The described LIO circuit 106 and GIO circuit 108 offer significant area savings. If the memory array comprises four libraries instead of two, each segment bit line will include four bit lines, and each GIO circuit 108 will be coupled to four LIO circuits 106. Because increasing the number of memory libraries does not increase the number of GIO circuits 108, the area savings from moving complex circuitry from LIO circuits 106 to GIO circuits 108 increase with the number of memory libraries.

[0031] Figure 4 This is a schematic diagram of an integrated circuit 400 including a memory array 102 according to one embodiment. Figure 4 Only a single memory cell 104 of the memory array 102 is illustrated. Figure 4 In the example, memory cell 104 is an SRAM memory cell including two cross-coupled inverters 124a and 124b, but other types of memory cells may be used without departing from the scope of this disclosure. For simplicity, only one read port and latching element (the transfer transistor of the 6T element is not shown) of the 6T SRAM cell are shown. Similarly, Figure 4 Only one LIO 106 and GIO 108 circuit associated with only one port is shown.

[0032] A single bit line BL is coupled to memory cell 104 via NMOS transistors N1 and N2. Figure 4 In the example, memory array 102 can be a sub-library memory array in which memory array 102 is divided into multiple libraries. Each column of memory cells in each library can be coupled to a single bit line or multiple bit lines by means of a multiplexer. Each bit line is coupled to LIO circuit 106. A single word line WL is coupled to the gate of transistor N2 and multiple columns can be driven based on the size of the memory array. Word line WL is connected to word line driver 134. For simplicity, only one cell of a column is shown connected to a single bit line.

[0033] Bit line BL is coupled to the drain terminals of PMOS transistor P1 and NMOS transistor N3. The gate of PMOS transistor P1 receives the bit line precharge signal BPC. The gate of NMOS transistor N3 receives the bit line hold signal BK. The source of PMOS transistor P1 is coupled to the high supply voltage VDD. The source of NMOS transistor N3 is grounded.

[0034] LIO circuit 106 includes a first sensing stage 110. The first sensing stage 110 includes an inverter 126 and an arrangement of NMOS transistors N4 and N5 and PMOS transistors P2 and P3. The input of inverter 126 is coupled to bit line BL. The output of inverter 126 is supplied to the gate terminals of transistors N5 and P2. The gate of transistor N4 receives a select signal SEL. The gate of transistor P3 receives a select signal SELB, which is the logical complement of SEL. The source terminal of transistor P3 is coupled to VDD. The source terminal of transistor N4 is coupled to ground.

[0035] LIO circuit 106 includes a precharge detector 128 coupled to pseudo bit line DBL and pseudo inverter 132. Pseudo-circuit elements can be shared across various bit lines on the same port. LIO circuit 106 also includes selection circuitry 130 that generates selection signals SEL and SELB. The output of LIO circuit 106 is the drain terminals of transistors N5 and P2. The output of LIO circuit 106 is coupled to GIO circuit 108.

[0036] The GIO circuit 108 (shown for one port and one global bit line) includes a global bit line GBL and a second sensing stage 114. The second sensing stage 114 includes an inverter 140, a NOR gate 138, and a NAND gate 136. The second sensing stage 114 also includes an NMOS transistor N6 and a PMOS transistor P5. The global bit line GBL is coupled to the output of the LIO circuit 106, which goes into the input of the inverter 140. The global bit line GBL is also coupled to a holding circuit 142 and the drain terminal of the PMOS transistor P4. The gate terminal of transistor P4 receives the global precharge signal GPC. The source of transistor P4 is coupled to VDD.

[0037] The output of inverter 140 is coupled to the inputs of NOR gate 138 and NAND gate 136. The second input of NAND gate 136 receives the evaluation signal EVAL. The second input of NOR gate 138 receives the evaluation signal EVALB, which is the logical complement of EVAL. The output of NAND gate 136 is coupled to the gate terminal of PMOS transistor P5. The output of NOR gate 138 is coupled to the gate of transistor N6. The source of transistor N6 is coupled to ground. The source of transistor P5 is coupled to VDD. The drain terminals of transistors N6 and P5 are coupled together and correspond to the output terminal OUT of GIO circuit 108. GIO circuit 108 also includes latch 116, which latches the output terminal of GIO circuit 108 at the latest value supplied at the drain terminals of transistors N6 and P5. Latch 116 is coupled to holding circuit 142.

[0038] Figure 5 The illustration shows an embodiment of the invention.Figure 4 Timing diagram 500 shows the timing of various signals generated during the read operation of memory cell 104. Figure 4 The operation of the circuit device will be combined Figure 5 To describe it.

[0039] Figure 5 The clock signal CK is illustrated. At time t1, the clock signal CK transitions from a low logic level to a high hold value. The rising edge of the clock signal CK causes the bit line hold signal BK, the bit line precharge signal BPC, and the global bit line precharge signal GPC to transition from a high logic level to a low logic level (e.g., ground) at time t2 to prepare for a read operation of memory cell 104. As used herein, a high logic level may correspond to the power supply voltage VDD. A low logic level may correspond to ground.

[0040] When BK goes low, transistor N3 is turned off, decoupling the bit line BL from ground. When BPC goes low, transistor P1 is turned on, coupling the bit line BL to VDD. This precharges the bit line BL to VDD in preparation for a read operation. When GPC goes low, transistor P4 is turned on, coupling the global bit line GBL to VDD. This precharges the global bit line GBL to VDD in preparation for a read operation.

[0041] At time t3, bit line BL is pre-charged to VDD because the bit line pre-charge signal BPC has already coupled the bit line to VDD. In fact, once transistor P1 is turned on by BPC, bit line BL will begin to increase towards VDD. The charging of bit line BL also causes pseudo bit line DBL to charge. The charging of pseudo bit line DBL is detected by detector 128. The circuit operates on the assumption that if pseudo bit line DBL has reached VDD, then bit line BL will also reach VDD. Therefore, detector 128 senses when bit line BL is pre-charged instead of when pseudo bit line DBL is pre-charged.

[0042] At time t4, in response to detector 128 detecting that the dummy bit line is precharged, BPC and GPC transition from low logic level to high logic level. When BPC and GPC transition to high logic level, transistors P1 and P4 are turned off. This decouples bit line BL and global bit line GBL from VDD.

[0043] At time t4, in response to detector 128 detecting that the pseudo bit line DBL has been precharged, word line WL and select signal SEL go high. Word line driver 134 drives word line WL to VDD. Library select circuit 130 drives SEL to VDD. When word line WL goes high, transistor N2 is turned on. Depending on the value of the data stored in memory cell 104, bit line BL will transition to a low logic level or remain at a high logic level. The data value stored in memory cell 104 corresponds to the voltage at the output of inverter 124a. If the data value is 1 (VDD), transistor N1 is turned on and bit line BL is coupled to ground via N1 and N2 (because WL is high). If the data value is 0 (ground), transistor N1 is not turned on and bit line BL is not coupled to ground. In this case, bit line BL remains at a high logic level from the start of precharge.

[0044] exist Figure 5 In the example, the value stored in the memory cell is 1. Therefore, the bit line BL is coupled to ground, and at time t5, the bit line has switched to ground. When the bit line BL is grounded, the input of the inverter 126 of the LIO circuit 106 is grounded. The output of the inverter 126 goes high. Because the output of the inverter 126 is high, transistor P2 becomes non-conducting and transistor N5 becomes conducting. Since the select signal SEL is high, transistor N4 is conducting. Since the complementary select signal SELB is low, transistor P3 is conducting. Since P2 is not conducting, the drains of P2 and N5 are decoupled from VDD. Since N4 and N5 are conducting, the drains of P2 and N5 are coupled to ground. Therefore, the output of the LIO circuit 106 is grounded (low logic level). The operation of the first sensing stage 110 corresponds to the first sensing operation. The first sensing operation senses the data value stored in the memory cell 104 by sensing the complement of the data value stored in the memory cell 104.

[0045] At time t6, the global bit line GBL transitions to a low logic level. This is because, as described above, the output of LIO circuit 106 has transitioned to a low logic level. It is worth noting that, in practice, the global bit line GBL is coupled to the output of all LIO circuits 106, and all LIO circuits 106 are coupled to their respective bit lines in the memory array 102. However, transistors N4 and P3 of the other LIO circuits 106 are not turned on because SEL is low for them, as they are not selected for read operations. Only one LIO circuit 106 is selected for a read operation at a time. In this case, Figure 4 The LIO circuit 106 shown is selected for the read operation. The selection circuit 130 in the unselected LIO circuit 106 outputs a low value SEL.

[0046] At time t6, the evaluation signal EVAL goes high. The evaluation signal EVAL goes high in response to the word line WL going high, but with a delay. The delay value is selected to ensure that the global bit line GBL receives the data value (in this case, two's complement) stored in the memory unit 104. In practice, the evaluation signal EVAL may go high slightly earlier or slightly later than t6.

[0047] When GBL goes low at time t6, the input of inverter 140 receives a low logic level. Therefore, the output of inverter 140 provides a high logic level. NAND gate 136 receives a high EVAL signal and a high logic level from inverter 140. Therefore, NAND gate 136 outputs a low logic level. NOR gate 138 receives a low EVALB signal and a high logic level from inverter 140. Therefore, NOR gate 138 outputs a low logic level. The low logic level output by NOR gate 138 turns off transistor N6, thereby decoupling transistor N6 and the drain terminal of P5 from ground. The low voltage output by NAND gate 136 turns on transistor P5, thereby coupling transistor N6 and the drain terminal of P5 to VDD. Since the output OUT of GIO circuit 108 is coupled to the drain terminals of transistor N6 and P5, the output of GIO circuit 108 is a high logic level at time t7. This is the value stored in memory cell 104. Latch 116 latches the output OUT of GIO circuit 108 to this value. At t8, the evaluation signal EVAL transitions from a high logic level to a low logic level (managed by an internal delay). However, because latch 116 has already latched the output of GIO circuit 108 to the latest value, the output OUT of GIO circuit 108 remains at a high logic level.

[0048] At time t9, the bit line hold signal BK transitions to a high logic level, internally timed. Similarly, word line driver 134 drives word line WL to a low logic level, and library select circuit 130 also drives select signal SEL to a low logic level. Because transistor N3 is now turned on, bit line BL is coupled to ground. Therefore, bit line BL is grounded after each read operation. Conversely, the global bit line GBL is not grounded after each read operation. Instead, the global bit line GBL is held at the latest value between read cycles by hold circuit 142.

[0049] Figure 6 This is a schematic diagram of an integrated circuit 600 including a multi-port memory cell 104. The multi-port memory cell 104 is an SRAM memory cell including cross-coupled inverters 124a and 124b. Four bit lines BL1-BL4 and four word lines WL1-WL4 are coupled to the memory cell 104.

[0050] Inverter 124a includes a PMOS transistor P6 and an NMOS transistor N7 with gate and drain terminals coupled together. Inverter 124b includes a PMOS transistor P7 and an NMOS transistor N8 with gate and drain terminals coupled together. The source terminals of transistors P7 and P6 are coupled to VDD. The source terminals of transistors N8 and N7 are coupled to ground. The drain terminals of transistors P6 and N7 correspond to the output of memory cell 104, which drives the gate terminals of N11, N13, N15, and N17. Therefore, the value of the data stored in memory cell 104 is the logic level at the drain terminals of transistors P6 and N7.

[0051] NMOS transistor N9 is coupled between the output of inverter 124b and the dummy bit line BLF. NMOS transistor N10 is coupled between the output of inverter 124a and the true bit line BLT. The gate terminals of transistors N9 and N10 receive the word line write signal WLW for writing data to memory cell 104. Therefore, N9, N10, BLF, and BLT are used only for write operations to memory cell 104.

[0052] NMOS transistors N11, N13, N15, and N17 have source terminals coupled to ground and gate terminals coupled to the output of memory cell 104. NMOS transistors N12, N14, N16, and N18 are coupled between their respective bit lines BL1-BL4 and their respective transistors in N11, N13, N15, and N17. The gate terminals of N12, N14, N16, and N18 are coupled to their respective word lines WL1-WL4. The transistors coupled to bit lines BL1-BL4 perform operations related to… Figure 4 and 5 The transistors N1 and N2 described have the same function.

[0053] Each bit line BL1-BL4 is coupled to the corresponding LIO circuits 106a-106d. The LIO circuits 106a-106d are identical to each other. Figure 6 Only the LIO circuit 106d coupled to bit line BL4 is shown in detail. LIO circuits 106a-106d and... Figure 4 The LIO circuit 106 is identical. Each circuit in LIO circuits 106a-106d is connected to the global bit line of the corresponding GIO circuit 108. Figure 6 The functions of LIO circuits 106a-106d and GIO circuits 108a-108d and related information Figure 4 and Figure 5 The LIO circuit 106 and GIO circuit 108 shown and described are basically the same.

[0054] When data is read from memory cell 104 into one of the ports, the corresponding word line and bit line are selected. The selected word line driver drives the word line high. (See also: Regarding...) Figure 4 and Figure 5 The selected positioning line is pre-charged in preparation for the read operation. (See also: Regarding...) Figure 4 and Figure 5 As described, the corresponding LIO 106 receives a high SEL signal, and data from the memory cell is sensed by the first sensing level 110 and transmitted to the global bit line GBL of the GIO circuit 108. (See also: ...) Figure 4 and Figure 5 As described, the GIO circuit 108 senses the data value on the global bit line GBL and outputs the data value at the output OUT.

[0055] Figure 7 This is a flowchart of a method 700 for reading data from a memory cell according to one embodiment. At 702, according to one embodiment, method 700 includes storing a data value in the memory cell. At 704, according to one embodiment, method 700 includes selecting a memory cell for a read operation. According to one embodiment, at 706, method 700 includes outputting a data value to a bit line coupled to the memory cell. At 708, according to one embodiment, method 700 includes sensing a data value from the bit line using local I / O circuitry coupled to the read bit line. At 710, according to one embodiment, method 700 includes providing a data value from local I / O circuitry to global I / O circuitry by selectively enabling the local I / O circuitry. At 712, according to one embodiment, method 700 includes using global I / O circuitry to sense a data value. At 714, according to one embodiment, method 700 includes outputting a data value from the global I / O circuitry.

[0056] The various embodiments described above can be combined to provide further embodiments. Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalence claimed by such claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An integrated circuit, comprising: Memory units are configured to store data values; Bit lines are coupled to the memory cells; Local I / O circuitry is coupled to the bit line and includes a first sensing level configured to sense the data value from the bit line when the bit line is selected for a read operation. as well as A global I / O circuit, coupled to the local I / O circuit, and comprising: A global bit line can be selectively coupled to receive the data value from the local I / O circuit that is coupled to the bit line selected for the read operation; as well as The second sensing stage includes evaluation circuitry configured to sense the data values ​​on the global bit lines. The first sensing stage includes a first inverter having an input coupled to the corresponding bit line. The second sensing stage includes a second inverter having an input coupled to the global bit line.

2. The integrated circuit according to claim 1, wherein the second sensing stage comprises: The first logic gate has the following characteristics: The first input is coupled to the output of the second inverter; The second input is configured to receive the first evaluation enable signal; as well as The output is coupled to the global I / O circuit.

3. The integrated circuit according to claim 2, wherein the second sensing stage comprises: The second logic gate has: The first input is coupled to the output of the second inverter; The second input is configured to receive a second evaluation enable signal; as well as The output is coupled to the global I / O circuit.

4. The integrated circuit of claim 3, wherein the global I / O circuit includes a latch coupled to the output of the first logic gate and the output of the second logic gate.

5. The integrated circuit according to claim 4, wherein the first logic gate is a NAND gate and the second logic gate is a NOR gate.

6. The integrated circuit of claim 1, wherein the first sensing stage includes a selection circuit coupled to the output of the first inverter and configured to selectively provide the data value to the global bit line in response to a selection signal by inverting a signal output from the first inverter.

7. The integrated circuit of claim 6, wherein the selection circuit comprises: The first NMOS transistor has a gate terminal coupled to the output of the first inverter and a drain terminal coupled to the global bit line; as well as The first PMOS transistor has a gate terminal coupled to the output of the first inverter and a drain terminal coupled to the drain terminal of the first NMOS transistor.

8. The integrated circuit of claim 7, wherein the selection circuit comprises: The second NMOS transistor has a drain terminal coupled to the source terminal of the first NMOS transistor and a source terminal coupled to ground; as well as The second PMOS transistor has a drain terminal coupled to the source terminal of the first PMOS transistor and a source terminal coupled to a high-voltage power supply.

9. An integrated circuit, comprising: A memory array comprising columns of memory cells separated into libraries; The segmented bit lines associated with the column of memory cells comprise multiple bit lines that are not contiguous with each other, and each bit line is coupled to a memory cell of the corresponding library. Multiple local I / O circuits are each coupled to a corresponding bit line of the segmented bit line and include a first sensing level configured to sense data values ​​from memory cells of the corresponding library when the memory cells of the library are selected for a read operation. Global I / O circuitry, coupled to each of the local I / O circuitry and comprising: Global bit lines can be selectively coupled to receive the data value from the local I / O circuitry coupled to the memory cell selected for the read operation; as well as The second sensing stage includes evaluation circuitry configured to sense the data values ​​on the global bit lines. The first sensing level includes a first inverter having an input coupled to the bit line, and the second sensing level includes a second inverter having an input coupled to the global bit line.

10. The integrated circuit of claim 9, wherein the memory array is an SRAM memory array.

11. The integrated circuit of claim 9, wherein the memory cell is a multi-port memory cell.

12. The integrated circuit of claim 11, wherein the first sensing level is configured to sense the data value from a selected memory cell by sensing the data value from the corresponding bit line.

13. A method for reading data, comprising: Store the data values ​​in the memory unit; Select the memory cell for the read operation; The data value is output to a bit line coupled to the memory cell; The data value from the bit line is sensed using local I / O circuitry coupled to the bit line. The local I / O circuitry includes a first sensing stage configured to sense the data value from the bit line when the bit line is selected for a read operation. The first sensing stage includes a first inverter having an input coupled to the corresponding bit line. By selectively enabling the local I / O circuit, the data value from the local I / O circuit is provided to the global I / O circuit, which is coupled to the local I / O circuit and includes a global bit line that can be selectively coupled to receive the data value from the local I / O circuit coupled to the bit line selected for the read operation. And a second sensing stage, including evaluation circuitry configured to sense the data value on the global bit line, the second sensing stage including a second inverter having an input coupled to the global bit line; The global I / O circuitry is used to sense the data value; as well as The data value is output from the global I / O circuit.

14. The method of claim 13, wherein using the local I / O circuit to sense the data value comprises: The data value is inverted using the first inverter of the local I / O circuit.

15. The method of claim 14, wherein providing the data value from the local I / O circuit to the global I / O circuit comprises: The data value from the local I / O circuit is provided to the global bit line of the global I / O circuit.

16. The method of claim 15, wherein using the global I / O circuit to sense the data value comprises: Invert the data values ​​from the global bit line.

17. The method of claim 13, further comprising: The bit line is discharged between each read operation by coupling it to ground. as well as Between each read operation, the global bit line is held at a voltage corresponding to the data value of the latest read operation.

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