Method of forming dynamic random access memory

Abstract

A method for forming a dynamic random access memory includes: forming a first trench and a second trench through the active region along the second direction, the first trench and the second trench each extending from the first surface to the second surface, and the first trench is located in the word line region, and the second trench is located in the channel region; forming a word line gate structure and a first isolation structure on the first trench sidewall, and two word line gate structures in each first trench are isolated from each other by the first isolation structure; forming a second isolation structure in the second trench; after forming the word line gate structure, the first isolation structure and the second isolation structure, the substrate is thinned from the direction of the second surface to the first surface until the second trench is exposed. The first trench and the second trench are formed in the same photoetching process, which is beneficial to forming a uniform device channel and improving the stability of device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a dynamic random access memory. Background Technology

[0002] With the rapid development of technology, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.

[0003] A basic memory cell in Dynamic Random Access Memory (DRAM) consists of a storage transistor and a storage capacitor, while a memory array consists of multiple storage cells. The storage capacitor stores the charge representing the stored information, and the storage transistor acts as a switch controlling the inflow and outflow of charge from the storage capacitor. The storage transistor is also connected to the internal circuitry within the memory and receives control signals from the internal circuitry. Each storage transistor contains an active region, a drain region, and a gate. The gate controls the current flow between the source and drain regions and connects to the word line. The drain region forms the bit line contact region to connect to the bit line, and the source region forms the memory node contact region to connect to the storage capacitor. With the continuous development of integrated circuit manufacturing technology, there is a need to further increase the device density of memory chips to achieve greater data storage capacity.

[0004] However, existing dynamic random access memory still has many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a dynamic random access memory, which can improve the stability of device performance.

[0006] To address the aforementioned problems, the present invention provides a method for forming a dynamic random access memory (DRAM), comprising: providing a substrate having a first surface and a second surface opposite to each other; the substrate including a plurality of mutually discrete active regions parallel to a first direction, and the plurality of active regions arranged along a second direction, the first direction being perpendicular to the second direction; each active region including a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each active region being spaced apart along the first direction; forming a first trench and a second trench penetrating the active regions along the second direction, the first trench and the second trench both extending from the first surface to the second surface, and the first trench being located within the word line region and the second trench being located within the channel region; forming a word line gate structure and a first isolation structure on the sidewall of the first trench, and the two word line gate structures in each of the first trenches being isolated from each other by the first isolation structure; forming a second isolation structure in the second trench; and after forming the word line gate structure, the first isolation structure and the second isolation structure, thinning the substrate from the second surface to the first surface until the second trench is exposed.

[0007] Optionally, the width of the first groove is greater than the width of the second groove.

[0008] Optionally, the method for forming the plurality of first trenches and the plurality of second trenches includes: forming a first mask layer on the first surface, the first mask layer having a first opening and a second opening, the first opening exposing the surface of the word line region, the second opening exposing a portion of the surface of the channel region, the size of the first opening along the first direction being larger than the size of the second opening along the first direction; etching the active region using the first mask layer as a mask to form the plurality of first trenches and the plurality of second trenches.

[0009] Optionally, the first mask layer includes a plurality of mutually independent sidewalls, each of which has the same dimension along the first direction.

[0010] Optionally, the word line grid structure is formed first, and then the second isolation structure is formed; the method further includes: after forming the plurality of first trenches and the plurality of second trenches, forming a protective layer in the plurality of second trenches; after forming the word line grid structure and before forming the second isolation structure, removing the protective layer in the plurality of second trenches to expose the plurality of second trenches.

[0011] Optionally, the method for forming the protective layer includes: forming an initial protective layer in the plurality of first trenches and the plurality of second trenches; forming a second mask layer on the first surface, the second mask layer exposing the surface of the initial protective layer in the plurality of first trenches; using the second mask layer as a mask, etching the initial protective layer in the plurality of first trenches to expose the surface of the plurality of first trenches, thereby forming the protective layer with the initial protective layer in the plurality of second trenches.

[0012] Optionally, the method for forming the plurality of first trenches and the plurality of second trenches includes: forming a first mask layer on the first surface, the first mask layer having a first opening and a second opening, the first opening exposing a portion of the word line region surface, the second opening exposing a portion of the channel region surface, the first opening and the second opening having the same size; etching the active region using the first mask layer as a mask to form a plurality of initial first trenches and the plurality of second trenches; etching the plurality of initial first trenches to form the plurality of first trenches.

[0013] Optionally, the word line grid structure is formed first, and then the second isolation structure is formed; the method further includes: after forming the plurality of initial first trenches and the plurality of second trenches, and before etching the plurality of initial first trenches, forming a protective layer in the plurality of second trenches; after forming the protective layer, etching the plurality of initial first trenches to form the plurality of first trenches; after forming the word line grid structure, and before forming the second isolation structure, removing the protective layer in the plurality of second trenches to expose the plurality of second trenches.

[0014] Optionally, the method for forming the protective layer includes: forming an initial protective layer within the plurality of initial first trenches and the plurality of second trenches; forming a second mask layer on the first surface, the second mask layer exposing the surface of the initial protective layer within the plurality of initial first trenches; using the second mask layer as a mask, etching the initial protective layer within the plurality of initial first trenches to expose the surface of the plurality of initial first trenches, thereby forming the protective layer with the initial protective layer within the plurality of second trenches.

[0015] Optionally, the word line grid structure includes a word line grid layer.

[0016] Optionally, the method for forming the word line gate structure and the first isolation structure includes: forming an initial word line gate layer in each of the first trenches; etching a portion of the initial word line gate layer from the first surface to the second surface; forming a plurality of third trenches parallel to the second direction in the substrate; the third trenches penetrating the initial word line gate layer from the first surface to the second surface to form the word line gate layer; and forming the first isolation structure in the third trenches.

[0017] Optionally, the method for forming the word line grid structure and the first isolation structure includes: forming an initial word line grid layer on the sidewall and bottom of the first trench and on the first surface, wherein the initial word line grid layer in the first trench has an initial third trench; removing the initial word line grid layer at the bottom of the first trench to form a third trench with the initial third trench; forming the first isolation structure in the third trench; and after forming the first isolation structure, removing the initial word line grid layer exposed by the first isolation structure to form the word line grid layer with the initial word line grid layer.

[0018] Optionally, the word line grid structure further includes a gate dielectric layer located between the first trench sidewall and the word line grid layer.

[0019] Optionally, the formation process of the gate dielectric layer includes an oxidation process; the method of forming the gate dielectric layer includes: forming the gate dielectric layer on the sidewall of the first trench before forming the word line gate layer.

[0020] Optionally, before forming the gate dielectric layer, the method further includes: oxidizing the sidewall of the first trench to form an oxide layer on the sidewall of the first trench; and removing the oxide layer.

[0021] Optionally, before forming the word line grid structure, a first insulating layer is formed at the bottom of the first trench; the word line grid structure is located on the first insulating layer.

[0022] Optionally, the thinning process includes: thinning the substrate from the second surface toward the first surface until the surface of the first insulating layer or the surface of the second isolation structure is exposed.

[0023] Optionally, the top surface of the first insulating layer is higher than or flush with the bottom surface of the second trench.

[0024] Optionally, the method for forming the first insulating layer includes: forming an initial first insulating layer in the first trench; and etching back the initial first insulating layer to form the first insulating layer.

[0025] Optionally, it further includes: after forming the word line gate structure, the first isolation structure, and the second isolation structure, forming a first source / drain doped region in the first surface of each of the active regions; after forming the first source / drain doped region, forming a plurality of capacitor structures on the first surface, each capacitor structure being electrically connected to one of the first source / drain doped regions; after the thinning process, forming a second source / drain doped region in the second surface of each of the active regions; forming a plurality of bit lines parallel to the first direction on the second surface, each bit line being electrically connected to a plurality of the second source / drain doped regions in one of the active regions.

[0026] Optionally, the top surface of the word line grid structure is lower than the first surface, and the top of the word line grid structure has a second insulating layer.

[0027] Optionally, the method for forming the word line grid structure and the second insulating layer further includes: after forming the first isolation structure and before forming the second isolation structure, forming the second insulating layer in the first trench and on the word line grid structure.

[0028] Optionally, the second isolation structure has a closed gap.

[0029] Optionally, the thinning process includes a mechanical-chemical grinding process.

[0030] Optionally, a third isolation layer may also be provided between adjacent active regions.

[0031] Optionally, the first trench has a first width value, the second trench has a second width value, and the difference between the first width value and the second width value ranges from 5 nanometers to 50 nanometers; the first trench has a first depth value, the second trench has a second depth value, and the difference between the first depth value and the second depth value ranges from 50 nanometers to 100 nanometers.

[0032] Optionally, the formation process of the first trench and the second trench includes a self-aligned dual imaging process.

[0033] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0034] In the method of forming the technical solution of the present invention, a first trench and a second trench are formed along the second direction through the active region. The first trench and the second trench both extend from the first surface to the second surface, and the first trench is located in the word line region, and the second trench is located in the channel region. The first trench and the second trench are formed by a single photolithography process, which does not require consideration of the alignment deviation problem of two photolithography processes, which is beneficial to forming a uniform device channel and improving the stability of device performance.

[0035] Further, a first mask layer is formed on the substrate surface. The first mask layer has a first opening and a second opening. The first opening exposes the surface of the word line region, and the second opening exposes a portion of the surface of the channel region. The size of the first opening along the first direction is larger than the size of the second opening along the first direction. The active region is etched using the first mask layer as a mask to form the plurality of first trenches and the plurality of second trenches. Because the size of the first opening is larger than the size of the second opening, the width of the formed first trench is larger than that of the second trench, and under the influence of the photolithography load effect, the depth of the formed first trench is greater than that of the second trench.

[0036] Furthermore, the active region is etched using the first mask layer as a mask to form a plurality of initial first trenches and a plurality of second trenches; the plurality of initial first trenches are then etched to form the plurality of first trenches. Forming the first trenches by etching the initial first trenches is more advantageous for the method of forming the first and second trenches using the loading effect, and it is also beneficial for controlling the size and depth of the formed first trenches.

[0037] Furthermore, before forming the gate dielectric layer, the method further includes: oxidizing the sidewalls of the first trench to form an oxide layer on the sidewalls of the first trench; and removing the oxide layer. This method not only improves the quality of the formed gate dielectric layer and enhances the gate control capability of the gate oxide, but also increases the width of the first trench.

[0038] Furthermore, the second isolation structure has closed gaps, which can improve the insulation capacity of the second isolation structure and increase the isolation effect. Attached Figure Description

[0039] Figure 1 and Figure 2 This is a cross-sectional schematic diagram of a dynamic random access memory.

[0040] Figures 3 to 14 This is a schematic diagram of the structure of each step in a method for forming a dynamic random access memory according to an embodiment of the present invention;

[0041] Figures 15 to 27 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory according to another embodiment of the present invention. Detailed Implementation

[0042] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0043] As described in the background section, existing dynamic random access memories still have many problems. These will be explained in detail below.

[0044] Figure 1 and Figure 2 This is a cross-sectional schematic diagram of a dynamic random access memory.

[0045] Please refer to Figure 1 The dynamic random access memory (DRAM) includes: a substrate having a first surface 100 and a second surface 101 opposite to each other; the substrate including a plurality of mutually discrete active regions parallel to a first direction, and the plurality of active regions arranged along a second direction, the first direction being perpendicular to the second direction; each active region including a plurality of word line regions I and a plurality of channel regions II, and the plurality of word line regions I and the plurality of channel regions II in each active region being spaced apart along the first direction; a word line gate trench (not shown in the figure) located in each word line region I, the word line gate trench extending from the first surface 100 to the second surface 101, and the word line gate trench penetrating the active region along the second direction; a first insulating layer 102 located at the bottom of the word line gate trench, the second surface 101 exposing the first insulating layer 102; and two mutually discrete word line gate structures 103 located in each word line gate trench and on the first insulating layer 102; bit A second insulating layer 104 is located within the word line gate trench and on the word line gate structure 103; a first isolation trench (not shown) is located between two word line gate structures 103 and within the second insulating layer 104; a first isolation structure 105 is located within the first isolation trench; a second isolation trench (not shown) is located within each of the channel regions II; a second isolation structure 106 is located within the second isolation trench; a first source / drain doped region 107 is located within the first surface 100 of each of the channel regions II; a plurality of capacitor structures 108 are located on the first surface 100, each capacitor structure 108 being electrically connected to one of the first source / drain doped regions 107; a second source / drain doped region 109 is located within the second surface 101 of each of the channel regions II; a plurality of bit lines 110 are located on the second surface 101 parallel to the first direction, each bit line 110 being electrically connected to a plurality of the second source / drain doped regions 109 in one of the active regions.

[0046] The above structure is a vertical channel memory, whose channels are obtained by forming the word line gate trench and the second isolation trench, respectively. In the two photolithography processes that form the word line gate trench and the second isolation trench, optical alignment deviations and dimensional errors in the photolithography and etching processes can cause inconsistencies in the size of adjacent conductive channels, such as... Figure 2 As shown, channel A is larger than channel B, which results in poor uniformity of the electrical performance of the formed device and reduces the stability of the device performance.

[0047] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure, comprising forming a first trench and a second trench extending through the active region along a second direction. Both the first trench and the second trench extend from the first surface to the second surface, with the first trench located within the word line region and the second trench located within the channel region. The first trench and the second trench are formed using a single photolithography process, eliminating the need to consider alignment deviations from two photolithography processes, thus facilitating the formation of uniform device channels and improving the stability of device performance.

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Figures 3 to 14 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory according to an embodiment of the present invention.

[0050] Please refer to Figures 3 to 5 , Figure 3 yes Figure 4 and Figure 5 A top-view structural diagram. Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along the DD1 direction. Figure 5 yes Figure 3 A cross-sectional structural schematic diagram along the direction of EE1 shows a substrate 200 having a first surface 200a and a second surface 200b. The substrate 200 includes a plurality of mutually discrete active regions parallel to a first direction X, and the plurality of active regions are arranged along a second direction Y. The first direction X is perpendicular to the second direction Y. Each active region includes a plurality of word line regions 201 and a plurality of channel regions 202, and the plurality of word line regions 201 and the plurality of channel regions 202 in each active region are arranged at intervals along the first direction X.

[0051] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0052] In this embodiment, a third isolation layer 203 is also provided between adjacent active regions.

[0053] The method for forming the active region and the third isolation layer 203 includes: forming a patterned layer (not shown in the figure) on a first surface 200a of the substrate 200, the patterned layer exposing a portion of the surface of the first surface 200a; using the patterned layer as a mask, etching the first surface 200a to form the active region in the substrate 200, with an opening (not shown in the figure) between adjacent active regions; and forming the third isolation layer 203 in the opening.

[0054] The material of the third isolation layer 203 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0055] The word line region 201 is used to form a word line gate structure, and the channel region 202 is used to form a channel for the device.

[0056] Subsequently, a first trench and a second trench are formed that penetrate the active region along the second direction Y. Both the first trench and the second trench extend from the first surface 200a to the second surface 200b, and the first trench is located in the word line region 201, while the second trench is located in the channel region 202.

[0057] In this embodiment, the method for forming the plurality of first trenches and the plurality of second trenches is described in reference [reference needed]. Figure 6 .

[0058] Please refer to Figure 6 , Figure 6 The view direction is the same Figure 5 A first mask layer 204 is formed on the first surface 200a. The first mask layer 204 has a first opening 205 and a second opening 206. The first opening 205 exposes the surface of the word line region 201, and the second opening 206 exposes a portion of the surface of the channel region 202. The size of the first opening 205 along the first direction X is larger than the size of the second opening 206 along the first direction X. The active region is etched using the first mask layer 204 as a mask to form the plurality of first trenches 207 and the plurality of second trenches 208.

[0059] After forming the plurality of first trenches 207 and the plurality of second trenches 208, the first mask layer 204 is also removed.

[0060] The width of the first trench 207 is greater than the width of the second trench 208. The width refers to the dimension along the surface direction of the substrate 200.

[0061] Since the size of the first opening 205 is larger than the size of the second opening 206, the width of the first trench 207 is greater than that of the second trench 208, and under the influence of the load effect of photolithography, the depth of the first trench 207 is greater than that of the second trench 208.

[0062] The first trench 207 and the second trench 208 are formed by a single photolithography process, which eliminates the need to consider the alignment deviation problem of two photolithography processes, thus facilitating the formation of uniform device channels and improving the stability of device performance.

[0063] The formation process of the first trench 207 and the second trench 208 includes a self-aligned dual imaging process.

[0064] Specifically, the first mask layer 204 includes a plurality of mutually independent sidewalls (not shown in the figure), each of which has the same dimension along the first direction X. Since the sidewalls have the same dimension along the first direction X, etching the active region using the first mask layer 304 as a mask results in a device channel with the same width. The width refers to the direction along the first direction X.

[0065] In this embodiment, the method for forming the first mask layer 204 includes: forming a first mask material layer (not shown in the figure) on the first surface 200a; forming a plurality of sacrificial layers (not shown in the figure) on the surface of the first mask material layer, wherein the plurality of sacrificial layers are parallel to the second direction Y and arranged along the first direction X; forming a patterned material layer (not shown in the figure) on the surface of the first mask material layer, the sidewalls of the sacrificial layers and the top surface; etching back the patterned material layer and forming a patterned layer on the sidewalls of the sacrificial layers; using the patterned layer as a mask, etching the first mask material layer to form the plurality of mutually independent sidewalls.

[0066] In this embodiment, the material of the first mask material layer is silicon nitride, the material of the patterning material layer is silicon oxide, and the material of the sacrificial layer is amorphous carbon.

[0067] In this embodiment, the first trench 207 and the second trench 208 are formed simultaneously in a single photolithography etching process, which can reduce the number of processes and save production costs.

[0068] The first trench 207 has a first width value m, and the second trench 208 has a second width value n. The difference between the first width value m and the second width value n ranges from 5 nanometers to 50 nanometers. The first trench 207 has a first depth value h1, and the second trench 208 has a second depth value h2. The difference between the first depth value h1 and the second depth value h2 ranges from 50 nanometers to 100 nanometers.

[0069] Subsequently, a word line grid structure and a first isolation structure are formed on the sidewall of the first trench 207, and the two word line grid structures in each of the first trenches 207 are isolated from each other by the first isolation structure; a second isolation structure is formed in the second trench 208.

[0070] In this embodiment, the word line grid structure is formed first, followed by the second isolation structure. In another embodiment, the second isolation structure may be formed first, followed by the word line grid structure.

[0071] Please refer to Figure 7 , Figure 7 The view direction is the same Figure 5 After forming the plurality of first trenches 207 and the plurality of second trenches 208, a protective layer 209 is formed in the plurality of second trenches 208.

[0072] The method for forming the protective layer 209 includes: forming an initial protective layer (not shown in the figure) in the plurality of first trenches 207 and the plurality of second trenches 208; forming a second mask layer (not shown in the figure) on the first surface 200a, the second mask layer exposing the surface of the initial protective layer in the plurality of first trenches 207; using the second mask layer as a mask, etching the initial protective layer in the plurality of first trenches 207 to expose the surface of the plurality of first trenches 207, and forming the protective layer 209 with the initial protective layer in the plurality of second trenches 208.

[0073] The protective layer 209 is made of organic materials. These organic materials are easily filled into the first trench 207 and the second trench 208 by spin coating or spraying, and are also easily removed completely during subsequent removal.

[0074] In this embodiment, the organic material includes organic carbon.

[0075] In this embodiment, the formation process of the protective layer 209 includes a spin coating process.

[0076] Subsequently, a word line grid structure and a first isolation structure are formed on the sidewall of the first trench. The word line grid structure includes a word line grid layer. For the method of forming the word line grid structure and the first isolation structure in this embodiment, please refer to... Figures 8 to 9 .

[0077] Please refer to Figure 8 , Figure 8 The view direction is the same Figure 5 An initial word line gate layer is formed within each of the first trenches 207.

[0078] In this embodiment, before forming the word line grid structure, a first insulating layer 210 is formed at the bottom of the first trench 207.

[0079] Specifically, before forming the initial word line grid layer, a first insulating layer 210 is formed at the bottom of the first trench 207.

[0080] The top surface of the first insulating layer 210 is higher than or flush with the bottom surface of the second trench 208. This provides space for the subsequent formation of second source / drain doped regions within the second surface 200b of each active region. In this embodiment, the top surface of the first insulating layer 210 is higher than the bottom surface of the second trench 208.

[0081] The method for forming the first insulating layer 210 includes: forming an initial first insulating layer (not shown in the figure) in the first trench 207; and etching back the initial first insulating layer to form the first insulating layer 210.

[0082] The method for forming the initial first insulating layer includes: forming a first dielectric material layer (not shown in the figure) in the first trench 207 and on the first surface 200a; planarizing the first dielectric material layer until the surface of the first surface 200a is exposed.

[0083] The material of the first insulating layer 210 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0084] In this embodiment, the initial word line gate layer includes an initial work function layer 212 and an initial gate 213 located on the initial work function layer 212.

[0085] In this embodiment, the method for forming the initial word line gate layer includes: forming a power function material layer (not shown in the figure) on the surface of the first surface 200a and the first insulating layer 210; forming a gate material layer (not shown in the figure) on the power function material layer, wherein the power function material layer and the gate material layer fill the first trench 207; planarizing the power function material layer and the gate material layer until the surface of the first surface 200a is exposed, forming the initial power function layer 212 with the power function material layer, and forming the initial gate 213 with the gate material layer.

[0086] In this embodiment, before forming the word line gate layer, the gate dielectric layer 211 is also formed on the sidewall of the first trench 207.

[0087] Specifically, before forming the initial word line gate layer, the gate dielectric layer 211 is also formed on the sidewall of the first trench 207.

[0088] The formation process of the gate dielectric layer 211 includes an oxidation process.

[0089] Please refer to Figure 9 , Figure 9 The view direction is the same Figure 5 A portion of the initial word line gate layer is etched from the first surface 200a to the second surface 200b, and a plurality of third trenches (not shown in the figure) parallel to the second direction Y are formed in the substrate 200. The third trenches penetrate the initial word line gate layer from the first surface 200a to the second surface 200b to form the word line gate layer; the first isolation structure 216 is formed in the third trenches.

[0090] The word line grid structure includes a word line grid layer.

[0091] In this embodiment, the word line gate layer includes a work function layer 215 and a gate 214 located on the work function layer 215. Specifically, the work function layer 215 is formed with the initial work function layer 212; and the gate 214 is formed with the initial gate 213.

[0092] The gate 214 is made of metal or silicon. In this embodiment, the gate 214 is made of tungsten.

[0093] The word line grid structure also includes a grid dielectric layer 211 located between the sidewall of the first trench 207 and the word line grid layer.

[0094] In this embodiment, the word line grid structure is located on the first insulating layer 210.

[0095] The material of the first isolation structure 216 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0096] The method of forming the first isolation structure 216 includes: forming a second dielectric material layer in the third trench and on the first surface 200a; planarizing the second dielectric material layer until the surface of the first surface 200a is exposed.

[0097] In this embodiment, the top surface of the word line gate structure is lower than the surface of the first surface 200a, and the top of the word line gate structure has a second insulating layer. For the method of forming the word line gate structure and the second insulating layer, please refer to [reference needed]. Figure 10 .

[0098] Please refer to Figure 10 , Figure 10 The view direction is the same Figure 5 The word line gate structure and the first isolation structure 216 are etched back.

[0099] In this embodiment, the top surface of the word line grid structure is lower than the surface of the first surface 200a. In other embodiments, the top surface of the word line grid structure is flush with the surface of the first surface 200a.

[0100] In this embodiment, the work function layer 215 and the gate dielectric layer 211 are also etched back. In other embodiments, the word line gate structure, the first isolation structure 216, and the work function layer 215 may also be etched back, but the gate dielectric layer 211 is not etched back.

[0101] Please continue to refer to this. Figure 10 After the first isolation structure 216 is formed, and before the second isolation structure is formed, a second insulating layer 217 is formed on the word grid structure within the plurality of first trenches 207.

[0102] Specifically, after the word line grid structure and the first isolation structure 216 are etched back, and before the second isolation structure is formed, the second insulating layer 217 is also formed on the word line grid structure and the first isolation structure 216 within the plurality of first trenches 207.

[0103] The material of the second insulating layer 217 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0104] The method of forming the second insulating layer 217 includes: forming a third dielectric material layer on the word line grid structure, the first isolation structure 216 and the first surface 200a; planarizing the second dielectric material layer until the surface of the first surface 200a is exposed.

[0105] Please refer to Figure 11 , Figure 11 The view direction is the same Figure 5 After the word line grid structure is formed, and before the second isolation structure is formed, the protective layer 209 in the plurality of second trenches 208 is removed, so that the plurality of second trenches 208 are exposed.

[0106] The process for removing the protective layer 209 within the second trench 208 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the protective layer 209 within the second trench 208 is a dry etching process.

[0107] Please continue to refer to this. Figure 11 A second isolation structure 218 is formed within the second trench 208.

[0108] In this embodiment, the second isolation structure 218 has a closed gap. This gap can improve the insulation capability of the second isolation structure 218 and increase the isolation effect. In other embodiments, the second isolation structure may not have the gap.

[0109] The material of the second isolation structure 218 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0110] The method of forming the second isolation structure 218 includes: forming a fourth dielectric material layer in the second trench 208 and on the first surface 200a; planarizing the fourth dielectric material layer until the first surface 200a is exposed.

[0111] In this embodiment, the formation process of the second isolation structure 218 includes plasma-enhanced chemical vapor deposition (PECVD). The PECVD process facilitates the early closure of the top opening of the second trench 208, and facilitates the formation of voids within the second isolation structure 218.

[0112] Please refer to Figure 12 , Figure 12 The view direction is the same Figure 5 After forming the word line gate structure, the first isolation structure 216 and the second isolation structure 218, a first source / drain doped region 219 is formed in the first surface 200a of each active region; after forming the first source / drain doped region 219, a plurality of capacitor structures 220 are formed on the first surface 100a, and each capacitor structure 220 is electrically connected to one of the first source / drain doped regions 219.

[0113] The method for forming the first source / drain doped region 219 includes: implanting a first dopant ion into the active region from the first surface 200a, wherein the first dopant ion includes an N-type ion or a P-type ion. In this embodiment, the first dopant ion is an N-type ion.

[0114] The method for forming the capacitor structure 220 includes: forming a first dielectric layer (not shown in the figure) on the first surface 200a; forming a plurality of first grooves (not shown in the figure) in the first dielectric layer, wherein the first grooves expose the surfaces of a plurality of first source / drain doped regions 219; and forming the capacitor structure 220 in the first grooves.

[0115] The capacitor structure 220 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0116] The dielectric layer can be planar or U-shaped.

[0117] When the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0118] When the dielectric layer is U-shaped, the surface of the first electrode layer is uneven, and the surface of the second electrode layer is uneven; or, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0119] The material of the first electrode layer includes: a metal or a metal nitride; the material of the second electrode layer includes: a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0120] In this embodiment, a capacitor plug 221 is also provided between the capacitor structure 220 and the first source / drain doped region 219. In other embodiments, the capacitor structure 220 is directly connected to the first source / drain doped region 219, without the need for a capacitor plug.

[0121] In this embodiment, the method for forming the capacitor plug 221 includes: the first groove further having a first contact hole (not shown in the figure), the first contact hole exposing the surface of the first source / drain doped region 219; and forming the capacitor plug 221 in the first contact hole.

[0122] Please refer to Figure 13 , Figure 13 The view direction is the same Figure 5 After forming the word line gate structure, the first isolation structure 216 and the second isolation structure 218, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the second trench 208 is exposed.

[0123] Specifically, after forming the plurality of capacitor structures 220, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the second trench 208 is exposed.

[0124] The thinning process includes: thinning the substrate 200 from the second surface 200b toward the first surface 200a until the surface of the first insulating layer 210 or the surface of the second isolation structure 218 is exposed.

[0125] The thinning process includes a mechanical-chemical grinding process.

[0126] In this embodiment, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the surface of the first insulating layer 210 is exposed.

[0127] Please refer to Figure 14 , Figure 14 The view direction is the same Figure 5 After the thinning process, a second source / drain doped region 222 is formed in the second surface 200b of each active region; a plurality of bit lines 224 parallel to the first direction X are formed on the second surface 200b, and each bit line 224 is electrically connected to a plurality of second source / drain doped regions 222 in an active region.

[0128] The method for forming the second source / drain doped region 222 includes: implanting a second dopant ion into the active region from the second surface 200b, wherein the second dopant ion includes an N-type ion or a P-type ion. In this embodiment, the second dopant ion is an N-type ion.

[0129] The method for forming the plurality of bit lines 224 includes: forming a second dielectric layer (not shown in the figure) on the surface of the second surface 200b; forming a plurality of second grooves (not shown in the figure) in the second dielectric layer, wherein the second grooves extend along the X direction and one of the second grooves exposes a portion of the surface of the plurality of active regions; and forming the bit lines 224 in the second grooves.

[0130] In this embodiment, a bit line plug 223 is also provided between the bit line 224 and the second source / drain doped region 222. In other embodiments, the bit line 224 is directly connected to the second source / drain doped region 222, without the need for a bit line plug.

[0131] In this embodiment, the bit line plug formation method includes: the second groove also has a second contact hole (not shown in the figure), the second contact hole exposes the surface of the second source / drain doped region 222; and the bit line plug 223 is formed in the second contact hole.

[0132] Figures 15 to 27 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory according to another embodiment of the present invention.

[0133] In this embodiment, please Figures 3 to 5 Continue to refer to Figure 15 For the method of forming the plurality of first trenches and the plurality of second trenches, please refer to Figures 15 to 17 .

[0134] Please refer to Figure 15 , Figure 15 The view direction is the same Figure 5A first mask layer 304 is formed on the first surface 200a. The first mask layer 304 has a first opening 305 and a second opening 306. The first opening 305 exposes a portion of the surface of the word line region 201, and the second opening 306 exposes a portion of the surface of the channel region 202. The first opening 305 and the second opening 306 have the same size. The active region is etched using the first mask layer 304 as a mask to form a plurality of initial first trenches 307 and a plurality of second trenches 308.

[0135] The formation process of the initial first trench 307 and the second trench 308 includes a self-aligned dual imaging process.

[0136] After forming the initial first trench 307 and the second trench 308, the first mask layer 304 is also removed.

[0137] Subsequently, the plurality of initial first trenches 307 are etched to form the plurality of first trenches. In this embodiment, after the initial first trenches and the second trenches are formed, and before the plurality of initial first trenches 307 are etched, please refer to... Figure 16 .

[0138] Please refer to Figure 16 , Figure 16 The view direction is the same Figure 5 After the plurality of initial first trenches 307 and the plurality of second trenches 308 are formed, and before etching the plurality of initial first trenches 307, a protective layer 309 is formed in the plurality of second trenches 308.

[0139] The protective layer 309 serves to protect the second trench 308 during subsequent etching of the plurality of initial first trenches 307.

[0140] The method for forming the protective layer 309 includes: forming an initial protective layer (not shown in the figure) within the plurality of initial first trenches 307 and the plurality of second trenches 308; forming a second mask layer (not shown in the figure) on the first surface 200a, the second mask layer exposing the surface of the initial protective layer within the plurality of initial first trenches 307; using the second mask layer as a mask, etching the initial protective layer within the plurality of initial first trenches 307 to expose the surface of the plurality of initial first trenches 307, thereby forming the protective layer 309 with the initial protective layer within the plurality of second trenches 308.

[0141] The protective layer 309 is made of organic materials. The organic materials are easy to fill in the initial first trench 307 and the second trench 308 by spin coating or spraying, and are also easy to remove completely in subsequent removal.

[0142] In this embodiment, the organic material includes organic carbon.

[0143] In this embodiment, the formation process of the protective layer 309 includes a spin coating process.

[0144] Please refer to Figure 17 , Figure 17 The view direction is the same Figure 5 After the protective layer 309 is formed, the plurality of initial first trenches 307 are etched to form the plurality of first trenches 303.

[0145] The first trench 303 and the second trench 308 are formed by a single photolithography process, which eliminates the need to consider the alignment deviation problem of two photolithography processes, thus facilitating the formation of uniform device channels and improving the stability of device performance.

[0146] In this embodiment, the first trench 303 is formed by etching the initial first trench 307. This method is more conducive to forming the first trench and the second trench by the load effect, and it is also beneficial to control the size and depth of the first trench formed.

[0147] The method of etching the plurality of initial first trenches 307 further includes: forming a third mask layer (not shown in the figure) on the first surface 200a and the protective layer 309; using the third mask layer as a mask, etching the plurality of initial first trenches 307 to form the plurality of first trenches 303.

[0148] The etching process for the plurality of initial first trenches 307 includes one or a combination of dry etching and wet etching. In this embodiment, the etching process for the plurality of initial first trenches 307 is a dry etching process, which is beneficial for forming trenches with better morphology.

[0149] In this embodiment, the first trench 303 is formed by etching the initial first trench 307, which can reduce the instability of the load effect caused by the uneven size of the first opening 305 and the second opening 306, and facilitate the control of the size and depth of the formed first trench 303.

[0150] Subsequently, a word line grid structure and a first isolation structure are formed on the sidewall of the first trench 303, and the two word line grid structures in each of the first trenches 303 are isolated from each other by the first isolation structure; a second isolation structure is formed in the second trench 308. In this embodiment, before forming the word line grid structure, a first insulating layer is formed at the bottom of the first trench. The method for forming the first insulating layer is described in [reference needed]. Figure 18 .

[0151] Please refer to Figure 18 An insulating material layer (not shown in the figure) is formed in the first trench 303 and on the first surface 200a; the insulating material layer is planarized until the surface of the first surface 200a is exposed; after the planarization process, the insulating material layer is etched back to form the first insulating layer 310.

[0152] The material of the first insulating layer 310 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0153] The top surface of the first insulating layer 310 is higher than or flush with the bottom surface of the second trench 308. In this embodiment, the top surface of the first insulating layer 310 is flush with the bottom surface of the second trench 308.

[0154] In this embodiment, the word line grid structure and the first isolation structure are located on the first insulating layer 310.

[0155] The word line grid structure includes a word line grid layer. For the method of forming the word line grid structure and the first isolation structure in this embodiment, please refer to [reference needed]. Figures 19 to 22 .

[0156] Please refer to Figure 19 An initial word line grid layer is formed on the sidewall and bottom of the first trench 303 and on the first surface 200a. The initial word line grid layer in the first trench 303 has an initial third trench 314.

[0157] In this embodiment, the initial word line gate layer includes a work function material layer 312 and a gate material layer 313 located on the work function material layer 312.

[0158] In this embodiment, the initial word line gate layer is also located on the surface of the first insulating layer 310.

[0159] In this embodiment, before forming the initial word line gate layer, a gate dielectric layer 311 is formed on the sidewall of the first trench 303.

[0160] The formation process of the gate dielectric layer 311 includes an oxidation process.

[0161] Specifically, after the first insulating layer 310 is formed, the sidewalls of the first trench 303 exposed by the first insulating layer 310 are surface-oxidized using an oxidation process to form the gate dielectric layer 311.

[0162] In other embodiments, before forming the gate dielectric layer 311, the method further includes: oxidizing the sidewalls of the first trench to form an oxide layer on the sidewalls of the first trench; and removing the oxide layer. This method not only improves the quality of the formed gate dielectric layer and enhances the gate control capability of the gate oxide, but also increases the width of the first trench.

[0163] Please refer to Figure 20 Remove the initial word line grid layer at the bottom of the first trench 303 to form the third trench 315 with the initial third trench 314.

[0164] The process of removing the initial word line gate layer at the bottom of the first trench 303 includes one or a combination of dry etching and wet etching.

[0165] In this embodiment, the process for removing the initial word line gate layer at the bottom of the first trench 303 is a dry etching process.

[0166] In this embodiment, the initial word line gate layer on the surface of the substrate 200 is retained, which can protect the surface of the substrate 200 during subsequent etching processes. In other embodiments, the initial word line gate layer on the surface of the substrate 200 is also etched away while the initial word line gate layer at the bottom of the first trench 303 is removed.

[0167] Please refer to Figure 21 The first isolation structure 316 is formed within the third trench 315.

[0168] In this embodiment, the top surface of the first isolation structure 316 is lower than the first surface 200a. In other embodiments, the top surface of the first isolation structure 316 may be flush with the first surface 200a.

[0169] The material of the first isolation structure 316 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0170] The method for forming the first isolation structure 316 includes: forming a dielectric material layer in the third trench 315 and on the first surface 200a; planarizing the dielectric material layer until the surface of the first surface 200a is exposed; and after the planarization process, etching back the dielectric material layer to form the first isolation structure 316.

[0171] In this embodiment, the gate dielectric layer 311 is etched back at the same time as the dielectric material layer. In other embodiments, the gate dielectric layer may not be etched back.

[0172] Please refer to Figure 22After forming the first isolation structure 316, the initial word line gate layer exposed by the first isolation structure 316 is removed, and the word line gate layer is formed from the initial word line gate layer.

[0173] The word line grid structure includes the word line grid layer.

[0174] In this embodiment, the word line gate layer includes a work function layer 318 and a gate 317 located on the work function layer 318. Specifically, the work function layer 318 is formed with the initial work function layer 312; and the gate 317 is formed with the gate material layer 313.

[0175] The gate 317 is made of metal or silicon. In this embodiment, the gate is made of tungsten.

[0176] In this embodiment, the word line grid structure further includes a gate dielectric layer 311 located between the sidewall of the first trench 303 and the word line grid layer.

[0177] In this embodiment, the word line grid structure is located on the first insulating layer 310.

[0178] In this embodiment, the word line grid structure is formed first, followed by the second isolation structure. In another embodiment, the second isolation structure may be formed first, followed by the word line grid structure.

[0179] Please refer to Figure 23 After the first isolation structure 316 is formed, and before the second isolation structure is formed, a second insulating layer 320 is formed on the word grid structure within the plurality of first trenches 303.

[0180] The material of the second insulating layer 320 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0181] The method of forming the second insulating layer 320 includes: forming an insulating material layer (not shown in the figure) in the first surface 200a and the plurality of first trenches 303; planarizing the insulating material layer until the first surface 200a is exposed.

[0182] Please refer to Figure 24 After the word line grid structure is formed, and before the second isolation structure is formed, the protective layer 309 in the second trench 308 is removed, so that the second trench 308 is exposed.

[0183] Specifically, after the second insulating layer 320 is formed and before the second isolation structure is formed, the protective layer 309 in the second trench 308 is removed, exposing the second trench 308.

[0184] The process for removing the protective layer 309 within the second trench 308 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the protective layer 309 within the second trench 308 is a dry etching process.

[0185] Please continue to refer to this. Figure 24 A second isolation structure 321 is formed within the second trench 308.

[0186] In this embodiment, the second isolation structure 321 has a closed gap. This gap can improve the insulation capability of the second isolation structure 321 and increase the isolation effect. In other embodiments, the second isolation structure may not have the gap.

[0187] The material of the second isolation structure 321 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0188] In this embodiment, the formation process of the second isolation structure 321 includes plasma-enhanced chemical vapor deposition (PECVD). PECVD facilitates the early closure of the top opening of the second trench 308, thereby creating voids within the second isolation structure 321.

[0189] Please refer to Figure 25 , Figure 25 The view direction is the same Figure 5 After forming the word line gate structure, the first isolation structure 316 and the second isolation structure 321, a first source / drain doped region 322 is formed in the first surface 200a of each active region; after forming the first source / drain doped region 322, a plurality of capacitor structures 323 are formed on the first surface 200a, and each capacitor structure 323 is electrically connected to one of the first source / drain doped regions 322.

[0190] The method for forming the first source / drain doped region 322 includes: implanting a first dopant ion into the active region from the first surface 200a, wherein the first dopant ion includes an N-type ion or a P-type ion. In this embodiment, the first dopant ion is an N-type ion.

[0191] The method for forming the capacitor structure 323 includes: forming a first dielectric layer (not shown in the figure) on the first surface 200a; forming a plurality of first grooves (not shown in the figure) in the first dielectric layer, wherein the first grooves expose the surfaces of a plurality of first source / drain doped regions 322; and forming the capacitor structure 323 in the first grooves.

[0192] The capacitor structure 323 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0193] The dielectric layer can be planar or U-shaped.

[0194] When the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0195] When the dielectric layer is U-shaped, the surface of the first electrode layer is uneven, and the surface of the second electrode layer is uneven; or, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0196] The material of the first electrode layer includes: a metal or a metal nitride; the material of the second electrode layer includes: a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0197] In this embodiment, a capacitor plug 324 is further provided between the capacitor structure 323 and the first source / drain doped region 322. In other embodiments, the capacitor structure 323 is directly connected to the first source / drain doped region 322, without the need for a capacitor plug.

[0198] In this embodiment, the method for forming the capacitor plug 324 includes: the first groove further having a first contact hole (not shown in the figure), the first contact hole exposing the surface of the first source / drain doped region 322; and forming the capacitor plug 324 in the first contact hole.

[0199] Please refer to Figure 26 , Figure 26 The view direction is the same Figure 5 After forming the word line gate structure, the first isolation structure 316 and the second isolation structure 321, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the second trench 308 is exposed.

[0200] Specifically, after forming the plurality of capacitor structures 323, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the second trench 308 is exposed.

[0201] The thinning process includes: thinning the substrate 200 from the second surface 200b toward the first surface 200a until the surface of the first insulating layer 310 or the surface of the second isolation structure 321 is exposed.

[0202] The thinning process includes a mechanical-chemical grinding process.

[0203] In this embodiment, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the surface of the first insulating layer 310 is exposed.

[0204] Please refer to Figure 27 , Figure 27 The view direction is the same Figure 5 After the thinning process, a second source / drain doped region 325 is formed in the second surface 200b of each active region; a plurality of bit lines 326 parallel to the first direction X are formed on the second surface 200b, and each bit line 326 is electrically connected to a plurality of second source / drain doped regions 325 in an active region.

[0205] The method for forming the second source / drain doped region 325 includes: implanting a second dopant ion into the active region from the second surface 200b, wherein the second dopant ion includes an N-type ion or a P-type ion. In this embodiment, the second dopant ion is an N-type ion.

[0206] The method for forming the plurality of bit lines 326 includes: forming a second dielectric layer (not shown in the figure) on the surface of the second surface 200b; forming a plurality of second grooves (not shown in the figure) in the second dielectric layer, wherein the second grooves extend along the X direction and one of the second grooves exposes a portion of the surface of the plurality of active regions; and forming the plurality of bit lines 326 in the second grooves.

[0207] In this embodiment, bit line plugs 327 are also provided between the plurality of bit lines 326 and the second source / drain doped region 325. In other embodiments, the plurality of bit lines 326 are directly connected to the second source / drain doped region 325 without the need for bit line plugs.

[0208] In this embodiment, the bit line plug formation method includes: the second groove further having a second contact hole (not shown in the figure), the second contact hole exposing the surface of the second source / drain doped region 325; and forming the bit line plug 327 in the second contact hole.

[0209] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a dynamic random access memory, characterized in that, include: A substrate is provided having a first surface and a second surface opposite to each other. The substrate includes a plurality of mutually discrete active regions parallel to a first direction, and the plurality of active regions are arranged along a second direction, the first direction being perpendicular to the second direction. Each active region includes a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each active region are arranged at intervals along the first direction. A first trench and a second trench are formed that penetrate the active region along the second direction, and the formation process of the first trench and the second trench includes the same photolithography process. The first trench and the second trench both extend from the first surface to the second surface, and the first trench is located in the word line area and the second trench is located in the channel area. A word line grid structure and a first isolation structure are formed on the sidewall of the first trench, and the two word line grid structures in each of the first trenches are isolated from each other by the first isolation structure. A second isolation structure is formed within the second trench; After forming the word line gate structure, the first isolation structure and the second isolation structure, the substrate is thinned from the second surface to the first surface until the second trench is exposed.

2. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The width of the first groove is greater than the width of the second groove.

3. The method for forming a dynamic random access memory as described in claim 2, characterized in that, The method for forming the plurality of first trenches and the plurality of second trenches includes: forming a first mask layer on the first surface, the first mask layer having a first opening and a second opening, the first opening exposing the surface of the word line region, the second opening exposing a portion of the surface of the channel region, the size of the first opening along the first direction being larger than the size of the second opening along the first direction; etching the active region using the first mask layer as a mask to form the plurality of first trenches and the plurality of second trenches.

4. The method for forming a dynamic random access memory as described in claim 3, characterized in that, The first mask layer includes a plurality of mutually independent sidewalls, each of which has the same dimension along the first direction.

5. The method for forming a dynamic random access memory as described in claim 3, characterized in that, The method further includes: first forming the word line grid structure, and then forming the second isolation structure; the method also includes: after forming the plurality of first trenches and the plurality of second trenches, forming a protective layer in the plurality of second trenches; after forming the word line grid structure, and before forming the second isolation structure, removing the protective layer in the plurality of second trenches to expose the plurality of second trenches.

6. The method for forming a dynamic random access memory as described in claim 5, characterized in that, The method for forming the protective layer includes: forming an initial protective layer in the plurality of first trenches and the plurality of second trenches; forming a second mask layer on the first surface, the second mask layer exposing the surface of the initial protective layer in the plurality of first trenches; using the second mask layer as a mask, etching the initial protective layer in the plurality of first trenches to expose the surface of the plurality of first trenches, and forming the protective layer with the initial protective layer in the plurality of second trenches.

7. The method for forming a dynamic random access memory as described in claim 2, characterized in that, The method for forming the plurality of first trenches and the plurality of second trenches includes: forming a first mask layer on the first surface, the first mask layer having a first opening and a second opening, the first opening exposing a portion of the surface of the word line region, the second opening exposing a portion of the surface of the channel region, the first opening and the second opening having the same size; etching the active region using the first mask layer as a mask to form a plurality of initial first trenches and the plurality of second trenches; etching the plurality of initial first trenches to form the plurality of first trenches.

8. The method for forming a dynamic random access memory as described in claim 7, characterized in that, The method further includes: first forming the word line grid structure, and then forming the second isolation structure; the method further includes: after forming the plurality of initial first trenches and the plurality of second trenches, and before etching the plurality of initial first trenches, forming a protective layer in the plurality of second trenches; after forming the protective layer, etching the plurality of initial first trenches to form the plurality of first trenches; after forming the word line grid structure, and before forming the second isolation structure, removing the protective layer in the plurality of second trenches to expose the plurality of second trenches.

9. The method for forming a dynamic random access memory as described in claim 8, characterized in that, The method for forming the protective layer includes: forming an initial protective layer in the plurality of initial first trenches and the plurality of second trenches; forming a second mask layer on the first surface, the second mask layer exposing the surface of the initial protective layer in the plurality of initial first trenches; using the second mask layer as a mask, etching the initial protective layer in the plurality of initial first trenches to expose the surface of the plurality of initial first trenches, thereby forming the protective layer with the initial protective layer in the plurality of second trenches.

10. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The word line grid structure includes a word line grid layer.

11. The method for forming a dynamic random access memory as described in claim 10, characterized in that, The method for forming the word line gate structure and the first isolation structure includes: forming an initial word line gate layer in each of the first trenches; etching a portion of the initial word line gate layer from the first surface to the second surface; forming a plurality of third trenches parallel to the second direction in the substrate; the third trenches penetrating the initial word line gate layer from the first surface to the second surface to form the word line gate layer; and forming the first isolation structure in the third trenches.

12. The method for forming a dynamic random access memory as described in claim 10, characterized in that, The method for forming the word line grid structure and the first isolation structure includes: forming an initial word line grid layer on the sidewall and bottom of the first trench and on the first surface, wherein the initial word line grid layer in the first trench has an initial third trench; removing the initial word line grid layer at the bottom of the first trench to form a third trench with the initial third trench; forming the first isolation structure in the third trench; and after forming the first isolation structure, removing the initial word line grid layer exposed by the first isolation structure to form the word line grid layer with the initial word line grid layer.

13. The method for forming a dynamic random access memory as described in claim 10, characterized in that, The word line grid structure further includes a grid dielectric layer located between the first trench sidewall and the word line grid layer.

14. The method for forming a dynamic random access memory as described in claim 13, characterized in that, The formation process of the gate dielectric layer includes an oxidation process; the method of forming the gate dielectric layer includes: forming the gate dielectric layer on the sidewall of the first trench before forming the word line gate layer.

15. The method for forming a dynamic random access memory as described in claim 14, characterized in that, Before forming the gate dielectric layer, the method further includes: oxidizing the sidewall of the first trench to form an oxide layer on the sidewall of the first trench; and removing the oxide layer.

16. The method for forming a dynamic random access memory as described in claim 1, characterized in that, Before forming the word line grid structure, a first insulating layer is formed at the bottom of the first trench; the word line grid structure is located on the first insulating layer.

17. The method for forming a dynamic random access memory as described in claim 16, characterized in that, The thinning process includes: thinning the substrate from the second surface toward the first surface until the surface of the first insulating layer or the surface of the second isolation structure is exposed.

18. The method for forming a dynamic random access memory as described in claim 16, characterized in that, The top surface of the first insulating layer is higher than or flush with the bottom surface of the second trench.

19. The method for forming a dynamic random access memory as described in claim 16, characterized in that, The method for forming the first insulating layer includes: forming an initial first insulating layer in the first trench; and etching back the initial first insulating layer to form the first insulating layer.

20. The method for forming a dynamic random access memory as described in claim 1, characterized in that, Also includes: After forming the word line gate structure, the first isolation structure and the second isolation structure, a first source / drain doped region is formed in the first surface of each of the active regions; After the first source / drain doped region is formed, a plurality of capacitor structures are formed on the first surface, and each capacitor structure is electrically connected to one of the first source / drain doped regions; after the thinning process, a second source / drain doped region is formed in the second surface of each of the active regions; A plurality of bit lines parallel to the first direction are formed on the second surface, and each bit line is electrically connected to a plurality of second source / drain doped regions in an active region.

21. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The top surface of the word line grid structure is lower than the first surface, and the top of the word line grid structure has a second insulating layer.

22. The method for forming a dynamic random access memory as described in claim 21, characterized in that, The method for forming the word line grid structure and the second insulating layer further includes: after forming the first isolation structure and before forming the second isolation structure, forming the second insulating layer in the first trench and on the word line grid structure.

23. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The second isolation structure has a closed gap.

24. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The thinning process includes a mechanical-chemical grinding process.

25. The method for forming a dynamic random access memory as described in claim 1, characterized in that, A third isolation layer is also provided between adjacent active regions.

26. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The first trench has a first width value, the second trench has a second width value, and the difference between the first width value and the second width value ranges from 5 nanometers to 50 nanometers; the first trench has a first depth value, the second trench has a second depth value, and the difference between the first depth value and the second depth value ranges from 50 nanometers to 100 nanometers.

27. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The formation process of the first trench and the second trench includes a self-aligned dual imaging process.

Images