semiconductor memory devices

Abstract

A semiconductor memory device includes a substrate, a plurality of bonding pads, a first conductive layer, a plurality of first capacitors, a plurality of second capacitors, a second conductive layer, and a plurality of third capacitors. The substrate has an active region. The active region includes a first region, a second region, and a third region. The third region surrounds the first region. The second region surrounds the first and third regions. The bonding pads are disposed on the first region. The first conductive layer is disposed on the second region. The first capacitors are respectively disposed on the bonding pads. The second capacitors are disposed on the first conductive layer. The second conductive layer is disposed on the second capacitors. The third capacitors are disposed in the third region. The second conductive layer is not electrically connected to the third capacitors. This reduces signal noise.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device. Background Art

[0002] As the integration density of semiconductor memory devices such as dynamic random access memory (DRAM) increases, the demand for higher storage capacity and higher operating speed of semiconductor memory devices also increases. In addition, semiconductor memory devices may include capacitors that provide various functions.

[0003] As the integration density of semiconductor memory devices increases, the number of operating circuits increases proportionally, so that noise may be generated in the external power supply voltage VDD and the ground voltage VSS during read and write operations. Summary of the Invention

[0004] Therefore, the present invention provides a semiconductor memory device having a plurality of capacitors that can be electrically decoupled from each other.

[0005] According to one embodiment of the present invention, a semiconductor memory device includes a substrate, a plurality of bonding pads, a first conductive layer, a plurality of first capacitors, a plurality of second capacitors, a second conductive layer, and a plurality of third capacitors. The substrate has an active region. The active region includes a first region, a second region, and a third region. The third region surrounds the first region. The second region surrounds the first and third regions. The bonding pads are disposed on the first region. The first conductive layer is disposed on the second region. The first capacitors are respectively disposed on the bonding pads. The second capacitors are disposed on the first conductive layer. The second conductive layer is disposed on the second capacitors. The third capacitors are disposed in the third region. The second conductive layer is not electrically connected to the third capacitors.

[0006] In one embodiment of the present invention, the second conductive layer includes a first connection region. The first connection region is located above the second capacitor. The power supply is connected to the first conductive layer or the second conductive layer.

[0007] In one embodiment of the present invention, the second conductive layer includes a second connection region connected to the first connection region, and the second conductive layer in the second connection region extends in a direction perpendicular to the connection surface of the active region.

[0008] In one embodiment of the present invention, the first conductive layer and the bonding pads in the first region are formed on the same horizontal plane.

[0009] In one embodiment of the present invention, the second capacitors are connected in parallel.

[0010] In one embodiment of the present invention, the substrate includes a first insulating layer and bit lines. The bit lines are located below the first insulating layer in a first region.

[0011] In one embodiment of the present invention, the substrate includes a plurality of contact structures, the bonding pads are respectively disposed on the contact structures, and the top surfaces of the contact structures and the top surface of the first insulating layer are on the same level.

[0012] In one embodiment of the present invention, the bottom of the contact structure and the bottom of the bit line are on the same horizontal plane.

[0013] In one embodiment of the present invention, the second insulating layer is disposed on the second region, the second capacitor is disposed in the second insulating layer, and the second conductive layer covers the second insulating layer in the second region.

[0014] In one embodiment of the present invention, the second region includes a plurality of sub-regions, a plurality of gaps are provided between the sub-regions, and each sub-region accommodates some of the second capacitors.

[0015] By configuring the second capacitor as described above, the noise from the power supply can be reduced, so that the second capacitor can be used as a low-pass filter to remove signal noise. The second capacitor can also be used as a reference capacitor or decoupling capacitor required by peripheral circuits.

[0016] The foregoing has generally outlined the features and technical advantages of the present invention so that the detailed description disclosed below may be better understood. Additional features and technical advantages of the present invention are described below and form the subject matter of the present invention. Those skilled in the art will appreciate that the disclosed concepts and specific embodiments may serve as a basis for modifying or designing other structures or processes to achieve the objectives of the present invention. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit or scope of the present invention.

[0017] It is to be understood that both the foregoing general description and the following detailed description are intended to provide further explanation of the present invention by way of illustration. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention may be more fully understood by reading the following detailed description of the embodiments in conjunction with the accompanying drawings:

[0019] Figure 1A A schematic top view of a semiconductor memory device is shown according to one embodiment of the present invention;

[0020] Figure 1B yes Figure 1A a simplified top view of a semiconductor memory device;

[0021] Figure 2 yes Figure 1A a cross-sectional view of the semiconductor memory device along line segment LL';

[0022] Figure 3A is a schematic cross-sectional view of a capacitor according to one embodiment of the present invention;

[0023] Figure 3B is a schematic cross-sectional view of a capacitor according to one embodiment of the present invention;

[0024] Figure 4 is a top view schematically illustrating a semiconductor memory device according to another embodiment of the present invention;

[0025] Figure 5 is a semiconductor structure according to an embodiment of the present invention; and

[0026] Figure 6A and Figure 6B Schematically drawn Figure 5 Partial equivalent circuit. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numerals are used in the accompanying drawings and the description to refer to the same or like parts.

[0028] With reference to the accompanying drawings, the illustrated thicknesses of layers and regions may be schematically increased to facilitate explanation. When a first layer is referred to as being "on a second layer" or "on a substrate," this may mean that the first layer is formed directly on the second layer or on the substrate, or it may also mean that a third layer may be present between the first layer and the second layer or substrate.

[0029] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the "first element," "component," "region," "layer," or "portion" discussed below may also be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0030] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the concepts disclosed herein. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It should be further understood that the terms "comprise" and "include," when used in the present invention, indicate the presence of the recited features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0031] As used herein, the terms "patterning" and "patterned" are used in the present invention to describe the operation of forming a predetermined pattern on a surface. The patterning operation includes various steps and processes, and varies according to different embodiments. In some embodiments, a patterning process is used to pattern an existing film or layer. The patterning process includes forming a mask on the existing film or layer and using etching or other removal processes to remove the unmasked film or layer. The mask can be a photoresist or a hard mask. In some embodiments, a patterning process is used to directly form a patterned layer on the surface. The patterning process includes forming a photosensitive film on the surface, performing a photolithography process and a development process. The remaining photosensitive film is retained and integrated into the semiconductor device.

[0032] Please refer to Figure 1A and Figure 1B . Figure 1A A schematic top view of a semiconductor memory device 100 is shown according to one embodiment of the present invention. Figure 1B yes Figure 1A A simplified top view of a semiconductor memory device 100. For illustrative purposes, Figure 1B , the central conductive layer 136 located in the first region 111 , the second conductive layer 130 , and the first conductive layer 125 having the contact 126 located in the second region 112 are not shown.

[0033] like Figure 1A and Figure 1B As shown in FIG. 1 , in this embodiment, the semiconductor memory device 100 includes a substrate 110. Figure 1B As shown, substrate 110 includes an active region, wherein the active region includes a first region 111, a second region 112, and a third region 113. In some embodiments, substrate 110 may include a plurality of transistors located within the active region. Second region 112 surrounds first region 111. Third region 113 is located between first region 111 and second region 112.

[0034] Specifically, in this embodiment, the first region 111 is in the shape of a square, and the outline of the second region 112 is in the shape of a square ring.

[0035] like Figure 1BAs shown, the semiconductor memory device 100 further includes a plurality of first capacitors 135, a plurality of second capacitors 140, and a plurality of third capacitors 145. The first capacitors 135, the second capacitors 140, and the third capacitors 145 are respectively located in the first region 111, the second region 112, and the third region 113. In other words, the first capacitors 135 are surrounded by the second capacitors 140.

[0036] In this embodiment, the first capacitor 135 and the second capacitor 140 are decoupled from each other. Specifically, in this embodiment, a plurality of transistors formed in the first region 111 of the active region are formed in the first region 111 of the active region of the substrate 110 and are respectively connected to the first capacitor 135 to form a plurality of memory cells. The second capacitor 140 surrounding the first capacitor 135 is electrically decoupled from the first capacitor 135, or is electrically insulated from each other. The decoupled second capacitor 140 surrounds the first capacitor 135, thereby reducing the noise effect of the first capacitor 135 and improving the current base supply drop. In other words, this also reduces the noise effect of the memory cell formed on the substrate 110 and improves the current base supply drop. The second capacitor 140 electrically isolates the first capacitor 135 from other circuits outside the substrate 110. Please refer to the following discussion for details.

[0037] Back to Figure 1A In this embodiment, semiconductor memory device 100 further includes a second conductive layer 130 located in second region 112 and a central conductive layer 136 located in first region 111. Therefore, in this embodiment, second capacitor 140 is connected in parallel. Second conductive layer 130 is located on top of second capacitor 140 and is connected to second capacitor 140 to have the same voltage. Similarly, central conductive layer 136 is located on top of first capacitor 135 and is connected to first capacitor 135 to have the same voltage. This allows the electrical signal stored in the memory cell formed by first capacitor 135 to be more stable.

[0038] In this embodiment, no conductive layer is formed on the top surface of the third capacitor 145. The third capacitor 145 is located on the third region 113, which surrounds the first region 111. The third capacitors 145 are not connected to each other. The first capacitor 135, the second capacitor 140, and the third capacitor 145 can be formed in the same manufacturing process. When forming the first capacitor 135, the second capacitor 140, and the third capacitor 145, an etching process is performed to facilitate capacitor manufacturing.

[0039] like Figure 1A and Figure 1BAs shown, the first capacitor 135, the second capacitor 140 and the third capacitor 145 are arranged in different parallel rows. However, the arrangement of the first capacitor 135, the second capacitor 140 and the third capacitor 145 is not in the same manner. Figure 1A and Figure 1B In some embodiments, the first capacitor 135 , the second capacitor 140 , and the third capacitor 145 can be arranged in a hexagonal form.

[0040] In this embodiment, the first capacitor 135, the second capacitor 140, and the third capacitor 145 are not electrically connected to each other. In other words, the first capacitor 135, the second capacitor 140, and the third capacitor 145 are electrically insulated from each other, and the third capacitor 145 is used to ensure that the second capacitor 140 is not coupled to the first capacitor 135.

[0041] Please refer to Figure 2 . Figure 2 yes Figure 1A A cross-sectional view of the semiconductor memory device 100 along line LL′.

[0042] like Figure 2 As shown, semiconductor memory device 100 includes a substrate 110 having an active region including a first region 111, a second region 112, and a third region 113. First region 111 is surrounded by third region 113 and second region 112, in sequence. In other words, second region 112 can be considered a closed loop surrounding first region 111. First capacitor 135, second capacitor 140, and third capacitor 145 are located within first region 111, second region 112, and third region 113, respectively. In other words, first capacitor 135 is surrounded by third capacitor 145 and second capacitor 140. The top surface of third capacitor 145 is open.

[0043] The active region of substrate 110 includes a contact surface 110S. Semiconductor memory device 100 includes a plurality of bonding pads 120 and a first conductive layer 125 located on contact surface 110S. Bonding pads 120 are located in first region 111 and third region 113. First capacitors 135 are connected to bonding pads 120, respectively. First conductive layer 125 is located on second region 112. First conductive layer 125 extends along direction D1. Second capacitor 140 is connected to first conductive layer 125. In this embodiment, first conductive layer 125 can be formed on the same horizontal plane as bonding pads 120 on first region 111, and bonding pads 120 and first conductive layer 125 can be formed of the same material.

[0044] The semiconductor memory device 100 further includes a contact structure 115, a first insulating layer 150, a second insulating layer 155 and a bit line 160. Figure 2 In the embodiment, the second insulating layer 155 is below the contact surface 110S. The contact structure 115 , the first insulating layer 150 and the bit line 160 are located within the second insulating layer 155 .

[0045] The contact structure 115 is electrically isolated from the bit line 160. In some embodiments, an air isolation dielectric is disposed between the contact structure 115 and the bit line 160 to electrically isolate the contact structure 115 from the bit line 160.

[0046] In the first region 111, the contact structures 115 are connected to the bonding pads 120 on the contact surface 110S. The bonding pads 120 in the first region 111 are located between the first capacitor 135 and the contact structures 115. Specifically, the contact structures 115 are connected to the transistors below, and the first capacitors 135 are connected to the transistors through the bonding pads 120. The transistors are formed in the substrate 110 and below the contact structures 115. For the purpose of simplicity, Figure 2 Only one transistor T among the multiple transistors located below the contact structure 115 is schematically depicted in FIG. Figure 2 One transistor T is connected to one of the contact structures 115. Thus, the lower plurality of transistors T within the substrate 110 and the plurality of first capacitors 135 located on the contact surface 110S can form multiple memory cells. The central conductive layer 136 is located on top of the first capacitors 135 and connects the first capacitors 135 to the same voltage. This makes the electrical signal stored in the memory cell formed by the first capacitors 135 and the transistors thereunder more stable.

[0047] like Figure 2 As shown, in this embodiment, the top surfaces of the plurality of contact structures 115 are aligned with the top surfaces of the first insulating layer 150 and the second insulating layer 155. In this embodiment, the top surfaces of the plurality of contact structures 115, the top surfaces of the first insulating layer 150 and the second insulating layer 155, and the contact surface 110S of the substrate 110 are located at the same level. In addition, the bottom surfaces of the plurality of contact structures 115 and the bottom surfaces of the plurality of bit lines 160 are located at the same level.

[0048] Below the contact surface 110S and between the plurality of contact structures 115, the first insulating layer 150 and the bit lines 160 in the first region 111 are located within the second insulating layer 155. The bit lines 160 are located below the first insulating layer 150 in the first region 111. The first insulating layer 150 covers the bit lines 160.

[0049] exist Figure 2 In the embodiment, the contact surface 110S extends along a first direction D1, and the first capacitor 135 extends along another second direction D2. In the present embodiment, the first direction D2 is perpendicular to the second direction D2.

[0050] The contact 137 is located above the central conductive layer 136 , allowing a user to provide voltage through the contact 137 .

[0051] In this embodiment, no contact structure is provided below the contact surface 110S of the substrate 110 in the second region 112. Thus, the second capacitors 140 in the second region 112 are not coupled to the first capacitors 135. In this embodiment, the second capacitors 140 extend along the second direction D2 and are connected in parallel.

[0052] like Figure 2 As shown, the second conductive layer 130 includes a first connection region 131 and a second connection region 132. The first connection region 131 is located above the second capacitor 140. The second connection region 132 is connected to the upper portion of the second capacitor 140. The second conductive layer 130 in the first connection region 131 and the second connection region 132 extends in a second direction D2 perpendicular to the first direction D1 extending from the contact surface 110S. In this embodiment, the second connection region 132 of the second conductive layer 130 contacts one side of the second capacitor 140, such that the second connection region 132 is supported by the side of the second capacitor 140.

[0053] like Figure 2 As shown, in this embodiment, the contact 126 extending along the second direction D2 is formed on the first conductive layer 125 , and the power source can be connected to the first conductive layer 125 through the contact 126 .

[0054] The contact 134 is located on the second conductive layer 130, and the user can provide voltage through the contact 134. In some embodiments, the power source is electrically connected to the second conductive layer 130 through the contact 134. In some embodiments, the power source is electrically connected to the second connection area 132 of the second conductive layer 130.

[0055] The third region 113 surrounds the first region 111. The second region 112 surrounds the third region 113. A plurality of third capacitors 145 are located in the third region 113. Below the contact surface 110S of the substrate 110 are a contact structure 115, a first insulating layer 150, and a bit line 160. The contact structure 115 is connected to the third capacitors 145 via a bonding pad 120. However, no conductive layer is provided to connect the third capacitors 145 to the same voltage. Therefore, the third capacitors 145 can be considered dummy capacitors to further prevent electrical coupling between the first capacitor 135 and the second capacitor 140.

[0056] In some embodiments, the material of the first insulating layer 150 includes silicon nitride (SiN).

[0057] In some embodiments, the material of the bonding pad 120 and the first conductive layer 125 includes tungsten or titanium nitride (TiN).

[0058] In some embodiments, the materials of the first capacitor 135 , the second capacitor 140 , and the third capacitor 145 include high-k dielectric materials.

[0059] In this way, if Figure 2 As shown, the semiconductor memory device 100 includes a memory cell formed by a first capacitor 135 and a transistor T, and the memory cell is surrounded by a decoupled second capacitor 140. The first capacitor 135 and the second capacitor 140 are not electrically coupled to each other. In other words, the first capacitor 135 and the second capacitor 140 are electrically insulated from each other.

[0060] In some embodiments, the gaps between the first capacitor 135, the second capacitor 140, and the third capacitor 145 are filled with a filler material. For simplicity of illustration, the filler material is omitted in the drawings. In some embodiments, the filler material includes a dielectric material.

[0061] Please refer to Figure 3A and Figure 3B . Figure 3A FIG. 5 is a schematic cross-sectional view of a capacitor 600A according to one embodiment of the present invention. Figure 3B FIG2 is a schematic cross-sectional view of capacitor 600B according to one embodiment of the present invention. In some embodiments, first capacitor 135, second capacitor 140, and third capacitor 145 may be capacitor 600A or capacitor 600B, but this does not limit the type of capacitor used in the present invention. In some embodiments, capacitor 600A or capacitor 600B may be a capacitor unit structure of one of first capacitor 135, second capacitor 140, and third capacitor 145.

[0062] like Figure 3AAs shown, capacitor 600A includes a bottom electrode 610, a high-k dielectric 620, a top electrode 630, and a conductive material 640. The bottom electrode 610 of capacitor 600A is a U-shaped container. The M-shaped high-k dielectric 620 covers the bottom electrode 610. The M-shaped top electrode 630 further covers the high-k dielectric 620 and is located between the bottom electrode 610 and the top electrode 630. The M-shaped top electrode 630 forms a receiving space, and the conductive material 640 is formed in the receiving space formed by the top electrode 630.

[0063] When capacitor 600A is used as first capacitor 135, second capacitor 140, and third capacitor 145, the bottom electrode 610 of each capacitor 600A is electrically connected to a bonding pad 120 in the first region 111 or the first conductive layer 125 in the second region 112, and the top electrode 630 and conductive material 640 of each capacitor 600A are electrically connected to the central conductive layer 136 in the first region 111 or the first connection region 131 of the second conductive layer 130 in the second region 112. For example, when capacitor 600A is used as the first capacitor 135 in the first region 111, the bottom electrode 610 is connected to one of the corresponding bonding pads 120, while the top electrode 630 and conductive material 640 are connected to the central conductive layer 136. When capacitor 600A is used as the second capacitor 140 in the second region 112, the bottom electrode 610 is connected to the same first conductive layer 125, while the top electrode 630 and conductive material 640 are connected to the first connection region 131 of the second conductive layer 130.

[0064] As such, the capacitor 600A is able to store charge after a voltage difference is applied between the bottom electrode 610 and the top electrode 630 via the high-k dielectric 620 between the bottom electrode 610 and the top electrode 630 .

[0065] Figure 3B Another capacitor 600B is shown. Figure 3B As shown, capacitor 600B includes a pillar-shaped bottom electrode 610, a high-k dielectric 620, and a top electrode 630. The high-k dielectric 620 covers the pillar-shaped bottom electrode 610, while the top electrode 630 further covers the pillar-shaped bottom electrode 610 and the high-k dielectric 620. The high-k dielectric 620 is located between the bottom electrode 610 and the top electrode 630. Similarly, charge can be stored in capacitor 600B by applying a voltage difference between the bottom electrode 610 and the top electrode 630.

[0066] When capacitor 600B is used as first capacitor 135, second capacitor 140, and third capacitor 145, the bottom electrode 610 of each capacitor 600B is electrically connected to the bonding pad 120 in the first region 111 or the first conductive layer 125 in the second region 112, and the top electrode 630 of each capacitor 600B is electrically connected to the central conductive layer 136 in the first region 111 or the first connection region 131 of the second conductive layer 130 in the second region 112. For example, when capacitor 600B is used as the first capacitor 135 in the first region 111, the bottom electrode 610 is connected to one of the corresponding bonding pads 120, and the top electrode 630 is connected to the central conductive layer 136. When capacitor 600B is used as the second capacitor 140 in the second region 112, the bottom electrode 610 is connected to the same first conductive layer 125, and the top electrode 630 and the conductive material 640 are connected to the first connection region 131 of the second conductive layer 130.

[0067] Please refer to Figure 4 . Figure 4 FIG. 1 is a top view schematically illustrating a semiconductor memory device 300 according to another embodiment of the present invention.

[0068] Similar to Figure 1A and Figure 1B ,exist Figure 4 , the semiconductor memory device 300 includes a substrate 310. However, Figure 4 The semiconductor memory device 300 and Figure 1A 、 Figure 1B The difference between the semiconductor memory device 100 and the semiconductor memory device 300 lies in the shape of the second region 312 surrounding the first region 311 and the third region 313. The third region 313 is located between the first region 311 and the second region 312. The semiconductor memory device 300 includes a substrate 310, which includes an active region having a first region 311, a second region 312, and a third region 313. The second region 312 includes four sub-regions 312a, 312b, 312c, and 312d. The third region 313 is located between the first region 311 and the sub-regions 312a, 312b, 312c, and 312d.

[0069] A plurality of capacitors are located on a substrate 310 of the semiconductor memory device 300. A plurality of first capacitors 335 are located on a first region 311.

[0070] A plurality of second capacitors 340 are located on the second region 312. Each of the sub-regions 312a, 312b, 312c, and 312d houses a plurality of second capacitors 340. In this embodiment, the sub-regions 312a, 312b, 312c, and 312d are rectangular. Specifically, the second capacitors 340 include capacitors 340a, 340b, 340c, and 340d located on the sub-regions 312a, 312b, 312c, and 312d, respectively. Similarly, the second capacitors 340 of capacitors 340a, 340b, 340c, and 340d are not coupled to the first capacitor 335 in the first region 311. In other words, the second capacitors 340 of capacitors 340a, 340b, 340c, and 340d are electrically isolated from the first capacitor 335 in the first region 311. Thus, the decoupling capacitors 340 a , 340 b , 340 c and 340 d surround the first capacitor 335 to avoid noise influence.

[0071] There are multiple gaps between the sub-regions 312a, 312b, 312c and 312d. Figure 4 As shown, gap g1 is between square sub-regions 312a and 312b, gap g2 is between square sub-regions 312a and 312d, gap g3 is between square sub-regions 312c and 312d, and gap g4 is between square sub-regions 312b and 312d. Each of sub-regions 312a, 312b, 312c, and 312d is adjacent to one side of the square first region 311.

[0072] In this embodiment, the first capacitor 335 is formed by a conductive layer (similar to Figure 2 For the second region 312, the second capacitors 340 (e.g., capacitors 340a, 340b, 340c, and 340d) in the same sub-region (e.g., sub-regions 312a, 312b, 312c, and 312d) are connected to each other through corresponding conductive layers (similar to Figure 2 For the purpose of simple explanation, Figure 4 The conductive layer for connecting the capacitor is not shown.

[0073] A plurality of third capacitors 345 are located in the third region 313. Similarly, no conductive layer is disposed above the third capacitors 345, and the third capacitors 345 are non-conductive. Thus, the first capacitors 335 and the second capacitors 340 can be further electrically isolated.

[0074] In some embodiments, the semiconductor memory device 100 and the semiconductor memory device 300 can be formed by the following process.

[0075] First, an active region is formed on a substrate, and a plurality of active devices including word lines and bit lines can be formed in the active region.

[0076] Then, the first, second and third regions of the active area are defined, for example Figure 2 The illustrated first region 111, second region 112 and third region 113 have bonding pads formed in the first region, a first conductive layer formed in the second region, the second conductive layer being, for example, a bottom cell plate, and capacitors formed on the active region and isolated from the bit lines.

[0077] After the capacitor is formed, a top cell plate is formed to cover the first region, the second region, and the third region, and the top cell plate is divided into the first conductive layer of the second region (eg, Figure 2 The second conductive layer 130 in the first region) and the conductive layer of the first region (eg Figure 2 The central conductive layer 136 in the third region is removed. Portions of the top cell plate in the third region are removed, thereby isolating the capacitors in the second region from the capacitors in the first region. In some embodiments, the portion of the top cell plate in the third region can be removed using photolithography and etching processes. The capacitors in the second region can be considered decoupling capacitors.

[0078] Subsequently, contacts are formed on the divided top cell board.

[0079] Finally, metal wiring is formed to remove the connection between the capacitors and to provide power management or power regulators. For example, the metal wiring can be connected to Figure 2 The contacts 126 are shown.

[0080] For the semiconductor memory device 300, a top cell plate can be formed to cover all of the first region 311, the second region 312 including sub-regions 312a, 312b, 312c, and 312d, and the third region 313. Subsequently, the portion of the top cell plate corresponding to the third region 313 is removed through photolithography and etching processes, thereby defining decoupling sub-regions 312a, 312b, 312c, and 312d that decouple the second region 312 from the active first region 311.

[0081] Please refer to Figure 5 . Figure 5 FIG. 5 is a semiconductor structure 500 according to an embodiment of the present invention.

[0082] like Figure 5As shown, the semiconductor structure 500 includes a substrate 510 and semiconductor memory devices 100, 200, 300, and 400. The semiconductor memory devices 100, 200, 300, and 400 can be considered as semiconductor chips on the substrate 510. In other words, the substrate 510 can be considered as a common substrate for the semiconductor memory devices 100, 200, 300, and 400. For the purpose of simplicity, the capacitors on the semiconductor memory devices 100, 200, 300, and 400 are not shown. Figure 5 As previously described, semiconductor memory device 100 includes a first region 111, a second region 112, and a third region 113. Semiconductor memory device 200 is similar to semiconductor memory device 100 and includes a substrate 210. The active region of substrate 210 includes a first region 211, a second region 212 surrounding but electrically isolated from first region 211, and a third region 213 located between first region 211 and second region 212. Semiconductor memory device 300 includes a first region 311, a second region 312, and a decoupled third region 313. Second region 312 includes square-shaped sub-regions 312a, 312b, 312c, and 312d. Similar to the semiconductor memory device 300 , the semiconductor memory device 400 includes a substrate 410 , wherein an active region of the substrate 410 includes a first region 411 , a second region surrounding the first region 411 , and a third region 413 located between the first region 411 and the second region for further decoupling, wherein the second region includes L-shaped sub-regions 412 a and 412 b .

[0083] The four semiconductor memory devices 100, 200, 300, and 400 are integrated on a substrate 510, and the semiconductor structure 500 can be considered as an integrated memory device. Connection circuits for connecting capacitors in different semiconductor memory devices 100, 200, 300, and 400 can be formed in the substrate 510. For the purpose of simplicity of illustration, the connection circuits are not shown. Figure 5 superior.

[0084] In some embodiments, some second regions (eg, second regions 112, 212 and sub-regions 312a-312d and 412a, 412b) in different semiconductor memory devices 100, 200, 300, and 400 may be connected to each other. Figure 6A and Figure 6B . Figure 6A and Figure 6B Schematically drawn Figure 5 Partial equivalent circuit.

[0085] like Figure 6AAs shown, the second region 112 and the sub-regions 312a and 312d can be connected to each other through the connection circuit in the substrate 510. In this embodiment, the second region 112 and the sub-regions 312a and 312d are equivalently connected in parallel. The equivalent capacitance of the second region 112 is capacitance C 112 , the equivalent capacitance of sub-region 312a is capacitance C 312a , the equivalent capacitance of sub-region 312d is C 312d . Equivalent capacitance C 312a and capacitor C 312d and the equivalent capacitance C 112 in parallel.

[0086] exist Figure 6B In the embodiment, sub-areas 312b and 312c can be connected to each other through the connection circuit in the substrate 510. The equivalent capacitance of sub-area 312b is capacitance C 312b , the equivalent capacitance of sub-region 312c is capacitance C 312c . Equivalent capacitance C 312b and capacitor C 312c and the equivalent resistance R serial Series connection.

[0087] In some embodiments, the second capacitors in the second region 112, the second region 212, the sub-regions 312a-312d, and the sub-regions 412a and 412b can be used in series or in parallel with other independent decoupling capacitors, thereby reducing the area occupied by the second power decoupling capacitors in the second region 112, the second region 212, the sub-regions 312a-312d, and the sub-regions 412a and 412b, thereby reducing the chip area of ​​the semiconductor memory devices 100, 200, 300, and 400.

[0088] In summary, by configuring the second decoupling capacitor around the first capacitor forming the memory cell as described above, noise from the power supply or high-frequency signals can be reduced, allowing the second capacitor to function as a low-pass filter to remove signal noise. The second capacitor can also serve as a reference capacitor or decoupling capacitor required by peripheral circuits.

[0089] Although the present invention has been described above in terms of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

[0090] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In summary, the present invention is intended to encompass modifications and variations of the present invention, as long as these modifications and variations fall within the scope of the present invention.

[0091]

Explanation of symbols

[0092] 100:Semiconductor memory device

[0093] 110:Substrate

[0094] 110S: Contact surface

[0095] 111: District 1

[0096] 112: District 2

[0097] 113: District 3

[0098] 115: Contact structure

[0099] 120: Bonding pad

[0100] 125: first conductive layer

[0101] 126:Contact

[0102] 130: second conductive layer

[0103] 131: First connection area

[0104] 132: Second connection area

[0105] 134:Contact

[0106] 135: first capacitor

[0107] 136: Central conductive layer

[0108] 137:Contact

[0109] 140: Second capacitor

[0110] 145: The third capacitor

[0111] 150: first insulating layer

[0112] 155: Second insulation layer

[0113] 160: bit line

[0114] 200:Semiconductor memory device

[0115] 210:Substrate

[0116] 211: District 1

[0117] 212: District 2

[0118] 213: District 3

[0119] 300: semiconductor memory device

[0120] 310:Substrate

[0121] 311: District 1

[0122] 312: District 2

[0123] 312a, 312b, 312c, 312d: Sub-areas

[0124] 313: District 3

[0125] 335: first capacitor

[0126] 340: Second capacitor

[0127] 340a, 340b, 340c, 340d: Capacitors

[0128] 345: The third capacitor

[0129] 400: semiconductor memory device

[0130] 410:Substrate

[0131] 411: District 1

[0132] 412: District 2

[0133] 412a, 412b: Sub-area

[0134] 413: District 3

[0135] 500:Semiconductor Structure

[0136] 510:Substrate

[0137] 600A, 600B: Capacitor

[0138] 610: bottom electrode

[0139] 620: High dielectric constant dielectric

[0140] 630: Top electrode

[0141] 640: Conductive material

[0142] C 112 ,C 312a ,C 312b ,C 312c ,C 312d :capacitance

[0143] D1, D2: direction

[0144] g1,g2,g3,g4: gap

[0145] L-L': line segment

[0146] R serial :resistance

[0147] T: Transistor.

Claims

1. A semiconductor memory device, characterized in that: include: A substrate having an active region, wherein the active region has a first region, a second region, and a third region, the third region surrounds the first region, and the second region surrounds the first region and the third region; A plurality of bonding pads are disposed on the first region and the third region; a first conductive layer disposed on the second region; A plurality of first capacitors are respectively disposed on the bonding pads in the first region; a plurality of second capacitors disposed on the first conductive layer; A second conductive layer is disposed on the second capacitors; and A plurality of third capacitors are respectively disposed on the bonding pads in the third region, wherein the second conductive layer is not electrically connected to the third capacitors.

2. The semiconductor memory device according to claim 1, wherein The second conductive layer includes a first connection region located above the second capacitors, and a power source is connected to the first conductive layer or the second conductive layer.

3. The semiconductor memory device according to claim 2, wherein The second conductive layer includes a second connection region connected to the first connection region. The second conductive layer in the second connection region extends along a direction perpendicular to the connection surface of the active region.

4. The semiconductor memory device according to claim 1, wherein The first conductive layer and the bonding pads in the first region are formed on the same horizontal plane.

5. The semiconductor memory device according to claim 1, wherein The second capacitors are connected in parallel or in series.

6. The semiconductor memory device according to claim 1, wherein The substrate includes a first insulating layer and a plurality of bit lines, and the bit lines are located under the first insulating layer in the first region.

7. The semiconductor memory device according to claim 6, wherein The substrate includes a plurality of contact structures. The bonding pads are respectively arranged on the contact structures. The top surfaces of the contact structures and the top surface of the first insulating layer are on the same level.

8. The semiconductor memory device according to claim 7, wherein The bottoms of the contact structures and the bottoms of the bit lines are on the same level.

9. The semiconductor memory device according to claim 1, wherein The second insulating layer is arranged in the second region, the second capacitors are arranged on the second insulating layer, and the first conductive layer covers the second insulating layer in the second region.

10. The semiconductor memory device according to claim 1, wherein The second region includes a plurality of sub-regions with a plurality of gaps between the sub-regions, and each of the sub-regions accommodates some of the second capacitors.

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