A clock synchronization method and related device

Abstract

The embodiment of the present application discloses a clock synchronization method and related devices, which can be applied to smart phones or wireless speakers. The method includes: obtaining a first time slice group, the first time slice group including multiple first time slices. The first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially the same. According to the first time slice group, the first detection clock or the second detection clock is adjusted. Through the sliding window technology, the timestamp data is effectively multiplexed in adjacent time slices, and the number of detection signals sent by the computing device per unit time is reduced as much as possible under the premise of providing a sufficient number of time slices. Under the premise of ensuring clock synchronization, the burden on the computing device and the network is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a clock synchronization method and related devices. Background Art

[0002] With the expansion of computing device functionality and the growth of product categories, computing devices have become ubiquitous in people's lives and work. Computing devices broadly refer to machines and equipment with computing and processing capabilities, including but not limited to multimedia audio-visual and entertainment devices in home systems, and sensor and processing modules in automotive systems. Computing devices can communicate with each other via wireless networks such as Wireless Fidelity (Wi-Fi), wireless radio frequency networks, or Bluetooth. Clock synchronization is an essential component of computing device communication, ensuring data sharing, inter-device coordination, and interaction at designated times.

[0003] Let's take the Huygens processing method as an example. In a wireless network, each server periodically probes other servers. Specifically, the server periodically sends a probe packet carrying a timestamp to the other servers. In each cycle, the server obtains multiple timestamp quads: <TX a ,RX b ,tx b ,rx a >, each quadruple corresponds to the server that sends the detection packet and the server that receives the detection packet. For each quadruple, a set of upper bounds and lower bounds are calculated, where upper bound = (RX b -TX a ) and the offset lower bound lower bound=(tx b -rx a The clock offset and drift between the clock of the server that sends the probe packet and the clock of the server that receives the probe packet are related to the upper and lower bounds of the offset.<upper bound,lower bound> Data is processed using machine learning methods to determine the clock offset and drift rate between two clocks. Clock offset refers to the relative difference between two clocks, that is, the difference between the times displayed by two clocks at the same moment. Drift refers to the rate at which the clock offset between two clocks changes over time. It is generally expressed in microseconds per second (us / s), representing the magnitude of the clock offset change per unit of time (e.g., 1 second).

[0004] However, after obtaining the above-mentioned clock offset and offset speed, how to perform clock synchronization based on the clock offset (also called offset amount) and offset speed remains a blank. Summary of the Invention

[0005] The embodiments of the present application provide a clock synchronization method, which reduces the operating burden of computing devices and networks while ensuring clock synchronization.

[0006] In a first aspect, an embodiment of the present application provides a clock synchronization method, the method comprising:

[0007] Obtain a first time slice group, where the first time slice group includes multiple first time slices, each of which includes multiple first timestamps, wherein the first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially identical, and the first timestamps include a time when the first detection clock sends a detection signal and a time when the second detection clock receives the detection signal;

[0008] The first detection clock or the second detection clock is adjusted according to the first time slice group.

[0009] In an optional implementation, the computing device (corresponding to the first detection clock) obtains the first time slice group.

[0010] In another optional implementation, other computing devices (corresponding to the second detection clock) obtain the first time slice group.

[0011] Optionally, the computing device's clock may be the first detection clock, and the clocks of other computing devices (or servers) detected by the computing device are referred to as second detection clocks. The second detection clock may be the clock of one other computing device (or one server), or the clocks of multiple other computing devices (or multiple servers), without limitation.

[0012] Optionally, the computing device's clock may be a second detection clock, and the clocks of other computing devices (or servers) detected by the computing device are referred to as first detection clocks. The first detection clock may be the clock of one other computing device (or one server), or the clocks of multiple other computing devices (or multiple servers), without limitation.

[0013] In this embodiment, a sliding window technique is used to effectively reuse timestamp data in adjacent time slices. This minimizes the number of probe signals sent by computing devices per unit time while providing a sufficient number of time slices. This reduces the burden on computing devices and the network while ensuring clock synchronization.

[0014] In conjunction with the first aspect, in a possible implementation of the first aspect, adjusting the first detection clock or the second detection clock according to the first time slice group includes:

[0015] Calculating a plurality of first offset velocities according to the first time slice group, wherein each first offset velocity corresponds to an offset velocity of a first time slice;

[0016] Calculating a first measurement value based on the multiple first offset velocities, where the first measurement value indicates jitter of the clock in the first time slice group. The first measurement value may be a standard deviation of the multiple first offset velocities or a variance of the multiple first offset velocities, which is not limited here.

[0017] The first detection clock or the second detection clock is adjusted according to the first measurement value and the first offset speed.

[0018] In the embodiment of the present application, after calculating multiple first offset speeds based on the first time slice group, a first measurement value is calculated based on the multiple first offset speeds. The first measurement value can effectively indicate the jitter of the clock in the first time slice group, thereby improving the accuracy of detecting whether clock synchronization is performed.

[0019] In conjunction with the first aspect, in a possible implementation of the first aspect, when the first measurement value is less than a first threshold, adjusting the first detection clock or the second detection clock includes:

[0020] adjusting a first clock frequency according to the plurality of first offset speeds, wherein the first clock frequency is a clock frequency of the first detection clock or a clock frequency of the second detection clock;

[0021] And / or, adjusting the first clock offset according to the first offset, wherein the first offset is determined by the first time slice group, and the first clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock.

[0022] In the embodiment of the present application, clock synchronization can be achieved by adjusting the first clock frequency, adjusting the first clock offset, or adjusting the first clock frequency and adjusting the first clock offset at the same time, thereby improving the flexibility of the solution implementation.

[0023] In conjunction with the first aspect, in a possible implementation of the first aspect, before adjusting the first detection clock or the second detection clock, the method further includes:

[0024] The first time slice includes at least one first sub-time slice;

[0025] When the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value, adjusting the first clock frequency and / or the first clock offset;

[0026] When the product of the time length of the first sub-time slice and the first offset is less than a preset synchronization accuracy value, the first clock offset is adjusted.

[0027] Optionally, assuming that the original clock offset before clock adjustment is d0 and the length of the first sub-time slice is t0, if the clock frequency is not adjusted, the maximum clock offset within the first sub-time slice is d0*t0. If the resulting value of d0*t0 is less than or equal to the preset synchronization accuracy value, then the first clock frequency does not need to be adjusted and only the first offset can be adjusted; however, if the resulting value of d0*t0 is greater than the preset synchronization accuracy value, then the clock frequency and / or the first offset need to be adjusted.

[0028] In the embodiment of the present application, clock frequency adjustment can easily cause clock oscillation. Therefore, by detecting the relationship between the product of the length of the first sub-time slice and the first offset and a preset synchronization accuracy value, frequent clock frequency adjustment can be avoided, thereby improving clock stability.

[0029] In conjunction with the first aspect, in a possible implementation of the first aspect, after adjusting the first clock frequency according to the multiple first offset speeds, the method further includes:

[0030] generating a second threshold value, the second threshold value being smaller than the first threshold value;

[0031] The first threshold is updated using the second threshold.

[0032] In the embodiment of the present application, after adjusting the clock frequency, the difficulty of adjusting the clock frequency is increased by adjusting the total number of time slices included in the time slice group and adjusting the first threshold (using the second threshold to update the first threshold).

[0033] In conjunction with the first aspect, in a possible implementation of the first aspect, after adjusting the first clock frequency according to the multiple first offset speeds, the method further includes:

[0034] Initialize the first timestamp, the first time slice, and the first offset.

[0035] In the embodiment of the present application, after the clock frequency is adjusted, the historical data (first timestamp, first time slice and first offset) is initialized to prevent invalid historical data from affecting subsequent clock synchronization.

[0036] In conjunction with the first aspect, in a possible implementation of the first aspect, after adjusting the first clock frequency according to the multiple first offset speeds, the method further includes:

[0037] Determine a total number of first time slices, where the total number of first time slices is the total number of first time slices included in the first time slice group;

[0038] generating a second time slice total, the second time slice total being greater than the first time slice total;

[0039] A first time slice group is acquired according to the total number of second time slices and the plurality of first timestamps.

[0040] In an embodiment of the present application, to avoid frequent clock frequency adjustments, the computing device may also increase the total number of time slices in the first time slice group to make clock frequency adjustments easier. Specifically, the computing device determines a first total number of time slices, where the first total number of time slices is the total number of first time slices included in the first time slice group. Secondly, the computing device generates a second total number of time slices, where the second total number of time slices is greater than the first total number of time slices. Thirdly, the computing device obtains the first time slice group based on the second total number of time slices and the plurality of first timestamps.

[0041] In conjunction with the first aspect, in a possible implementation of the first aspect, when the first measurement value is greater than the first threshold, adjusting the first detection clock or the second detection clock includes:

[0042] Acquire a second time slice group, where the second time slice group includes multiple first time slices, and the total number of first time slices included in the second time slice group is less than the total number of first time slices included in the first time slice group;

[0043] Calculating a second measurement value based on the total number of first time slices included in the second time slice group and the first offset speed, wherein the second measurement value indicates a jitter condition of a clock in the second time slice group;

[0044] When the second measurement value is less than a third threshold, the second clock offset is adjusted according to the first offset, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

[0045] Specifically, the second measurement value is similar to the first measurement value and may be the standard deviation of the multiple first offset velocities in the second time slice group. The second measurement value may also be the variance of the multiple first offset velocities in the second time slice group.

[0046] In conjunction with the first aspect, in a possible implementation of the first aspect, after adjusting the second clock offset according to the first offset, the method further includes:

[0047] Get the first timestamp;

[0048] A second timestamp is generated according to the first offset and the first timestamp, wherein the second timestamp is a difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp.

[0049] In the embodiment of the present application, when only the second clock offset is adjusted, the historical timestamp data (first timestamp) can be processed and then used again. Specifically, the first timestamp is processed using the first offset to obtain a second timestamp. The second timestamp is the difference between the first timestamp and the first offset. After obtaining the second timestamp, it is used to update the first timestamp. While ensuring a sufficient number of samples (timestamps), this reduces the burden on the network and computing equipment.

[0050] In conjunction with the first aspect, in a possible implementation of the first aspect, calculating multiple first offset velocities according to the first time slice group includes:

[0051] Get the offset of the first time slice in the first time slice group and the end time of the first time slice;

[0052] Performing linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line;

[0053] A first offset speed and a first offset amount are determined according to the fitting straight line.

[0054] The first offset velocity is the slope of the fitted line;

[0055] The first offset is the value of the ordinate of the fitting line when the abscissa of the fitting line is the end time of the first time slice.

[0056] In this embodiment, the computing device calculates a fitted straight line using a linear regression method for the offset of the first time slice and the end time of the first time slice, wherein the end time of the first time slice is an independent variable and the offset of the first time slice is a dependent variable.

[0057] In the embodiment of the present application, a linear regression method is used to eliminate transmission errors caused by timestamp errors or jitters in the wireless network from the calculated first offset speed and first offset, thereby improving the accuracy of time synchronization.

[0058] In a second aspect, an embodiment of the present application provides a computing device, which includes a transceiver module and a processing module. Specifically:

[0059] a transceiver module, configured to obtain a first time slice group, where the first time slice group includes multiple first time slices, each of which includes multiple first timestamps, wherein the first timestamps in the first time slices are continuous, and corresponding first timestamps in two adjacent first time slices are partially identical, and the first timestamps include a time when the first detection clock sends a detection signal and a time when the second detection clock receives the detection signal;

[0060] The processing module is configured to adjust the first detection clock or the second detection clock according to the first time slice group.

[0061] In some optional embodiments of the present application,

[0062] a processing module, configured to calculate a plurality of first offset velocities according to the first time slice group, wherein each first offset velocity corresponds to an offset velocity of a first time slice;

[0063] a processing module, configured to calculate a first measurement value according to the plurality of first offset velocities, the first measurement value indicating a jitter condition of a clock in the first time slice group;

[0064] The processing module is configured to adjust the first detection clock or the second detection clock according to the first measurement value and the first offset speed.

[0065] In some optional embodiments of the present application,

[0066] a processing module, configured to adjust a first clock frequency according to the plurality of first offset speeds, wherein the first clock frequency is a clock frequency of the first detection clock or a clock frequency of the second detection clock;

[0067] and / or,

[0068] The processing module is used to adjust the first clock offset according to the first offset, wherein the first offset is determined by the first time slice group, and the first clock offset is the clock offset of the first detection clock or the clock offset of the second detection clock.

[0069] In some optional embodiments of the present application,

[0070] a processing module, configured to adjust the first clock frequency and / or the first clock offset if the first time slice includes at least one first sub-time slice and the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value;

[0071] The processing module is configured to adjust the first clock offset when the product of the time length of the first sub-time slice and the first offset is less than a preset synchronization accuracy value.

[0072] In some optional embodiments of the present application,

[0073] a processing module, configured to generate a second threshold value, wherein the second threshold value is smaller than the first threshold value;

[0074] The processing module is configured to update the first threshold using the second threshold.

[0075] In some optional embodiments of the present application,

[0076] The processing module is used to initialize the first timestamp, the first time slice and the first offset.

[0077] In some optional embodiments of the present application,

[0078] The processing module is further configured to determine a total number of first time slices, where the total number of first time slices is a total number of first time slices included in the first time slice group;

[0079] The processing module is further configured to generate a second total number of time slices, the second total number of time slices being greater than the first total number of time slices;

[0080] The transceiver module is further configured to obtain a first time slice group according to the total number of second time slices and the plurality of first timestamps.

[0081] In some optional embodiments of the present application,

[0082] a transceiver module, configured to obtain a second time slice group, where the second time slice group includes a plurality of first time slices, and the total number of first time slices included in the second time slice group is less than the total number of first time slices included in the first time slice group;

[0083] a processing module, configured to calculate a second measurement value according to the total number of first time slices included in the second time slice group and the first offset speed, wherein the second measurement value indicates a jitter condition of a clock in the second time slice group;

[0084] The processing module is used to adjust the second clock offset according to the first offset when the second measurement value is less than the third threshold, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

[0085] In some optional embodiments of the present application,

[0086] The transceiver module is further used to obtain a first timestamp;

[0087] The processing module is further configured to generate a second timestamp according to the first offset and the first timestamp, wherein the second timestamp is a difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp.

[0088] In some optional embodiments of the present application,

[0089] The first measurement value is a standard deviation of a plurality of first offset velocities;

[0090] Alternatively, the first measurement value is a variance of a plurality of first offset velocities.

[0091] In some optional embodiments of the present application,

[0092] The transceiver module is further configured to obtain an offset of a first time slice in the first time slice group and an end time of the first time slice;

[0093] The processing module is further configured to perform linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line;

[0094] The processing module is further configured to determine a first offset speed and a first offset amount according to the fitted straight line.

[0095] In some optional embodiments of the present application,

[0096] The first offset velocity is the slope of the fitted line;

[0097] The first offset is the value of the ordinate of the fitting line when the abscissa of the fitting line is the end time of the first time slice.

[0098] In a third aspect, an embodiment of the present application provides a computing device, including a processor and a transceiver, specifically:

[0099] a transceiver configured to obtain a first time slice group, the first time slice group including a plurality of first time slices, the first time slices including a plurality of first timestamps, wherein the first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially identical, and the first timestamps include a time when the first detection clock sends a detection signal and a time when the second detection clock receives the detection signal;

[0100] The processor is configured to adjust the first detection clock or the second detection clock according to the first time slice group.

[0101] In some optional embodiments of the present application,

[0102] a processor, configured to calculate a plurality of first offset velocities according to the first time slice group, wherein each first offset velocity corresponds to an offset velocity of a first time slice;

[0103] a processor, configured to calculate a first measurement value based on the plurality of first offset velocities, the first measurement value indicating jitter of a clock in the first time slice group;

[0104] The processor is configured to adjust the first detection clock or the second detection clock according to the first measurement value and the first offset speed.

[0105] In some optional embodiments of the present application,

[0106] a processor, configured to adjust a first clock frequency according to the plurality of first offset speeds, wherein the first clock frequency is a clock frequency of the first detection clock or a clock frequency of the second detection clock;

[0107] and / or,

[0108] The processor is configured to adjust a first clock offset according to a first offset, wherein the first offset is determined by a first time slice group, and the first clock offset is a clock offset of a first detection clock or a clock offset of a second detection clock.

[0109] In some optional embodiments of the present application,

[0110] a processor, configured to adjust the first clock frequency and / or the first clock offset if the first time slice includes at least one first sub-time slice and the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value;

[0111] The processor is configured to adjust the first clock offset when the product of the time length of the first sub-time slice and the first offset is less than a preset synchronization accuracy value.

[0112] In some optional embodiments of the present application,

[0113] a processor, configured to generate a second threshold value, the second threshold value being smaller than the first threshold value;

[0114] The processor is configured to update the first threshold using the second threshold.

[0115] In some optional embodiments of the present application,

[0116] The processor is configured to initialize the first timestamp, the first time slice, and the first offset.

[0117] In some optional embodiments of the present application,

[0118] The processor is further configured to determine a total number of first time slices, where the total number of first time slices is a total number of first time slices included in the first time slice group;

[0119] The processor is further configured to generate a second total number of time slices, the second total number of time slices being greater than the first total number of time slices;

[0120] The transceiver is further configured to obtain a first time slice group according to the total number of second time slices and the plurality of first timestamps.

[0121] In some optional embodiments of the present application,

[0122] The transceiver is configured to obtain a second time slice group, where the second time slice group includes a plurality of first time slices, and the total number of the first time slices included in the second time slice group is less than the total number of the first time slices included in the first time slice group;

[0123] a processor, configured to calculate a second measurement value based on the total number of first time slices included in the second time slice group and the first offset speed, wherein the second measurement value indicates jitter of the clock in the second time slice group;

[0124] The processor is configured to adjust the second clock offset according to the first offset when the second measurement value is less than a third threshold, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

[0125] In some optional embodiments of the present application,

[0126] The transceiver is further configured to obtain a first timestamp;

[0127] The processor is further configured to generate a second timestamp based on the first offset and the first timestamp, wherein the second timestamp is a difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp.

[0128] In some optional embodiments of the present application,

[0129] The first measurement value is a standard deviation of a plurality of first offset velocities;

[0130] Alternatively, the first measurement value is a variance of a plurality of first offset velocities.

[0131] In some optional embodiments of the present application,

[0132] The transceiver is further configured to obtain an offset of a first time slice in the first time slice group and an end time of the first time slice;

[0133] The processor is further configured to perform linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line;

[0134] The processor is further configured to determine a first offset speed and a first offset amount according to the fitted straight line.

[0135] In some optional embodiments of the present application,

[0136] The first offset velocity is the slope of the fitted line;

[0137] The first offset is the value of the ordinate of the fitting line when the abscissa of the fitting line is the end time of the first time slice.

[0138] In a fourth aspect, an embodiment of the present application provides a computing device that can implement the functions performed by the computing device in the method involved in the first aspect above. The computing device includes a processor, a memory, a receiver connected to the processor, and a transmitter connected to the processor; the memory is used to store program code and transmit the program code to the processor; the processor is used to drive the receiver and the transmitter to execute the method of the first aspect above according to the instructions in the program code; the receiver and the transmitter are respectively connected to the processor to execute the operations of the computing device in the method of each aspect above. Specifically, the transmitter can perform a sending operation, and the receiver can perform a receiving operation. Optionally, the receiver and the transmitter can be radio frequency circuits, and the radio frequency circuit receives and sends messages through an antenna; the receiver and the transmitter can also be communication interfaces, the processor and the communication interface are connected through a bus, and the processor receives or sends messages through the communication interface.

[0139] In a fifth aspect, an embodiment of the present application provides a computing device, which may include an entity such as a terminal device or a chip, and the computing device includes: a processor and a memory; the memory is used to store instructions; the processor is used to execute the instructions in the memory, so that the computing device executes a method as described in any one of the first aspects above.

[0140] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes any possible implementation method as described in the first aspect above.

[0141] In the seventh aspect, an embodiment of the present application provides a computer program product (or computer program) that stores one or more computer-executable instructions. When the computer-executable instructions are executed by the processor, the processor executes any possible implementation method of the aforementioned first aspect.

[0142] In an eighth aspect, the present application provides a chip system, which includes a processor for supporting a computer device in implementing the functions described in the above aspects. In one possible design, the chip system also includes a memory for storing program instructions and data necessary for the computer device. The chip system can be composed of a chip alone or include a chip and other discrete components. BRIEF DESCRIPTION OF THE DRAWINGS

[0143] Figure 1a A schematic diagram of clock detection according to an embodiment of the present application;

[0144] Figure 1b This is a schematic diagram of the processing results of the Huygens processing method;

[0145] Figure 1c A schematic diagram of an application scenario proposed in an embodiment of the present application;

[0146] Figure 2 This is a schematic diagram of the hardware structure of the computing device in the embodiment of the present application;

[0147] Figure 3a A schematic diagram of an embodiment of a clock synchronization method proposed in an embodiment of the present application;

[0148] Figure 3b This is a schematic diagram of generating a first timestamp in an embodiment of the present application;

[0149] Figure 3c A schematic diagram of a time slice involved in the prior art;

[0150] Figure 3d A schematic diagram of a first time slice proposed in an embodiment of the present application;

[0151] Figure 4a A schematic diagram of another embodiment of a clock synchronization method proposed in an embodiment of the present application;

[0152] Figure 4b A schematic diagram of a simulation experiment involved in an embodiment of the present application;

[0153] Figure 5 A schematic diagram of another embodiment of a clock synchronization method proposed in an embodiment of the present application;

[0154] Figure 6 This is another schematic diagram of a simulation experiment involved in an embodiment of the present application;

[0155] Figure 7 This is another schematic diagram of a simulation experiment involved in an embodiment of the present application;

[0156] Figure 8 This is a schematic diagram of an embodiment of a computing device in an embodiment of the present application. DETAILED DESCRIPTION

[0157] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances. This is merely a way of distinguishing when describing objects with the same properties in the embodiments of the present application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, so that a process, method, system, product or apparatus that includes a series of units is not necessarily limited to those units, but may include other units not expressly listed or inherent to these processes, methods, products or apparatuses.

[0158] The technical solutions in the embodiments of the present application will be clearly described below in conjunction with the drawings in the embodiments of the present application. In the description of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the present application is merely a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the present application, "at least one" refers to one or more items, and "multiple items" refers to two or more items. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or multiple items. For example, at least one of a, b, or c can mean a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or multiple.

[0159] First, see Figure 1a , Figure 1a Schematic diagram of clock detection involved in the embodiment of the present application. When detection clock 1 needs to synchronize the clock of detection clock 2, detection clock 1 first sends a detection packet 1 to detection clock 2 and records the sending time TX a When the detection clock 2 recognizes the detection packet 1, it records its receiving time RX b Then the detection clock 2 sends a detection packet 2 to the detection clock 1 and sends RX b And the sending time tx of detection packet 2 b After receiving the detection packet 2, the detection clock 1 records its receiving time rx a .

[0160] In the Network Time Protocol (NTP) and Precision Time Protocol (PTP), the client calculates the one-way delay (OWD) and offset using four timestamps. Specifically, let the accurate clock be t, and the offsets of detection clock 1 and detection clock 2 relative to the accurate clock be Δt. a and Δt b , then the clock of detection clock 1 is t a =t+Δt a , the clock of detection clock 2 is t b =t+Δt b , the clock deviation between detection clock 1 and detection clock 2 is offset = Δt b -Δt a Assuming that the OWD of probe packets 1 and 2 are the same, probe clock 1 can calculate:

[0161]

[0162]

[0163] Based on this OWD and offset, probe clock 1 can modify its local clock to synchronize with probe clock 2.

[0164] Currently, clock synchronization methods are all based on these four timestamps, differing in how they are generated and processed. Timestamps can be generated at different locations on intelligent computing devices, which will in turn have a certain impact on detection accuracy. The NTP protocol obtains the system time from the central processing unit as a timestamp. Since probe packets may be queued in the network card, the estimated OWD is biased, which affects the offset estimation and ultimately only achieves millisecond-level accuracy. The PTP protocol obtains the timestamp when the probe packet is sent from the network card. It has higher accuracy but requires hardware support for the PTP protocol. The Data Center Time Protocol (DTP) operates in wired network scenarios.

[0165] Based on this, the Huygens processing method was proposed, which is a batch timestamp processing method. In a wireless network, each server periodically probes other servers. Specifically, the server periodically sends a probe packet carrying a timestamp to the other servers. This probe packet can also be called a probe signal. In each cycle, the server obtains multiple timestamp quads: <TX a ,RX b ,tx b ,rx a >, each quadruple corresponds to the server that sends the detection packet and the server that receives the detection packet. For each quadruple, a set of upper bounds and lower bounds are calculated, where upper bound = (RX b -TX a ) and the offset lower bound lower bound=(tx b -rx aThe clock offset and drift between the clock of the server that sends the probe packet and the clock of the server that receives the probe packet are related to the upper and lower bounds of the offset.<upperbound,lower bound> Data is processed using machine learning methods to obtain the clock offset and offset rate between two clocks. Clock offset (Offset) refers to the relative difference between two clocks, that is, the difference between the times displayed by two clocks at the same moment. Drift rate (Drift) refers to the rate at which the clock offset between two clocks changes over time. It is generally expressed in microseconds / second (us / s), representing the magnitude of the clock offset change per unit time (e.g., 1 second). Specifically, multiple groups of timestamps are processed using a support vector machine (SVM) to obtain clock offset and offset rate. For example, see Figure 1b , Figure 1b Schematic diagram of the processing results of the Huygens processing method. Figure 1b In the figure, the vertical coordinate of the upper boundary point is rx a , the horizontal coordinate of the upper boundary point is (tx b -rx a ); the vertical coordinate of the lower boundary point is (RX b -TX a ), the vertical coordinate of the lower boundary point is TX a .For example Figure 1b Shown: the vertical coordinate rx of most upper boundary points a Greater than -96 microseconds, the vertical coordinate TX of most lower nodes a Less than -94 microseconds.

[0166] To meet the data volume requirements of machine learning, clock-synchronized devices must send a large number of probe packets within a certain period of time and provide timestamps for these probe packets. Furthermore, a computing device may simultaneously probe the clocks of multiple other computing devices, posing a significant challenge to the speed at which devices can provide timestamps.

[0167] Based on this, an embodiment of the present application proposes a clock synchronization method. First, a computing device obtains a first time slice group, the first time slice group including multiple first time slices, each of which includes multiple first timestamps, wherein the first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially identical, and the first timestamps include the time when the first detection clock sends a detection signal and the time when the second detection clock receives the detection signal; second, the computing device adjusts the first detection clock or the second detection clock based on the first time slice group.

[0168] Optionally, the first detection clock may be the clock of a computing device, in which case the second detection clock is the clock of another computing device; the first detection clock may also be the clock of another computing device, in which case the second detection clock is the clock of the computing device, and there is no limitation here.

[0169] It can be seen that the timestamp data is effectively reused in adjacent time slices. On the premise of providing a sufficient number of time slices, the number of detection packets sent by the computing device per unit time is reduced as much as possible, reducing the burden on the computing device and the network.

[0170] To facilitate understanding, first, we introduce some application scenarios of this solution. Figure 1c , Figure 1c A schematic diagram of an application scenario proposed in an embodiment of the present application.

[0171] In an optional implementation, the method proposed in the embodiment of the present application is Figure 1c The mobile phone in the system operates. First, the mobile phone sends a detection packet to a speaker with which the mobile phone has established a wireless connection, and the mobile phone receives the detection packet from the speaker. Second, the mobile phone determines multiple first timestamps based on the time when the detection packet was sent and the time when the detection packet was received. Third, the mobile phone obtains a first time slice group based on the multiple first timestamps. Third, the mobile phone adjusts the first detection clock or the second detection clock based on the first time slice group. When the first detection clock is the mobile phone's clock, the second detection clock is the speaker's clock; alternatively, when the first detection clock is the speaker's clock, the second detection clock is the mobile phone's clock.

[0172] In another optional implementation, the method proposed in the embodiment of the present application is Figure 1c The speaker in the system operates. First, the speaker sends a detection packet to a mobile phone with which the speaker has established a wireless connection, and the speaker receives the detection packet from the mobile phone. Second, the speaker determines multiple first timestamps based on the time when the detection packet was sent and the time when the detection packet was received. Third, the speaker obtains a first time slice group based on the multiple first timestamps. Third, the speaker adjusts the first detection clock or the second detection clock based on the first time slice group. When the first detection clock is the speaker's clock, the second detection clock is the mobile phone's clock; alternatively, when the first detection clock is the mobile phone's clock, the second detection clock is the speaker's clock.

[0173] Understandably, Figure 1c The mobile phone in the following is a terminal device. Figure 1c It may also be other terminal devices described below.

[0174] In the embodiments of the present application, the computing device may also be referred to as user equipment (UE), terminal equipment, or electronic equipment. The computing device involved in the embodiments of the present application is a device with wireless transceiver functions, which can communicate with one or more core networks (CN) via an access network device in a network device, or can communicate with other computing devices (or electronic devices) via other technical means, where the other technical means include but are not limited to: wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication technology (NFC), infrared technology (IR), ZigBee and other wireless communication solutions. The computing device may also be referred to as an access terminal, terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, wireless network equipment, user agent or user device, etc. Computing devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on the water (such as ships); and they can also be deployed in the air (such as airplanes, balloons, and satellites).The computing device may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a smartphone, a mobile phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a handheld device with wireless communication capabilities, a computing device, or other devices connected to a wireless modem, an in-vehicle device, a wearable device, an unmanned aerial vehicle device, or a terminal in a road side unit (RSU) in the Internet of Things, vehicle to everything (V2X), or intelligent driving scenarios, a terminal of any form in a fifth generation (5G) mobile communication network and future networks, a relay user device, or a terminal in a future evolved public land mobile communication network (PLMN), etc., wherein the relay user device may be, for example, a 5G residential gateway (RG). For example, the computing device can be a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. The embodiments of the present application are not limited to this. Exemplarily, the computing device includes but is not limited to: smart speakers, smart refrigerators, or other household appliances such as smart air conditioners.

[0175] As an example and not a limitation, in the embodiment of the present application, the terminal device may also be a wearable device. Wearable devices may also be called wearable smart devices, which are a general term for wearable devices that are intelligently designed and developed using wearable technology for daily wear, such as glasses, gloves, watches, clothing, and shoes. A wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are fully functional, large in size, and can achieve complete or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as those that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0176] A clock synchronization method provided in the present application can be applied to various communication systems, for example, the Internet of Things (IoT), narrowband Internet of Things (NB-IoT), long term evolution (LTE), fifth generation (5G) communication systems, LTE and 5G hybrid architectures, new radio (NR) systems, and new communication systems emerging in future communication developments. The 5G communication system of the embodiment of the present application may include at least one of a non-standalone (NSA) 5G communication system and a standalone (SA) 5G communication system. The communication system may also be a public land mobile network (PLMN) network, a device-to-device (D2D) network, a machine-to-machine (M2M) network, or other networks.

[0177] In addition, the embodiments of the present application may also be applicable to other future-oriented communication technologies, such as 6G systems. The network architecture and service scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the present application and do not constitute a limitation on the technical solutions provided by the present application. Those skilled in the art will appreciate that with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided by the present application are also applicable to similar technical problems.

[0178] Figure 2 Schematic diagram of the hardware structure of the computing device in the embodiment of the present application. The computing device may be a possible implementation of the computing device in the embodiment of the present application. Figure 2As shown, the computing device includes at least a processor 204, a memory 203, and a transceiver 202. The memory 203 is further used to store instructions 2031 and data 2032. Optionally, the computing device may also include an antenna 206, an I / O (Input / Output) interface 210, and a bus 212. The transceiver 202 further includes a transmitter 2021 and a receiver 2022. In addition, the processor 204, the transceiver 202, the memory 203, and the I / O interface 210 are communicatively connected to each other via the bus 212, and the antenna 206 is connected to the transceiver 202.

[0179] The processor 204 can be a general-purpose processor, such as but not limited to a central processing unit (CPU), or a special-purpose processor, such as but not limited to a digital signal processor (DSP), an application-specific integrated circuit (ASIC), and a field programmable gate array (FPGA). The processor 204 can also be a neural processing unit (NPU). In addition, the processor 204 can also be a combination of multiple processors. In particular, in the technical solution provided in the embodiment of the present application, the processor 204 can be used to execute the relevant steps of the clock synchronization method in the subsequent method embodiment. The processor 204 can be a processor specially designed to perform the above steps and / or operations, or it can be a processor that performs the above steps and / or operations by reading and executing the instructions 2031 stored in the memory 203. The processor 204 may need to use data 2032 in the process of performing the above steps and / or operations.

[0180] The transceiver 202 includes a transmitter 2021 and a receiver 2022. In an optional implementation, the transmitter 2021 is configured to transmit signals via the antenna 206. The receiver 2022 is configured to receive signals via at least one of the antennas 206. In particular, in the technical solutions provided in the embodiments of the present application, the transmitter 2021 can be configured to execute, via at least one of the antennas 206, operations performed by a transceiver module in a computing device, for example, when the clock synchronization method in the subsequent method embodiments is applied to the computing device.

[0181] In the embodiment of the present application, transceiver 202 is used to support the computing device in performing the aforementioned receiving and transmitting functions. The processor with processing functions is referred to as processor 204. Receiver 2022 may also be referred to as an input port, receiving circuit, etc., and transmitter 2021 may be referred to as a transmitter or transmitting circuit, etc.

[0182] The processor 204 can be used to execute instructions stored in the memory 203 to control the transceiver 202 to receive and / or send messages, thereby completing the functions of the computing device in the embodiment of the method of the present application. As an implementation method, the functions of the transceiver 202 can be implemented by a transceiver circuit or a dedicated transceiver chip. In the embodiment of the present application, the transceiver 202 receiving a message can be understood as the transceiver 202 inputting a message, and the transceiver 202 sending a message can be understood as the transceiver 202 outputting a message.

[0183] The memory 203 may be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical memory, and registers. The memory 203 is specifically used to store instructions 2031 and data 2032. The processor 204 can perform the steps and / or operations in the embodiment of the method of the present application by reading and executing the instructions 2031 stored in the memory 203. The data 2032 may be required in the process of performing the operations and / or steps in the embodiment of the method of the present application.

[0184] Optionally, the computing device may further include an I / O interface 210 , which is used to receive instructions and / or data from a peripheral device and output instructions and / or data to the peripheral device.

[0185] The following describes the method part of the embodiment of this application. Figure 3a , Figure 3a Schematic diagram of a clock synchronization method proposed in an embodiment of the present application. A clock synchronization method proposed in an embodiment of the present application includes:

[0186] 301. Obtain a first time slice group.

[0187] In this embodiment, in an optional implementation manner, the computing device (corresponding to the first detection clock) obtains the first time slice group.

[0188] In another optional implementation, other computing devices (corresponding to the second detection clock) obtain the first time slice group.

[0189] Optionally, the computing device's clock may be the first detection clock, and the clocks of other computing devices (or servers) detected by the computing device are referred to as second detection clocks. The second detection clock may be the clock of one other computing device (or one server), or the clocks of multiple other computing devices (or multiple servers), without limitation.

[0190] Optionally, the computing device's clock may be a second detection clock, and the clocks of other computing devices (or servers) detected by the computing device are referred to as first detection clocks. The first detection clock may be the clock of one other computing device (or one server), or the clocks of multiple other computing devices (or multiple servers), without limitation.

[0191] Specifically, the first time slice group includes multiple first time slices, and the first time slice includes multiple first timestamps, wherein the first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially the same, and the first timestamps include the moment when the first detection clock sends the detection signal, and the moment when the second detection clock receives the detection signal.

[0192] For the sake of convenience, the clock on a computing device (such as a mobile phone) is used as the first detection clock, and the clock on another computing device (such as a speaker) is used as the second detection clock. Figure 3b , Figure 3b This is a schematic diagram of the generation of the first timestamp in the embodiment of the present application. For each detection, a detection signal (such as a data packet or an empty packet) in two directions is sent between the first detection clock and the second detection clock, generating a total of 4 timestamps. Detect the sending and receiving times of the two detection signals on the two clocks respectively, for example Indicates the time the first detection clock sends the detection signal during the first detection. Within a certain period of time, the first detection clock sends k detection signals to the second detection clock, and the second detection clock sends k detection signals to the first detection clock, performing k detections, where k is a positive integer. After k detections, 4*k timestamps form multiple first timestamps.

[0193] For easier understanding, see Figure 3c and Figure 3d , Figure 3c A time slice diagram is shown in Figure 3c In , each time slice includes multiple timestamps, and the timestamps in each time slice are independent of each other. Figure 3cThe time slice division method shown in Figure 3d In the example, the first time slice group includes two first time slices, and each first time slice includes 8 first timestamps. Figure 3d It can be seen that two adjacent first time slices include two identical first time stamps (the first time stamps shown by the shadows). Figure 3d The time slice division method shown in the figure reuses timestamp data in adjacent time slices (i.e., the first timestamps corresponding to adjacent first time slices are partially the same), providing sufficient time slice data while obtaining less timestamp data. This reduces the burden on computing devices and networks while ensuring clock synchronization.

[0194] 302. Adjust the first detection clock or the second detection clock according to the first time slice group.

[0195] In this embodiment, multiple first offset velocities are calculated based on the first time slice group, where each first offset velocity corresponds to an offset velocity of a first time slice. A first measurement value is calculated based on the multiple first offset velocities, the first measurement value indicating the jitter of the clock within the first time slice group. The first detection clock or the second detection clock is adjusted based on the first measurement value and the first offset velocity.

[0196] The first measurement value may be the standard deviation of multiple first offset velocities, or the variance of multiple first offset velocities, which is not limited here. The following description takes the first measurement value being the standard deviation of multiple first offset velocities as an example:

[0197] First, calculate the n first offset velocities dr corresponding to the n first time slices i (i=0,1,…,n), where n is a positive integer;

[0198] Secondly, calculate the average value meanDr of n first offset velocities;

[0199] Again, calculate the variance of the n first offset velocities

[0200] Next, the standard deviation of the n first offset velocities is calculated based on the variance. Specifically, the standard deviation is obtained by taking the square root of the variance. The standard deviation of the n first offset velocities is also called the standard deviation of the n first time slices.

[0201] In this embodiment, a sliding window technique is used to effectively reuse timestamp data in adjacent time slices. This minimizes the number of probe signals sent by computing devices per unit time while providing a sufficient number of time slices. This reduces the burden on computing devices and the network while ensuring clock synchronization.

[0202] Optional, in Figures 3a to 3d On the basis of , in order to further improve the accuracy of time synchronization, the first offset speed and the first offset can be further processed. For details, please refer to Figure 4a , Figure 4a A clock synchronization method according to an embodiment of the present application is provided as a schematic diagram of another embodiment of the present application. The clock synchronization method according to an embodiment of the present application includes:

[0203] 401. Obtain an offset of a first time slice in a first time slice group and an end time of the first time slice.

[0204] In this embodiment, the processing of the first offset speed and the first offset by the computing device is described as an example. The computing device obtains the offset of the first time slice and the end time of the first time slice from the first time slice group.

[0205] 402. Perform linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line.

[0206] In this embodiment, the computing device calculates a fitted straight line using a linear regression method for the offset of the first time slice and the end time of the first time slice, wherein the end time of the first time slice is an independent variable and the offset of the first time slice is a dependent variable.

[0207] Specifically, the processing of n first time slices is taken as an example for explanation, where n is a positive integer and the nth first time slice is the latest time slice (relative to the n first time slices). Each first time slice can be expressed as: [Ti, Ofi] (i = 0, 1, ..., n), where Ti is the end time of the first time slice and Ofi is the offset of the first time slice.

[0208] First, the average value meanT of the end times of the n first time slices is calculated, and the average value meanOf of the offsets of the n first time slices is calculated.

[0209] Secondly, calculate

[0210]

[0211] Next, calculate the first drift velocity, which is: drift2 = sum1 / sum2;

[0212] Calculate the first offset, which is: offset2 = (meanOf - drift2*meanT) + drift2*Tn.

[0213] 403. Determine a first offset speed and a first offset amount according to the fitted straight line.

[0214] In this embodiment, the slope of the fitting straight line obtained by the computing device is the offset speed of the first time slice (i.e., the first offset speed), and the value of the fitting straight line at the end moment of the first time slice is the offset of the first time slice (i.e., the first offset).

[0215] In the embodiment of the present application, the linear regression method is used to eliminate the transmission error caused by the timestamp error or the jitter of the wireless network in the calculated first offset speed and the first offset. The accuracy of time synchronization is improved. For example, please refer to Figure 4b , Figure 4b This is a schematic diagram of a simulation experiment involved in the embodiment of this application. Figure 4b As shown, the first offset obtained after processing using the linear regression method is relatively smooth, while the first offset not processed using the linear regression method has a larger jitter.

[0216] Based on the above embodiments, the computing device can also use a variety of methods to adjust the first detection clock or the second detection clock. Figure 5 , Figure 5 A clock synchronization method according to an embodiment of the present application is provided as a schematic diagram of another embodiment of the present application. The clock synchronization method according to an embodiment of the present application includes:

[0217] 501. Calculate a plurality of first offset velocities according to a first time slice group.

[0218] In this embodiment, the calculation device first calculates a plurality of first offset speeds according to the first time slice group, wherein each first offset speed corresponds to an offset speed of a first time slice. The specific calculation method is the same as that described above. Figures 4a to 4b The embodiments shown are similar and will not be described again here.

[0219] 502. Calculate a first measurement value according to the multiple first offset velocities.

[0220] In this embodiment, a first measurement value is calculated based on the multiple first offset velocities, and the first measurement value indicates the jitter of the clock in the first time slice group. The first measurement value can be the standard deviation of the multiple first offset velocities, or the variance of the multiple first offset velocities.

[0221] Specifically, the method for calculating the first measurement value in step 502 is similar to the method for calculating the first measurement value in step 302, and will not be repeated here.

[0222] Exemplarily, in step 502 , a first measurement value is calculated according to a plurality of first offset velocities corresponding to N1 first time slices, where N1 is a positive integer.

[0223] 503. Detect whether the first measurement value is less than or equal to a first threshold.

[0224] In this embodiment, the computing device detects whether the first measurement value is less than or equal to a first threshold, where the first threshold is denoted as τ1.

[0225] If the first measurement value is less than or equal to the first threshold, it means that the offset speed of the latest N1 first time slices is stable enough and the clock frequency can be adjusted.

[0226] If the first measurement value is greater than the first threshold, it means that the offset speed of the latest N1 first time slices is unstable and the clock frequency cannot be adjusted.

[0227] 504. Adjust the first clock frequency according to the multiple first offset speeds.

[0228] In this embodiment, the computing device adjusts a first clock frequency based on a plurality of first offset speeds. The first clock frequency is the clock frequency of the first detection clock or the clock frequency of the second detection clock. Specifically, the clock frequency of the first detection clock is adjusted to increase or decrease, or the clock frequency of the second detection clock is adjusted to increase or decrease.

[0229] For example, when the first detection clock is a clock of a computing device (e.g., a mobile phone) and the second detection clock is a clock of another computing device (e.g., a speaker), the computing device can adjust the clock frequency of the first detection clock and the computing device can also adjust the clock frequency of the second detection clock.

[0230] After the first clock frequency is adjusted, the clock frequency changes. Therefore, the first timestamp, the first time slice, and the first offset measured at the original clock frequency are no longer of reference value. The process proceeds to step 507.

[0231] It should be noted that after executing step 504, you can first execute step 505 and then execute step 507; you can also execute step 507 without executing step 505 after executing step 504; after executing step 503, execute step 505 first and then step 504, and finally execute step 507. There is no limitation here.

[0232] In an optional implementation, after step 503, step 505 (adjusting the first clock offset) may be performed first. The specific method is as follows:

[0233] The first time slice includes at least one first sub-time slice, that is, the first sub-time slice includes one or more first timestamps, and the length of the first sub-time slice is less than or equal to the first time slice; when the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value, adjusting the first clock frequency and / or the first clock offset;

[0234] When the product of the time length of the first sub-time slice and the first offset is less than a preset synchronization accuracy value, the first clock offset is adjusted.

[0235] Optionally, assuming that the original clock offset before clock adjustment is d0 and the length of the first sub-time slice is t0, if the clock frequency is not adjusted, the maximum clock offset within the first sub-time slice is d0*t0. If the resulting value of d0*t0 is less than or equal to the preset synchronization accuracy value, then the first clock frequency does not need to be adjusted and only the first offset can be adjusted; however, if the resulting value of d0*t0 is greater than the preset synchronization accuracy value, then the clock frequency and / or the first offset need to be adjusted.

[0236] 505. Adjust the first clock offset according to the first offset.

[0237] In this embodiment, the computing device adjusts the first clock offset according to the first offset, wherein the first offset is determined by the first time slice group, and the first clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock.

[0238] For example, when the first offset indicates that the clock offset between the first detection clock and the second detection clock is 5 microseconds, the first clock offset is determined to be 5 microseconds, and the computing device adjusts the first detection clock or the second detection clock according to the 5 microseconds.

[0239] It should be noted that when step 504 needs to be executed, the execution order of step 504 and step 505 is not limited here.

[0240] 506. Generate a second threshold, and use the second threshold to update the first threshold, wherein the second threshold is greater than the first threshold.

[0241] In this embodiment, after executing step 504, in order to avoid frequent adjustment of the clock frequency causing clock oscillation, the computing device generates a second threshold and uses the second threshold to update the first threshold, where the second threshold is greater than the first threshold.

[0242] Optionally, the computing device may further increase the total number of time slices in the first time slice group to increase the difficulty of adjusting the clock frequency. Specifically, the computing device determines a first total number of time slices, where the first total number of time slices is the total number of first time slices included in the first time slice group; then, the computing device generates a second total number of time slices, where the second total number of time slices is greater than the first total number of time slices; and finally, the computing device obtains the first time slice group based on the second total number of time slices and the plurality of first timestamps.

[0243] 507. Initialize the first timestamp, the first time slice, and the first offset.

[0244] In this embodiment, after executing step 504, i.e., after adjusting the first clock frequency, the clock frequency changes. Therefore, the first timestamp, first time slice, and first offset measured at the original clock frequency are no longer of reference value. The first timestamp, first time slice, and first offset are initialized. Specifically, the first timestamp, first time slice, and first offset are reset to zero.

[0245] 508. Obtain a second time slice group.

[0246] In this embodiment, when the first measurement value is greater than the first threshold, the computing device obtains a second time slice group, where the second time slice group includes multiple first time slices, and the total number of first time slices included in the second time slice group is less than the total number of first time slices included in the first time slice group. Exemplarily, the second time slice group includes N2 first time slices, where N2 is a positive integer and N2 is less than N1.

[0247] 509. Calculate a second measurement value according to the total number of first time slices included in the second time slice group and the first offset speed.

[0248] In this embodiment, a second measurement value is calculated based on the total number of first time slices included in the second time slice group and the first offset speed. The second measurement value indicates the jitter of the clock in the second time slice group.

[0249] The second measurement value is similar to the first measurement value and may be a standard deviation of the plurality of first offset velocities in the second time slice group. The second measurement value may also be a variance of the plurality of first offset velocities in the second time slice group.

[0250] 510. When the second measurement value is less than a third threshold, adjust the second clock offset according to the first offset.

[0251] In this embodiment, when the second measurement value is less than the third threshold, the second clock offset is adjusted according to the first offset, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

[0252] For example, when the first offset indicates that the clock offset between the first detection clock and the second detection clock is 5 microseconds, the first clock offset is determined to be 5 microseconds, and the computing device adjusts the first detection clock or the second detection clock according to the 5 microseconds.

[0253] 511. Get the first timestamp.

[0254] In this embodiment, after the second clock offset is adjusted, the computing device obtains a first timestamp, which is a historical timestamp.

[0255] 512. Generate a second timestamp according to the first offset and the first timestamp.

[0256] In this embodiment, the computing device generates a second timestamp according to the first offset and the first timestamp, wherein the second timestamp is the difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp among the multiple first timestamps.

[0257] In the embodiment of the present application, after adjusting the clock frequency, the historical data (first timestamp, first time slice and first offset) are initialized to prevent invalid historical data from affecting subsequent clock synchronization. After adjusting the clock frequency, the difficulty of adjusting the clock frequency is increased by adjusting the total number of time slices included in the time slice group and adjusting the first threshold (using the second threshold to update the first threshold). Under the premise of ensuring clock synchronization, avoid frequent adjustments to the clock frequency, which may cause clock oscillations. For example, please refer to Figure 6 and Figure 7 , Figure 6 This is another simulation experiment schematic diagram involved in the embodiments of the present application. Figure 7 This is another simulation experiment diagram related to the embodiment of the present application. After adopting the solution proposed in the embodiment of the present application, the detection clock (computing device) eliminates the large jitter in the offset speed and offset in a relatively short period of time.

[0258] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of method. It is understandable that, in order to realize the above functions, the computing device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the modules and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0259] The embodiment of the present application can divide the computing device into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. In actual implementation, there may be other division methods.

[0260] The following is a detailed description of the computing device in this application. Figure 8 , Figure 8 This is a schematic diagram of an embodiment of a computing device in an embodiment of the present application. The computing device 800 includes:

[0261] The transceiver module 801 is configured to obtain a first time slice group, where the first time slice group includes multiple first time slices, each of which includes multiple first timestamps. The first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices have the same portion. The first timestamps include the time when the first detection clock sends a detection signal and the time when the second detection clock receives the detection signal.

[0262] The processing module 802 is configured to adjust the first detection clock or the second detection clock according to the first time slice group.

[0263] In some optional embodiments of the present application,

[0264] A processing module 802 is configured to calculate a plurality of first offset velocities according to the first time slice group, wherein each first offset velocity corresponds to an offset velocity of a first time slice;

[0265] A processing module 802 is configured to calculate a first measurement value based on the plurality of first offset velocities, where the first measurement value indicates a jitter condition of a clock in a first time slice group;

[0266] The processing module 802 is configured to adjust the first detection clock or the second detection clock according to the first measurement value and the first offset speed.

[0267] In some optional embodiments of the present application,

[0268] A processing module 802 is configured to adjust a first clock frequency according to the plurality of first offset speeds, wherein the first clock frequency is a clock frequency of the first detection clock or a clock frequency of the second detection clock;

[0269] and / or,

[0270] The processing module 802 is configured to adjust a first clock offset according to a first offset, wherein the first offset is determined by a first time slice group, and the first clock offset is a clock offset of a first detection clock or a clock offset of a second detection clock.

[0271] In some optional embodiments of the present application,

[0272] A processing module 802 is configured to adjust the first clock frequency and / or the first clock offset when the first time slice includes at least one first sub-time slice and the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value;

[0273] The processing module 802 is configured to adjust the first clock offset when the product of the length of the first sub-time slice and the first offset is less than a preset synchronization accuracy value.

[0274] In some optional embodiments of the present application,

[0275] Processing module 802, configured to generate a second threshold value, where the second threshold value is smaller than the first threshold value;

[0276] The processing module 802 is configured to update the first threshold using the second threshold.

[0277] In some optional embodiments of the present application,

[0278] The processing module 802 is configured to initialize the first timestamp, the first time slice, and the first offset.

[0279] In some optional embodiments of the present application,

[0280] The processing module 802 is further configured to determine a total number of first time slices, where the total number of first time slices is the total number of first time slices included in the first time slice group;

[0281] The processing module 802 is further configured to generate a second total number of time slices, where the second total number of time slices is greater than the first total number of time slices;

[0282] The transceiver module 801 is further configured to obtain a first time slice group according to the total number of second time slices and the plurality of first timestamps.

[0283] In some optional embodiments of the present application,

[0284] The transceiver module 801 is configured to obtain a second time slice group, where the second time slice group includes multiple first time slices, and the total number of first time slices included in the second time slice group is less than the total number of first time slices included in the first time slice group;

[0285] A processing module 802 is configured to calculate a second measurement value according to the total number of first time slices included in the second time slice group and the first offset speed, where the second measurement value indicates a jitter condition of a clock in the second time slice group;

[0286] Processing module 802 is used to adjust the second clock offset according to the first offset when the second measurement value is less than the third threshold, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

[0287] In some optional embodiments of the present application,

[0288] The transceiver module 801 is further configured to obtain a first timestamp;

[0289] The processing module 802 is further configured to generate a second timestamp according to the first offset and the first timestamp, wherein the second timestamp is a difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp.

[0290] In some optional embodiments of the present application,

[0291] The first measurement value is a standard deviation of a plurality of first offset velocities;

[0292] Alternatively, the first measurement value is a variance of a plurality of first offset velocities.

[0293] In some optional embodiments of the present application,

[0294] The transceiver module 801 is further configured to obtain an offset of a first time slice in a first time slice group and an end time of the first time slice;

[0295] The processing module 802 is further configured to perform linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line;

[0296] The processing module 802 is further configured to determine a first offset speed and a first offset amount according to the fitted straight line.

[0297] In some optional embodiments of the present application,

[0298] The first offset velocity is the slope of the fitted line;

[0299] The first offset is the value of the ordinate of the fitting line when the abscissa of the fitting line is the end time of the first time slice.

[0300] In a possible implementation, the transceiver module 801 is used to execute Figure 3a In the corresponding embodiment, steps 301, Figure 4a In the corresponding embodiment, step 401, Figure 5 The corresponding steps are 508 and 511 in the embodiment.

[0301] In a possible implementation, the processing module 802 is configured to execute Figure 3a In the corresponding embodiment, step 303, Figure 4a Steps 402 to 403 in the corresponding embodiment, Figure 5 These correspond to steps 501 to 507, 509 to 510 and 512 in the embodiment.

[0302] It should be noted that the information interaction, execution process, etc. between the modules and components in the computing device 800 are the same as those in the present application. Figures 3a to 5The corresponding method embodiments are based on the same concept. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0303] The computing device in the above embodiment may be an independent computing device, or a chip used in a computing device or other combined devices, components, etc. that can realize the functions of the above computing device. When the computing device is an independent computing device, the transceiver module may be a transceiver, which may include an antenna and a radio frequency circuit, etc., and the processing module may be a processor, such as a baseband chip, etc. When the computing device is a component having the functions of the above computing device, the transceiver module may be a radio frequency unit, and the processing module may be a processor. When the computing device is a chip system, the transceiver module may be the input port and output interface of the chip system, and the processing module may be the processor of the chip system, such as a central processing unit (CPU).

[0304] In the embodiment of the present application, the memory included in the computing device is mainly used to store software programs and data, such as the first time slice group described in the above embodiment. The computing device also has the following functions:

[0305] a transceiver configured to obtain a first time slice group, the first time slice group including a plurality of first time slices, the first time slices including a plurality of first timestamps, wherein the first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially identical, and the first timestamps include a time when the first detection clock sends a detection signal and a time when the second detection clock receives the detection signal;

[0306] The processor is configured to adjust the first detection clock or the second detection clock according to the first time slice group.

[0307] In some optional embodiments of the present application,

[0308] The processor is specifically configured to calculate a plurality of first offset speeds according to the first time slice group, wherein each first offset speed corresponds to an offset speed of a first time slice;

[0309] a processor, specifically configured to calculate a first measurement value based on the plurality of first offset speeds, the first measurement value indicating a jitter condition of a clock in the first time slice group;

[0310] The processor is specifically configured to adjust the first detection clock or the second detection clock according to the first measurement value and the first offset speed.

[0311] In some optional embodiments of the present application,

[0312] The processor is specifically configured to adjust a first clock frequency according to the plurality of first offset speeds, wherein the first clock frequency is a clock frequency of the first detection clock or a clock frequency of the second detection clock;

[0313] and / or,

[0314] The processor is specifically configured to adjust a first clock offset according to a first offset, wherein the first offset is determined by a first time slice group, and the first clock offset is a clock offset of a first detection clock or a clock offset of a second detection clock.

[0315] In some optional embodiments of the present application,

[0316] The processor is specifically configured to adjust the first clock frequency and / or the first clock offset when the first time slice includes at least one first sub-time slice and the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value;

[0317] The processor is specifically configured to adjust the first clock offset when the product of the time length of the first sub-time slice and the first offset is less than a preset synchronization accuracy value.

[0318] In some optional embodiments of the present application,

[0319] a processor, specifically configured to generate a second threshold value, where the second threshold value is smaller than the first threshold value;

[0320] The processor is specifically configured to update the first threshold using the second threshold.

[0321] In some optional embodiments of the present application,

[0322] The processor is specifically configured to initialize the first timestamp, the first time slice, and the first offset.

[0323] In some optional embodiments of the present application,

[0324] The processor is further configured to determine a total number of first time slices, where the total number of first time slices is a total number of first time slices included in the first time slice group;

[0325] The processor is further configured to generate a second total number of time slices, the second total number of time slices being greater than the first total number of time slices;

[0326] The transceiver is further configured to obtain a first time slice group according to the total number of second time slices and the plurality of first timestamps.

[0327] In some optional embodiments of the present application,

[0328] The transceiver is specifically configured to obtain a second time slice group, where the second time slice group includes a plurality of first time slices, and the total number of first time slices included in the second time slice group is less than the total number of first time slices included in the first time slice group;

[0329] a processor, specifically configured to calculate a second measurement value according to the total number of first time slices included in the second time slice group and the first offset speed, wherein the second measurement value indicates a jitter condition of a clock in the second time slice group;

[0330] The processor is specifically used to adjust the second clock offset according to the first offset when the second measurement value is less than the third threshold, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

[0331] In some optional embodiments of the present application,

[0332] The transceiver is further configured to obtain a first timestamp;

[0333] The processor is further configured to generate a second timestamp based on the first offset and the first timestamp, wherein the second timestamp is a difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp.

[0334] In some optional embodiments of the present application,

[0335] The first measurement value is a standard deviation of a plurality of first offset velocities;

[0336] Alternatively, the first measurement value is a variance of a plurality of first offset velocities.

[0337] In some optional embodiments of the present application,

[0338] The transceiver is further configured to obtain an offset of a first time slice in the first time slice group and an end time of the first time slice;

[0339] The processor is further configured to perform linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line;

[0340] The processor is further configured to determine a first offset speed and a first offset amount according to the fitted straight line.

[0341] In some optional embodiments of the present application,

[0342] The first offset velocity is the slope of the fitted line;

[0343] The first offset is the value of the ordinate of the fitting line when the abscissa of the fitting line is the end time of the first time slice.

[0344] In one possible implementation, the transceiver is configured to perform Figure 3a In the corresponding embodiment, steps 301, Figure 4a In the corresponding embodiment, step 401, Figure 5 The corresponding steps are 508 and 511 in the embodiment.

[0345] In one possible implementation, the processor is configured to execute Figure 3a In the corresponding embodiment, step 303, Figure 4a Steps 402 to 403 in the corresponding embodiment, Figure 5 These correspond to steps 501 to 507, 509 to 510 and 512 in the embodiment.

[0346] It should be noted that the information interaction, execution process, etc. between the modules and components of the computing device are different from those in this application. Figure 3a-Figure 5 The corresponding method embodiments are based on the same concept. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0347] It should be noted that for the specific implementation of the computing device and the beneficial effects it brings, please refer to Figure 3a-Figure 5 The descriptions in the corresponding method embodiments will not be repeated here one by one.

[0348] An embodiment of the present application further provides a processing device, which includes a processor and an interface; the processor is used to execute the clock synchronization method of any of the above method embodiments.

[0349] It should be understood that the above-mentioned processing device can be a chip, and the processor can be implemented by hardware or by software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor can be a general-purpose processor, which is implemented by reading the software code stored in the memory. The memory can be integrated into the processor or can be located outside the processor and exist independently.

[0350] Here, "implemented through hardware" means that the functions of the aforementioned modules or units are realized through hardware processing circuits that do not have program instruction processing capabilities. This hardware processing circuit can be composed of discrete hardware components or integrated circuits. To reduce power consumption and size, it is often implemented in the form of integrated circuits. Hardware processing circuits can include ASICs (application-specific integrated circuits) or PLDs (programmable logic devices); PLDs can include FPGAs (field programmable gate arrays) and CPLDs (complex programmable logic devices). These hardware processing circuits can be individually packaged as a semiconductor chip (such as an ASIC) or integrated with other circuits (such as a CPU or DSP) to form a single semiconductor chip. For example, multiple hardware circuits and a CPU can be formed on a silicon substrate and packaged as a single chip, which is also called an SoC. Alternatively, circuits for implementing FPGA functions and a CPU can be formed on a silicon substrate and packaged as a single chip, which is also called a SoPC (system on a programmable chip).

[0351] An embodiment of the present application also provides a computer-readable storage medium, comprising instructions, which, when executed on a computer, enables the computer to control a computing device to execute any one of the implementation methods shown in the aforementioned method embodiments.

[0352] An embodiment of the present application also provides a computer program product, which includes computer program code. When the computer program code runs on a computer, it enables the computer to execute any one of the implementation methods shown in the aforementioned method embodiments.

[0353] An embodiment of the present application also provides a chip system, including a memory and a processor, the memory is used to store computer programs, and the processor is used to call and run computer programs from the memory, so that the chip executes any one of the implementation methods shown in the aforementioned method embodiments.

[0354] An embodiment of the present application also provides a chip system, including a processor, which is used to call and run a computer program so that the chip executes any one of the implementation methods shown in the aforementioned method embodiments.

[0355] It should also be noted that the device embodiments described above are merely illustrative, in which the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0356] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general-purpose hardware, and of course can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be diverse, such as analog circuits, digital circuits, or dedicated circuits. However, for the present application, software program implementation is a better implementation method in most cases. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a number of instructions for enabling a computer device to execute the methods of each embodiment of the present application.

[0357] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0358] A computer program product includes one or more computer instructions. When a computer program instruction is loaded and executed on a computer, a process or function according to an embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instruction may be transmitted from a website, a computer, a computing device, or a data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website, a computer, a computing device, or a data center. The computer-readable storage medium may be any available medium that a computer can store or a computing device, a data center, or other data storage device that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0359] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0360] Additionally, the terms "system" and "network" are often used interchangeably herein.

[0361] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0362] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0363] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0364] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0365] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0366] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application.

[0367] In short, the above description is only a preferred embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included in the scope of protection of this application.

Claims

1. A clock synchronization method, characterized in that: include: Obtain a first time slice group, where the first time slice group includes multiple first time slices, each of the first time slices includes multiple first timestamps, wherein the first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially identical, and the first timestamps include a time when a first detection clock sends a detection signal and a time when a second detection clock receives the detection signal; The first detection clock or the second detection clock is adjusted according to the first time slice group.

2. The method according to claim 1, characterized in that Adjusting the first detection clock or the second detection clock according to the first time slice group includes: Calculating a plurality of first offset velocities according to the first time slice group, wherein the first offset velocities correspond one-to-one to the offset velocities corresponding to the first time slices; Calculating a first measurement value based on the multiple first offset speeds, where the first measurement value indicates a jitter condition of a clock in the first time slice group; The first detection clock or the second detection clock is adjusted according to the first measurement value and the first offset speed.

3. The method according to claim 2, characterized in that When the first measurement value is less than a first threshold, adjusting the first detection clock or the second detection clock includes: adjusting a first clock frequency according to the plurality of first offset speeds, wherein the first clock frequency is a clock frequency of the first detection clock or a clock frequency of the second detection clock; and / or, The first clock offset is adjusted according to the first offset, wherein the first offset is determined by the first time slice group, and the first clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock.

4. The method according to claim 3, characterized in that Before adjusting the first detection clock or the second detection clock, the method further includes: The first time slice includes at least one first sub-time slice; When the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value, adjusting the first clock frequency and / or the first clock offset; When the product of the time length of the first sub-time slice and the first offset is less than the preset synchronization accuracy value, the first clock offset is adjusted.

5. The method according to claim 3, characterized in that After adjusting the first clock frequency according to the multiple first offset speeds, the method further includes: generating a second threshold value, wherein the second threshold value is smaller than the first threshold value; The first threshold is updated using the second threshold.

6. The method according to claim 3, characterized in that After adjusting the first clock frequency according to the multiple first offset speeds, the method further includes: Initialize the first timestamp, the first time slice, and the first offset.

7. The method according to claim 3, characterized in that After adjusting the first clock frequency according to the multiple first offset speeds, the method further includes: Determine a total number of first time slices, where the total number of the first time slices is the total number of the first time slices included in the first time slice group; generating a second total number of time slices, wherein the second total number of time slices is greater than the first total number of time slices; The first time slice group is acquired according to the total number of the second time slices and the multiple first timestamps.

8. The method according to claim 3, characterized in that When the first measurement value is greater than the first threshold, adjusting the first detection clock or the second detection clock includes: Acquire a second time slice group, where the second time slice group includes multiple first time slices, and the total number of the first time slices included in the second time slice group is less than the total number of the first time slices included in the first time slice group; Calculating a second measurement value based on the total number of the first time slices included in the second time slice group and the first offset speed, wherein the second measurement value indicates jitter of the clock in the second time slice group; When the second measurement value is less than a third threshold, the second clock offset is adjusted according to the first offset, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

9. The method according to claim 8, characterized in that After adjusting the second clock offset according to the first offset, the method further includes: Obtaining the first timestamp; A second timestamp is generated according to the first offset and the first timestamp, wherein the second timestamp is a difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp.

10. The method according to any one of claims 2 to 9, characterized in that The first measurement value is a standard deviation of the plurality of first offset velocities; Alternatively, the first measurement value is the variance of the plurality of first offset velocities.

11. The method according to any one of claims 3 to 9, characterized in that Calculating the plurality of first offset velocities according to the first time slice group includes: Obtaining an offset of the first time slice in the first time slice group and an end time of the first time slice; Performing linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line; The first offset speed and the first offset amount are determined according to the fitting straight line.

12. The method according to claim 11, characterized in that The first offset velocity is the slope of the fitting straight line; The first offset is the value of the ordinate of the fitting straight line when the abscissa of the fitting straight line is the end time of the first time slice.

13. A computing device, characterized in that include: a transceiver module, configured to obtain a first time slice group, where the first time slice group includes multiple first time slices, each of the first time slices includes multiple first timestamps, wherein the first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially identical, and the first timestamps include a time when a first detection clock sends a detection signal and a time when a second detection clock receives the detection signal; A processing module is configured to adjust the first detection clock or the second detection clock according to the first time slice group.

14. The computing device according to claim 13, wherein: The processing module is configured to calculate a plurality of first offset velocities based on the first time slice group, wherein the first offset velocities correspond one-to-one to the offset velocities corresponding to the first time slices; The processing module is configured to calculate a first measurement value based on the multiple first offset speeds, where the first measurement value indicates a jitter condition of a clock in the first time slice group; The processing module is configured to adjust the first detection clock or the second detection clock according to the first measurement value and the first offset speed.

15. The computing device according to claim 14, wherein: The processing module is configured to adjust a first clock frequency according to the multiple first offset velocities when the first measurement value is less than a first threshold, wherein the first clock frequency is the clock frequency of the first detection clock or the clock frequency of the second detection clock; and / or, The processing module is used to adjust the first clock offset according to the first offset, wherein the first offset is determined by the first time slice group, and the first clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock.

16. The computing device according to claim 15, characterized in that the processing module being configured to adjust the first clock frequency and / or the first clock offset if the first time slice includes at least one first sub-time slice and the product of the time length of the first sub-time slice and the first offset is greater than or equal to a preset synchronization accuracy value; The processing module is configured to adjust the first clock offset when the product of the time length of the first sub-time slice and the first offset is less than the preset synchronization accuracy value.

17. The computing device according to claim 15, wherein: The processing module is configured to generate a second threshold value, where the second threshold value is smaller than the first threshold value; The processing module is configured to update the first threshold using the second threshold.

18. The computing device according to claim 15, wherein: The processing module is configured to perform initialization processing on the first timestamp, the first time slice, and the first offset.

19. The computing device according to claim 15, wherein: The processing module is further configured to determine a total number of first time slices, where the total number of first time slices is the total number of first time slices included in the first time slice group; The processing module is further configured to generate a second total number of time slices, where the second total number of time slices is greater than the first total number of time slices; The transceiver module is further configured to obtain the first time slice group according to the total number of the second time slices and the multiple first timestamps.

20. The computing device of claim 15, wherein: The transceiver module is configured to obtain a second time slice group, where the second time slice group includes a plurality of the first time slices, and the total number of the first time slices included in the second time slice group is less than the total number of the first time slices included in the first time slice group; The processing module is configured to calculate a second measurement value according to the total number of the first time slices included in the second time slice group and the first offset speed, wherein the second measurement value indicates a jitter condition of a clock in the second time slice group; The processing module is used to adjust the second clock offset according to the first offset when the second measurement value is less than a third threshold, wherein the second clock offset is the clock offset of the first detection clock, or the clock offset of the second detection clock, and the third threshold is greater than the first threshold.

21. The computing device of claim 20, wherein: The transceiver module is further configured to obtain the first timestamp; The processing module is further configured to generate a second timestamp based on the first offset and the first timestamp, wherein the second timestamp is a difference between the first timestamp and the first offset, and the second timestamp is used to update the first timestamp.

22. The computing device according to any one of claims 14 to 21, characterized in that The first measurement value is a standard deviation of the plurality of first offset velocities; Alternatively, the first measurement value is the variance of the plurality of first offset velocities.

23. The computing device according to any one of claims 15 to 21, characterized in that The transceiver module is further configured to obtain an offset of the first time slice in the first time slice group and an end time of the first time slice; The processing module is further configured to perform linear regression processing on the offset of the first time slice in the first time slice group and the end time of the first time slice to obtain a fitting straight line; The processing module is further configured to determine the first offset speed and the first offset amount according to the fitting straight line.

24. The computing device of claim 23, wherein: The first offset velocity is the slope of the fitting straight line; The first offset is the value of the ordinate of the fitting straight line when the abscissa of the fitting straight line is the end time of the first time slice.

25. A computing device, characterized in that include: a processor and a transceiver connected to the processor; The processor is configured to execute a program code stored in a memory, and when the program code is executed, causes the computing device to perform the method according to any one of claims 1 to 12.

26. The computing device of claim 25, wherein: The system further comprises a memory for storing the program code, wherein the memory is configured to transmit the program code to the processor.

27. A computer-readable storage medium, characterized in that The computer-readable storage medium has program instructions, and when the program instructions are directly or indirectly executed, the method according to any one of claims 1 to 12 is executed.

28. A chip system, characterized in that: The chip system includes one or more processors and a memory, wherein the memory stores program instructions. When the program instructions are executed in the one or more processors, the method according to any one of claims 1 to 12 is executed.

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