Detection circuit and wake-up method

Abstract

The present disclosure relates to a detection circuit and a wake-up method. A detection circuit and a wake-up method are disclosed. The detection circuit is applied in a high-definition multimedia interface (HDMI) receiver after entering a power saving mode in a fixed rate link (FRL) mode to detect whether a HDMI transmitter starts to transmit a video packet through the FRL link. The detection circuit includes a signal detection circuit and a FRL packet judgment circuit. The signal detection circuit detects whether there is a signal on the FRL link. If there is, it means that there is a FRL packet on the FRL link. Then, according to the variable value characteristics of the video packet and / or the fixed value characteristics of the gap packet, the FRL packet judgment circuit judges whether the FRL packet is a video packet. If it is, the FRL packet judgment circuit wakes up the HDMI receiver from the power saving mode to parse the video packet and display the video.

Description

TECHNICAL FIELD

[0001] The present application relates to a detection circuit and a wake-up method, in particular, to a detection circuit and a wake-up method suitable for a High Definition Multimedia Interface (HDMI) receiver in a Fixed Rate Link (FRL) mode entering a power saving mode. BACKGROUND

[0002] The FRL mode is a new transmission mode defined by the HDMI 2.1 specification, and before entering the FRL mode, the HDMI transmitter and the HDMI receiver (or Source and Sink) must first perform link training to confirm the maximum transmission bandwidth between each other. After link training, the HDMI transmitter and the HDMI receiver can be in the FRL link state. Then, before transmitting image packets, the HDMI transmitter will first transmit gap packets so that the HDMI transmitter can prepare image data during this time. However, the length of time for transmitting gap packets depends on the time for the HDMI transmitter to prepare image data, and in order not to miss image data, the HDMI receiver can maintain the FRL link state and wait for the HDMI transmitter to transmit image packets.

[0003] In addition, since the gap packets do not carry image data, when the HDMI receiver has no image to display, in order to avoid consuming unnecessary power consumption, the HDMI receiver can also define a period of time after receiving no image packets, and then disconnect the FRL link and enter the power saving mode, but this will cause the following problems. 1. If the HDMI transmitter takes too long to prepare image data, and sends out image packets when the HDMI receiver has already entered the power saving mode, the HDMI receiver will not be able to distinguish the image packets transmitted by the HDMI transmitter because the FRL link has been disconnected, so that the HDMI receiver will miss the image data and cannot display the image.

[0004] 2. HDMI receiver also stops sending back status to HDMI transmitter in power saving mode, such as SCDC (Status and Control Data Channel) and EDID (Enhanced Display Identification Data) update, and the HPD (Hot Plug Detect) pin will not be pulled low because the cable is still connected, so the HDMI transmitter has no way to know that the HDMI receiver has disconnected the FRL link. Therefore, the HDMI transmitter will continue to transmit image packets and will not re-perform link training to restart the FRL link. As can be seen, unless the cable is unplugged, the HDMI receiver will not be able to receive image packets and display images again after it is awakened because its receiving interface circuit has already returned to the initial state (i.e., the set parameters are lost). In order to overcome the above problems, the HDMI receiver needs a mechanism that can automatically wake up and display images by detecting whether the HDMI transmitter starts transmitting image packets after entering the power saving mode. SUMMARY

[0005] Therefore, embodiments of the present application provide a detection circuit suitable for use in an HDMI receiver that enters a power saving mode in FRL mode to detect whether the HDMI transmitter starts transmitting image packets through the FRL link, and the detection circuit includes a signal detection circuit and an FRL packet judgment circuit. The signal detection circuit detects whether there is a signal on the FRL link. If there is, it means that there is an FRL packet on the FRL link. Then, according to the variable value characteristics of the image packet and / or the fixed value characteristics of the gap packet, the FRL packet judgment circuit judges whether the FRL packet is an image packet. If not, the HDMI receiver remains in the power saving mode. If so, the FRL packet judgment circuit wakes up the HDMI receiver from the power saving mode to parse the image packet and display the image.

[0006] In addition, embodiments of the present application provide a wake-up method suitable for use in an HDMI receiver that enters a power saving mode in FRL mode. After entering the power saving mode, the HDMI receiver turns off the main circuit responsible for parsing the image packet and displaying the image, and the wake-up method includes the following steps. First, using the signal detection circuit, it is detected whether there is a signal on the FRL link. If there is, it means that there is an FRL packet on the FRL link. Then, using the FRL packet judgment circuit, it is judged whether the FRL packet is an image packet according to the variable value characteristics of the image packet and / or the fixed value characteristics of the gap packet. If not, return to the step of using the signal detection circuit to detect whether there is a signal on the FRL link. If so, using the FRL packet judgment circuit, wake up the HDMI receiver from the power saving mode so that the main circuit is turned on to parse the image packet and display the image.

[0007] For further understanding of the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings provided are only for reference and illustration, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of the detection circuit provided by an embodiment of the present application.

[0009] Figure 2 is a circuit schematic diagram of the signal detection circuit in Figure 1

[0010] Figure 3 is a schematic diagram of the FRL transmission rate judgment circuit in the detection circuit of Figure 1

[0011] Figure 4 is a schematic diagram of the character difference in the gap packet and the image packet.

[0012] Figure 5 is a step flow chart of the wake-up method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following is to illustrate the embodiments of the present application through specific embodiments. The advantages and effects of the present application can be understood by the person skilled in the art from the content provided in the present specification. The present application can be implemented or applied through other different embodiments, and each detail in the present specification can be modified and changed based on different viewpoints and applications without departing from the concept of the present application. In addition, the drawings of the present application are only simple schematic illustrations, and are not intended to depict the actual size. The following embodiments will further illustrate the related technical content of the present application, but the content provided is not intended to limit the protection scope of the present application.

[0014] It should be understood that although the terms of "first", "second", "third" and the like can be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another element, or one signal from another signal. In addition, the term "or" used herein can include any one or more combinations of the associated listed items as appropriate.

[0015] ​​It is noted that the present application does not limit the specific condition for the HDMI receiver to enter the power saving mode in the FRL mode. For example, when the HDMI transmitter takes too long to prepare the image data, the HDMI receiver can enter the power saving mode. Please refer to Figure 1 , Figure 1 is a block diagram of the detection circuit provided by the embodiment of the present application. The detection circuit 12 is applied in the HDMI receiver 1 after entering the power saving mode in the FRL mode, to detect whether the HDMI transmitter 2 starts to transmit the image packet through the FRL link 3 (i.e. the transmission channel), and the detection circuit 12 comprises a signal detection circuit 120, an FRL transmission rate judgment circuit 122 and an FRL packet judgment circuit 124.

[0016] The signal detection circuit 120, the FRL transmission rate judgment circuit 122 and the FRL packet judgment circuit 124 can be realized by pure hardware, or by hardware combined with firmware or software. In addition, the signal detection circuit 120, the FRL transmission rate judgment circuit 122 and the FRL packet judgment circuit 124 can be integrated or separately arranged. In summary, the present application also does not limit the specific implementation mode of the detection circuit 12. In the embodiment, the signal detection circuit 120 detects whether there is a signal on the FRL link 3. If yes, it means that there is the FRL packet on the FRL link 3.

[0017] Secondly, according to the conversion density of the aforementioned signal in a time interval, the FRL transmission rate judgment circuit 122 can judge the transmission rate on the FRL link 3. Because in the power saving mode, the receiving interface circuit (not shown) of the HDMI receiver 1 also stops receiving the signal and returns to the initial state, in order to correctly receive and analyze the signal on the FRL link 3, the HDMI receiver 1 must re-set the parameters of the receiving interface circuit according to the transmission rate judged by the FRL transmission rate judgment circuit 122, to successfully convert the signal on the FRL link 3 into the signal that can be analyzed by the HDMI receiver 1. Figure 1

[0018] Then, according to the variable value characteristics of the image packet and / or the fixed value characteristics of the gap packet, the FRL packet judgment circuit 124 can judge whether the aforementioned FRL packet is the image packet. If not, it means that the HDMI transmitter 2 is still preparing the image data, so the HDMI receiver 1 maintains in the power saving mode. If yes, it means that the HDMI transmitter 2 starts to transmit the image packet through the FRL link 3, so the FRL packet judgment circuit 124 wakes up the HDMI receiver 1 from the power saving mode, to analyze the image packet and display the image.

[0019] ​Specifically, the signal detection circuit 120 can periodically detect whether a signal is present on the FRL link 3. If a signal is present, it indicates that a video packet is likely present on the FRL link 3. If not, the HDMI receiver 1 remains in power saving mode and awaits the next detection by the signal detection circuit 120. Furthermore, because HDMI is a high-speed differential signal, the signal detection circuit 120 can determine whether a signal is present on the FRL link 3 by determining whether the magnitude of the differential signal input from the FRL link 3 exceeds a voltage range between an upper voltage limit of +Vth and a lower voltage limit of -Vth.

[0020] Please also refer to Figure 2 , Figure 2 yes Figure 1 The circuit diagram of the signal detection circuit 120 is shown in FIG. Figure 2 As shown, the signal detection circuit 120 may include a comparator 1201. The first non-inverting input and the first inverting input of the comparator 1201 receive a differential signal input from the FRL link 3. The second non-inverting input and the second inverting input of the comparator 1201 receive an upper voltage limit +Vth and a lower voltage limit -Vth, respectively. When the magnitude of the differential signal exceeds the upper voltage limit +Vth or falls below the lower voltage limit -Vth, the comparator 1201 determines that a signal is present on the FRL link 3. Furthermore, the transmission rate on the FRL link 3 can range from 3 Gbps to 12 Gbps. Therefore, the HDMI receiver 1 must use an FRL transmission rate determination circuit 122 to determine the transmission rate on the FRL link 3. This allows the HDMI receiver 1 to configure its receiving interface circuit according to the transmission rate to receive data.

[0021] Please also refer to Figure 3 , Figure 3 yes Figure 1 Schematic diagram of the FRL transmission rate determination circuit 122 determining the transmission rate based on the signal's transition density within a time interval T. It should be understood that the data encoding scheme for FRL packets is 16b / 18b, which converts 16 bits to 18 bits through a lookup table. The converted 18 bits have a DC balance characteristic, meaning the number of 0s and 1s is equal. Therefore, based on this encoding scheme, this embodiment can infer that within the same time interval T, a signal with a higher transmission rate will have a higher transition density.

[0022] For example, the number of potential transitions of a signal using 6 Gbps in the same time interval T will be twice the number of potential transitions of a signal using 3 Gbps. Therefore, if the FRL transmission rate determination circuit 122 can first know that the number of potential transitions of a signal using 3 Gbps is 12 in the same time interval T, then the calculated number of potential transitions of 24 indicates that the transmission rate on the FRL link 3 is 6 Gbps. In summary, the number of potential transitions described above is only an example and is not intended to limit the present application. In addition, please refer to Figure 4 , Figure 4 is a schematic diagram of the difference between the gap packet and the image packet.

[0023] For the convenience of explanation, Figure 4 The symbols "SR", "GAP", "Video", and "Parity" represent the Scrambler Reset character, the gap character, the video character, and the parity character of the Forward Error Correction (FEC), respectively. The Start Super Block character and the Scrambler Reset character are both comma characters (Comma Characters) that can be used to achieve character alignment, and the Start Super Block character is denoted as "SSB" in this article, but Figure 4 only the Scrambler Reset character is used as an example. According to the HDMI 2.1 specification, the gap packet is composed of three characters: "SR / SSB", "GAP", and "Parity". In addition to the first two characters being constant values, the parity character calculated by the FEC for the gap character is also a constant value. In addition, after being dispersed and 16b / 18b encoded, the three characters of the gap packet will be converted into fixed cyclic constant values. In contrast, the video character in the video packet will be a variable value according to the video content, and the parity character calculated by the FEC for the video character will also be a variable value, and will still be a variable value after being dispersed and 16b / 18b encoded. Therefore, by distinguishing these characteristics, the FRL packet determination circuit 124 can determine whether the FRL packet is a video packet without needing to parse the content of the FRL packet.

[0024] For example, the FRL packet judging circuit 124 can identify whether the characters in the current FRL packet are variable values or not. When the characters are not variable values, the FRL packet judging circuit 124 can determine that the current FRL packet is not a video packet, and thus the HDMI receiver 1 remains in the power saving mode. Alternatively, when the characters are variable values, the FRL packet judging circuit 124 can determine that the current FRL packet is a video packet, and thus the FRL packet judging circuit 124 wakes up the HDMI receiver 1 to display the video. Alternatively, the FRL packet judging circuit 124 can identify whether the characters in the current FRL packet are fixed cyclic constant values or not. When the characters are fixed cyclic constant values, the FRL packet judging circuit 124 can determine that the current FRL packet is not a video packet but a gap packet, and thus the HDMI receiver 1 remains in the power saving mode. Alternatively, when the characters are not fixed cyclic constant values, the FRL packet judging circuit 124 can determine that the current FRL packet is a video packet, and thus the FRL packet judging circuit 124 wakes up the HDMI receiver 1 to display the video.

[0025] Similarly, the FRL packet judging circuit 124 can identify whether the characters in the current FRL packet are variable values or fixed cyclic constant values. When the characters are fixed cyclic constant values, the FRL packet judging circuit 124 can determine that the current FRL packet is not a video packet but a gap packet, and thus the HDMI receiver 1 remains in the power saving mode. Alternatively, when the characters are variable values, the FRL packet judging circuit 124 can determine that the current FRL packet is a video packet, and thus the FRL packet judging circuit 124 wakes up the HDMI receiver 1 to display the video. In summary, the present application does not limit the specific implementation of the FRL packet judging circuit 124 to determine whether the FRL packet is a video packet based on the variable value characteristics of the video packet and / or the constant value characteristics of the gap packet, and those skilled in the art should be able to design according to actual needs or applications. In addition, since this identification method only requires a simple numerical verification circuit, the area and cost of the FRL packet judging circuit 124 can be greatly reduced, and the power consumption of the detection circuit 12 in the power saving mode to detect whether the HDMI transmitter 2 starts to transmit the video packet through the FRL link 3 can be reduced.

[0026] However, the main circuit 10 of the HDMI receiver 1 responsible for parsing the video packets and displaying the video consumes up to hundreds of milliwatts, but the general power saving mode requires power consumption to be only tens of milliwatts, so after entering the power saving mode, the HDMI receiver 1 turns off the main circuit 10 to save power consumption. In addition, in order to detect whether the HDMI transmitter 2 starts to transmit video packets without consuming a large amount of power consumption in the power saving mode, the present application can further separate the power domain D1 of the detection circuit 12 from the power domain D2 of the main circuit 10, so that after entering the power saving mode, the HDMI receiver 1 turns off the power domain D2 of the main circuit 10 to save power consumption, and only turns on the power domain D1 of the detection circuit 12 to detect whether the HDMI transmitter 2 starts to transmit video packets through the FRL link 3.

[0027] Finally, please refer to Figure 5 , Figure 5 is a step flow chart of the wake-up method provided by the embodiment of the present application. Since the detailed step flow has been described as described above, only a summary is made here without further elaboration. As shown in Figure 5 , in step S510 after entering the power saving mode, the HDMI receiver 1 turns off the main circuit 10 responsible for parsing the video packets and displaying the video to save power consumption, and in step S520, the signal detection circuit 120 is used to detect whether there is a signal on the FRL link 3. If not, return to step S520. If there is, it means that there is an FRL packet on the FRL link 3, so the HDMI receiver 1 will perform step S530 to use the FRL transmission rate judgment circuit 122 to judge the transmission rate on the FRL link 3 according to the conversion density of the aforementioned signal in a time interval T. In addition, the HDMI receiver 1 must also reset the parameters of the receiving interface circuit according to the transmission rate judged by the FRL transmission rate judgment circuit 122, so as to successfully convert the signal on the FRL link 3 into a signal that the HDMI receiver 1 can parse.

[0028] As mentioned previously, since the signal detection circuit 120 can detect whether there is a signal on the FRL link 3 every certain period of time, the HDMI receiver 1 will wait for the next detection of the signal detection circuit 120 in step S520. Then, in step S540, the FRL packet judgment circuit 124 judges whether the aforementioned FRL packet is an image packet according to the variable value characteristics of the image packet and / or the fixed value characteristics of the gap packet. If not, it means that the HDMI transmitter 2 is still preparing image data, so the HDMI receiver 1 can return to step S520 to wait for the next detection of the signal detection circuit 120. If yes, it means that the HDMI transmitter 2 starts to transmit image packets through the FRL link 3, so the HDMI receiver 1 can execute step S550 to wake up the HDMI receiver 1 from the power saving mode by the FRL packet judgment circuit 124, so that the main circuit 10 is turned on to parse the image packet and display the image.

[0029] It is noted that since the present application does not limit the specific condition of the HDMI receiver 1 entering the power saving mode in the FRL mode, and the FRL packet judgment circuit 124 can also identify the gap packet according to the multiple fixed values of the multiple characters in the current FRL packet, other embodiments can also use the detection circuit 12 to distinguish whether the received packet is a gap packet or an image packet after the link training. When the received packet is identified as a gap packet, the HDMI receiver 1 can enter the power saving mode, and when the received packet is identified as an image packet, the HDMI receiver 1 can exit the power saving mode, i.e., wake up the HDMI receiver 1 to parse the image packet and display the image. Since the details of the detection circuit 12 have been described as mentioned above, they will not be described here.

[0030] In summary, the embodiments of the present application provide a detection circuit and a wake-up method, which are suitable for the HDMI receiver entering the power saving mode in the FRL mode, to automatically wake up the HDMI receiver by detecting whether the HDMI transmitter starts to transmit image packets. The detection circuit and the wake-up method are not too complex, so they can not only reduce the circuit area and cost, but also save power consumption without losing the purpose of the HDMI receiver entering the power saving mode.

[0031] The above provided content is only the preferred feasible embodiments of the present application, and does not limit the patent application scope of the present application, so any equivalent technical changes made according to the content of the present application specification and drawings are included in the patent application scope of the present application.

[0032]

Symbol Description

[0033] 1: HDMI receiver

[0034] 10: Main circuit

[0035] 12: detection circuit

[0036] 120: signal detection circuit

[0037] 1201: comparator

[0038] +Vth: upper limit voltage

[0039] -Vth: lower limit voltage

[0040] 122: FRL transmission rate determination circuit

[0041] 124: FRL packet determination circuit

[0042] D1, D2: power supply area

[0043] 2: HDMI transmitter

[0044] 3: FRL link

[0045] T: time interval

[0046] SR: scrambling reset character

[0047] GAP: gap character

[0048] Video: video character

[0049] Parity: parity character

[0050] S510-S550: flow steps

Claims

1. A detection circuit for use in a high definition multimedia interface (HDMI) receiver entering a power saving mode in a fixed rate link (FRL) mode to detect whether a HDMI transmitter has started transmitting video packets over a FRL link, the detection circuit comprising: a signal detection circuit to detect whether a signal is present on the FRL link, and if so, to indicate that a FRL packet is present on the FRL link; a FRL packet determination circuit to determine whether the FRL packet is a video packet based on variable value characteristics of the video packet and / or constant value characteristics of a gap packet; if not, the HDMI receiver remains in the power saving mode; and if so, the FRL packet determination circuit wakes up the HDMI receiver from the power saving mode to parse the video packet and display video.

2. The detection circuit of claim 1, further comprising: a FRL transmission rate determination circuit to determine a transmission rate on the FRL link based on a transition density of the signal over a time interval.

3. The detection circuit of claim 2, wherein the HDMI receiver must reconfigure parameters of a receive interface circuit based on the transmission rate determined by the FRL transmission rate determination circuit to successfully convert the signal on the FRL link to a signal that the HDMI receiver can parse.

4. The detection circuit of claim 1, wherein the signal detection circuit detects whether the signal is present on the FRL link every so often; if so, it indicates that the video packet is likely present on the FRL link; if not, the HDMI receiver remains in the power saving mode and waits for the next detection by the signal detection circuit.

5. The detection circuit of claim 1, wherein the signal detection circuit determines whether the signal is present on the FRL link by determining whether a magnitude of a differential signal input from the FRL link exceeds a voltage range between an upper voltage limit and a lower voltage limit.

6. The detection circuit of claim 5, wherein the signal detection circuit comprises: a comparator having a first non-inverting input and a first inverting input to receive the differential signal input from the FRL link, and a second non-inverting input and a second inverting input to receive the upper voltage limit and the lower voltage limit, respectively, such that when the magnitude of the differential signal is above the upper voltage limit or below the lower voltage limit, the comparator determines that the signal is present on the FRL link.

7. The detection circuit of claim 1, wherein the FRL packet determination circuit determines whether the FRL packet is the video packet based on the variable value characteristics of the video packet and / or the constant value characteristics of the gap packet by: identifying whether a plurality of characters within the FRL packet are a plurality of variable values; when the characters are not the variable values, the FRL packet determination circuit determines that the FRL packet is not the video packet; and when the characters are the variable values, the FRL packet determination circuit determines that the FRL packet is the video packet. ​ ​ ​ 8. The detection circuit of claim 1, wherein the FRL packet judging circuit judges whether the FRL packet is the video packet according to the variable value characteristic of the video packet and / or the constant value characteristic of the gap packet, and the judging comprises: identifying whether the characters in the FRL packet are constant cyclic constant values; when the characters are the constant cyclic constant values, the FRL packet judging circuit judges that the FRL packet is not the video packet; and when the characters are not the constant cyclic constant values, the FRL packet judging circuit judges that the FRL packet is the video packet.

9. The detection circuit of claim 1, wherein the FRL packet judging circuit judges whether the FRL packet is the video packet according to the variable value characteristic of the video packet and / or the constant value characteristic of the gap packet, and the judging comprises: identifying whether the characters in the FRL packet are variable values or constant cyclic constant values; when the characters are the constant cyclic constant values, the FRL packet judging circuit judges that the FRL packet is not the video packet; and when the characters are the variable values, the FRL packet judging circuit judges that the FRL packet is the video packet.

10. A wake-up method for a HDMI receiver in a FRL mode, wherein after entering the power saving mode, the HDMI receiver turns off a main circuit responsible for parsing a video packet and displaying a video, and the wake-up method comprises: using a signal detection circuit to detect whether there is a signal on a FRL link, and if there is, it indicates that there is a FRL packet on the FRL link; using a FRL packet judging circuit to judge whether the FRL packet is the video packet according to the variable value characteristic of the video packet and / or the constant value characteristic of the gap packet; if not, returning to using the signal detection circuit to detect whether there is the signal on the FRL link; and if yes, using the FRL packet judging circuit to wake up the HDMI receiver from the power saving mode, so that the main circuit is turned on to parse the video packet and display the video.

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