Hardware-implemented serial communication high dynamic range baud rate identification method and circuit

Abstract

The application provides a kind of hardware implemented serial communication high dynamic range baud rate identification method and circuit, the serial communication high dynamic range baud rate identification method and circuit include the following steps: the baud rate of the header is collected by baud rate collection circuit;According to the baud rate collected, the data of each bit of the header is accurately identified by bit data collection circuit;The width between adjacent edges in the header is timed and judged by single-bit duration detection circuit.The beneficial effects of the application are: (1) the identification range of baud rate can be greatly improved by midpoint sampling mechanism, and the correctness of the collected data is effectively guaranteed;(2) once the baud rate error is detected, the entire identification circuit will be reset immediately, so after detecting the error baud rate, it can quickly recover to the initial state to detect the next correct bit rate header in time, improving the robustness of the entire baud rate identification circuit;(3) as software execution is not required, the bandwidth of CPU can be released for use by other peripherals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of fast charging of mobile terminal equipment, in particular to a hardware- implemented serial communication high dynamic range baud rate identification method and circuit. BACKGROUND

[0002] In order to realize fast charging of mobile terminal equipment, many fast charging protocols have appeared. The fast charging protocol is usually a serial bus with UART as the basic frame structure. The sending end selects a baud rate to send data, and a preset character is used at the beginning, and the receiving end needs to identify the accurate baud rate according to the preset character of the data sent, and further parse the correct data.

[0003] In the existing baud rate identification method, it is usually based on software collection, which will occupy a large amount of CPU bandwidth and time, and the time of software execution will cause low identification accuracy and large error. SUMMARY

[0004] The present application aims to provide a hardware- implemented serial communication high dynamic range baud rate identification method and circuit to solve the problem of occupying a large amount of CPU bandwidth and time in the baud rate identification method based on software implementation, and the time of software execution will cause low identification accuracy and large error.

[0005] The present application provides a hardware- implemented serial communication high dynamic range baud rate identification method, which comprises the following steps:

[0006] The baud rate of the header is collected by the baud rate collection circuit;

[0007] The data of each bit of the header is accurately identified by the bit data collection circuit according to the collected baud rate;

[0008] The width between adjacent edges in the header is timed and judged by the single-bit duration detection circuit.

[0009] Further, the method for collecting the baud rate by the baud rate collection circuit comprises:

[0010] (1) The time between the first falling edge and the first rising edge is the baud rate BR0 of the current received byte, which is collected by a high-frequency clock signal;

[0011] (2) For subsequent B1-B6 bits, sampling is performed according to the baud rate BR0 of the current received byte, and the data is put into a data shift register;

[0012] (3) Between the first falling edge and the rising edge of the B7 bit, there are 8 bits in total, including the start bit and B0 to B6. By sampling the time between the first falling edge and the rising edge of the B7 bit, the average baud rate BR6 up to the B6 bit is obtained.

[0013] (4) For the subsequent B7 bit and end bit, sample them according to the average baud rate BR6 and put them into the data shift register;

[0014] (5) At the end of the end bit, on the one hand, it is determined whether the data in the data shift register is a pre-fixed value, and on the other hand, it is determined whether the average baud rate BR6 is within the preset baud rate range; if both conditions are met, the average baud rate BR6 is output as the final acquired baud rate.

[0015] Furthermore, the method of accurately identifying each bit of data in the packet header according to the acquired baud rate by the bit data acquisition circuit includes:

[0016] (1) Calculate the baud rate midpoint time based on the acquired baud rate;

[0017] (2) According to the baud rate midpoint time, sampling is performed at the midpoint of each bit in the packet header, thereby accurately identifying the data of each bit in the packet header.

[0018] Furthermore, the method for timing and judging the width between adjacent edges in the packet header by using a single-bit duration detection circuit includes:

[0019] (1) From the first falling edge, the baud rate recognition starts, and the hardware timer is started at the same time. When the next edge comes, the timer value T0 is obtained; at the same time, the timer is restarted and stopped at the next edge, and the timing is T1. And so on, 7 timer results T0, T1, ..., T6 are obtained; when the timer stops, it is judged whether the timer is within the set baud rate range. If it exceeds the range, the baud rate is considered to be wrong and the entire recognition circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit, and the single bit duration detection circuit are reset;

[0020] (2) When starting the timer, it is also determined whether the timer is within the set baud rate range. If it is out of the range, the baud rate is considered to be wrong and the entire identification circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit, and the single bit duration detection circuit are reset;

[0021] (3) The seven results T0, T1, ..., T6 of each timer are also compared with each other and must be within the same baud rate range. If the baud rate range is exceeded, the baud rate is considered to be wrong and the entire recognition circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit, and the single-bit duration detection circuit are reset.

[0022] The application provides a hardware-achieved serial communication high dynamic range baud rate identification circuit, which comprises a baud rate collection circuit, a bit data collection circuit and a single-bit time length detection circuit.

[0023] The baud rate collection circuit is used for collecting the baud rate of the packet header.

[0024] The bit data collection circuit is used for accurately identifying the data of each bit of the packet header according to the collected baud rate.

[0025] The single-bit time length detection circuit is used for timing and judging the width between adjacent edges in the packet header.

[0026] In some embodiments, the baud rate collection circuit, the bit data collection circuit and the single-bit time length detection circuit are realized by using a counter, a latch and a logic circuit.

[0027] In conclusion, due to the adoption of the above technical scheme, the application has the following advantages:

[0028] The serial communication high dynamic range baud rate identification method and circuit realized by hardware can greatly improve the identification range of the baud rate by using the midpoint sampling mechanism, effectively guarantee the correctness of the collected data, reset the whole identification circuit as soon as the baud rate error is detected, and thus quickly recover to the initial state to detect the next correct bit rate packet header in time, thereby improving the robustness of the whole baud rate identification circuit. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings in the embodiments will be briefly introduced as follows, and it should be understood that the following drawings only show some embodiments of the application, and thus should not be regarded as a limitation on the scope, and other related drawings can also be obtained by those skilled in the art without creative labor on the basis of the drawings.

[0030] Figure 1 It is a schematic diagram of the hardware-achieved serial communication high dynamic range baud rate identification circuit of the embodiment of the application.

[0031] Figure 2 It is a structural schematic diagram of the baud rate collection circuit of the embodiment of the application.

[0032] Figure 3 It is a structural schematic diagram of the bit data collection circuit of the embodiment of the application.

[0033] Figure 42 is a schematic diagram of the structure of a single-bit duration detection circuit according to an embodiment of the present invention.

[0034] Figure 5 This is a diagram explaining the working timing of the baud rate acquisition circuit according to an embodiment of the present invention.

[0035] Figure 6 This is a diagram explaining the working timing of the bit data acquisition circuit according to an embodiment of the present invention.

[0036] Figure 7 This is a diagram explaining the working timing of the single-bit duration detection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0039] Example

[0040] like Figure 1 As shown, this embodiment proposes a hardware-implemented serial communication high dynamic range baud rate identification circuit, including a baud rate acquisition circuit, a bit data acquisition circuit and a single bit duration detection circuit; the baud rate acquisition circuit, the bit data acquisition circuit and the single bit duration detection circuit are interconnected;

[0041] In this embodiment, the baud rate acquisition circuit, bit data acquisition circuit, and single-bit duration detection circuit are implemented using a counter, a latch, and a logic circuit. Specific details are as follows:

[0042] The baud rate acquisition circuit is used to acquire the baud rate of the packet header; the structure of the baud rate acquisition circuit in this embodiment is as follows Figure 2As shown, first, rising edge and falling edge detection of the received signal is realized through trigger D1 and two AND gates; the number of detected edges (rising edge and falling edge) is counted through counter C1; when the number of edges is 0, it indicates that data reception starts, at this time, counter C2 and counter C3 are started; when the number of edges is 1, it indicates that start bit and B0 bit are received, at this time, the count value of counter C2 is latched through latch L1, and the lowest bit of data (i.e. divided by 2) is removed to obtain baud rate BR0; when the number of edges is 8, it indicates that B6 bit is received, at this time, the count value of counter C3 is latched through latch L2, and the lowest three bits of data (i.e. divided by 8) are removed to obtain average baud rate BR6; the collected baud rate data is output to bit data collection circuit to provide a reference for data collection.

[0043] Bit data collection circuit, used for accurately identifying the data of each bit of the header according to the collected baud rate; the structure of the bit data collection circuit in the embodiment is as shown in Figure 3 When the count value of the counter C4 is less than 6, baud rate BR0 is selected; when the count value of the counter C4 is greater than 6, baud rate BR6 is selected; C3 is a baud rate counter, which is started at the falling edge of uart_rx, when the count value of the counter C3 reaches half of the selected baud rate, the currently received value is latched through latch L3 to realize midpoint sampling of each bit to obtain the midpoint time of each bit; when the count value of the counter C3 reaches the value of the selected baud rate, the counter C4 is incremented by 1 to indicate that 1-bit value collection is completed, and the counter C3 is cleared to start counting again; when 8-bit value collection is completed, i.e. the counter C4 is incremented to 8, the value of the register group D2 is latched, and the value is the collected value of each bit; the value is compared with the preset correct value to obtain a signal indicating whether the header data is correct; the signal result is output to the baud rate collection circuit, and if the collected data result is incorrect, the whole system is reset;

[0044] Single-bit time length detection circuit, used for timing and judging the width between adjacent edges in the header; the structure of the single-bit time length detection circuit in the embodiment is as shown in Figure 4 Timing between adjacent edges is realized; the input signal is the rising edge and falling edge of the received signal realized in the baud rate collection module, the counter C5 is cleared and starts counting when each edge arrives, and the count value of the counter is latched; by comparing the latched count value with the preset correct range, if the comparison result indicates that the preset range is exceeded, a reset signal is output to reset the whole system;

[0045] Based on this hardware-implemented serial communication high dynamic range baud rate recognition circuit, a hardware-implemented serial communication high dynamic range baud rate recognition method can be implemented. Through high-frequency clock sampling in the hardware, the baud rate recognition accuracy can be improved, and the recognition dynamic range can be reduced to 20%, thereby reducing the system communication bit error rate and freeing up CPU bandwidth for use by other peripherals. The method includes the following steps:

[0046] S1, collects the baud rate of the packet header through the baud rate collection circuit;

[0047] like Figure 5 As shown, the preset character is a packet header of 0xAA, and the method of collecting the baud rate by the baud rate collection circuit includes:

[0048] (1) The time between the first falling edge and the first rising edge is the start bit and the B0 bit. The time between the first falling edge and the first rising edge is collected by a high-frequency clock signal (generally at least 10 times the baud rate to be collected, the higher the frequency, the smaller the baud rate error). This is the baud rate BR0 of the currently received byte.

[0049] (2) For the subsequent B1 to B6 bits, sample them according to the baud rate BR0 of the currently received byte and place them into the data shift register;

[0050] (3) Between the first falling edge and the rising edge of bit B7, there are 8 bits, including the start bit and bits B0 to B6. By sampling the time between the first falling edge and the rising edge of bit B7, the average baud rate BR6 up to bit B6 is obtained. At this time, the difference between BR0 and BR6 is compared. If the difference exceeds 10%, it is determined that the baud rate recognition is wrong and the circuit returns to the initial state.

[0051] (4) For the subsequent B7 bit and end bit, sample them according to the average baud rate BR6 and put them into the data shift register;

[0052] (5) At the end of the end bit, on the one hand, it is determined whether the data in the data shift register is a pre-fixed value, and on the other hand, it is determined whether the average baud rate BR6 is within the preset baud rate range; if both conditions are met, the average baud rate BR6 is output as the final acquired baud rate.

[0053] S2, accurately identifies each bit of data in the packet header according to the acquired baud rate through the bit data acquisition circuit;

[0054] like Figure 6As shown, the preset character is a header of 0xAA, based on the baud rate acquisition circuit, the B0-B7 bits and the end bit will get the baud rate through step S1, and the data of the current bit is collected; the method for accurately identifying the data of each bit of the header by the bit data acquisition circuit according to the collected baud rate comprises:

[0055] (1) based on the baud rate obtained in the above steps, the midpoint time of the baud rate of each bit is obtained through a hardware counter;

[0056] (2) according to the baud rate midpoint time, sampling is performed at the midpoint of each bit of the header, such as D0-D7 in Figure 6 , so as to accurately identify the data of each bit of the header.

[0057] Compared with sampling at other positions, the midpoint sampling mechanism in the bit data acquisition circuit of the application can greatly improve the identification range of the baud rate, and effectively ensure the correctness of the collected data.

[0058] S3, the width between adjacent edges in the header is timed and judged by a single-bit duration detection circuit;

[0059] As shown in Figure 7 , the preset character is a header of 0xAA, for data with a fixed baud rate, the width of adjacent edges is within a fixed range. Therefore, the method for timing and judging the width between adjacent edges in the header by the single-bit duration detection circuit comprises:

[0060] (1) from the first falling edge, start baud rate identification, and start a hardware timer at the same time, when the next edge comes, get the timer value T0; at the same time, restart the timer, and stop at the next edge, the timing is T1, and so on, get 7 results T0, T1, …, T6 of the timer; when the timer stops, judge whether the timer is within the set baud rate range, if it is out of range, it is considered that the baud rate is wrong and the whole identification circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit and the single-bit duration detection circuit are reset;

[0061] (2) when starting the timer, it is also judged whether the timer is within the set baud rate range, if it is out of range, it is considered that the baud rate is wrong and the whole identification circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit and the single-bit duration detection circuit are reset;

[0062] (3) for the 7 results T0, T1, …, T6 of each timer, the 7 results are also compared with each other, and must be within the same baud rate range, if it is out of the baud rate range, it is considered that the baud rate is wrong and the whole identification circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit and the single-bit duration detection circuit are reset.

[0063] The single-bit time length detection circuit in the application resets the whole identification circuit as soon as detecting baud rate error, so after detecting the error baud rate, the initial state can be quickly recovered to detect the next correct bit rate header in time, and the robustness of the whole baud rate identification circuit is improved.

[0064] The preferred embodiments of the application have been described above with the preferred embodiments, but not for limiting the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A hardware-implemented method for identifying baud rates in a high dynamic range for serial communication, characterized in that: The steps include: The baud rate of the packet header is collected through a baud rate collection circuit; Accurately identify each bit of data in the packet header according to the acquired baud rate through the bit data acquisition circuit; The width between adjacent edges in the packet header is timed and judged by a single-bit duration detection circuit; The method for accurately identifying each bit of data in the packet header according to the collected baud rate through the bit data acquisition circuit includes: (1) calculating the baud rate midpoint time according to the collected baud rate; (2) sampling at the midpoint of each bit of the packet header according to the baud rate midpoint time, thereby accurately identifying the data of each bit of the packet header, improving the recognition range of the baud rate through the midpoint sampling mechanism, and ensuring the correctness of the collected data; C4 is a counter for the number of bits of collected data, when the count value of this counter C4 is less than 6, the baud rate is selected as BR0; when the count value of the counter C4 is greater than 6, the baud rate is selected as BR6; C3 is a baud rate counter, which starts at the falling edge of uart_rx, and when the counter When the count value of counter C3 reaches half of the selected baud rate, the currently received value is latched by latch L3 to achieve midpoint sampling of each bit and obtain the midpoint time of each bit. When the count value of counter C3 reaches the value of the selected baud rate, counter C4 is incremented by one to indicate that one bit of value has been collected, and counter C3 is cleared to restart counting. When the 8-bit value is collected, that is, when counter C4 is incremented to 8, the value of register group D2 is latched, which is the value of each bit collected. This value is compared with the preset correct value to determine whether the packet header data is correct or not. This signal result is output to the baud rate collection circuit. If the collected data result is incorrect, the entire system is reset.

2. The hardware-implemented serial communication high dynamic range baud rate identification method according to claim 1, wherein: The method for collecting baud rate by using a baud rate collection circuit comprises: (1) The time between the first falling edge and the first rising edge is the start bit and the B0 bit. The time between the first falling edge and the first rising edge is collected by a high-frequency clock signal, and the baud rate BR0 of the current received byte is obtained. (2) For the subsequent B1 to B6 bits, sample them according to the baud rate BR0 of the current received byte and put them into the data shift register; (3) Between the first falling edge and the rising edge of the B7 bit, there are 8 bits in total, including the start bit and B0 to B6. By sampling the time between the first falling edge and the rising edge of the B7 bit, the average baud rate BR6 up to the B6 bit is obtained. (4) For the subsequent B7 bit and end bit, sample them according to the average baud rate BR6 and put them into the data shift register; (5) At the end of the end bit, on the one hand, it is determined whether the data in the data shift register is a pre-fixed value, and on the other hand, it is determined whether the average baud rate BR6 is within the preset baud rate range; if both conditions are met, the average baud rate BR6 is output as the final acquired baud rate.

3. The hardware-implemented serial communication high dynamic range baud rate identification method according to claim 2, wherein: The method for timing and judging the width between adjacent edges in the packet header by using a single-bit duration detection circuit includes: (1) From the first falling edge, the baud rate recognition starts, and the hardware timer is started at the same time. When the next edge comes, the timer value T0 is obtained; at the same time, the timer is restarted and stopped at the next edge, and the timing is T1. And so on, 7 timer results T0, T1, ..., T6 are obtained. When the timer stops, it is judged whether the timer is within the set baud rate range. If it exceeds the range, the baud rate is considered to be wrong and the entire recognition circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit, and the single bit duration detection circuit are reset. (2) When starting the timer, it is also determined whether the timer is within the set baud rate range. If it is out of the range, the baud rate is considered to be wrong and the entire identification circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit, and the single bit duration detection circuit are reset; (3) For each timer's 7 results T0, T1, ..., T6, the 7 results are also compared with each other and must be within the same baud rate range. If the baud rate range is exceeded, the baud rate is considered to be wrong and the entire recognition circuit is reset, that is, the baud rate acquisition circuit, the bit data acquisition circuit, and the single-bit duration detection circuit are reset.

4. A hardware-implemented serial communication high dynamic range baud rate recognition circuit, used to implement the hardware-implemented serial communication high dynamic range baud rate recognition method according to any one of claims 1 to 3, characterized in that: It includes a baud rate acquisition circuit, a bit data acquisition circuit and a single bit duration detection circuit; the baud rate acquisition circuit, the bit data acquisition circuit and the single bit duration detection circuit are connected to each other; Baud rate acquisition circuit, used to acquire the baud rate of the packet header; A bit data acquisition circuit is used to accurately identify each bit of data in the packet header according to the acquired baud rate; The single-bit duration detection circuit is used to perform timing judgment on the width between adjacent edges in the packet header.

5. The hardware-implemented serial communication high dynamic range baud rate identification circuit according to claim 4, characterized in that: The baud rate acquisition circuit, the bit data acquisition circuit and the single-bit duration detection circuit are implemented by using a counter, a latch and a logic circuit.

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