A radar target echo simulation method and device based on intra-pulse memory
By using intra-pulse storage technology, combined with pulse detection, storage and frequency conversion modules, radar target echo simulation with large delay and low inherent delay was achieved under the condition of limited internal storage resources of FPGA. This solved the problem of insufficient storage resources in ultra-wideband radar and met the requirements of radar detection range and accuracy.
Patent Information
- Application Number
- CN202111672329.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-31
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2041-12-31
AI Technical Summary
Existing technologies struggle to simulate radar target echoes with large latency and low inherent latency under limited storage resources, especially in ultra-wideband radars where they cannot meet the requirements for detection range and accuracy.
By employing intra-pulse storage technology, a combination of pulse detection module, pulse storage module, down-conversion module, intra-pulse storage module, and up-conversion module is used to achieve delay and frequency shift processing of radar signals. Only single-bit pulse flag signals are fully stored, while multi-phase large-width signals are stored intra-pulse.
With limited storage resources, it achieves large latency at the millisecond level and inherent latency at the hundred-nanosecond level, meeting the simulation requirements of ultra-wideband radar and reducing storage space requirements.
Smart Images
Figure CN114384480B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of radar target echo simulation and digital signal processing, and particularly relates to a radar target echo simulation method and device based on intra-pulse storage, an electronic device and a storage medium. BACKGROUND
[0002] The radar echo simulator is an important guarantee resource for radar performance testing, and is widely used in the fields of radar research and development, and performance testing and calibration of radar equipment.
[0003] The realization of radar target echo simulation mainly includes simulation of target echo in distance and speed, and the realization is usually achieved by receiving, storing, frequency shifting and forwarding the radar transmitted signal. The delay is realized by controlling the storage depth, so as to realize the simulation of radar target echo in distance, and the Doppler effect is simulated by controlling the frequency shift frequency, so as to realize the simulation of radar target echo in speed.
[0004] With the development of radio equipment and the progress of radio detection technology, higher requirements are put forward for the detection distance and accuracy of radar, and accordingly, higher requirements are put forward for the frequency shift range, accuracy and delay range and accuracy of the radar target echo simulation device. The common way to modify the radar signal is the ultra-wideband radar technology, that is, the instantaneous bandwidth of the signal is large.
[0005] At present, the method based on orthogonal modulation can realize a frequency shift range of 50MHz and a frequency shift accuracy of 0.7Hz, which can meet the demand of radar target echo simulation in speed simulation. However, for the delay simulation, a larger delay storage capacity, a faster storage speed and a lower inherent delay are required. At present, the full storage method is generally used to realize the delay, and the commonly used storage devices include the internal BRAM resource of FPGA and the external QDR or DDR external storage. The internal storage of FPGA can meet the demand of storage speed and inherent delay, but the storage capacity is small; the external storage can meet the demand of storage capacity, but the storage speed and inherent delay are difficult to meet the demand. Therefore, the full storage method is difficult to meet the demand of ultra-wideband and large detection distance. SUMMARY
[0006] The present application provides a radar target echo generation scheme based on intra-pulse storage, which ensures the realization of large delay simulation under the condition of certain storage resources.
[0007] In order to achieve the above object, the radar target echo simulation device comprises a pulse detection module, a pulse storage module, a down-conversion module, an intra-pulse storage module and an up-conversion module.
[0008] The method is used for the radar target echo simulation device, and the radar target echo simulation method comprises the following steps.
[0009] Step one: the pulse detection module receives an input signal to obtain a pulse detection mark; while the pulse detection is performed, the down-conversion module performs down-conversion processing on the input signal to obtain a zero intermediate frequency signal.
[0010] Step two: the pulse storage module realizes delay of the pulse mark signal, directly forwards the pulse mark signal as a write signal of the intra-pulse storage module.
[0011] Step three: the intra-pulse storage module receives the zero intermediate frequency signal output by the down-conversion module.
[0012] Step four: the delayed signal output by the intra-pulse storage module is quadrature modulated to realize frequency shift operation on the signal, and the frequency-shifted signal is output.
[0013] Step five: the up-conversion module performs up-conversion operation on the frequency-shifted signal to move the zero intermediate frequency signal to the original frequency, so as to obtain the delayed and frequency-shifted output signal.
[0014] Preferably, step one is realized by the following method: step one: the pulse detection module receives an input signal, obtains a pulse detection mark through phase number decomposition, absolute value taking and threshold monitoring, and while the pulse detection is performed, the down-conversion module performs down-conversion processing on the input signal to obtain a zero intermediate frequency signal.
[0015] Preferably, step two is realized by the following method: step two: the pulse storage module receives the pulse mark signal output by the pulse detection module, stores the signal into a dual-port memory, controls the storage depth according to the delay amount of the required delay, so as to realize delay of the pulse mark signal, and the delayed pulse mark signal is used as a read control signal of the intra-pulse storage module; in addition, the pulse mark signal is directly forwarded as a write signal of the intra-pulse storage module.
[0016] Preferably, the third step is realized by the following method: the intrapulse storage module receives the output zero intermediate frequency signal of the frequency down-conversion module, and stores and reads the zero intermediate frequency signal according to the storage read and write control instructions output by the pulse storage module, since the write instruction is a pulse envelope, thus only the intrapulse signal is stored; and then the read instruction has been delayed, thus the read signal is the delayed signal.
[0017] In another aspect, the application further provides an electronic device, comprising: a processor and a memory, wherein the memory has computer readable instructions stored thereon, and the computer readable instructions are executed by the processor to realize the intrapulse storage based radar target echo simulation method as described above.
[0018] In another aspect, the application further provides a computer readable storage medium, wherein the computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to realize the intrapulse storage based radar target echo simulation method as described above.
[0019] The application has the following beneficial effects:
[0020] In the signal delay processing of the application, only the single-bit pulse mark signal is fully stored, and only the intrapulse signal of the multi-phase and large bit width input signal is stored, so that the storage space is greatly reduced. Due to the greatly reduced storage space, the method can realize a large delay amount only by using the storage space in the FPGA, and can also meet a lower inherent delay. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 The figure is a schematic diagram of the simulation method of the application;
[0022] Figure 2 The figure is a schematic diagram of the pulse detection module of the application;
[0023] Figure 3 The figure is a schematic diagram of the pulse storage module of the application;
[0024] Figure 4 The figure is a schematic diagram of the intrapulse storage module of the application.
[0025] 1-pulse detection module, 2-pulse storage module, 3-frequency down-conversion module, 4-intrapulse storage module, 5-frequency up-conversion module. DETAILED DESCRIPTION
[0026] The application content of the application will be further described below in combination with the drawings and examples.
[0027] Example one: as Figure 1As shown, the radar target echo simulation method based on intra-pulse storage provided by the embodiment comprises a pulse detection module 1, a pulse storage module 2, a down-conversion module 3, an intra-pulse storage module 4 and an up-conversion module 5. The radar target echo simulation device comprises a pulse detection module, a pulse storage module, a down-conversion module, an intra-pulse storage module and an up-conversion module. The pulse detection module is connected with a radar signal at an input end. The pulse detection module is connected with the pulse storage module at an output end. The pulse storage module storage control signal output end is connected with the intra-pulse storage module control signal end. The down-conversion module is connected with a radar signal at an input end. The down-conversion module output end is connected with the intra-pulse storage module input end.
[0028] The pulse detection module 1 realizes pulse detection of the pulse signal. The principle diagram is as shown in the figure. Figure 2 Firstly, the input signal is split into multiple phases according to the sampling rate, data rate and other information. The absolute value of each phase signal is obtained. Then, the signal absolute value is compared with the signal threshold to obtain the detection of each phase. Finally, the detection results of all phases are processed by OR to obtain the pulse signal mark, which is a single-bit signal. The intra-pulse signal is high and the others are low.
[0029] The pulse storage module 2 stores the pulse mark signal. The principle is as shown in the figure. Figure 3 Firstly, the pulse mark signal output by the pulse detection module 1 is received and stored. The pulse mark signal is delayed according to the delay control amount to serve as the read control signal of the intra-pulse storage module 3. In addition, the pulse mark signal directly serves as the write control signal of the intra-pulse storage.
[0030] The intra-pulse storage module 3 realizes storage of the intra-pulse signal. The principle is as shown in the figure. Figure 4 On one hand, the signal output by the down-conversion module 4 is received. On the other hand, the control instruction of the pulse storage module 2 is received. When the write control signal of the intra-pulse storage is high, the write control is performed. When the read control signal of the intra-pulse storage is high, the stored intra-pulse storage signal is read.
[0031] The radar target echo simulation method based on intra-pulse storage provided by the embodiment comprises the following steps:
[0032] Step one: the pulse detection module 1 receives the input signal, obtains the pulse detection mark through the phase number decomposition, absolute value taking, threshold monitoring and other steps. At the same time of pulse detection, the down-conversion module 3 performs down-conversion processing on the input signal to obtain the zero intermediate frequency signal.
[0033] Step 2: The pulse storage module 2 receives the pulse mark signal output by the pulse detection module 1, stores the signal into a dual-port memory, and controls the storage depth according to the delay amount of the required delay, so as to realize the delay of the pulse mark signal and output the delayed pulse mark signal as the read control signal of the intra-pulse storage module 4; in addition, the pulse mark signal is directly forwarded as the write signal of the intra-pulse storage module 4.
[0034] Step 3: The intra-pulse storage module 4 receives the zero intermediate frequency signal output by the frequency down conversion module 3, and stores and reads the zero intermediate frequency signal according to the memory read and write control instructions output by the pulse storage module 2; since the write instruction is a pulse envelope, only the intra-pulse signal is stored; and then the read instruction has been delayed, so the read signal is the delayed signal.
[0035] Step 4: The quadrature modulation module 5 performs quadrature modulation on the delayed signal output by the intra-pulse storage module 4, realizes the frequency shift operation of the signal, and outputs the frequency-shifted signal.
[0036] Step 5: The frequency up conversion module 6 performs frequency up conversion on the frequency-shifted signal, moves the zero intermediate frequency signal to the original frequency, so as to obtain the output signal after delay and frequency shift.
[0037] When the radar target simulator simulates the radar target echo of the ultra-wideband radar, only the intra-pulse signal of the radar pulse is stored, and the FPGA internal high-speed storage resource is used for storage, so that the millisecond-level large delay amount can be realized under the condition of limited storage resource, and the low inherent delay requirement can be met.
[0038] When the signal delay processing is performed, only the single-bit pulse mark signal is fully stored, and only the intra-pulse signal of the multi-phase and large bit-width input signal is stored, so that the storage space is greatly reduced. Due to the greatly reduced storage space, the FPGA internal storage space can be used to realize the large delay amount, and the low inherent delay can also be met. In the project relying on the method, only the FPGA internal storage space is used, the millisecond-level large delay amount can be realized under the input of the ultra-wideband instantaneous bandwidth, and the inherent delay is in the order of hundreds of nanoseconds.
[0039] In another aspect, the embodiment of the present application also provides an electronic device, which comprises a processor and a memory, and the memory stores computer readable instructions, and the computer readable instructions are executed by the processor to realize the radar target echo simulation method based on intra-pulse storage as described in the above embodiment.
[0040] Specifically, the memory and the processor can be general memory and processor, which are not specifically limited herein, and when the processor runs computer readable instructions stored in the memory, the method for simulating radar target echo based on intra-pulse storage described in the above embodiments can be executed.
[0041] In another aspect, the embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method for simulating radar target echo based on intra-pulse storage described in the above embodiments.
[0042] Those skilled in the art can understand that all or part of the steps of the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer readable storage medium, which can include a flash disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.
[0043] It should be understood that the above detailed description of the technical solutions of the present application by means of the preferred embodiments is illustrative rather than limiting. Those skilled in the art can modify the technical solutions recorded in the embodiments or make equivalent replacements to part of the technical features on the basis of the description of the present application; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A radar target echo simulation device based on intra-pulse memory, characterized by: The radar target echo simulation device comprises a pulse detection module, a pulse storage module, a down-conversion module, an intra-pulse storage module and an up-conversion module. The pulse detection module receives an input signal, obtains a pulse detection mark through phase number decomposition, absolute value taking and threshold monitoring, and outputs the pulse detection mark. The down-conversion module performs down-conversion processing on the input signal to obtain a zero intermediate frequency signal while the pulse detection is performed. The pulse storage module receives a pulse mark signal output by the pulse detection module, stores the pulse mark signal in a dual-port memory, controls the storage depth according to a delay amount of a required delay, thereby realizing delay of the pulse mark signal, and uses the delayed pulse mark signal as a read control signal of the intra-pulse storage module; in addition, the pulse mark signal is directly forwarded as a write control signal of the intra-pulse storage module. The intra-pulse storage module receives a zero intermediate frequency signal output by the down-conversion module, and stores and reads the zero intermediate frequency signal according to the read and write control signals output by the pulse storage module, wherein the write control signal is a pulse envelope and only stores the intra-pulse signal; the read control signal is delayed, and the read zero intermediate frequency signal is a delayed zero intermediate frequency signal.
2. A radar target echo simulation method based on intra-pulse memory, characterized in that: The method is used for a radar target echo simulation device, and comprises the following steps: Step one: the pulse detection module receives an input signal, obtains a pulse detection mark, and outputs a pulse mark signal; while the pulse detection is performed, the down-conversion module performs down-conversion processing on the input signal to obtain a zero intermediate frequency signal. Step two: the pulse storage module delays the pulse mark signal and directly forwards the pulse mark signal as a write signal of the intra-pulse storage module. Step three: the intra-pulse storage module receives a zero intermediate frequency signal output by the down-conversion module. Step four: a delayed signal output by the intra-pulse storage module is quadrature modulated to realize frequency shift operation on the signal, and the frequency-shifted signal is output. Step five: the up-conversion module performs up-conversion operation on the frequency-shifted signal to move the zero intermediate frequency signal to an original frequency, thereby obtaining a delayed and frequency-shifted output signal. Step one is realized by the following method: the pulse detection module receives an input signal, obtains a pulse detection mark through phase number decomposition, absolute value taking and threshold monitoring, and outputs the pulse detection mark; while the pulse detection is performed, the down-conversion module performs down-conversion processing on the input signal to obtain a zero intermediate frequency signal. The step two is realized by the following method: the step two pulse storage module receives the pulse mark signal output by the pulse detection module, stores the pulse mark signal into the dual-port memory, and controls the storage depth according to the delay amount of the required delay, so as to realize the delay of the pulse mark signal, and take the delayed pulse mark signal as the read control signal of the intra-pulse storage module; in addition, the pulse mark signal is directly forwarded as the write signal of the intra-pulse storage module. The step three is realized by the following method: the step three intra-pulse storage module receives the output zero intermediate frequency signal of the frequency down conversion module, and stores and reads the zero intermediate frequency signal according to the read and write control signals output by the pulse storage module, the write control signal is the pulse envelope, and only the intra-pulse signal is stored; the read control signal is delayed, and the read zero intermediate frequency signal is the delayed zero intermediate frequency signal.
3. An electronic device, comprising: Comprise: A processor and a memory, the memory has computer readable instructions stored thereon, the computer readable instructions are executed by the processor to realize the radar target echo simulation method based on intra-pulse storage as claimed in claim 2.
4. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the radar target echo simulation method based on intra-pulse storage as claimed in claim 2.