Control circuit of power improvement circuit and semiconductor integrated circuit device

Abstract

A control circuit of a power improvement circuit having a DC / DC converter according to the present application includes an operation circuit. The operation circuit is configured to generate a third voltage by multiplying a first voltage and a second voltage, and generate a fourth voltage by applying an offset voltage to the third voltage. The first voltage has a full-wave rectified waveform. The second voltage is generated by amplifying an error of a first detection voltage corresponding to an output voltage of the DC / DC converter and a reference voltage. A semiconductor integrated circuit device is a semiconductor integrated circuit device including a terminal configured to apply a power supply voltage, and includes an abnormality detection circuit configured to detect an abnormality, an output stop circuit configured to stop an output of the semiconductor integrated circuit device when the abnormality is detected by the abnormality detection circuit, and a suppression circuit configured to suppress a consumption current of the semiconductor integrated circuit device when the abnormality is detected by the abnormality detection circuit.

Description

TECHNICAL FIELD

[0001] The application described in this specification relates to a control circuit of a power improvement circuit and a semiconductor integrated circuit device. BACKGROUND

[0002] The power improvement circuit monitors an AC input voltage and an AC input current of a power supply device that performs AC / DC conversion, makes their phases substantially coincide, and makes the power be in a state close to 1 (i.e., 100%). (See, for example, Patent Literature 1.)

[0003] Figure 13 is a diagram showing a schematic configuration example of a power improvement circuit of a conventional semiconductor integrated circuit device. Figure 13 The power improvement circuit shown has a conventional semiconductor integrated circuit device 101, an output circuit 102, a resistor 103, a capacitor 104, inductors 105 and 106, and a diode 107.

[0004] The conventional semiconductor integrated circuit device 101 controls a switching transistor in the output circuit 102. The output circuit 102 converts a voltage V H rectified by the output circuit 102 into a regulated output voltage V DC , and supplies it to a load 108.

[0005] The inductor 105 is provided in a power supply line LN1, and the inductor 106 is magnetically coupled to the inductor 105.

[0006] The resistor 103 is provided between a terminal VCC of the conventional semiconductor integrated circuit device 101 and the power supply line LN1. The capacitor 104 is provided between the terminal VCC of the conventional semiconductor integrated circuit device 101 and a ground potential. The diode 107 is provided between the terminal VCC of the conventional semiconductor integrated circuit device 101 and the inductor 106.

[0007] The current flowing in the resistor 103 is always supplied to the terminal VCC of the conventional semiconductor integrated circuit device 101, and the current flowing in the diode 107 is supplied only when the switching transistor in the output circuit 102 performs a switching operation. The voltage applied to the terminal VCC is used as a power supply voltage V CC in the conventional semiconductor integrated circuit device 101.

[0008] The conventional semiconductor integrated circuit device 101 has a comparator 101A. The comparator 101A is a hysteresis comparator that compares the power supply voltage V CC with a threshold voltage and outputs a low voltage lock signal UVLO indicating the comparison result. If the power supply voltage V CCIf the voltage is above the threshold voltage, then the low-voltage blocking signal UVLO becomes low (indicating the normal state level). If the power supply voltage V... CC If the threshold voltage is not reached, the low-voltage blocking signal UVLO becomes high (indicating an abnormal state). The threshold voltage used by comparator 101A is determined based on the level of the low-voltage blocking signal UVLO, setting the first threshold voltage V... TH1 With the second threshold voltage V TH2 To make a transformation.

[0009] The conventional semiconductor integrated circuit device 101 detects the power supply voltage V CC Low voltage, output voltage V DC In the event of abnormal conditions such as overvoltage or overheating, the switching action of the switching transistor in the output circuit 102 is stopped. On the other hand, the conventional semiconductor integrated circuit device 101, when not detecting the power supply voltage V, CC Low voltage, output voltage V DC Under certain abnormal conditions such as overvoltage or overheating, the switching transistor in the output circuit 102 will switch on or off.

[0010] Furthermore, conventional semiconductor integrated circuit devices 101 enter a so-called standby state during the period when the low voltage blocking signal UVLO is at a high level (indicating an abnormal state), thus reducing power consumption.

[0011] [Background Technical Documents]

[0012] [Patent Literature]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 2012-182968 Summary of the Invention

[0014] [The problem the invention aims to solve]

[0015] The distortion of AC input current is expressed as Total Harmonic Distortion (THD). When THD is high, there are concerns about its adverse effects on other machines besides those equipped with power improvement circuitry. In other words, it is desirable to control THD reduction within the power improvement circuitry.

[0016] Figure 14 This indicates the power supply voltage V of the conventional semiconductor integrated circuit device 101. CC The timing diagram of the waveform. At time t1, some anomaly is detected, and the switching action of the switching transistor stops.

[0017] If the switching operation of the switching transistor stops, no current will flow in the diode 107. And, the consumption current of the conventional semiconductor integrated circuit device 101 is greater than the current flowing in the resistor 103, the power supply voltage V CC is gradually reduced.

[0018] If the power supply voltage V CC is reduced to the first threshold voltage V TH1 , the conventional semiconductor integrated circuit device 101 becomes the standby state by the low voltage lockout, the consumption current of the conventional semiconductor integrated circuit device 101 is less than the current flowing in the resistor 103, the power supply voltage V CC is gradually increased.

[0019] If the power supply voltage V CC is increased to the second threshold voltage V TH2 , the low voltage lockout is released, and the conventional semiconductor integrated circuit device 101 does not become the standby state. At this time, if the detection of some abnormality continues, the power supply voltage V CC is again gradually reduced.

[0020] The power supply voltage V CC is repeatedly reduced and increased as long as the detection of some abnormality continues.

[0021] Here, at the second time point t2, the abnormality other than the low voltage of the power supply voltage V CC is eliminated. Even if the abnormality other than the low voltage of the power supply voltage V CC is eliminated, since the low voltage lockout is in effect at the second time point t2, the switching operation of the switching transistor is not immediately resumed. At the third time point t3 at which the power supply voltage V CC is increased to the second threshold voltage V TH2 , the low voltage lockout is finally released, the switching operation of the switching transistor is resumed, and the power supply voltage V CC is further increased.

[0022] In addition, if the load 108 becomes a heavy load at the second time point t2, the power supply voltage V CC is reduced because the switching transistor cannot respond to the load variation while the switching operation is stopped.

[0023] If the power supply voltage V CC is not reduced while the switching transistor in the output circuit 102 stops the switching operation, the switching operation can be quickly resumed when the abnormality is eliminated.

[0024] In order to prevent the power supply voltage V CCdecrease, consider increasing the capacitance of the capacitor 104. However, in the method, the cost of the capacitor 104 increases. Furthermore, since the length of the stop period of the switching operation is uncertain when the abnormality is eliminated, even if the capacitance of the capacitor 104 is increased, if the stop period of the switching operation is long, the power supply voltage V CC decreases.

[0025] To prevent the power supply voltage V CC decreases, consider decreasing the resistance value of the resistor 103 to increase the current flowing in the resistor 103. However, in the method, the cost of the resistor 103 increases.

[0026] As described above, the conventional semiconductor integrated circuit device 101 has a problem of poor load response characteristics.

[0027] [Technical Means to Solve the Problem]

[0028] The control circuit described in this specification is a control circuit of a power improvement circuit having a DC / DC converter, and is configured as follows (1st configuration) : an input voltage detection terminal configured to receive a 1st voltage having a full-wave rectified waveform; an error amplifier circuit configured to amplify an error between a 1st detection voltage corresponding to an output voltage of the DC / DC converter and a reference voltage to generate a 2nd voltage; an operation circuit configured to generate a 3rd voltage by multiplying the 1st voltage and the 2nd voltage, and generate a 4th voltage by applying an offset voltage to the 3rd voltage; a comparator configured to compare a 2nd detection voltage corresponding to a current flowing in a switching transistor of the DC / DC converter with the 4th voltage; and a drive circuit configured to turn on / off drive the switching transistor, and according to an output of the comparator, turn off the switching transistor whenever the 2nd detection voltage is higher than the 4th voltage.

[0029] Furthermore, in the control circuit of the 1st configuration, the operation circuit can be configured to make the offset voltage variable depending on the 1st voltage (2nd configuration).

[0030] Furthermore, in the control circuit of the 2nd configuration, the operation circuit can be configured to make the offset voltage variable in such a manner that the higher the 1st voltage, the smaller the offset voltage (3rd configuration).

[0031] Furthermore, in the control circuit of the 3rd configuration, the operation circuit can be configured to make the offset voltage variable in such a manner that the higher the 1st voltage, the more linearly smaller the offset voltage (4th configuration).

[0032] Further, in the control circuit of any one of the first to fourth configurations, the minimum value of the offset voltage can be zero or more (fifth configuration).

[0033] Further, in the control circuit of any one of the second to fifth configurations, the operation circuit can be configured to include a constant current circuit configured to generate a constant current and a first current generation circuit configured to generate a first current corresponding to the first voltage, and the offset voltage can be generated based on a current after the first current is drawn from the constant current (sixth configuration).

[0034] The power improvement circuit described in the present specification is configured as a configuration in which an output circuit of a DC / DC converter includes a switching transistor, and the control circuit of any one of the first to sixth configurations is configured to drive the switching transistor (seventh configuration).

[0035] The electronic machine described in the present specification is configured as a configuration in which a rectifier circuit is configured to full-wave rectify an alternating voltage, and the power improvement circuit of the seventh configuration is configured to receive an output voltage of the rectifier circuit (eighth configuration).

[0036] The semiconductor integrated circuit device described in the present specification is configured as a configuration in which a terminal is configured to be applied with a power supply voltage, an abnormality detection circuit is configured to detect an abnormality, an output stop circuit is configured to stop an output of the semiconductor integrated circuit device when an abnormality is detected by the abnormality detection circuit, and a suppression circuit is configured to suppress a consumption current of the semiconductor integrated circuit device when an abnormality is detected by the abnormality detection circuit (ninth configuration).

[0037] Further, in the semiconductor integrated circuit device of the first configuration, the semiconductor integrated circuit device can further include an overvoltage detection circuit configured to detect that the power supply voltage is an overvoltage, and a current drawing circuit configured to draw a current from the terminal when the overvoltage of the power supply voltage is detected by the overvoltage detection circuit (tenth configuration).

[0038] Further, in the semiconductor integrated circuit device of the first or second configuration, the suppression circuit can include an oscillation circuit configured to oscillate a clock signal, and a logic circuit that operates based on the clock signal, and the oscillation circuit can be in a disabled state when an abnormality is detected by the abnormality detection circuit (eleventh configuration).

[0039] The load driving circuit described in the present specification is configured as a configuration in which the semiconductor integrated circuit device of any one of the first to third configurations is included, and a load is driven based on an output of the semiconductor integrated circuit device (twelfth configuration).

[0040] Further, in the load driving circuit of the 4th configuration, the power supply voltage can be larger when the output of the semiconductor integrated circuit device is stopped than when the output of the semiconductor integrated circuit device is not stopped (13th configuration).

[0041] Further, in the load driving circuit of the 4th or 5th configuration, the load driving circuit can be a power improvement circuit (14th configuration).

[0042] The electronic machine described in this specification is configured as follows (15th configuration): provided are a load; and the load driving circuit of any one of the 4th to 6th configurations that drives the load.

[0043] Further, in the electronic machine of the 7th configuration, the electronic machine can be a lighting machine that can perform at least one of dimming and color adjustment (16th configuration).

[0044] [Effects of the Invention]

[0045] The control circuit described in this specification can suppress the THD of the power improvement circuit.

[0046] The semiconductor integrated circuit device described in this specification can improve the load response characteristic. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 FIG. 1 is a diagram showing a configuration of an electronic machine according to an embodiment.

[0048] Figure 2 FIG. 2 is a diagram showing an example of a power improvement circuit.

[0049] Figure 3 FIG. 3 is a diagram showing an example of an offset voltage generation circuit.

[0050] Figure 4 FIG. 4 is a diagram showing an example of a 1st operation circuit.

[0051] Figure 5 FIG. 5 is a diagram showing an example of a 1st conversion circuit.

[0052] Figure 6 FIG. 6 is a diagram showing an example of a 2nd conversion circuit.

[0053] Figure 7 FIG. 7 is a diagram showing an example of a 2nd operation circuit.

[0054] Figure 8 FIG. 8 is a waveform chart of an AC voltage and an input current.

[0055] Figure 9is a view showing an example of a power improvement circuit.

[0056] Figure 10 is a view showing an example of a suppression circuit.

[0057] Figure 11 is a view showing an example of an overvoltage detection circuit and a current extraction circuit.

[0058] Figure 12 is a timing chart showing a waveform of a power supply voltage of an IC.

[0059] Figure 13 is a view showing an example of a schematic configuration of a power improvement circuit including a conventional semiconductor integrated circuit device.

[0060] Figure 14 is a timing chart showing a waveform of a power supply voltage of a conventional semiconductor integrated circuit device. DETAILED DESCRIPTION

[0061] In this specification, a reference voltage means a voltage that is fixed in an ideal state, and a voltage that actually slightly varies due to a temperature change or the like.

[0062] In this specification, a constant current means a current that is fixed in an ideal state, and a current that actually slightly varies due to a temperature change or the like.

[0063] In this specification, a constant voltage means a voltage that is fixed in an ideal state, and a voltage that actually slightly varies due to a temperature change or the like.

[0064] Figure 1 is a circuit diagram showing a configuration of an electronic machine 1 of an embodiment. As the electronic machine 1, for example, an electric appliance such as a television, a refrigerator, an air conditioner, or the like, or a computer, or the like can be exemplified. The electronic machine 1 can also be a lighting machine that can perform at least one of dimming and color adjustment, for example. As a light emitting element used in the lighting machine, for example, an LED (Light Emitting Diode), an organic EL (Electro-Luminescence), or the like can be exemplified. In the lighting machine, a load varies when a setting of dimming or color adjustment is changed. In the lighting machine, if the load responsiveness is improved, the time required from an instruction of a change in the setting of dimming or color adjustment by a transmission signal from a remote control transmitter or the like to completion of the change in the setting of dimming or color adjustment can be shortened.

[0065] The electronic device 1 includes a fuse 2, a capacitor 3, a filter 4, a rectifier circuit 5, a capacitor 6, and a power factor correction (PFC) circuit 7. The electronic device 1 also includes a DC / DC converter 8, a microcomputer 9, and a signal processing circuit 10. The electronic device 1 is divided into a primary side and a secondary side that are insulated from each other, with an isolation transformer (not shown) of the DC / DC converter 8 as a boundary.

[0066] The rectifier circuit 5 is, for example, a rectifier circuit of a diode bridge. An alternating voltage V AC is supplied to the rectifier circuit 5 via the fuse 2, the capacitor 3, and the filter 4. The rectifier circuit 5 full-wave-rectifies the alternating voltage V AC to generate a first voltage V H . Thus, the first voltage V H has a full-wave-rectified waveform.

[0067] The first voltage V H is supplied to the PFC circuit 7 via the capacitor 6. The PFC circuit 7 has a step-up DC / DC converter (switching regulator) that generates an output voltage V H from the first voltage V DC . The PFC circuit 7 improves the power by making the first voltage V H in phase with an input current I AC .

[0068] The DC / DC converter 8 receives the output voltage V DC of the PFC circuit 7, steps it down, and supplies it to each of the load, that is, the microcomputer 9 and the signal processing circuit 10.

[0069] The microcomputer 9 controls the entire electronic device 1. The signal processing circuit 10 is a block that performs specific signal processing, and can include, for example, an interface circuit that performs communication with an external device, an image processing circuit, a sound processing circuit, and the like. Of course, in an actual electronic device 1, a plurality of signal processing circuits 10 are provided according to the function thereof.

[0070] The above is a description of the configuration of the electronic device 1. Thus, by performing AC / DC conversion in an electronic device that includes a rectifier circuit 5 that full-wave-rectifies an alternating voltage V AC , and a PFC circuit 7 that steps up a first voltage V H that has been full-wave-rectified to generate an output voltage V DC . Next, details of the PFC circuit 7 mounted in the electronic device 1 will be described.

[0071] Figure 2is a circuit diagram showing the configuration of the PFC circuit 7 according to an embodiment. The PFC circuit 7 has a step-up DC / DC converter (switching regulator) as described above. Note that the PFC circuit 7 can have a DC / DC converter other than the step-up type, unlike the present embodiment.

[0072] The PFC circuit 7 includes an IC 700, resistors R1 to R9, capacitors C1 to C6, diodes D1 and D2, inductors L1 and L2, and a switching transistor M1. In the present embodiment, the switching transistor M1 is an NMOS (Negative channel Metal Oxide Semiconductor) transistor.

[0073] The IC 700 is a control circuit of the PFC circuit 7. The IC 700 includes a terminal VCC, a terminal GND, a terminal ZCD, a terminal OUT, a terminal CS, a terminal MULT, a terminal EO, and a terminal VS.

[0074] The terminal MULT is supplied with a voltage V H , which is a voltage divided by resistors R1 and R2 of the PFC circuit 7. H MULT The other end of the resistor R2 and the other end of the capacitor C5 are connected to a ground potential. With this configuration, the voltage divided by the resistors R1 and R2 of the PFC circuit 7, that is, the voltage V DC is supplied to the terminal MULT.

[0075] The one end of the resistor R1 is connected to the one end of the inductor L1 and the anode of the diode D1. The other end of the inductor L1 is connected to the anode of the diode D2 and the drain of the switching transistor M1. The cathodes of the diodes D1 and D2 are connected to the one end of the capacitor C1. The other end of the capacitor C1 is connected to a ground potential, the gate of the switching transistor M1 is connected to the terminal OUT via the resistor R8, and the source of the switching transistor M1 is connected to a ground potential via the resistor R9. With this configuration, the PFC circuit 7 has the step-up DC / DC converter (switching regulator). The output voltage of the step-up DC / DC converter (switching regulator), that is, the voltage V DC is output from the one end of the capacitor C1.

[0076] The inductor L1 is magnetically coupled to the inductor L2. The one end of the inductor L2 is connected to the terminal ZCD via the resistor R7. The other end of the inductor L2 is connected to a ground potential. With this configuration, the IC 700 can detect the zero-crossing of the current flowing in the inductor L1 by monitoring the voltage supplied to the terminal ZCD.

[0077] The one end of the resistor R3 is supplied with a voltage V DCThe other end of the resistor R3 is connected to one end of the resistor R4, one end of the capacitor C2, and the terminal VS. The other end of the resistor R4 and the other end of the capacitor C2 are connected to the ground potential. With this configuration, the voltage V DC divided by the resistors R3 and R4, that is, the first detection voltage V S is supplied to the terminal VS.

[0078] One end of the resistor R9 is connected to the source of the switching transistor Ml, and the other end of the resistor R9 is connected to the ground potential. Between the two ends of the resistor R9, a voltage proportional to the current flowing in the switching transistor Ml (the drain current of the switching transistor Ml) is generated. The voltage generated between the two ends of the resistor R9 is removed of high frequency components by the RC circuit (low pass filter) composed of the resistor R6 and the capacitor C6, and the second detection voltage V CS is generated. The second detection voltage V CS is supplied to the CS. The second detection voltage V CS is a voltage corresponding to the current flowing in the switching transistor.

[0079] One end of the resistor R5 and one end of the capacitor C3 are connected to the terminal EO. The other end of the resistor R5 is connected to one end of the capacitor C4. The other end of the capacitor C3 and the other end of the capacitor C4 are connected to the ground potential. The power supply voltage V CC is supplied to the terminal VCC, and the terminal GND is connected to the ground potential.

[0080] The PFC circuit 7 is an example of a load driving circuit that drives a load based on an output of a semiconductor integrated circuit device. The load of the PFC circuit 7 is the DC / DC converter 8, the microcomputer 9, and the signal processing circuit 10. Note that the load driving circuit that drives a load based on an output of a semiconductor integrated circuit device is not limited to a power improvement circuit, and can be, for example, a power supply circuit that does not perform power improvement, or the like.

[0081] Figure 9 is a circuit diagram showing the configuration of the PFC circuit 7 according to an embodiment. The PFC circuit 7 has the boost type DC / DC converter (switching regulator) as described above. Note that the PFC circuit 7 can have a DC / DC converter other than the boost type, unlike the present embodiment.

[0082] The PFC circuit 7 includes an IC 700, resistors Rl to R9, capacitors Cl to C6, diodes Dl and D2, inductors LI and L2, and a switching transistor Ml. In the present embodiment, the switching transistor Ml is an NMOS transistor.

[0083] A control circuit of the PFC circuit 7. Further, the IC 700 is a packaged semiconductor integrated circuit device. The IC 700 has a terminal VCC, a terminal GND, a terminal ZCD, a terminal OUT, a terminal CS, a terminal MULT, a terminal EO, and a terminal VS.

[0084] A first voltage V H is applied to one end of a resistor R1. The other end of the resistor R1 is connected to one end of a resistor R2, one end of a capacitor C5, and the terminal MULT. The other end of the resistor R2 and the other end of the capacitor C5 are connected to a ground potential. With this configuration, a voltage divided by the resistors R1 and R2 of the first voltage V H is supplied to the terminal MULT as a first voltage V MULT .

[0085] One end of the resistor R1 is connected to one end of an inductor LI and an anode of a diode Dl. The other end of the inductor LI is connected to an anode of a diode D2 and a drain of a switching transistor Ml. Cathodes of the diodes Dl and D2 are connected to one end of a capacitor Cl. The other end of the capacitor Cl is connected to a ground potential, a gate of the switching transistor Ml is connected to the terminal OUT via a resistor R8, and a source of the switching transistor Ml is connected to the ground potential via a resistor R9. With this configuration, the PFC circuit 7 has a step-up DC / DC converter (switching regulator). An output voltage of the step-up DC / DC converter (switching regulator), that is, a voltage V DC is output from one end of the capacitor Cl.

[0086] The inductor LI is magnetically coupled to an inductor L2. One end of the inductor L2 is connected to the terminal ZCD via a resistor R7. The other end of the inductor L2 is connected to the ground potential. With this configuration, the IC 700 can detect a zero point of a current flowing in the inductor LI by monitoring a voltage supplied to the terminal ZCD.

[0087] A voltage V DC is applied to one end of a resistor R3. The other end of the resistor R3 is connected to one end of a resistor R4, one end of a capacitor C2, and the terminal VS. The other end of the resistor R4 and the other end of the capacitor C2 are connected to a ground potential. With this configuration, a voltage divided by the resistors R3 and R4 of the voltage V DC is supplied to the terminal VS as a first detection voltage V S .

[0088] One end of the resistor R9 is connected to the source of the switching transistor Ml, and the other end of the resistor R9 is connected to the ground potential. Between the both ends of the resistor R9, a voltage proportional to the current flowing in the switching transistor Ml (the drain current of the switching transistor Ml) is generated. The voltage generated between the both ends of the resistor R9 is removed of high frequency components by the RC circuit (low pass filter) composed of the resistor R6 and the capacitor C6, and the second detection voltage V CS is generated. The second detection voltage V CS is supplied to the CS. The second detection voltage V CS is a voltage corresponding to the current flowing in the switching transistor.

[0089] One end of the resistor R5 and one end of the capacitor C3 are connected to the terminal EO. The other end of the resistor R5 is connected to one end of the capacitor C4. The other end of the capacitor C3 and the other end of the capacitor C4 are connected to the ground potential. The power supply voltage V CC is supplied to the terminal VCC, and the terminal GND is connected to the ground potential.

[0090] One end of the resistor R10, one end of the capacitor C7, and the cathode of the diode D3 are connected to the terminal VCC. The other end of the resistor R10 is supplied with the first voltage V H . The anode of the diode D3 is connected to the connection node of the inductor L2 and the resistor R7. Note that, unlike the present embodiment, the configuration in which the diode D3 is not provided can also be adopted.

[0091] Hereinafter, the specific configuration of the IC 700 will be described.

[0092] The IC 700 is provided with a Zener diode 701, a comparator 702, a band gap reference voltage circuit 703, a constant voltage circuit 704, and an overheat protection circuit 705. The anode of the Zener diode 701 is connected to the ground potential, and the cathode of the Zener diode 701 is connected to the terminal VCC.

[0093] The Zener diode 701 clamps the power supply voltage V CC to the Zener voltage. The inverting input terminal of the comparator 702, the band gap reference voltage circuit 703, and the constant voltage circuit 704 are connected to the terminal VCC.

[0094] The comparator 702 is a hysteresis comparator, compares the power supply voltage V CC with the threshold voltage, and outputs a low voltage lock signal UVLO indicating the comparison result. If the power supply voltage V CC is equal to or higher than the threshold voltage, the low voltage lock signal UVLO becomes low (a level indicating a normal state), and if the power supply voltage V CCIf the threshold voltage is not reached, the low-voltage blocking signal UVLO becomes high (indicating an abnormal state). The threshold voltage used by comparator 702 is determined based on the level of the low-voltage blocking signal UVLO, setting the first threshold voltage V... TH1 (e.g., 8 [V]) and the second threshold voltage V TH2 (e.g., 13[V]) is transformed.

[0095] The bandgap reference voltage circuit 703 uses a power supply voltage V. CC A reference voltage is generated and supplied to the constant voltage circuit 704.

[0096] The constant voltage circuit 704 uses a power supply voltage V. CC It generates a constant voltage from the reference voltage and supplies it to various parts of IC700.

[0097] The overheat protection circuit 705 detects the ambient temperature. When the ambient temperature is above the threshold temperature, it outputs a high-level (indicating an abnormal state) overheat protection signal TSD. When the ambient temperature is below the threshold temperature, it outputs a low-level (indicating a normal state) overheat protection signal TSD.

[0098] IC700 also includes comparator 706, startup overboost-down circuit 707, comparator 708, and comparator 709.

[0099] Comparator 706 will detect the first voltage V S With threshold voltage V TH3 (e.g., 2.25V) is compared, and the comparison result is output to the start-up overboost reduction circuit 707. When the first detected voltage V S Threshold voltage V TH3 When the above occurs, the output signal of converter 706 becomes high (indicating an abnormal state), and when the first detected voltage V... S The threshold voltage V was not reached TH3 When this occurs, the output signal of converter 706 becomes low (indicating the normal state level).

[0100] During startup, the overboost / downshift circuit 707 outputs a startup overboost / downshift signal OVR. The startup overboost / downshift circuit 707 is based on the output signal of comparator 706 and the output voltage V of comparator 30 (described later). COMP If the first detected voltage V during startup S Rise to threshold voltage V TH3 Then, the overboost voltage reduction signal OVR during startup is set to a high level (indicating an abnormal state), and otherwise, the overboost voltage reduction signal OVR is set to a low level (indicating a normal state), until the second voltage V2 (described later) drops and becomes the constant voltage V (described later). BURSTuntil then.

[0101] The comparator 708 compares the first detection voltage V S with a threshold voltage V TH4 (for example, 0.3 [V]) and outputs a comparison result, that is, a short-circuit protection signal SP. If the first detection voltage V S is the threshold voltage V TH4 or more, the short-circuit protection signal SP becomes a low level (a level indicating a normal state), and if the first detection voltage V S is less than the threshold voltage V TH4 , the short-circuit protection signal SP becomes a high level (a level indicating an abnormal state).

[0102] The comparator 709 is a hysteresis comparator that compares the first detection voltage V S with a threshold voltage and outputs a static overvoltage protection signal SOVP indicating a comparison result. If the first detection voltage V S is the threshold voltage or more, the static overvoltage protection signal SOVP becomes a high level (a level indicating an abnormal state), and if the first detection voltage V S is less than the threshold voltage, the static overvoltage protection signal SOVP becomes a low level (a level indicating a normal state). The threshold voltage used by the comparator 709 is switched between a fifth threshold voltage V TH5 (for example, 2.6 [V]) and a sixth threshold voltage V TH6 (for example, 2.7 [V]) depending on the level of the static overvoltage protection signal SOVP.

[0103] The IC 700 further includes an error amplification circuit 710, an OR gate 711, an NMOS transistor 712, an arithmetic circuit 713, a Zener diode 714, a comparator 715, and a drive circuit DRV1.

[0104] The error amplification circuit 710 amplifies an error between a first detection voltage V DC corresponding to an output voltage V S of a step-up DC / DC converter (switching regulator) provided in the PFC circuit 7 and a reference voltage V REF and generates a second voltage V2. The amplification rate of the error amplification circuit 710 can also be 1. The error amplification circuit 710 supplies the second voltage V2 to the terminal EO and the arithmetic circuit 713.

[0105] The OR gate 711 outputs the logic sum of the low-voltage blocking signal UVLO and the startup overboost-down signal OVR to the gate of NMOS transistor 712. The drain of NMOS transistor 712 is connected to terminal EO, and the source of NMOS transistor 712 is connected to ground. NMOS transistor 712 is a switch used to discharge the second voltage applied to terminal EO. Therefore, when at least one of the low-voltage blocking signal UVLO and the startup overboost-down signal OVR is low, NMOS transistor 712 is turned on, and the second voltage V2 drops.

[0106] Operational circuit 713 converts AC voltage (first voltage) V MULT Multiplying the second voltage V2 by the third voltage generates a third voltage, to which an offset voltage V is applied. OFFSET This generates the fourth voltage V4. Alternatively, the operational circuit 713 may not apply an offset voltage V to the third voltage. OFFSET The third voltage V3 and the fourth voltage V4 are set to the same voltage.

[0107] The fourth voltage V4 is connected to the inverting input terminal of comparator 715. The cathode of Zener diode 714 is connected to the inverting input terminal of comparator 715, and the anode of Zener diode 714 is connected to ground. Zener diode 714 clamps the fourth voltage V4 into a Zener voltage.

[0108] Comparator 715 will detect the second voltage V corresponding to the current flowing in switching transistor M1. CS The voltage is compared with the fourth voltage V4, and the output is a voltage V representing the comparison result. COMP .

[0109] The drive circuit DRV1 turns the drive switching transistor M1 on / off, based on the output of comparator 715, which is the voltage V. COMP Whenever the second detection voltage V CS When the voltage is higher than the fourth voltage V4, the switching transistor M1 is turned off. In other words, the drive circuit DRV1 is based on the output of comparator 715, which is the voltage V. COMP Disconnect the switching transistor M1. The configuration of the drive circuit DRV1 is not particularly limited, as long as well-known techniques are used.

[0110] Figure 2 , 9Fig. 7 shows a circuit diagram of a drive circuit DRV1. The drive circuit DRV1 includes a comparator 716, a monoflop circuit 717, a timer 718, an OR gate 719, an RS flip-flop 720, an AND gate 721, a pre-driver 722, a gate clamp circuit 723, a PMOS transistor 724, an NMOS transistor 725, and a resistor 726.

[0111] The comparator 716 is a hysteresis comparator that compares a voltage applied to a terminal ZCD with a threshold voltage and outputs a comparison result to the monoflop circuit 717. If the voltage applied to the terminal ZCD is equal to or higher than the threshold voltage, the output signal of the comparator 716 becomes a low level, and if the voltage applied to the terminal ZCD is lower than the threshold voltage, the output signal of the comparator 716 becomes a high level. The threshold voltage used by the comparator 716 is switched between a seventh threshold voltage V TH7 (for example, 0.67 [V]) and an eighth threshold voltage V TH8 (for example, 0.9 [V]) according to the level of the output signal of the comparator 716.

[0112] If the output signal of the comparator 716 becomes a high level, the monoflop circuit 717 supplies a monoflop pulse to a first input terminal of the OR gate 719.

[0113] If the timer 718 counts a certain time, a signal of a high level is supplied to a second input terminal of the OR gate 719. The counting of the timer 718 is reset each time the pre-driver 722 receives a signal of a high level from the AND gate.

[0114] The OR gate 719 supplies the output signal of the monoflop circuit 717 and the logical sum of the timer 718 to a set terminal (S) of the RS flip-flop 720. A reset terminal (R) of the RS flip-flop 720 is supplied with the output of the comparator 715, that is, the voltage V COMP . The output (Q) of the RS flip-flop 48 becomes a high level at each positive edge of the voltage applied to the set terminal (S) and becomes a low level at each positive edge of the voltage applied to the reset terminal (R).

[0115] The AND gate 720 supplies the logical product of a low voltage lockout signal UVLO, the output signal of the RS flip-flop 720, an inverted signal of a static overvoltage protection signal SOVP, an inverted signal of a short circuit protection signal SP, and an inverted signal of an overheat protection signal TSD to the pre-driver 722.

[0116] The pre-driver 722 turns on / off the PMOS transistor 724 and the NMOS transistor 725 complementarily based on the output of the AND gate 720.

[0117] The source of the PMOS transistor 724 is connected to the gate clamp circuit 723, and the drain of the PMOS transistor 724 is connected to the drain of the NMOS transistor 725, the terminal OUT, and one end of the resistor 726. The source of the NMOS transistor 725 is connected to the ground potential and the other end of the resistor 726. The gate clamp circuit 723 generates a voltage that is a certain voltage from the power supply voltage V CC The high-level voltage applied to the terminal OUT is clamped to a certain voltage by the gate clamp circuit 723. The high-level voltage applied to the terminal OUT is clamped to a certain voltage by the gate clamp circuit 723, and the high-level voltage applied to the terminal OUT does not exceed the gate-source withstand voltage of the switching transistor Ml when the voltage rises. CC The high-level voltage applied to the terminal OUT is clamped to a certain voltage by the gate clamp circuit 723. The high-level voltage applied to the terminal OUT is clamped to a certain voltage by the gate clamp circuit 723, and the high-level voltage applied to the terminal OUT does not exceed the gate-source withstand voltage of the switching transistor Ml when the voltage rises.

[0118] The above is a description related to the configuration of the PFC circuit 7. Next, a specific configuration example of the offset voltage generation circuit 713A provided in the operation circuit 713 will be described.

[0119] Figure 3 An example of the offset voltage generation circuit 713A is shown. The offset voltage generation circuit 713A includes a constant current generation circuit 713Al, a first current generation circuit 713A2, and a resistor R10.

[0120] The constant current generation circuit 713Al includes a current mirror circuit composed of PMOS transistors M2 and M3 and a current source ISl. A constant voltage V DD The source and back gate of the PMOS transistor M2 and the source and back gate of the PMOS transistor M3 are applied with the constant voltage V The drain of the PMOS transistor M2 and one end of the resistor R10 are connected to a node Nl. The other end of the resistor R10 is connected to the ground potential. The constant current generation circuit 713Al generates a constant current I0 and supplies the constant current I0 to the node Nl. The value of the constant current I0 is not particularly limited, but for example, in a case where the constant current value output from the current source ISl is set to 1 [μA] and the current mirror ratio is set to 6: 1, the value of the constant current I0 is 167 [nA].

[0121] The first current generation circuit 713A2 includes an operational amplifier OP1, a sweep-out type current mirror circuit composed of PMOS transistors M4 and M5, an NMOS transistor M6, a resistor Rl l, and a pull-out type current mirror circuit composed of NMOS transistors M7 and M8. A constant voltage VDD applied to the source and back gate of the PMOS transistor M4 and the source and back gate of the PMOS transistor M5. The gate and drain of the PMOS transistor M4 and the gate of the PMOS transistor M5 are connected to the drain of the NMOS transistor M6. The source and back gate of the NMOS transistor M6 are connected to one end of the resistor R11 and the inverting input terminal of the operational amplifier OP1. The other end of the resistor R11 is connected to the ground potential. The first non-inverting input terminal of the operational amplifier OP1 is supplied with the first voltage V MULT A constant voltage of, for example, 2.5 [V] is supplied to the second non-inverting input terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is connected to the gate of the NMOS transistor M6. The operational amplifier OP1 outputs a signal amplified by the difference between the voltage obtained by adding the first voltage V MULT and the constant voltage of, for example, 2.5 [V] and the voltage supplied to the inverting input terminal. The gate of the PMOS transistor M5 is connected to the drain and gate of the NMOS transistor M7 and the gate of the NMOS transistor M8. The source and back gate of the NMOS transistor M7 and the source and back gate of the NMOS transistor M8 are connected to the ground potential. The drain of the NMOS transistor M8 is connected to the node N1. The first current generating circuit 713A2 generates the first current II, and the first current II is drawn from the node N1. The first current II corresponds to the alternating voltage (the first voltage) V MULT and is variable. Specifically, the higher the alternating voltage (the first voltage) V MULT , the larger the first current II. Figure 3 In the example shown, the higher the alternating voltage (the first voltage) V MULT , the more linearly the first current II increases.

[0122] The current flowing from the node N1 to the resistor R10 after the first current II is drawn from the constant current IO, that is, the differential current (I0-I1). The product of the differential current (I0-I1) and the resistance value of the resistor R10 becomes the offset voltage V OFFSET . Therefore, the offset voltage V OFFSET corresponds to the alternating voltage (the first voltage) V MULT and is variable. Specifically, the higher the alternating voltage (the first voltage) V MULT , the smaller the offset voltage V OFFSET .

[0123] Figure 3 In the example shown, the higher the alternating voltage (the first voltage) V MULT , the more linearly the offset voltage V OFFSET decreases.

[0124] The range of the offset voltage V OFFSET is not particularly limited, but Figure 3In the example shown, for example, the value of the constant current I0is set to 167 [nA] as described above, the current mirror ratio of the sweep-out type current mirror circuit in the first current generating circuit 713A2 is set to 10:1, the resistance value of the current source, that is, the resistance R11, connected to the sweep-out type current mirror circuit is set to 2 [mΩ], the draw-out type current mirror ratio in the first current generating circuit 713A2 is set to 1:1, and the resistance value of the resistance R10 is set to 161.2 [kΩ], the offset voltage V OFFSET is variable in a range of 6.9 [mV] or more and 26.8 [mV] or less.

[0125] If the minimum value of the offset voltage V OFFSET is set to 6.9 [mV], for example, as in the example described above, the actual minimum value of the offset voltage V OFFSET according to the variation of the circuit constant can be set to zero or more.

[0126] If the minimum value of the offset voltage V OFFSET is less than zero, the offset voltage V Figure 3 in the example shown does not operate normally, and thus it is desirable that the minimum value of the offset voltage V OFFSET be zero or more. Also, since it is considered that no adverse situation occurs even if the minimum value of the offset voltage V OFFSET is less than zero, it is also considered that the minimum value of the offset voltage V OFFSET be less than zero.

[0127] Further, a trimming element that adjusts the circuit constant can be provided in the offset voltage generating circuit 713A, the variation of the circuit constant is suppressed, and the design value of the minimum value of the offset voltage V OFFSET is zero or close to zero. As the trimming element, for example, at least one fuse provided in a parallel circuit of a plurality of resistors in order to adjust the resistance value of the current source, that is, the resistance, connected to the sweep-out type current mirror circuit in the first current generating circuit 713A2 can be cited. The fuse can be cut by laser trimming, for example.

[0128] The above is a description of the configuration of the offset voltage generating circuit 713A. Next, a specific configuration example of the circuit of the arithmetic circuit 713 other than the offset voltage generating circuit 713A will be described. The arithmetic circuit 713 includes, in addition to the offset voltage generating circuit 713A, a first arithmetic circuit 713B, a first conversion circuit 713C, a second conversion circuit 713D, and a second arithmetic circuit 713E.

[0129] Figure 4represents an example of the first operation circuit 713B. The first operation circuit 713B includes resistors R12 to R15 and an operational amplifier OP2. The first end of the resistor R12 is applied with the second voltage V2. The other end of the resistor R12 and the first end of the resistor R13 are connected to the non-inverting input terminal of the operational amplifier OP2. The other end of the resistor R13 is connected to the ground potential. The first end of the resistor R14 is applied with a constant voltage V BURST . The other end of the resistor R14 and the first end of the resistor R15 are connected to the inverting input terminal of the operational amplifier OP2. The other end of the resistor R15 is connected to the output terminal of the operational amplifier OP2. The first operation circuit 713B outputs a voltage (V2-V BURST ) obtained by subtracting the constant voltage V BURST from the second voltage V2.

[0130] Figure 5 represents an example of the first conversion circuit 713C. The first conversion circuit 713C includes an operational amplifier OP3, a resistor R16, and an NPN bipolar transistor M9. The non-inverting input terminal of the operational amplifier OP3 is applied with a voltage (V2-V BURST ). The other end of the resistor R16 is connected to the ground potential. The collector and the base of the NPN bipolar transistor M9 are connected to the power supply terminal of the operational amplifier OP3. The emitter of the NPN bipolar transistor M9 is connected to the ground potential. The first conversion circuit 713C converts the voltage (V2-V BURST ) into a current (I2-I BURST ), and outputs the current (I2-I BURST ) as a base current of the NPN bipolar transistor M9.

[0131] Figure 6 represents an example of the second conversion circuit 713D. The second conversion circuit 713D includes an operational amplifier OP4, a resistor R17, and an NPN bipolar transistor M10. The non-inverting input terminal of the operational amplifier OP4 is applied with an alternating voltage (first voltage) V MULT . The other end of the resistor R17 is connected to the ground potential. The collector and the base of the NPN bipolar transistor M10 are connected to the power supply terminal of the operational amplifier OP4. The emitter of the NPN bipolar transistor M10 is connected to the ground potential. The second conversion circuit 713D converts the alternating voltage (first voltage) V MULT into a current I MULT , and outputs the current I MULT as a base current of the NPN bipolar transistor M10.

[0132] Figure 7An example of the second operation circuit 713E is shown. The second operation circuit 20E includes resistors R18 to R24, a current source IS2, NPN bipolar transistors M11 to M20, PMOS transistors M21 and M22, NMOS transistors M23 and M24, a PNP bipolar transistor M25, and a NOT gate NG1. The constant voltage V DDThe other end of the resistor R18 is connected to the collector of the NPN bipolar transistor Mll. The emitter of the NPN bipolar transistor Mll is connected to one end of the current source IS2 and the base of the NPN bipolar transistor Ml5. The other end of the current source IS2 is connected to the ground potential. The base and the emitter of the NPN bipolar transistor Ml 2 are connected to the base of the PNP bipolar transistor M25 and the collector of the NPN bipolar transistor Ml 3. The emitter of the NPN bipolar transistor Ml 3 is connected to the collector of the NPN bipolar transistor Ml 5. The emitter of the NPN bipolar transistor Ml 5 is connected to the emitter of the NPN bipolar transistor Ml 6. The other end of the resistor Rl 9 is connected to the collector of the NPN bipolar transistor Ml 4. The emitter of the NPN bipolar transistor Ml 4 is connected to the base of the NPN bipolar transistor Ml 1 and the collector of the NPN bipolar transistor Ml 6. The other end of the resistor R20 is connected to the collector of the NPN bipolar transistor Ml 7. The emitter of the NPN bipolar transistor Ml 7 is connected to the base of the NPN bipolar transistor Ml 6 and the collector of the NPN bipolar transistor Ml 8. The emitter of the NPN bipolar transistor Ml 8 is connected to the ground potential. The base of the NPN bipolar transistor Ml 8 is connected to the base and the collector of the NPN bipolar transistor Ml 0 in the second conversion circuit 713D. The NPN bipolar transistors Ml 0 and Ml 8 constitute a current mirror circuit. The other end of the resistor R21 is connected to the collector of the NPN bipolar transistor Ml 9. The emitter of the NPN bipolar transistor Ml 9 is connected to the base of the NPN bipolar transistor Ml 7 and the collector of the NPN bipolar transistor M20. The emitter of the NPN bipolar transistor M20 is connected to the ground potential. The base of the NPN bipolar transistor M20 is connected to the base and the collector of the NPN bipolar transistor M9 in the first conversion circuit 713C. The NPN bipolar transistors M9 and M20 constitute a current mirror circuit. The other end of the resistor R22 is connected to one end of the resistor R23, the gate of the NPN bipolar transistor Ml 3, the gate of the NPN bipolar transistor Ml 4, and the gate of the NPN bipolar transistor Ml 9. The other end of the resistor R23 is connected to the ground potential. The gate and the drain of the PMOS transistor M21 are connected to the gate of the PMOS transistor M22. The PMOS transistors M21 and M22 constitute a current mirror circuit. The drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M23 and the input terminal of the NOT gate. The gate of the NMOS transistor M23 is supplied with an enable signal EN. The source and the back gate of the NMOS transistor M23 are connected to the ground potential. The output terminal of the NOT gate is connected to the gate of the NMOS transistor M24. The source and the back gate of the NMOS transistor M24 are connected to the ground potential.The drain of NMOS transistor M24 is connected to one end of resistor R24. The other end of resistor R24 ​​is connected to the collector of PNP bipolar transistor M25 and one end of resistor R10. The other end of resistor R10 is connected to ground. The second operational circuit 713E converts the current (I2-I). BURST ) and current I MULT Multiply them, and the result of the multiplication is the output current I. OUT The output is connected to resistor R10. Resistor R10 will control the output current I. OUT Converted to voltage K×V MULT (V2-V BURST Furthermore, the constant K is determined by the ratio of the resistance value of resistor R16 to the resistance value of resistor R10 in the first conversion circuit 713C, and the ratio of the resistance value of resistor R17 to the resistance value of resistor R10 in the second conversion circuit 713D. The current I3 output by the current source IS2 in the second operational circuit 713E is related to the voltage V. MULT The voltage is proportional to the peak (maximum) value. Additionally, the second operational circuit 713E can switch between a powered-on state and a disabled state via the power-on signal EN.

[0133] Figure 7 The resistor R10 shown is set with Figure 3 The resistor R10 in the shown offset voltage generating circuit 713A is the same. Therefore, an offset voltage V is also applied to resistor R10. OFFSET Therefore, the fourth voltage V4 generated in resistor R10 as the voltage across its two ends is expressed by the following formula.

[0134] V4=K×V MULT (V2-V BURST )+V OFFSET

[0135] Here, to illustrate the effect of PFC circuit 7, the circuit after removing the offset voltage generation circuit 713A from PFC circuit 7 will be compared with PFC circuit 7.

[0136] After removing the offset voltage generation circuit 713A from the PFC circuit 7, the first voltage V is generated by the operation of the drive circuit DRV1. H The on-time of the switching transistor M1 near 0 [V] becomes shorter. Therefore, the first voltage V H When the voltage is near 0V, the capacitor 6 located on the output side of the rectifier circuit 5 cannot be fully discharged. As a result, the current output from the rectifier circuit 5 temporarily stops, and the input current I... AC Distortion occurs (reference) Figure 8 (dashed line).

[0137] On the other hand, in PFC circuit 7, the first voltage VH When near 0 [V], the offset voltage V OFFSET As the voltage increases, the fourth voltage V4 also increases, thus, through the operation of the drive circuit DRV1, the on-time of the switching transistor M1 becomes longer. Therefore, the first voltage V... H When the voltage is near 0V, the capacitor 6 located on the output side of the rectifier circuit 5 can be fully discharged, resulting in a smooth output current from the rectifier circuit 5 and suppression of the input current I. AC Distortion (reference) Figure 8 (The solid line). In other words, IC700 can suppress the THD of PFC circuit 7.

[0138] In addition, due to the first voltage V H Outside of 0[V], there is no need to increase the offset voltage V. OFFSET Therefore, it is expected that, as in the described embodiment, the offset voltage V OFFSET Variable. However, it is also permissible to apply a first voltage V. H The useless offset voltage V outside of 0 [V] OFFSET Fixed offset voltage V OFFSET .

[0139] The comparator 702, overheat protection circuit 705, comparator 708, and comparator 709 are respectively fault detection circuits for detecting faults in IC 700. When a fault is detected by the fault detection circuit, the AND gate 721 stops the output of IC 700. Furthermore, in this embodiment, stopping the output of IC 700 means that the voltage applied to terminal OUT remains at a low level, and the switching action of the switching transistor M1 stops.

[0140] IC700 also includes a suppression circuit 727. The suppression circuit 727 suppresses the current consumption of IC700 when an anomaly is detected by the anomaly detection circuit.

[0141] Figure 10 This is a diagram illustrating an example of the suppression circuit 727. Figure 10 The suppression circuit 727 shown includes an OR gate 727A and an oscillator 727B.

[0142] The OR gate 727A supplies the logic sum of the low voltage block signal UVLO, the static overvoltage protection signal SOVP, the short circuit protection signal SP, and the overheat protection signal TSD to the oscillator 727B.

[0143] The oscillator 727B becomes a disabled state when the output signal of the OR gate 727A is at a high level, and does not output the clock signal CLK. On the other hand, the oscillator 727B becomes an enabled state when the output signal of the OR gate 727A is at a low level, and outputs the clock signal CLK. When the clock signal CLK is not supplied, the operation circuit 713 stops operating. Therefore, when an abnormality is detected by the abnormality detection circuit, the consumption current of the oscillator 727B and the operation circuit 713 can be suppressed, and further, the consumption current of the IC 700 can be suppressed. In addition, the clock signal CLK output from the oscillator 727B can be supplied to a logic circuit other than the operation circuit 713.

[0144] The IC 700 further includes an overvoltage detection circuit 728 and a current drawing circuit 729 Figure 9 (not shown in the figure).

[0145] Figure 11 is a diagram showing an example of the overvoltage detection circuit 728 and the current drawing circuit 729.

[0146] The overvoltage detection circuit 728 is a hysteresis comparator that compares the power supply voltage V CC with a threshold voltage, and outputs the comparison result to the switch 729B described later. If the power supply voltage V CC is equal to or higher than the threshold voltage, the output signal of the overvoltage detection circuit 728 becomes a high level (a level indicating an overvoltage), and if the power supply voltage V CC does not reach the threshold voltage, it becomes a low level (a level indicating a non-overvoltage). The threshold voltage used by the overvoltage detection circuit 728 is switched between a ninth threshold voltage V TH9 (e.g., 34 [V]) and a tenth threshold voltage V TH10 (e.g., 38 [V]) according to the level of the output signal of the overvoltage detection circuit 728.

[0147] The current drawing circuit 729 includes a constant current source 729A and a switch 729B. One end of the switch 729B is connected to the terminal VCC via the constant current source 729A. The other end of the switch 729B is connected to the terminal GND. The switch 729B is turned on when the output signal of the overvoltage detection circuit 728 is at a high level, and is turned off when the output signal of the overvoltage detection circuit 728 is at a low level. Therefore, the constant current source 729A draws a constant current from the terminal VCC only when the power supply voltage V CC is an overvoltage. In addition, unlike this embodiment, when the power supply voltage V CC is an overvoltage, the power supply voltage V CC may be made larger, and the current drawn from the terminal VCC can be made larger. In such a variation, for example, the power supply voltage V CCAn error amplifier that amplifies an error of the reference voltage, and a current source that outputs a current value corresponding to the output of the error amplifier are implemented.

[0148] Figure 12 is a timing chart showing a waveform of the power supply voltage V CC of the IC 700. In addition, Figure 12 In the IC 700, in order to compare, a waveform of the power supply voltage V CC of the conventional semiconductor integrated circuit device 101 is also illustrated.

[0149] In the IC 700, since the consumption current of the IC 700 is suppressed by the suppression circuit 727 when the switching operation of the switching transistor Ml is stopped, the power supply voltage V CC can be increased. Thus, the IC 700, unlike the conventional semiconductor integrated circuit device 101, can respond to the load variation at the second time point t2. That is, the IC 700 can improve the load response compared to the conventional semiconductor integrated circuit device 101.

[0150] Further, in the PFC circuit 7, the power supply voltage V CC is made larger when the switching operation of the switching transistor Ml is stopped than when the switching operation of the switching transistor Ml is not stopped. Thus, the load response can be further improved. For example, by making the constant current value output from the constant current source in the IC 700 smaller than the constant current value output from the constant current source of the conventional semiconductor integrated circuit device 101, the power supply voltage V CC can be made larger when the switching operation of the switching transistor Ml is stopped than when the switching operation of the switching transistor Ml is not stopped.

[0151] Since the IC 700 is provided with the overvoltage detection circuit 728 and the current extraction circuit 729, when the power supply voltage V CC becomes an overvoltage, the power supply voltage V CC can be reduced.

[0152] Further, since the reduction of the power supply voltage V CC can be suppressed in the case of using the IC 700, the capacitance of the capacitor C7 can be reduced. Thus, for example, the capacitor C7 can be set to a low-priced ceramic capacitor instead of an electrolytic capacitor.

[0153] Further, if the capacitance of the capacitor C7 is reduced, the charging time of the capacitor C7 becomes shorter when the power is connected to the electronic machine 1, so the start-up time of the electronic machine 1 can be shortened.

[0154] [Explanation of Symbols]

[0155] 1: electronic machine

[0156] 5: rectifier circuit

[0157] 7: power improvement circuit

[0158] 700: IC

[0159] 705: overheat protection circuit

[0160] 702, 708, 709: comparator

[0161] 710: error amplifier circuit

[0162] 713: arithmetic circuit

[0163] 715: comparator

[0164] 721: AND gate

[0165] 727: suppression circuit

Claims

1. A control circuit that is a control circuit of a power improvement circuit having a DC / DC converter, comprising: an input voltage detection terminal configured to receive a first voltage having a full-wave rectified waveform; an error amplifier circuit configured to amplify an error between a first detection voltage corresponding to an output voltage of the DC / DC converter and a reference voltage, and generate a second voltage; an operation circuit configured to generate a third voltage by multiplying the first voltage and the second voltage, and generate a fourth voltage by applying an offset voltage to the third voltage; and a drive circuit configured to turn on / off a switching transistor in accordance with an output of a comparator, and turn off the switching transistor whenever the second detection voltage is higher than the fourth voltage.

2. The control circuit according to claim 1, wherein the operation circuit is configured to make the offset voltage variable in such a manner that the higher the first voltage, the smaller the offset voltage.

3. The control circuit according to claim 2, wherein the operation circuit is configured to make the offset voltage variable in such a manner that the higher the first voltage, the more linearly the offset voltage decreases.

4. The control circuit according to any one of claims 1 to 3, wherein a minimum value of the offset voltage is zero or more. The comparator is configured to compare a second detection voltage corresponding to a current flowing in the switching transistor of the DC / DC converter with the fourth voltage.

5. The control circuit according to any one of claims 1 to 3, wherein the operation circuit comprises: a constant current circuit configured to generate a constant current; and a first current generation circuit configured to generate a first current corresponding to the first voltage; and the offset voltage is generated based on a current drawn from the constant current after the first current is drawn.

6. A power improvement circuit comprising: an output circuit of a DC / DC converter including a switching transistor; and the control circuit according to any one of claims 1 to 5 configured to drive the switching transistor.

7. An electronic device comprising: a rectification circuit configured to full-wave rectify an alternating voltage; and the power improvement circuit according to claim 6 configured to receive an output voltage of the rectification circuit. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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