Methods for completing programmable atomic transactions

Abstract

The present application relates to a method for completing a programmable atomic transaction. In some examples, methods, systems, computing devices, and machine-readable media are disclosed for defining instructions for a programmable atomic transaction. These instructions, when executed as the last instruction, terminate the executing thread, wait for all outstanding store operations to complete, clear a programmable atomic lock, and send a completion response back to the issuing process. This ensures that the programmable atomic lock is cleared upon completion of the transaction. By coupling thread termination with clearing the lock bit, this ensures that the thread cannot terminate without clearing the lock.

Description

[0001] Statement on government support

[0002] This invention was made with U.S. Government support under DARPA Agreement No. HR00111890003. The U.S. Government has certain rights in this invention. Technical Field

[0003] The present application generally relates to chiplets and more particularly to a method for performing programmable atomic transactions. Background Art

[0004] Chiplets are an emerging technology for integrating various processing functionalities. Typically, a chiplet system consists of precision modules (each referred to as a "chiplet") that are integrated on an interposer and, in many instances, interconnected via one or more established networks as needed to provide the desired functionality to the system. The interposer and the contained chiplets can be packaged together to facilitate interconnection with other components of the larger system. Each chiplet can include one or more individual integrated circuits or "chips" (ICs), which may be combined with discrete circuit components and commonly coupled to a respective substrate for attachment to the interposer. Most or all of the chiplets in the system will be individually configured to communicate via one or more established networks.

[0005] The configuration of chiplets as individual modules of a system differs from such systems implemented on a single chip containing different device blocks (e.g., intellectual property (IP) blocks) on a substrate (e.g., a single die), such as a system on a chip (SoC), or multiple discrete packaged devices integrated on a printed circuit board (PCB). In general, chiplets offer better performance (e.g., lower power consumption, reduced latency, etc.) than discrete packaged devices, and chiplets offer greater production benefits than single die chips. These production benefits can include higher yields or reduced development costs and time.

[0006] A chiplet system may include, for example, one or more application (or processor) chiplets and one or more support chiplets. The distinction between application chiplets and support chiplets here is merely a reference to possible design scenarios for a chiplet system. Thus, for example, a synthetic vision chiplet system may include (by way of example only) an application chiplet for generating synthetic vision output, and support chiplets such as a memory controller chiplet, a sensor interface chiplet, or a communication chiplet. In a typical use case, a synthetic vision designer may design the application chiplet and obtain the support chiplets from other parties. Thus, design expense (e.g., in terms of time or complexity) is reduced by avoiding the design and production of functionality included in the support chiplets. Chipsets also support the tight integration of IP blocks that might otherwise be difficult, such as IP blocks manufactured using different process technologies or with different feature sizes (or utilizing different contact technologies or pitches). Thus, assemblies of multiple ICs or IC assemblies with different physical, electrical, or communication characteristics can be assembled in a modular manner to provide an assembly that implements the desired functionality. A chiplet system may also facilitate adaptation to the needs of different larger systems into which the chiplet system will be incorporated. In an example, an assembly of ICs or other assemblies may be optimized for power, speed, or heat generation for a specific function, as might be the case with a sensor, and may be more easily integrated with other devices than attempting to integrate them on a single die. Additionally, by reducing the overall size of the die, the yield of the chiplets tends to be higher than that of more complex single-die devices. Summary of the Invention

[0007] In one aspect, the present application provides a device comprising: a memory array; a memory controller coupled to the memory array, the memory controller including an internal memory storing a locking structure for controlling access to one or more memory locations of the memory array; a programmable atomic unit coupled to the memory controller and including: an instruction memory configured to store one or more instruction sets; and a processor configured to: receive a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in the instruction memory; set a lock for a portion of the memory array in a locking structure of the internal memory of the memory controller, the lock preventing subsequent access to the portion of the memory array; execute the instruction set; and execute an instruction to terminate execution of the instruction set, the instruction to terminate execution of the instruction set including an operation to clear the lock.

[0008] On the other hand, the present application provides a method comprising: at a programmable atomic unit coupled to a memory controller and including a processor: receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of the programmable atomic unit; setting a lock in a locking structure of an internal memory of the memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of the memory coupled to the memory controller; executing the instruction set; and executing an instruction to terminate execution of the instruction set, the instruction to terminate execution of the instruction set comprising an operation to clear the lock.

[0009] In another aspect, the present application provides a non-transitory machine-readable medium storing instructions that, when executed by a machine, cause the machine to perform operations including: receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of a programmable atomic unit; setting a lock in a locking structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; executing the instruction set; and executing an instruction to terminate execution of the instruction set, the instruction to terminate execution of the instruction set including an operation to clear the lock. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0011] Figure 1A and 1B Examples of chiplet systems according to some examples of the present disclosure are described.

[0012] Figure 2 Components of an example memory controller chiplet according to some examples of the present disclosure are illustrated.

[0013] Figure 3 Components in an example of a programmable atomic unit (PAU) according to some examples of the present disclosure are described.

[0014] Figure 4 A request packet for requesting execution of a specific programmable atomic transaction according to some examples of the present disclosure is described.

[0015] Figure 5 A programmable atomic transaction response message according to some examples of the present disclosure is described.

[0016] Figure 6 A flowchart illustrating a method of executing a programmable atomic abort instruction according to some examples of the present disclosure.

[0017] Figure 7 Example termination instructions according to some examples of the present disclosure are described.

[0018] Figure 8 is a block diagram of a memory controller according to some examples of the present disclosure.

[0019] Figure 9 is a block diagram of an example of a machine with which, in which, or through which embodiments of the present disclosure may operate according to some examples of the present disclosure. DETAILED DESCRIPTION

[0020] FIG1 , described below, provides an example of a chiplet system and the components operating therein. As explained below, such a chiplet system may include a memory controller having a programmable atomic unit that executes a programmable atomic transaction comprising one or more instructions. The programmable atomic unit sets a lock at the start of a programmable atomic transaction, which provides exclusive memory access to one or more memory locations of a memory controlled by the memory controller. For example, if the programmable atomic transaction is an increment operation that increments the value of a specified memory location, the programmable atomic unit sets a lock on the specified memory location, which persists until the programmable atomic transaction completes. This lock is set by the programmable atomic unit at the start of the programmable atomic transaction and must be cleared upon completion of the programmable atomic transaction. If the lock is not cleared, future programmable atomic transactions requiring that specific lock will not be allowed to execute. In some examples, as disclosed herein, a terminate instruction is defined that, when executed as the last instruction of a programmable atomic transaction, terminates the executing thread, waits for all outstanding stores to complete, clears the programmable atomic lock, and sends a completion response back to the issuing processor. This ensures that the programmable atomic lock is cleared upon completion of the programmable atomic transaction.

[0021] In some examples, the termination instruction is included in the programmable atomic transaction instruction set, as supplied by the creator of the programmable atomic transaction (e.g., by a process on an application chiplet). The programmable atomic unit can check to ensure that the termination instruction is the last instruction in the instruction set and reject instruction sets that do not meet this condition. In other examples, the termination instruction is not included in the instruction set and is automatically performed by the processor of the programmable atomic unit after reaching the last instruction of the programmable atomic transaction or after a threshold number of instructions in the instruction set.

[0022] Figure 1A and 1B An example of a chiplet system 110 according to an embodiment is illustrated. Figure 1A1 is a representation of a chiplet system 110 mounted on a peripheral board 105, which can be connected to a wider computer system, for example, via Peripheral Component Interconnect Express (PCIe). The chiplet system 110 includes a package substrate 115, an interposer 120, and four chiplets: an application chiplet 125, a host interface chiplet 135, a memory controller chiplet 140, and a memory device chiplet 150. Other systems may include many additional chiplets to provide additional functionality, as will become apparent from the following discussion. The packaging of the chiplet system 110 is illustrated with a lid or cover plate 165, but other packaging techniques and structures for chiplet systems may be used. Figure 1B is a block diagram that labels components in a chiplet system for clarity.

[0023] The application chiplet 125 is illustrated as including a network-on-chip (NOC) 130 to support a chiplet network 155 for inter-chiplet communication. In an example embodiment, the NOC 130 may be included on the application chiplet 125. In an example, the NOC 130 may be defined responsive to the selected supporting chiplets (e.g., chiplets 135, 140, and 150), thus enabling the designer to select an appropriate number or chiplet network connections or switches for the NOC 130. In an example, the NOC 130 may be located on a separate chiplet, or even within the interposer 120. In examples as discussed herein, the NOC 130 implements a chiplet protocol interface (CPI) network.

[0024] CPI is a packet-based network that supports virtual channels to enable flexible and high-speed interaction between chiplets. CPI implements a bridge from the intra-chiplet network to the chiplet network 155. For example, the Advanced Extensible Interface (AXI) is a widely used specification for designing intra-chip communications. However, the AXI specification covers a large number of physical design options, such as the number of physical channels, signal timing, power, etc. Within a single chip, these options are typically selected to meet design goals, such as power consumption, speed, etc. However, in order to achieve flexibility in chiplet systems, adapters such as CPI are used to interface between various AXI design options that can be implemented in various chiplets. CPI bridges the intra-chiplet network across the chiplet network 155 by implementing a mapping of physical channels to virtual channels and encapsulating time-based signaling with a packetized protocol.

[0025] The CPI can use a variety of different physical layers to transmit packets. The physical layer may include simple conductive connections, or may include drivers to increase voltage or otherwise facilitate signal transmission over longer distances. An example of such a physical layer may include the Advanced Interface Bus (AIB), which in various instances may be implemented in interposer 120. The AIB uses source-synchronous data transfer with a forwarded clock to transmit and receive data. Packets are transmitted across the AIB at either single data rate (SDR) or double data rate (DDR) relative to the transmitted clock. The AIB supports various channel widths. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60, ...), and for DDR mode, the AIB channel width is a multiple of 40 bits (40, 80, 120, ...). The AIB channel width includes both transmit and receive signals. The channel can be configured to have a symmetrical number of transmit (TX) and receive (RX) input / outputs (I / Os), or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). A channel can act as an AIB master or slave depending on which chiplet provides the master clock. The AIB I / O unit supports three clock modes: asynchronous (i.e., unclocked), SDR, and DDR. In various examples, unclocked mode is used for clocks and some control signals. SDR mode can use a dedicated SDR-only I / O unit or dual-use an SDR / DDR I / O unit.

[0026] In an example, a CPI packet protocol (e.g., point-to-point or routable) can use symmetrical receive and transmit I / O cells within an AIB channel. The CPI stream protocol allows for more flexible use of AIB I / O cells. In an example, an AIB channel in stream mode can configure I / O cells as all TX, all RX, or half TX and half RX. The CPI packet protocol can use the AIB channel in either SDR or DDR operating modes. In an example, the AIB channel is configured in increments of 80 I / O cells (i.e., 40 TX and 40 RX) for SDR mode and in increments of 40 I / O cells for DDR mode. The CPI stream protocol can use the AIB channel in either SDR or DDR operating modes. Here, in an example, the AIB channel is configured in increments of 40 I / O cells for both SDR and DDR modes. In an example, each AIB channel is assigned a unique interface identifier. The identifier is used during CPI reset and initialization to determine paired AIB channels across adjacent chiplets. In this example, the interface identifier is a 20-bit value consisting of a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses the AIB out-of-band shift register to transmit the interface identifier. Bits 32-51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0027] The AIB defines a stacked set of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels, plus auxiliary channels. Auxiliary channels contain signals used for AIB initialization. All AIB channels within a column (except auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and the same number of data I / O signals). In this example, AIB channels are numbered in consecutive increasing order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX is defined as AIB channel zero.

[0028] Typically, the CPI interface on individual chiplets may include serialization-deserialization (SERDES) hardware. SERDES interconnects are well suited for scenarios requiring high-speed signaling and low signal counts. However, SERDES may incur additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy check (CRC)), link-level retries, or forward error correction. However, when low latency or energy consumption is a primary concern for ultra-short-distance chiplet-to-chiplet interconnects, a parallel interface with a clock rate that allows data transfer with minimal latency may be utilized. CPI includes elements for minimizing both latency and energy consumption for these ultra-short-distance chiplet interconnects.

[0029] CPI uses a credit-based technique for flow control. For example, a receiver, such as application chiplet 125, provides credits representing available buffers to a transmitter, such as memory controller chiplet 140. In this example, a CPI receiver contains a buffer for each virtual channel for a given transmit time unit. Thus, if a CPI receiver supports five messages and a single virtual channel at a time, the receiver has five buffers arranged in five rows (e.g., one row per unit of time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of a CPI packet.

[0030] As the sender transmits to the receiver, the sender decrements the available credits based on the transmission. Once all the credits of the receiver are used up, the sender stops sending packets to the receiver. This ensures that the receiver always has an available buffer to store the transmission.

[0031] When the receiver processes the received packets and frees up the buffer, the receiver communicates the available buffer space back to the sender. The sender can then use this credit back to allow the transmission of additional information.

[0032] Also illustrated is a chiplet mesh network 160 that uses direct chiplet-to-chiplet technology without the need for a NOC 130. The chiplet mesh network 160 can be implemented in CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 160 typically implements a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while the other chiplets in the pipeline interface only interface with themselves.

[0033] In addition, dedicated device interfaces, such as one or more industry-standard memory interfaces 145 (e.g., synchronous memory interfaces, such as DDR5, DDR 6), can also be used to interconnect the chiplets. The connection of the chiplet system or individual chiplets to external devices (e.g., a larger system) can be through a desired interface (e.g., a PCIE interface). In an example, the external interface can be implemented, for example, through a host interface chiplet 135, which, in the depicted example, provides a PCIE interface external to the chiplet system 110. When industry conventions or standards have converged on such dedicated interfaces 145, such interfaces are typically adopted. The illustrated example of a double data rate (DDR) interface 145 connecting the memory controller chiplet 140 to a dynamic random access memory (DRAM) memory device 150 is such an industry convention.

[0034] Of the many possible supporting chiplets, the memory controller chiplet 140 is likely to be present in the chiplet system 110 due to the almost ubiquitous use of memory for computer processing and the use of mature, advanced technologies for memory devices. Therefore, using memory device chiplets 150 and memory controller chiplets 140 produced by other technologies enables chiplet system designers to obtain robust products produced by mature manufacturers. Typically, the memory controller chiplet 140 provides a memory device specific interface to read, write, or erase data. The memory controller chiplet 140 can often provide additional features such as error detection, error correction, maintenance operations, or atomic operation execution. For some types of memory, maintenance operations are often specific to the memory device 150, such as garbage collection in NAND flash or storage class memory, temperature adjustment in NAND flash memory (e.g., cross temperature management). In an example, maintenance operations may include logical to physical (L2P) mapping or management to provide a level of indirection between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at some times by a host processor or memory controller and at other times by the DRAM memory device or logic associated with one or more DRAM devices, such as an interface chip (in an example, a buffer).

[0035] An atomic transaction is one or more data manipulation operations that can be performed, for example, by the memory controller chiplet 140. In other chiplet systems, atomic transactions can be performed by other chiplets. For example, an atomic transaction that specifies "increment" in a command that includes a memory address and possibly an increment value can be performed by the application chiplet 125. Upon receiving the command, the memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 140 provides an indication of command success to the application chiplet 125. Atomic transactions avoid transmitting data across the chiplet mesh network 160, thereby reducing the latency of executing such commands.

[0036] Atomic transactions can be categorized as built-in atomic or programmable (e.g., custom) atomic transactions. Built-in atomic transactions are a limited set of operations that are immutably implemented in hardware. Programmable atomic transactions are small programs with one or more instructions (e.g., instruction sets) that can be executed on a programmable atomic unit (PAU) (e.g., a custom atomic unit (CAU)) of the memory controller chiplet 140. FIG1 illustrates an example of a memory controller chiplet discussing the PAU.

[0037] Memory device chiplet 150 can be or include any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, random access memory (RAM), such as DRAM, synchronous DRAM (SDRAM), Graphics Double Data Rate Type 6 SDRAM (GDDR6 SDRAM), and the like. Examples of non-volatile memory devices include, but are not limited to, NAND flash memory, storage class memory (e.g., phase change memory or memristor-based technology), ferroelectric RAM (FeRAM), and the like. The illustrated example includes memory device 150 as a chiplet; however, memory device 150 may reside elsewhere, such as in a different package on peripheral board 105. For many applications, multiple memory device chiplets may be provided. In an example, these memory device chiplets may each implement one or more memory technologies. In an example, a memory chiplet may include multiple stacked memory dies of different technologies, such as one or more SRAM devices stacked or otherwise communicating with one or more DRAM devices. The memory controller 140 can also be used to coordinate operations between multiple memory chiplets in the chiplet system 110; for example, utilizing one or more memory chiplets in one or more levels of cache storage and using one or more additional memory chiplets as main memory. The chiplet system 110 can also include multiple memory controllers 140, such as can be used to provide memory control functionality for separate processors, sensors, networks, etc. For example, the chiplet architecture of the chiplet system 110 provides the advantage of allowing adaptation to different memory storage technologies and different memory interfaces through updated chiplet configurations without requiring redesign of the rest of the system architecture.

[0038] Figure 2Components of an example memory controller chiplet 205 according to an embodiment are illustrated. The memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., for communicating with off-die memory 275), a network communication interface 225 (e.g., for interfacing with a chiplet network 285 and communicating with other chiplets), and a set of atomic and coalescing units 250. Components of this set may include, for example, a write coalescing unit 255, a memory hazard unit 260, an internal atomic unit 265 (for performing internal atomic transactions), or a programmable atomic unit (PAU) 270 (for performing programmable atomic transactions). The various components are illustrated logically and are not necessarily implemented. For example, the internal atomic unit 265 may include different devices along the path to the off-die memory. For example, the internal atomic unit 265 may be in an interface device / buffer on the memory chiplet, as discussed above. In contrast, the programmable atomic unit 270 may be implemented in a separate processor on the memory controller chiplet 205 (but in various examples may be implemented in other locations, such as on a memory chiplet).

[0039] The off-die memory controller 220 is directly coupled to the off-die memory 275 (e.g., via a bus or other communication connection) to provide write operations and read operations to and from one or more off-die memories, such as the off-die memory 275 and the off-die memory 280. In the depicted example, the off-die memory controller 220 is also coupled to the atomic and merge unit 250 for output and to the cache controller 215 (e.g., a memory-side cache controller) for input.

[0040] In an example configuration, cache controller 215 is directly coupled to cache 210 and may be coupled to network communication interface 225 for input (eg, incoming read or write requests) and coupled for output to off-die memory controller 220 .

[0041] The network communication interface 225 includes a packet decoder 230, a network input queue 235, a packet encoder 240, and a network output queue 245 to support a packet-based chiplet network 285, such as CPI. The chiplet network 285 can provide packet routing between and among processors, memory controllers, mixed-thread processors, configurable processing circuits, or communication interfaces. In such packet-based communication systems, each packet typically includes destination and source addressing, as well as any data payload or instructions. In an example, depending on the configuration, the chiplet network 285 can be implemented as a collection of crossbar switches with a folded Clos configuration, or as a mesh network providing additional connectivity.

[0042] In various examples, the chiplet network 285 can be part of an asynchronous switching fabric. Here, data packets can be routed along any of a variety of paths, such that any selected data packet can reach its addressed destination at any of a number of different times, depending on the routing. Additionally, the chiplet network 285 can be implemented, at least in part, as a synchronous communication network, such as a synchronous mesh communication network. Both configurations of communication networks are contemplated for use in accordance with examples of the present disclosure.

[0043] The memory controller chiplet 205 may receive a packet with, for example, a source address, a read request, and a physical address. In response, the off-die memory controller 220 or cache controller 215 will read the data from the specified physical address (which may be in the off-die memory 275 or in the cache 210) and assemble a response packet with the source address containing the requested data. Similarly, the memory controller chiplet 205 may receive a packet with a source address, a write request, and a physical address. In response, the memory controller chiplet 205 will write the data to the specified physical address (which may be in the cache 210 or in the off-die memory 275 or 280) and assemble a response packet with the source address containing confirmation that the data was stored in memory.

[0044] Thus, when possible, the memory controller chiplet 205 can receive read and write requests via the chiplet network 285 and use the cache controller 215 interfaced with the cache 210 to process the requests. If the cache controller 215 cannot handle the request, the off-die memory controller 220 handles the request by communicating with the off-die memory 275 or 280, the atomic and merge unit 250, or both. As mentioned above, one or more levels of cache can also be implemented in the off-die memory 275 or 280; and in some such instances can be directly accessed by the cache controller 215. Data read by the off-die memory controller 220 can be cached by the cache controller 215 in the cache 210 for subsequent use.

[0045] The atomic and merge unit 250 is coupled to receive (as input) the output of the off-die memory controller 220 and provides the output to the cache 210, the network communication interface 225, or directly to the chiplet network 285. The memory hazard unit 260, the write merge unit 255, and the built-in (e.g., predetermined) atomic unit 265 can each be implemented as a state machine with other combinational logic circuitry (e.g., adders, shifters, comparators, AND gates, OR gates, XOR gates, or any suitable combination thereof) or other logic circuitry. These components can also include one or more registers or buffers to store operands or other data. The PAU 270 can be implemented as one or more processor cores or control circuitry, as well as various state machines with other combinational logic circuitry or other logic circuitry, and can also include one or more registers, buffers, or memories to store addresses, executable instructions, operands, and other data, or can be implemented as a processor. In Figure 3 Example PAU270 is shown in FIG.

[0046] The write-merge unit 255 receives the read data and the request data and merges the request data and the read data to produce a single unit with the read data and a source address to be used in the response or return packet. The write-merge unit 255 provides the merged data to the write port of the cache 210 (or equivalently, to the cache controller 215 for writing to the cache 210). Optionally, the write-merge unit 255 provides the merged data to the network communication interface 225 to encode and prepare the response or return packet for transmission on the chiplet network 285.

[0047] When the request data is for a built-in atomic operation, the built-in atomic unit 265 receives the request and reads the data from the write-merging unit 255 or directly from the off-die memory controller 220. The atomic transaction is performed and the resulting data is written to the cache 210 using the write-merging unit 255 or provided to the network communication interface 225 to encode and prepare a response or return data packet for transmission on the chiplet network 285.

[0048] The built-in atomic unit 265 handles predefined atomic transactions, such as extract and increment or compare and swap. In an example, these transactions perform simple read-modify-write operations on a single memory location of 32 bytes or less in size. Atomic memory transactions are initiated from a request packet transmitted via the chiplet network 285. The request packet has a physical address, an atomic operator type, an operand size, and optionally up to 32 bytes of data. Atomic transactions read-modify-write cache memory lines of the cache 210, filling the cache memory as necessary. Atomic transaction responses can be simple completion responses or responses with up to 32 bytes of data. Example atomic memory transactions include extract and, extract and or, extract and exclusive or, extract and add, extract and subtract, extract and increment, extract and decrement, extract and min, extract and max, extract and swap, and compare and swap. In various example embodiments, 32-bit and 64-bit operations are supported, as well as operations on 16 or 32 bytes of data. The methods disclosed herein are also compatible with hardware supporting larger or smaller operations and more or less data.

[0049] Built-in atomic transactions can also involve requests for "standard" atomic criteria regarding the requested data, such as relatively simple, single-cycle integer atomics, such as extract and increment or compare and swap, which have the same throughput as regular memory read or write operations that do not involve atomic operations. For these operations, the cache controller 215 can typically reserve a cache line in the cache 210 by setting a hazard bit (in hardware) so that the cache line cannot be read by another process while in transition. Data is obtained from off-die memory 275 or cache 210 and provided to the built-in atomic unit 265 for the requested atomic transaction. After the atomic transaction, in addition to providing the resulting data to the packet encoder 240 to encode an outgoing data packet for transmission on the chiplet network 285, the built-in atomic unit 265 also provides the resulting data to the write-merge unit 255, which also writes the resulting data to the cache 210. After writing the resulting data to the cache 210, the memory hazard unit 260 clears any corresponding hazard bits that were set.

[0050] The PAU 270 implements high performance (high throughput and low latency) for programmable atomic transactions (also referred to as "custom atomic transactions" or "custom atomic operations") that is comparable to the performance of built-in atomic transactions. Instead of performing multiple memory accesses, in response to an atomic transaction request specifying a programmable atomic transaction and a memory address, the circuitry in the memory controller chiplet 205 transmits the atomic transaction request to the PAU 270 and sets the hazard bit stored in the memory hazard register corresponding to the memory address of the memory row used in the atomic operation to ensure that no other operations (read, write, or atomic transaction) are performed on the memory row, and then clears the hazard bit after the atomic transaction is completed. The additional, direct data path provided to the PAU 270 for executing programmable atomic transactions allows additional write operations without being subject to any limitations imposed by the bandwidth of the communication network and without increasing any congestion on the communication network.

[0051] The PAU 270 includes a multi-threaded processor 320, such as a multi-threaded processor based on the RISC-V ISA, having one or more processor cores and further having an extended instruction set for executing programmable atomic transactions. With the extended instruction set for executing programmable atomic transactions, the processor 320 of the PAU 270 may be embodied as one or more mixed-threaded processors. In some example embodiments, the processor 320 of the PAU 270 provides barrel-style round-robin instantaneous thread switching to maintain a high instruction-per-clock rate.

[0052] PAU 270 may include local memory 305, such as static random access memory (SRAM), NAND, phase change memory, etc. Local memory 305 may include registers 335, instruction memory 325, and cache 330. Local memory 305 is accessible by processor 320 through memory controller 310.

[0053] Programmable atomic transactions can be performed by the PAU 270, involving requests for programmable atomic transactions regarding requested data. A user can prepare programming code in the form of one or more instructions to provide such programmable atomic transactions. For example, a programmable atomic transaction can be a relatively simple multi-cycle operation, such as a floating-point addition, or a relatively complex multi-instruction operation, such as a Bloom filter insert. Programmable atomic transactions can be the same as or different from predetermined atomic transactions, as long as they are defined by the user rather than the system vendor. For these operations, the cache controller 215 can reserve a cache line in the cache 210 by setting a hazard bit (in hardware) so that the cache line cannot be read by another process while in transition. Data is obtained from the cache 210 or the off-chip memory 275 or 280 and provided to the PAU 270 for performing the requested programmable atomic transaction. Following the atomic operation, the PAU 270 provides the resulting data to the network communication interface 225 to directly encode an outgoing data packet with the resulting data for transmission over the chiplet network 285. Additionally, PAU 270 provides the resulting data to cache controller 215, which also writes the resulting data to cache 210. After writing the resulting data to cache 210, cache controller 215 will clear any corresponding hazard bits that were set.

[0054] In the selected example, the approach taken for programmable atomic transactions is to provide a plurality of generic programmable atomic transaction request types that can be sent from an originating source, such as a processor or other system component, to the memory controller chiplet 205 via the chiplet network 285. The cache controller 215 or the off-die memory controller 220 identifies the request as a programmable atomic transaction and forwards the request to the PAU 270. In a representative embodiment, the PAU 270: (1) is a programmable processing element capable of efficiently performing user-defined atomic transactions; (2) can perform loads and stores on memory, arithmetic and logical operations, and control flow decisions; and (3) utilizes the RISC-V ISA with a new specialized instruction set to facilitate interaction with such controllers 215, 220 to perform user-defined transactions in an atomic manner. In a desirable example, the RISC-V ISA contains a complete instruction set supporting high-level language operators and data types. The PAU 270 may fully leverage the RISC-V ISA, but will typically support a more limited instruction set and a limited register file size to reduce the die size of the unit when included within a memory controller chiplet 205.

[0055] As mentioned above, the memory hazard clearing unit 260 clears the set hazard bit of the reserved cache line before writing the read data to the cache 210. Therefore, when the write-merging unit 255 receives the request and the read data, the memory hazard clearing unit 260 can send a reset or clear signal to the cache 210 to reset the set memory hazard bit of the reserved cache line. Furthermore, resetting this hazard bit will also release the pending read or write request involving the specified (or reserved) cache line, thereby providing the pending read or write request to the inbound request multiplexer for selection and processing.

[0056] Figure 3 A block diagram illustrating a programmable atomic unit 270 according to some examples of the present disclosure. As previously described, the programmable atomic unit may include one or more programmable atomic transactions specified by one or more atomic instruction sets stored in the instruction memory 325 that operate on memory managed by the memory controller. The instructions for the atomic transactions may be specified by an application and / or process external to the programmable atomic unit 270, which may reside on the memory controller chiplet 205, another chiplet (e.g., the application chiplet 125), or an off-chiplet device. In some examples, the instructions for the programmable atomic transactions are loaded by the operating system when registered by the process. To execute a programmable atomic transaction, the initiating process sends a CPI message containing instructions to execute the requested programmable atomic transaction on the local memory 305 of the programmable atomic unit 270 by providing an index into the local memory of the programmable atomic unit 270. The programmable atomic transaction may utilize the cache 330, registers 335, and other memory of the local memory 305 during execution. The local memory controller 310 may manage the local memory 305. In some examples, the programmable atomic unit 270 may not require a local memory controller because the local memory 305 may be SRAM.

[0057] When requesting execution of a specific programmable atomic transaction, the requesting processor may send a CPI request packet indicating a specific memory location within the programmable atomic unit (e.g., a partition within the local memory 305), the CPI request including the previously loaded programmable atomic instruction to be executed, the location of the memory managed by the memory controller chiplet 205 (e.g., off-die memory 275, 280) on which the operation is to be performed, and one or more variable parameters. The processor (e.g., processor 320) then begins executing the instruction at the indicated partition. Figure 4 Describes a request packet used to request the execution of a specific programmable atomic transaction. The fields are described as:

[0058]

[0059] A programmable atomic transaction begins by executing the first instruction at a partition of the programmable atomic transaction's instruction RAM (e.g., local memory 305 of the programmable atomic unit 270) specified by a custom atomic partition index (CaPIdx). The operation begins at the first instruction within the partition. CaPIdx can also be used to index into a control structure containing additional information for the operation. The additional information includes a flag indicating whether the transaction is valid, the number of partitions used for the transaction, and instruction execution restrictions. The number of partitions is used to verify that the operation is being executed in the appropriate partition. If execution in an inappropriate partition is detected, an exception is detected and execution of the operation is terminated.

[0060] Provides a response to a programmable atomic transaction as a memory response. For example, Figure 5 Description of the response message. The fields of the response message are as follows:

[0061]

[0062] The programmable atomic unit can set a lock before executing a programmable atomic transaction, which provides exclusive memory access to an address range of system memory (e.g., memory 275, 280) controlled by the memory controller. The lock can be automatically set when the programmable atomic transaction begins execution, and the lock must be cleared when the programmable atomic transaction completes. If the lock is not cleared, future programmable atomic transactions that require the specific lock bit will not be allowed to begin execution.

[0063] Disclosed in some examples are methods, systems, computing devices, and machine-readable media that define instructions for a programmable atomic unit that, when executed, terminate the executing thread, wait for all outstanding store operations to complete, clear the programmable atomic lock, and send a completion response back to the issuing process. This ensures that the programmable atomic lock is cleared upon transaction completion. By coupling thread termination with clearing the lock bit, this ensures that the thread cannot terminate without clearing the lock.

[0064] Figure 6Flowchart illustrating a method 600 for executing a programmable atomic transaction and terminating an instruction according to some examples of the present disclosure. At operation 605, a programmable atomic unit may receive an instruction to execute a programmable atomic transaction. As previously described, the instruction may specify one of a plurality of programmable atomic transactions stored within a memory of the programmable atomic unit that define operations to be performed for a particular programmable atomic transaction. The instruction may specify a particular programmable atomic transaction based on a memory partition identifier as previously described. At operation 610, a lock associated with a memory address having a programmable atomic transaction request may be set, the memory (e.g., off-die memory 275, 280) being controlled by a memory controller. In some examples, the lock may be applied to one or more memory locations, for example, a range of memory locations specified by a base address.

[0065] At operation 612, the programmable atomic unit may perform an instruction for a programmable atomic transaction. Such an instruction may include reading a value from a memory controlled by a memory controller of which the programmable atomic unit 270 is a part (e.g., off-die memory 275, 280). Such an instruction may operate on the value read from the memory and may store the modified value back to the memory (e.g., off-die memory 275, 280). Such operations provide reduced latency for the process calling the PAU. At operation 615, the last programmable atomic instruction of the programmable atomic transaction may be executed. The instruction may be a termination instruction. The instruction may wait for outstanding store operations at operation 620, clear a lock at operation 625, and send a response at operation 630. The response is shown in Figure 5 It can contain status code, operation result, etc.

[0066] In some examples, a lock can be a bit in a register (e.g., a register stored in registers 335), a value stored at a memory location (e.g., in local memory 305, off-die memory 275, 280), etc. A lock can be more complex and can store information about when the lock was set, the calling process that set the lock, etc. In some examples, a lock can be set and cleared by submitting a memory address to a hash function that indexes into a table that is linked to a list. A lock is set by adding a structure to the linked list that indicates the programmable atom that currently has the lock.

[0067] Figure 7 Instance termination instructions 700 are illustrated according to some examples of the present disclosure. Figure 7 The EMD Atomic Return (EAR) instruction shown in contains the following variable parameters:

[0068]

[0069] The RC2 suffix options are as follows:

[0070] RC2 encoding suffix Variable argument count 0 .R0 or no suffix 0 1 .R1 1 2 .R2 2

[0071] The example assembly will be as follows:

[0072] Instance Assembly annotation EAR.R0 #0Return variable parameters EAR.R1 rs1 #1 in rs1 returns the variable parameter EAR.R2 rs1,rs2 #2 in rs1 and rs2 returns the variable parameter

[0073] Figure 8 A schematic diagram illustrating a memory controller 800 according to some examples of the present disclosure. Figure 8 is another example of a memory controller 205 and is shown with Figure 2 2. For example, caches 820 and 885 are instances of cache 210; DRAM 845 is an instance of off-die memory 275-280; atomic / write-merging 880 and programmable atomic unit 895 may be instances of atomic and merging unit 250; Figure 8 Other components of the 2D memory controller 220 and the cache controller 215 may be, for example, Figure 2 805 receives requests from the on-chip network and provides a small number of queues. The atomic request queue 810 receives requests from the programmable atomic unit and provides a small number of queues. The inbound request multiplexer (IRM) 815 selects between the sources of inbound memory requests. The three sources are, in order of priority: memory hazard requests, atomic requests, and inbound NOC requests. Cache (read) 802 and cache (write) 885 are SRAM data caches. The figure shows the caches (802 and 885) as two separate blocks, one providing read access and the other providing write access. The delay block 825 provides one or more pipeline stages to simulate the delay for SRAM cache read operations. A cache miss requires an access to memory to bring the desired data into the cache. During this DRAM access time, the memory row is unavailable for other requests. The memory hazard block (set block 830 and clear block 890) maintains a table of hazard bits indicating which memory rows are unavailable for access. Inbound requests attempting to access a hazard row are held by the memory hazard block until the hazard is cleared. Once the hazard is cleared, the request is resent through the inbound request multiplexer. The memory row tag address is hashed into a hazard bit index. The number of hazard bits can be chosen to set the probability of hazard collision to a sufficiently low level. The inbound DRAM control multiplexer (IDCM) 835 selects from inbound NOC requests and cache eviction requests. Group Request Queue 840 - Each individually managed DRAM bank has a dedicated group request queue to hold requests until they can be scheduled on the associated DRAM bank.

[0074] Scheduler 842 selects requests for available DRAM groups across group request queues 840. DRAM 845 represents one or more external DRAM devices. Request hit data queue 850 holds request data from cache hits until selected. Request miss data queue 855 holds data read from DRAM until selected. Miss request queue 860 holds request packet information for cache misses until a request is selected. Hit request queue 865 holds request packet information for cache hits until selected. Data select multiplexer (DSM) 870 selects between DRAM read data and cache hit read data. The selected data is written to the SRAM cache. Request select multiplexer (RSM) 875 selects between hit request queue 860 and miss request queue 865.

[0075] Atomic / Write Merge 880 merges request data and DRAM read data, or, if the request is built-in atomic, the memory data and request data are used as input for the atomic operation. Cache (Write) block 885 represents the write port for the SRAM cache. Data from the NOC write request and data from the DRAM read operation are written to the SRAM cache. Memory Hazard (Clear) block 890 represents the hazard clear operation for the memory hazard structure. Clearing the hazard releases pending NOC requests and sends them to the inbound request multiplexer. Programmable Atomic Unit 895 handles programmable atomic transactions. NOC Outbound Response Multiplexer (ORM) 897 selects between the memory controller response and the custom atomic unit response and sends the selection to the NOC.

[0076] Figure 9A block diagram illustrates an example machine 900, which may be utilized, implemented in, or by any one or more of the techniques (e.g., methods) discussed herein. As described herein, an example may include or be operated by logic or multiple components or mechanisms within the machine 900. A circuit system (e.g., processing circuitry) is a collection of circuits implemented in the tangible physical form of the machine 900, comprising hardware (e.g., simple circuits, gates, logic, etc.). Circuit system membership may be flexible over time. A circuit system includes components that can perform specified operations individually or in combination during operation. In an example, the hardware of a circuit system may be permanently designed to perform a specific operation (e.g., hardwired). In an example, the hardware of a circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include machine-readable media that can be physically modified (e.g., magnetic properties of fixed, centralized particles, electrically movable placement, etc.) to encode instructions for a specific operation. When the physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor or vice versa. Instructions enable embedded hardware (e.g., an execution unit or loading mechanism) to generate components of a circuit system in the hardware via variable connections to perform portions of a specific operation when in operation. Thus, in an example, the machine-readable media element is part of the circuit system or is communicatively coupled to other components of the circuit system when the device is in operation. In an example, any one of the physical components may be used in more than one component in more than one circuit system. For example, in operation, an execution unit may be used in a first circuit in a first circuit system at one point in time and reused by a second circuit in the first circuit system, or reused by a third circuit in the second circuit system at a different time. The following are additional examples of these components of machine 900.

[0077] In some embodiments, the machine 900 may be connected (e.g., using a network) to other machines. In a networked deployment, the machine 900 may operate as a server machine, a client machine, or both in a server-client network environment. In one example, the machine 900 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 900 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, a network router, a switch, or a bridge, or any other machine capable of executing (sequentially or otherwise) instructions that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein (e.g., cloud computing, Software as a Service (SaaS), or other computer cluster configurations).

[0078] The machine (e.g., a computer system) 900 may include a hardware processor 902 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 904, a static memory (e.g., memory or storage for firmware, microcode, basic input and output (BIOS), a unified extensible firmware interface (UEFI), etc.) 906, and a mass storage device 908 (e.g., a hard drive, a tape drive, a flash memory device, or other block device), some or all of which may communicate with each other via an interconnect (e.g., a bus) 930. The machine 900 may further include a display unit 910, an alphanumeric input device 912 (e.g., a keyboard), and a user interface (UI) navigation device 914 (e.g., a mouse). In an example, the display unit 910, the input device 912, and the UI navigation device 914 may be a touch screen display. The machine 900 may further include a mass storage device (e.g., a drive unit) 908, a signal generating device 918 (e.g., a speaker), a network interface device 920, and one or more sensors 916, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 900 may include an output controller 928, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0079] The registers of the processor 902, main memory 904, static memory 906, or mass storage device 908 may be or include a machine-readable medium 922 having stored thereon one or more sets of data structures or instructions 924 (e.g., software) that embody or are utilized by any one or more of the techniques or functionality described herein. The instructions 924 may also reside, completely or at least partially, within any of the registers of the processor 902, main memory 904, static memory 906, or mass storage device 908 during execution thereof by the machine 900. In an example, one or any combination of the hardware processor 902, main memory 904, static memory 906, or mass storage device 908 may constitute the machine-readable medium 922. Although the machine-readable medium 922 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 924.

[0080] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by the machine 900 and causing the machine 900 to perform any one or more of the techniques disclosed herein, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, acoustic signals, etc.). In an example, a non-transitory machine-readable medium includes a machine-readable medium having a plurality of particles that have an invariant (e.g., rest) mass and are therefore a composition of matter. Thus, a non-transitory machine-readable medium is a machine-readable medium that does not include a transitory propagating signal. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0081] In an example, information stored or otherwise provided on machine-readable medium 922 may represent instructions 924, such as the instructions 924 themselves or a format from which instructions 924 may be derived. Such a format from which instructions 924 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), etc. The information representing instructions 924 in machine-readable medium 922 may be processed by processing circuitry into instructions to implement any of the operations discussed herein. For example, deriving instructions 924 from the information (e.g., processed by processing circuitry) may include compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, packaging, unpacking, or otherwise manipulating the information into instructions 924.

[0082] In an example, the derivation of instructions 924 may include (e.g., by processing circuitry) assembling, compiling, or interpreting information to create instructions 924 from some intermediate or pre-processed format provided by machine-readable medium 922. When the information is provided in multiple parts, it may be combined, unpacked, and modified to create instructions 924. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted when transmitted over the network and, if necessary, decrypted, uncompressed, assembled (e.g., linked), and compiled or interpreted at the local machine (e.g., into a stand-alone executable library, etc.) and executed by the local machine.

[0083] The instructions 924 may further be transmitted or received over a communication network 926 via the network interface device 920 using a transmission medium utilizing any of a number of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a network known as a cellular network). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as ), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, and the like. In an example, network interface device 920 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to communication network 926. In an example, network interface device 920 may include multiple antennas for wireless communication using at least one of single-input, multiple-output (SIMO), multiple-input, multiple-output (MIMO), or multiple-input, single-output (MISO) technology. The term "transmission media" shall be taken to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 900, and includes digital or analog communication signals or other intangible media used to facilitate the communication of such software. Transmission media is machine-readable media. To better illustrate the methods and apparatus described herein, a set of non-limiting example embodiments are set forth below as numbered examples.

[0084] Other Notes and Examples

[0085] Embodiment 1 is a device comprising: a memory array; a memory controller coupled to the memory array, the memory controller comprising an internal memory storing a locking structure for controlling access to one or more memory locations of the memory array; a programmable atomic unit coupled to the memory controller and comprising: an instruction memory configured to store one or more instruction sets; and a processor configured to: receive a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in the instruction memory; set a lock for a portion of the memory array in the locking structure of the internal memory of the memory controller, the lock preventing subsequent access to the portion of the memory array; execute the instruction set; and execute an instruction to terminate the execution of the instruction set, the instruction to terminate the execution of the instruction set comprising an operation to clear the lock.

[0086] In example 2, the subject matter of example 1 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

[0087] In example 3, the subject matter of examples 1-2 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to wait for outstanding store operations to complete before clearing the lock.

[0088] In Example 4, the subject matter of Examples 1 to 3 includes, wherein the instructions for terminating the execution of the set of instructions further include: an operation for waiting for outstanding storage operations to complete before clearing the lock; and an operation for sending a response to the process that sent the instructions for executing the set of instructions after performing the operation for waiting for outstanding storage operations to complete and the operation for clearing the lock.

[0089] In example 5, the subject matter of example 4 includes, wherein the response comprises one or more values ​​stored in a register of the programmable atomic unit.

[0090] In example 6, the subject matter of examples 1-5 includes, wherein the lock is a bitmap in a register of the programmable atomic unit.

[0091] In Example 7, the subject matter of Examples 1-6 includes wherein the memory array comprises one or more random access memory (RAM) banks.

[0092] Example 8 is a method comprising: at a programmable atomic unit coupled to a memory controller and including a processor: receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of the programmable atomic unit; setting a lock in a locking structure of an internal memory of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; executing the instruction set; and executing an instruction to terminate the execution of the instruction set, the instruction to terminate the execution of the instruction set comprising an operation to clear the lock.

[0093] In example 9, the subject matter of example 8 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

[0094] In example 10, the subject matter of examples 8-9 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to wait for outstanding store operations to complete before clearing the lock.

[0095] In Example 11, the subject matter of Examples 8 to 10 includes, wherein the instructions for terminating the execution of the set of instructions further include: an operation for waiting for outstanding storage operations to complete before clearing the lock; and an operation for sending a response to the process that sent the instructions for executing the set of instructions after performing the operation for waiting for outstanding storage operations to complete and the operation for clearing the lock.

[0096] In Example 12, the subject matter of Example 11 includes, wherein the response comprises one or more values ​​stored in a register of the programmable atomic unit.

[0097] In example 13, the subject matter of examples 8-12 includes wherein the lock is a bitmap in a register of the programmable atomic unit.

[0098] In Example 14, the subject matter of Examples 8-13 includes wherein the memory array comprises one or more random access memory (RAM) banks.

[0099] Example 15 is a non-transitory machine-readable medium storing instructions that, when executed by a machine, cause the machine to perform operations comprising: receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of a programmable atomic unit; setting a lock in a locking structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; executing the instruction set; and executing an instruction to terminate the execution of the instruction set, the instruction to terminate the execution of the instruction set comprising an operation to clear the lock.

[0100] In example 16, the subject matter of example 15 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

[0101] In Example 17, the subject matter of Examples 15-16 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to wait for outstanding store operations to complete before clearing the lock.

[0102] In Example 18, the subject matter of Examples 15 to 17 includes, wherein the instructions for terminating the execution of the set of instructions further include: an operation for waiting for outstanding storage operations to complete before clearing the lock; and an operation for sending a response to the process that sent the instructions for executing the set of instructions after performing the operation for waiting for outstanding storage operations to complete and the operation for clearing the lock.

[0103] In Example 19, the subject matter of Example 18 includes, wherein the response comprises one or more values ​​stored in a register of the programmable atomic unit.

[0104] In example 20, the subject matter of examples 15-19 includes, wherein the lock is a bitmap in a register of the programmable atomic unit.

[0105] In Example 21, the subject matter of Examples 15-20 includes wherein the memory array comprises one or more random access memory (RAM) banks.

[0106] Example 22 is a device comprising: means for receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of the programmable atomic unit; means for setting a lock in a locking structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; means for executing the instruction set; and means for executing an instruction to terminate the execution of the instruction set, the instruction to terminate the execution of the instruction set comprising an operation to clear the lock.

[0107] In example 23, the subject matter of example 22 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

[0108] In Example 24, the subject matter of Examples 22-23 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to wait for outstanding store operations to complete before clearing the lock.

[0109] In Example 25, the subject matter of Examples 22 to 24 includes, wherein the instructions for terminating the execution of the set of instructions further include: an operation for waiting for the completion of outstanding storage operations before clearing the lock; and an operation for sending a response to the process that sent the instructions for executing the set of instructions after performing the operation for waiting for the completion of outstanding storage operations and the operation for clearing the lock.

[0110] In Example 26, the subject matter of Example 25 includes, wherein the response comprises one or more values ​​stored in a register of the programmable atomic unit.

[0111] In example 27, the subject matter of examples 22-26 includes, wherein the lock is a bitmap in a register of the programmable atomic unit.

[0112] In Example 28, the subject matter of Examples 22-27 includes wherein the memory array comprises one or more random access memory (RAM) banks.

[0113] Example 29 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to operate to implement any of Examples 1-28.

[0114] Example 30 is an apparatus comprising means for implementing any of Examples 1-28.

[0115] Example 31 is a system for implementing any of Examples 1-28.

[0116] Example 32 is a method for implementing any one of Examples 1-28.

[0117] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the present invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples (or one or more aspects thereof) using any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0118] In this document, as is common in patent documents, the term "a" is used to include one or more than one, regardless of any other instances or uses of "at least one" or "one or more." In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "A or B" may include "A but not B," "B but not A," and "A and B." In the appended claims, the terms "comprising" and "in which" are used as colloquial equivalents of the corresponding terms "including" and "wherein." In addition, in the appended claims, the terms "comprising" and "including" are open, that is, systems, devices, objects, or processes that include elements other than those listed after such terms in the claim are still considered to be within the scope of the claim. In addition, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0119] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) can be used in combination with each other. For example, a person of ordinary skill in the art can use other embodiments after consulting the above description. It should be understood that the embodiments will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above detailed description, various features can be grouped together to simplify the present disclosure. This should not be interpreted as intending that unclaimed disclosed features are necessary for any claim. Instead, the subject matter of the present invention may lie in features that are less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and it is considered that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined by reference to the appended claims and the full scope of equivalents granted by such claims.

Claims

1. A device comprising: memory arrays; a memory controller coupled to the memory array, the memory controller including an internal memory storing a locking data structure for controlling access to one or more memory locations of the memory array; a programmable atomic unit coupled to the memory controller and comprising: an instruction memory configured to store one or more instruction sets; and a processor configured to: receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in the instruction memory; setting a lock for a portion of the memory array in the lock data structure of the internal memory of the memory controller, the lock preventing subsequent access to the portion of the memory array, setting the lock by adding a data structure to a table of a linked list indexed by a hash of a memory address of the portion of the memory array; executing the instruction set; and Instructions to terminate the execution of the set of instructions are executed, the instructions to terminate the execution of the set of instructions including an operation to clear the lock by deleting the data structure added to the table of the linked list indexed using a hash of the memory address of the portion of the memory array.

2. The apparatus of claim 1, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

3. The apparatus of claim 1, wherein the instructions to terminate the execution of the set of instructions further comprise an operation to wait for outstanding store operations to complete before clearing the lock.

4. The apparatus of claim 1 , wherein the instructions to terminate the execution of the set of instructions further comprise: An operation to wait for outstanding storage operations to complete before clearing the lock; as well as An operation for sending a response to a process that sent the instruction to execute the set of instructions after performing the operation to wait for completion of outstanding store operations and the operation to clear the lock.

5. The apparatus of claim 4, wherein the response comprises one or more values ​​stored in registers of the programmable atomic unit. The apparatus of claim 1 , wherein the lock is a bitmap in a register of the programmable atomic unit.

7. The apparatus of claim 1, wherein the memory array comprises one or more random access memory (RAM) banks.

8. A method comprising: At a programmable atomic unit coupled to a memory controller and comprising a processor: receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of the programmable atomic unit; setting a lock in a locking data structure of an internal memory of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller, the lock being set by adding the data structure to a table of a linked list indexed using a hash of a memory address of the portion of the memory array; executing the instruction set; as well as Instructions to terminate the execution of the set of instructions are executed, the instructions to terminate the execution of the set of instructions including an operation to clear the lock by deleting the data structure added to the table of the linked list indexed using a hash of the memory address of the portion of the memory array.

9. The method of claim 8, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

10. The method of claim 8, wherein the instructions to terminate the execution of the set of instructions further comprise operations to wait for outstanding store operations to complete before clearing the lock.

11. The method of claim 8, wherein the instructions to terminate the execution of the set of instructions further comprise: An operation to wait for outstanding storage operations to complete before clearing the lock; as well as An operation for sending a response to a process that sent the instruction to execute the set of instructions after performing the operation to wait for completion of outstanding store operations and the operation to clear the lock.

12. The method of claim 11, wherein the response comprises one or more values ​​stored in registers of the programmable atomic unit.

13. The method of claim 8, wherein the lock is a bitmap in a register of the programmable atomic unit.

14. The method of claim 8, wherein the memory array comprises one or more random access memory (RAM) banks.

15. A non-transitory machine-readable medium storing instructions that, when executed by a machine, cause the machine to perform operations comprising: receiving a command to execute an instruction set corresponding to a programmable atomic transaction, the instruction set stored in a memory of the programmable atomic unit; setting a lock in a locking data structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller, the lock being set by adding a data structure to a table of a linked list indexed using a hash of a memory address of the portion of the memory array; executing the instruction set; as well as Instructions to terminate the execution of the set of instructions are executed, the instructions to terminate the execution of the set of instructions including an operation to clear the lock by deleting the data structure added to the table of the linked list indexed using a hash of the memory address of the portion of the memory array.

16. The non-transitory machine-readable medium of claim 15, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

17. The non-transitory machine-readable medium of claim 15, wherein the instructions to terminate the execution of the set of instructions further comprise an operation to wait for outstanding store operations to complete before clearing the lock.

18. The non-transitory machine-readable medium of claim 15, wherein the instructions to terminate the execution of the set of instructions further comprise: An operation to wait for outstanding storage operations to complete before clearing the lock; as well as An operation for sending a response to a process that sent the instruction to execute the set of instructions after performing the operation to wait for completion of outstanding store operations and the operation to clear the lock.

19. The non-transitory machine-readable medium of claim 18, wherein the response comprises one or more values ​​stored in registers of the programmable atomic unit.

20. The non-transitory machine-readable medium of claim 15, wherein the lock is a bitmap in a register of the programmable atomic unit.

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