Method, device and readable storage medium for atomic modification of instruction sequence

Abstract

An embodiment of the present application provides a method, device, and readable storage medium for atomically modifying an instruction sequence, wherein the method includes: when the first thread determines to modify the first instruction sequence, obtaining the starting address corresponding to the target first instruction included in the first instruction sequence; the first thread modifies the target first instruction and obtains the second instruction corresponding to the target first instruction, and the second thread executes the second instruction corresponding to the target first instruction and then jumps to the starting address corresponding to the first first instruction; the first thread obtains the second instruction sequence based on the second instruction corresponding to the target first instruction and the other N‑1 first instructions included in the first instruction sequence. In a multi-threaded environment, the second thread executes the instruction sequence being modified. When it executes the target first instruction, the second thread will jump to the starting address corresponding to the first first instruction until the first instruction sequence is completely modified, thereby ensuring the atomic modification of the instruction sequence.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, and readable storage medium for atomically modifying an instruction sequence. Background Art

[0002] A virtual machine (VM) is a complete computer system with complete hardware system functionality, running in a completely isolated environment, simulated through software. VMs typically support an independent instruction set, known as the VM instruction set. A VM relies on a local physical machine, using its execution engine to simulate the execution of a given VM instruction sequence on the local physical machine. VM execution engines include interpreters and compilers. Interpreters fetch, decode, and execute VM instructions individually, while compilers compile a continuous sequence of VM instructions into a native machine instruction sequence. When compiling a continuous VM instruction sequence, compilers typically perform deep optimizations based on certain assumptions to maximize the quality of the resulting native machine instruction sequence. For these optimizations based on certain assumptions, the VM also generates corresponding condition monitoring statements. When an assumption no longer holds, the VM prevents the execution of the native machine instruction sequence previously generated based on that assumption. In the prior art, VMs typically modify a compiled instruction sequence by modifying several instructions at the beginning of the sequence to jump to a fixed processing routine. In a multi-threaded environment, to ensure multi-threaded safety, atomic modifications must be implemented when modifying a compiled instruction sequence to ensure correct program execution. Atomic modification of instructions means that the instruction sequence executed by the executing thread is either exactly the instruction sequence before the modification or exactly the instruction sequence after the modification.

[0003] In the prior art, when implementing atomic modification of an instruction sequence, hardware memory access instructions are usually used. If the maximum atomic memory access instruction provided by the hardware is smaller than the total length of the instruction sequence to be modified, atomic modification of the instruction sequence cannot be implemented. Summary of the Invention

[0004] Embodiments of the present application provide a method, apparatus, and readable storage medium for atomically modifying an instruction sequence to implement atomic instruction sequence modification.

[0005] In a first aspect, an embodiment of the present application provides a method for atomically modifying an instruction sequence, comprising:

[0006] When the first thread determines to modify a first instruction sequence, it obtains a starting address corresponding to a target first instruction, wherein the first instruction sequence includes N first instructions, where N is a positive integer greater than 1, and the target first instruction is the first first instruction or the Nth first instruction included in the first instruction sequence;

[0007] The first thread modifies the target first instruction and obtains a second instruction corresponding to the target first instruction, wherein the second thread executes the second instruction corresponding to the target first instruction and then jumps to the first address corresponding to the first first instruction;

[0008] The first thread obtains a second instruction sequence according to the second instruction corresponding to the target first instruction and other N-1 first instructions included in the first instruction sequence.

[0009] In some possible designs, the first thread obtains the second instruction sequence according to the second instruction corresponding to the target first instruction and other N-1 first instructions included in the first instruction sequence, including:

[0010] The first thread modifies the other N-1 first instructions and obtains modified instructions corresponding to the other N-1 first instructions respectively;

[0011] The first thread obtains the second instruction sequence according to the second instruction corresponding to the target first instruction and the modified instructions corresponding to the other N-1 first instructions.

[0012] In some possible designs, if the target first instruction is the first first instruction included in the first instruction sequence;

[0013] The first thread modifies the other N-1 first instructions to obtain modified instructions corresponding to the other N-1 first instructions, including:

[0014] The first thread modifies the other N-1 first instructions according to a first preset order, and obtains second instructions corresponding to the other N-1 first instructions respectively, wherein the second thread jumps to the address corresponding to the first first instruction after executing each second instruction;

[0015] The first thread obtains the second instruction sequence according to the second instruction corresponding to the target first instruction and the second instructions corresponding to the other N-1 first instructions, including:

[0016] The first thread modifies the second instruction corresponding to the target first instruction and the second instructions corresponding to the other N-1 first instructions in accordance with the first preset order, and obtains N third instructions corresponding to the N first instructions respectively, and the second instruction sequence includes the N third instructions.

[0017] In some possible designs, the first preset order is an order from the Nth first instruction to the 1st first instruction.

[0018] In some possible designs, if the target first instruction is the Nth first instruction in the first instruction sequence;

[0019] The first thread modifies the other N-1 first instructions to obtain modified instructions corresponding to the other N-1 first instructions, including:

[0020] The first thread modifies the other N-1 first instructions and obtains third instructions corresponding to the other N-1 instructions respectively;

[0021] The first thread obtains the second instruction sequence according to the second instruction corresponding to the target first instruction and the modified instructions corresponding to the other N-1 first instructions, including:

[0022] The first thread modifies the second instruction corresponding to the Nth first instruction and obtains a third instruction corresponding to the Nth first instruction;

[0023] The first thread obtains the second instruction sequence according to the third instructions corresponding to the other N-1 first instructions and the third instruction corresponding to the Nth first instruction, where the second instruction sequence includes N third instructions.

[0024] In some possible designs, the first thread modifies the other N-1 first instructions to obtain third instructions corresponding to the other N-1 instructions, including:

[0025] The first thread modifies the other N-1 first instructions according to a second preset order to obtain third instructions corresponding to the other N-1 instructions respectively, wherein the second preset order is the order from the Nth first instruction to the 1st first instruction, or the order from the 1st first instruction to the Nth first instruction.

[0026] In some possible designs, when the first thread determines to modify the first instruction sequence, before obtaining the first address of the target first instruction included in the first instruction sequence, the following steps are further included:

[0027] Determining whether an assumption condition included in a monitoring statement corresponding to the first instruction sequence is established;

[0028] If it is determined that the assumption condition is not met, the first thread determines to modify the first instruction sequence.

[0029] In a second aspect, an embodiment of the present application provides an apparatus for atomically modifying an instruction sequence, comprising:

[0030] an acquisition module, configured to acquire a starting address corresponding to a target first instruction when determining to modify a first instruction sequence, wherein the first instruction sequence includes N first instructions, where N is a positive integer greater than 1, and the target first instruction is the first first instruction or the Nth first instruction included in the first instruction sequence;

[0031] a modification module, configured to modify the target first instruction to obtain a second instruction corresponding to the target first instruction; and obtain a second instruction sequence based on the second instruction corresponding to the target first instruction and the other N-1 first instructions included in the first instruction sequence;

[0032] The second thread executes the second instruction corresponding to the target first instruction and then jumps to the first address corresponding to the first first instruction.

[0033] In a third aspect, an embodiment of the present application provides an apparatus for atomically modifying an instruction sequence, comprising: a memory, a processor, and computer program instructions;

[0034] said memory storing said computer program instructions;

[0035] The processor executes the computer program instructions to perform the instruction sequence atomic modification method described in any one of the first aspects.

[0036] In a fourth aspect, an embodiment of the present application provides a readable storage medium, including: a program;

[0037] When the program is executed by a processor, it executes the instruction sequence atomic modification method described in any one of the first aspects.

[0038] The present application provides a method, device, and readable storage medium for atomically modifying an instruction sequence, wherein the method includes: when the first thread determines to modify the first instruction sequence, obtaining the first address corresponding to the target first instruction included in the first instruction sequence; the first thread modifies the target first instruction and obtains the second instruction corresponding to the target first instruction, and the second thread executes the second instruction corresponding to the target first instruction and then jumps to the first address corresponding to the first first instruction; the first thread obtains the second instruction sequence based on the second instruction corresponding to the target first instruction and the other N-1 first instructions included in the first instruction sequence. In a multi-threaded environment, the second thread executes the instruction sequence being modified. After the second thread executes the second instruction corresponding to the target first instruction, the second thread will jump to the first address corresponding to the first first instruction until the first instruction sequence is completely modified, thereby ensuring the atomic modification of the instruction sequence. Moreover, when the first thread modifies the first instruction sequence, the second thread may not perform locking, thereby improving overall processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0040] Figure 1 This is a flowchart of Example 1 of the method for atomically modifying an instruction sequence provided by this application;

[0041] Figure 2 This is a flowchart of Example 2 of the method for atomically modifying an instruction sequence provided by this application;

[0042] Figure 3 To adopt Figure 2 A schematic diagram of the instruction sequence change process when the method shown modifies the first instruction sequence;

[0043] Figure 4 This is a flowchart of Example 3 of the method for atomically modifying an instruction sequence provided by this application;

[0044] Figure 5 To adopt Figure 4 A schematic diagram of a process of changing an instruction sequence by modifying a first instruction sequence using the method shown;

[0045] Figure 6 This is a structural diagram of the first embodiment of the apparatus for atomically modifying an instruction sequence provided by the present application;

[0046] Figure 7This is a structural diagram of the second embodiment of the instruction sequence atomic modification device provided by this application;

[0047] Figure 8 This is a structural diagram of Example 3 of the instruction sequence atomic modification device provided in this application. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0049] In the prior art, atomic modification of instruction sequences typically requires the use of hardware memory access instructions. If the maximum atomic memory access instruction provided by the hardware is smaller than the total length of the instruction sequence to be modified, atomic modification of the instruction sequence cannot be achieved. For example, the instruction sequence to be modified consists of eight instructions, each 4 bytes long. In a standard MIPS architecture, the maximum atomic memory access length supported in a 64-bit system is 8 bytes, far smaller than the instruction length to be modified. Therefore, in a multi-threaded environment, the aforementioned method cannot achieve atomic modification of the instruction sequence.

[0050] In the prior art, there is also a method of achieving atomic modification of instruction sequences through "locking". Specifically, the execution thread is locked before performing a memory access operation and unlocked after the memory access operation. This method results in high resource consumption and low overall processing efficiency.

[0051] Therefore, the present application provides a method for atomic modification of an instruction sequence to achieve atomic modification of an instruction sequence. Due to the multi-threaded environment, when the modifying thread modifies the instruction sequence, the executing thread may execute the instruction sequence at the same time; if the modifying thread modifies part of the instructions in the instruction sequence, the modifying thread starts to execute the instruction sequence, and the modifying thread may not have completed the modification of the remaining instructions. The executing thread executes the instruction sequence with part of the instructions modified. This situation will cause the executing thread to jump to an illegal address, and thus the atomicity of the instruction sequence cannot be guaranteed. In this case, the present solution can jump to the specified address even if the executing thread executes the instruction sequence that has not been fully modified when the modifying thread has not completely modified the instruction sequence. Only when the modifying thread completes the modification of the instruction sequence, the executing thread will not jump to the specified address when executing the modified instruction sequence, thus ensuring the atomic modification of the instruction sequence. The specified address can be the address corresponding to the instruction at the head of the sequence.

[0052] The present application provides an atomic modification method for an instruction sequence: when determining to modify the first instruction sequence, obtain the first address corresponding to the target first instruction, and modify the target first instruction to be a second instruction that jumps to the specified address; then, modify the other first instructions in the first instruction sequence, and modify the second instruction corresponding to the target first instruction, thereby obtaining a modified instruction sequence.

[0053] The method for atomically modifying an instruction sequence provided by the embodiments of the present application achieves atomic modification of the instruction sequence, ensuring the accuracy of the execution result without relying on the atomic memory access instruction length provided by the hardware. Furthermore, the method provided by the embodiments of the present application does not require locking the execution thread, thereby improving overall processing efficiency and reducing resource waste.

[0054] Figure 1 This is a flowchart of Example 1 of the method for atomically modifying an instruction sequence provided in this application. The method for atomically modifying an instruction sequence provided in this application may be performed by the apparatus for atomically modifying an instruction sequence provided in this embodiment of the application. The apparatus for atomically modifying an instruction sequence may be implemented in any software and / or hardware manner. For example, the apparatus for atomically modifying an instruction sequence may include, but is not limited to, various electronic devices such as computers, smartphones, iPads, and servers.

[0055] like Figure 1 As shown, the method of this embodiment includes:

[0056] S101: When a first thread determines to modify a first instruction sequence, it obtains a first address corresponding to a target first instruction included in the first instruction sequence.

[0057] In some cases, when the compiler of a virtual machine compiles a virtual instruction sequence, it usually performs deep optimization based on certain assumptions. If it is determined that the original assumptions do not hold, it is determined that the first instruction sequence needs to be atomically modified, and the first thread is called to obtain the starting address of the target first instruction. The first thread is a thread used to modify the first instruction sequence. The first thread may also be called a modification thread, a first CPU thread, or other names. The first instruction sequence is the instruction sequence to be modified. The first instruction sequence includes N instructions, where N is a positive integer greater than 1.

[0058] Specifically, when the first thread determines to atomically modify the first instruction sequence, the first thread obtains the starting address of the target first instruction included in the first instruction sequence. Optionally, the target first instruction can be the first first instruction or the Nth first instruction included in the first instruction sequence. The starting address of the target first instruction obtained by the first thread can be a relative address of a register storing the target first instruction or an absolute address, which is not limited in this embodiment of the present application.

[0059] Optionally, the first address of the target first instruction may be passed to the first thread by the caller of the first thread.

[0060] S102: The first thread modifies the target first instruction according to the first address corresponding to the target first instruction, and obtains a second instruction corresponding to the target first instruction.

[0061] Specifically, the first thread modifies the instruction stored in the storage unit (eg, memory) corresponding to the first address of the target first instruction according to the first address of the target first instruction, thereby obtaining the second instruction corresponding to the target first instruction.

[0062] Illustratively, in this step, the first thread may modify the target first instruction according to the new assumption, thereby obtaining the second instruction corresponding to the target first instruction.

[0063] The second instruction corresponding to the target first instruction is a jump instruction, that is, the second thread instruction jumps to the first address corresponding to the first first instruction after executing the second instruction corresponding to the target first instruction. If the target first instruction is the first instruction included in the first instruction sequence, the second instruction corresponding to the target first instruction is an instruction that jumps to the target first instruction itself, and the second thread jumps to the first address corresponding to the target first instruction after executing the second instruction; if the target first instruction is the Nth first instruction included in the first instruction sequence, the second instruction corresponding to the target first instruction is an instruction that jumps to the first first instruction, that is, the second thread jumps to the first address corresponding to the first first instruction after executing the second instruction.

[0064] It should be noted that the second thread is an execution thread, and the second thread may be multiple threads.

[0065] S103: The first thread obtains a second instruction sequence according to the second instruction corresponding to the target first instruction and the other N-1 first instructions included in the first instruction sequence.

[0066] Specifically, after the first thread modifies the target first instruction, it can modify the other N-1 first instructions included in the first instruction sequence, and obtain the modified instructions corresponding to the other N-1 first instructions respectively; then, the first thread can obtain the second instruction sequence based on the second instruction corresponding to the target first instruction and the modified instructions corresponding to the other N-1 first instructions respectively, wherein the second instruction sequence is a modified instruction sequence. If the execution thread executes the second instruction sequence, the correct execution result can be obtained, thereby ensuring the safety of the thread.

[0067] Exemplarily, taking a first instruction sequence including eight first instructions, namely A1-A8, as an example, the instruction sequence atomic modification method provided in the embodiment of the present application is described in detail.

[0068] 1. The target first instruction is the first instruction A1

[0069] Specifically, the target first instruction is the first first instruction A1 included in the first instruction sequence. The first thread modifies first instruction A1 to obtain the second instruction B1 corresponding to first instruction A1. Next, the first thread modifies seven first instructions A2-A8, obtaining modified instructions C2-C8 corresponding to these seven first instructions. The first thread modifies second instruction B1 to C1, thereby obtaining a modified second instruction sequence, which includes eight instructions C1-C8. In a multi-threaded environment, the second thread may not perform locking. The second thread executes the modified instruction sequence and jumps to its own corresponding first address after executing second instruction B1. In other words, while modifying the first instruction sequence, the second thread loops and executes instructions in the address space corresponding to first instruction A1. After the modification of the first instruction sequence is complete, the second thread can execute the second instruction sequence, thus ensuring the atomic modification of the first instruction sequence and the accuracy of the second thread's execution results.

[0070] 2. The target first instruction is the first instruction A8

[0071] Specifically, if the target first instruction is instruction A8, the eighth instruction in the first instruction sequence, the first thread modifies instruction A8 to obtain the second instruction B8 corresponding to instruction A8. Next, the first thread modifies instructions A1-A7, obtaining modified instructions C1-C7 corresponding to these seven instructions. The first thread then modifies instruction B8 to C8, thereby obtaining a modified second instruction sequence consisting of instructions C1-C8. In a multi-threaded environment, the second thread can execute the modified instruction sequence without locking. After executing instruction B8, it jumps to the first address corresponding to instruction A1. In other words, while modifying the first instruction sequence, the second thread can loop through instructions in the address space corresponding to instructions A1-A8. After the modification of the first instruction sequence is complete, the second thread can execute the second instruction sequence, thus ensuring the atomic modification of the first instruction sequence and the accuracy of the second thread's execution results.

[0072] In this embodiment, when the first thread determines to modify the first instruction sequence, it obtains the starting address corresponding to the target first instruction included in the first instruction sequence; the first thread modifies the target first instruction, obtains the second instruction corresponding to the target first instruction, and the second thread executes the second instruction corresponding to the target first instruction and then jumps to the starting address corresponding to the first first instruction; the first thread obtains the second instruction sequence based on the second instruction corresponding to the target first instruction and the other N-1 first instructions included in the first instruction sequence.

[0073] In a multithreaded environment, conventional techniques typically implement locks when modifying instruction sequences. This lock is applied before a thread performs a memory access and unlocked afterward. This approach results in significant resource overhead for each memory access simulation, leading to lower overall processing efficiency. However, with this solution, in a multithreaded environment, while the first thread modifies the first instruction sequence, the second thread does not need to perform locks, thereby improving overall processing efficiency. Furthermore, when the second thread executes the modified instruction sequence and reaches the first address corresponding to the target first instruction, it will always jump to the first address corresponding to the first first instruction, ensuring atomic modification of the instruction sequence.

[0074] Optionally, in Figure 1 Based on the embodiment shown, in S101, when the first thread determines to modify the first instruction sequence, before obtaining the first address corresponding to the target first instruction included in the first instruction sequence, the following steps are further included:

[0075] S100: Determine whether the assumption condition included in the monitoring statement corresponding to the first instruction sequence is established.

[0076] Specifically, when compiling a virtual instruction sequence, the compiler of the virtual machine usually performs deep optimization based on certain assumptions. For this optimization based on several assumptions, the virtual machine usually generates corresponding assumption monitoring statements. Therefore, the first thread can determine whether atomic modification of the first instruction sequence is required by determining whether the assumptions included in the monitoring statements corresponding to the first instruction sequence are established.

[0077] For example, when the compiler compiles a virtual machine instruction sequence (expression: i=i+1), the compiler cannot determine the type of the object "i" in the expression. At this time, the compiler will make an assumption about the type of i. Since "1" in the expression is an integer, the compiler assumes that the type of i is an integer. The compiler also generates a monitoring statement for the assumption during compilation to handle the situation where the assumption fails.

[0078] During the actual execution of the program, if the actual type of "i" is an integer, the instruction sequence generated by the above compilation is successfully executed and the execution result is accurate. However, if the actual "i" passed in during the actual execution of the program is a floating-point number, the virtual machine will detect that the assumption condition "the type of i is an integer" does not hold. In this case, the translated instruction sequence needs to be modified to ensure the accuracy of the execution result.

[0079] Therefore, in this solution, whether the first instruction sequence needs to be atomically modified can be determined by monitoring whether the assumptions included in the monitoring statement corresponding to the first instruction sequence are met. In actual applications, the assumptions included in the monitoring statement may include one or more assumptions, which is not limited in this embodiment of the application.

[0080] In this solution, the target first instruction can be the instruction at the head of the first instruction sequence, that is, the first first instruction, or the first instruction at the end of the first instruction sequence, that is, the Nth first instruction. The following will introduce in detail how the first thread modifies the first instruction sequence in the above two cases.

[0081] Figure 2 This is a flow chart of the second embodiment of the method for atomically modifying an instruction sequence provided by this application. In this embodiment, the target first instruction is the first first instruction included in the first instruction sequence. Figure 2 As shown, the method of this embodiment includes:

[0082] S200: Determine whether the assumption condition included in the monitoring statement corresponding to the first instruction sequence is established.

[0083] S201: When a first thread determines to modify a first instruction sequence, it obtains a first address corresponding to a target first instruction included in the first instruction sequence.

[0084] In this embodiment, the target first instruction is the first first instruction included in the first instruction sequence.

[0085] S202: The first thread modifies the target first instruction according to the first address corresponding to the target first instruction, and obtains a second instruction corresponding to the target first instruction.

[0086] In this solution, steps S200-S202 and Figure 1 S100-S102 in the embodiment shown are similar, and can be referred to Figure 1 The detailed description of the illustrated embodiment will not be repeated here.

[0087] S203: The first thread modifies the other N-1 first instructions according to the first preset order, and obtains second instructions corresponding to the other N-1 first instructions respectively.

[0088] The first preset order is from the Nth first instruction to the 1st first instruction. That is, in this solution, after the first thread modifies the target first instruction to the second instruction, it modifies the other N-1 first instructions in reverse order to obtain the second instructions corresponding to the other N-1 first instructions.

[0089] The second instructions corresponding to the other N-1 first instructions are all instructions for jumping to the first address corresponding to the first first instruction.

[0090] By modifying the other N-1 first instructions in reverse order using the method in this step, in a multi-threaded environment, the second thread will jump to the starting address of the first first instruction after executing any one of the second instructions corresponding to the other N-1 first instructions. Before the first instruction is modified, the second thread will continuously jump in a loop according to the N-1 second instructions, thereby ensuring the accuracy of the execution result.

[0091] S204. The first thread modifies the second instruction corresponding to the target first instruction and the second instructions corresponding to the other N-1 first instructions according to the first preset order, and obtains N third instructions corresponding to the N first instructions. The second instruction sequence includes N third instructions.

[0092] The first preset order is from the Nth first instruction to the 1st first instruction. That is, in this solution, after the first thread modifies N first instructions into N second instructions, it modifies the N second instructions in reverse order to obtain N second instructions and N third instructions. In this solution, the second instruction sequence including the N third instructions is the instruction sequence obtained by atomically modifying the first instruction sequence.

[0093] By modifying the N second instructions in reverse order using the method in this step, in a multi-threaded environment, if the N second instruction sequences have not all been modified, during the process of the second thread executing the instruction sequence, since the unmodified second instructions are all instructions that jump to the starting address of the first first instruction, before the N second instructions are all modified, the second thread is guaranteed to cyclically jump between the unmodified second instructions and the first second instruction, thereby ensuring the accuracy of the execution result.

[0094] For example, referring to Figure 3 As shown, the first instruction sequence includes eight first instructions, A1-A8. In step 1, the first thread modifies first instruction A1 to obtain second instruction B1 corresponding to first instruction A1. In step 2, the first thread modifies A8-A2 in reverse order to obtain second instructions B8-B2 corresponding to A8-A2, respectively. These second instructions B1-B8 are instructions that jump to the starting address of first instruction A1. In step 3, the first thread modifies them in reverse order to obtain third instructions C8-C1 corresponding to second instructions B8-B1, respectively, thereby obtaining a second instruction sequence. The second instruction sequence includes the third instructions C1-C8.

[0095] Modifying the first instruction sequence in the above manner has at least the following beneficial effects:

[0096] In a multi-threaded environment, when the first thread atomically modifies the first instruction sequence, the second thread (ie, the execution thread) may not lock, thereby reducing the resources required for each memory access simulation and improving overall processing efficiency.

[0097] In a multi-threaded environment, since the N second instructions are all instructions that jump to the starting address of the first first instruction, before the first instruction sequence is completely modified, the second thread will not cause execution result errors when executing the above instruction sequence, thereby ensuring the accuracy of the execution result.

[0098] In a multi-threaded environment, this embodiment adopts a reverse order modification method to further ensure the atomic modification of the instruction sequence, thereby ensuring the accuracy of the execution result.

[0099] Figure 4 This is a flow chart of the third embodiment of the method for atomically modifying an instruction sequence provided by this application. In this embodiment, the target first instruction is the Nth first instruction included in the first instruction sequence. Figure 4 As shown, the method of this embodiment includes:

[0100] S300: Determine whether the assumption condition included in the monitoring statement corresponding to the first instruction sequence is established.

[0101] S301: When a first thread determines to modify a first instruction sequence, it obtains a first address corresponding to a target first instruction included in the first instruction sequence.

[0102] In this embodiment, the target first instruction is the Nth first instruction included in the first instruction sequence.

[0103] S302: The first thread modifies the target first instruction according to the first address corresponding to the target first instruction, and obtains a second instruction corresponding to the target first instruction.

[0104] In this solution, steps S300-S302 and Figure 1 S100-S102 in the embodiment shown are similar, and can be referred to Figure 1 The detailed description of the illustrated embodiment will not be repeated here.

[0105] S303: The first thread modifies the other N-1 first instructions and obtains third instructions corresponding to the other N-1 first instructions.

[0106] The first thread may modify the other N-1 first instructions according to a first preset order, or may modify the other N-1 first instructions according to a second preset order, or may modify the other N-1 first instructions in a random order. The second preset order is the order from the first first instruction to the Nth first instruction, and the first preset order is the order from the Nth first instruction to the first first instruction, as described above. It should be noted that in this embodiment, there is no restriction on the order in which the first thread modifies the other N-1 first instructions.

[0107] S304: The first thread modifies the second instruction corresponding to the target first instruction, and obtains a third instruction corresponding to the target first instruction.

[0108] S305 . The first thread obtains a second instruction sequence according to the third instructions corresponding to the other N−1 first instructions and the third instruction corresponding to the target first instruction. The second instruction sequence includes N third instructions.

[0109] For example, referring to Figure 5 As shown, the first instruction sequence includes eight first instructions, A1-A8. In step 1, the first thread modifies first instruction A8 to obtain second instruction B8 corresponding to first instruction A8; wherein, the above second instruction B8 are all instructions that jump to the first address of first instruction A1. In step 2, the first thread modifies first instructions A1-A7 to obtain third instructions C1-C7 corresponding to first instructions A1-A7 respectively; in step 3, the first thread modifies second instruction B8 to third instruction C8, thereby obtaining a second instruction sequence, which includes the above third instructions C1-C8.

[0110] Modifying the first instruction sequence in the above manner has at least the following beneficial effects:

[0111] In a multi-threaded environment, when the first thread atomically modifies the first instruction sequence, the second thread (ie, the execution thread) may not lock, thereby reducing the resources required for each memory access simulation and improving overall processing efficiency.

[0112] In a multi-threaded environment, since the second instruction corresponding to the Nth first instruction is an instruction that jumps to the starting address of the first first instruction, before all of the first N-1 first instructions are modified, the second thread will jump to the starting address corresponding to the first first instruction as long as it executes the second instruction corresponding to the Nth first instruction. Therefore, during the process of the first thread modifying the first N-1 first instruction sequence, regardless of the order in which the modifications are made, the execution result of the second thread will not be affected. Moreover, the atomic modification of the instruction sequence is only completed when the second instruction corresponding to the Nth first instruction is modified to the correct third instruction. When the second instruction corresponding to the Nth first instruction is modified, the first N-1 first instructions have all been successfully modified to the correct third instruction. Therefore, the second thread will not cause an execution error when executing the first N-1 third instructions.

[0113] Figure 6 This is a structural diagram of the first embodiment of the instruction sequence atomic modification device provided by this application. Figure 6 As shown, the apparatus 100 of this embodiment includes: an acquisition module 101 and a modification module 102 .

[0114] The acquisition module 101 is configured to acquire a first address corresponding to a target first instruction when determining to modify a first instruction sequence, wherein the first instruction sequence includes N first instructions, where N is a positive integer greater than 1, and the target first instruction is the first first instruction or the Nth first instruction included in the first instruction sequence;

[0115] The modification module 102 is used to modify the target first instruction according to the first address corresponding to the target first instruction, obtain the second instruction corresponding to the target first instruction; and obtain the second instruction sequence according to the second instruction corresponding to the target first instruction and the other N-1 first instructions included in the first instruction sequence.

[0116] The second thread executes the second instruction corresponding to the target first instruction and then jumps to the first address corresponding to the first first instruction.

[0117] The device provided in this embodiment can be used to perform Figure 1 The technical solution of the method embodiment shown has similar implementation principles and technical effects, which will not be repeated here.

[0118] In some possible designs, the modification module 102 is specifically used to modify the other N-1 first instructions, obtain the modified instructions corresponding to the other N-1 first instructions respectively; and obtain the second instruction sequence based on the second instruction corresponding to the target first instruction and the modified instructions corresponding to the other N-1 first instructions.

[0119] In some possible designs, if the target first instruction is the first first instruction included in the first instruction sequence; the modification module is specifically used to modify the other N-1 first instructions according to the first preset order, and obtain the second instructions corresponding to the other N-1 first instructions respectively, wherein the second thread jumps to the address corresponding to the first first instruction after executing each of the second instructions; and modify the second instruction corresponding to the target first instruction and the second instruction corresponding to the other N-1 first instructions according to the first preset order, and obtain N third instructions corresponding to the N first instructions respectively, and the second instruction sequence includes the N third instructions.

[0120] In some possible designs, if the first preset order is an order from the Nth first instruction to the 1st first instruction.

[0121] In some possible designs, if the target first instruction is the Nth first instruction included in the first instruction sequence; the modification module 102 is specifically used to modify the other N-1 first instructions, and obtain the third instructions corresponding to the other N-1 instructions respectively; and modify the second instruction corresponding to the Nth first instruction, and obtain the third instruction corresponding to the Nth first instruction; and obtain the second instruction sequence based on the third instructions corresponding to the other N-1 first instructions and the third instruction corresponding to the Nth first instruction, and the second instruction sequence includes N third instructions.

[0122] In some possible designs, the modification module 102 is specifically used to modify the other N-1 first instructions according to a second preset order, and obtain the third instructions corresponding to the other N-1 instructions respectively, wherein the second preset order is the order from the Nth first instruction to the 1st first instruction, or the order from the 1st first instruction to the Nth first instruction.

[0123] In some possible designs, the method further includes: a monitoring module 103 for determining whether an assumption condition included in a monitoring statement corresponding to the first instruction sequence is satisfied; and if it is determined that the assumption condition is not satisfied, determining to modify the first instruction sequence.

[0124] The device provided in this embodiment can also be used to perform Figures 2 to 5The technical solutions of any of the method embodiments shown have similar implementation principles and technical effects, which will not be repeated here.

[0125] Figure 7 This is a schematic diagram of the structure of the second embodiment of the instruction sequence atomic modification device provided by this application. Figure 7 As shown, the apparatus 200 of this embodiment includes: a memory 201 and a processor 202;

[0126] The memory 201 may be an independent physical unit, and may be connected to the processor 202 via a bus 203. The memory 201 and the processor 202 may also be integrated together and implemented through hardware.

[0127] The memory 201 is used to store computer program instructions, and the processor 202 calls the computer program instructions to execute the above Figures 1 to 5 The operations of any method embodiment.

[0128] Optionally, when part or all of the methods of the above embodiments are implemented by software, the apparatus 200 may also include only the processor 202. The memory 201 for storing programs is located outside the apparatus 200, and the processor 202 is connected to the memory via circuits / wires to read and execute the programs stored in the memory.

[0129] The processor 202 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.

[0130] The processor 202 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0131] The memory 201 may include a volatile memory, such as a random-access memory (RAM); the memory may also include a non-volatile memory, such as a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory may also include a combination of the above types of memory.

[0132] Figure 8 This is a schematic diagram of the structure of the third embodiment of the apparatus for atomically modifying an instruction sequence provided by the present application. The apparatus for atomically modifying an instruction sequence 1200 provided in this embodiment may be, for example, a computer, a tablet device, a personal digital assistant, or the like.

[0133] Reference Figure 8 As shown, the instruction sequence atomic modification device 1200 may include one or more of the following components: a processing component 102, a memory 104, a power component 106, a multimedia component 108, an audio component 1010, an input / output (I / O) interface 1012, a sensor component 1014, and a communication component 1016.

[0134] The processing component 102 generally controls the overall operation of the instruction sequence atomic modification device 1200, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 102 may include one or more processors 1020 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 102 may include one or more modules to facilitate interaction between the processing component 102 and other components. For example, the processing component 102 may include a multimedia module to facilitate interaction between the multimedia component 108 and the processing component 102.

[0135] The memory 104 is configured to store various types of data to support the operation of the instruction sequence atomic modification device 1200. Examples of such data include instructions for any application or method operating on the instruction sequence atomic modification device 1200, contact data, phone book data, messages, pictures, videos, etc. The memory 104 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0136] The power supply component 106 provides power to various components of the instruction sequence atomicity modification apparatus 1200. The power supply component 106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the instruction sequence atomicity modification apparatus 1200.

[0137] The multimedia component 108 includes a screen that provides an output interface between the instruction sequence atomic modification device 1200 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 108 includes a front camera and / or a rear camera. When the three-dimensional model construction device 1200 of the target object is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0138] The audio component 1010 is configured to output and / or input audio signals. For example, the audio component 1010 includes a microphone (MIC) that is configured to receive external audio signals when the instruction sequence atomic modification device 1200 is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode. The received audio signals may be further stored in the memory 104 or transmitted via the communication component 1016. In some embodiments, the audio component 1010 further includes a speaker for outputting audio signals.

[0139] I / O interface 1012 provides an interface between processing component 102 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0140] The sensor assembly 1014 includes one or more sensors for providing various status assessments for the instruction sequence atomicity modification device 1200. For example, the sensor assembly 1014 can detect the open / closed state of the instruction sequence atomicity modification device 1200, the relative positioning of components, such as the display and keypad of the instruction sequence atomicity modification device 1200. The sensor assembly 1014 can also detect changes in the position of the instruction sequence atomicity modification device 1200 or a component of the instruction sequence atomicity modification device 1200, the presence or absence of user contact with the instruction sequence atomicity modification device 1200, the orientation or acceleration / deceleration of the instruction sequence atomicity modification device 1200, and changes in the temperature of the instruction sequence atomicity modification device 1200. The sensor assembly 1014 can include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 1014 can also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1014 can also include an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0141] The communication component 1016 is configured to facilitate wired or wireless communication between the instruction sequence atomicity modification device 1200 and other devices. The instruction sequence atomicity modification device 1200 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G or 4G, or a combination thereof. In an exemplary embodiment, the communication component 1016 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1016 may also include a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0142] In an exemplary embodiment, the instruction sequence atomicity modification device 1200 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to execute the above method.

[0143] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium includes a program, and when the program is executed by a processor, it executes the instruction sequence atomic modification method of any of the above embodiments.

[0144] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for atomically modifying an instruction sequence, characterized in that: include: When the first thread determines to modify a first instruction sequence, obtaining a starting address corresponding to a target first instruction, the first instruction sequence includes N first instructions, where N is a positive integer greater than 1, and the target first instruction is the first first instruction or the Nth first instruction included in the first instruction sequence; The first thread modifies the target first instruction according to the first address corresponding to the target first instruction, and obtains a second instruction corresponding to the target first instruction, wherein the second thread executes the second instruction corresponding to the target first instruction and then jumps to the first address corresponding to the first first instruction; The first thread modifies other N-1 first instructions included in the first instruction sequence, and obtains modified instructions corresponding to the other N-1 first instructions respectively; The first thread obtains a second instruction sequence according to the second instruction corresponding to the target first instruction and the modified instructions corresponding to the other N-1 first instructions.

2. The method according to claim 1, characterized in that If the target first instruction is the first first instruction included in the first instruction sequence; The first thread modifies the other N-1 first instructions included in the first instruction sequence, and obtains modified instructions corresponding to the other N-1 first instructions, including: The first thread modifies the other N-1 first instructions according to a first preset order, and obtains second instructions corresponding to the other N-1 first instructions respectively, wherein the second thread jumps to the address corresponding to the first first instruction after executing each second instruction; The first thread obtains the second instruction sequence according to the second instruction corresponding to the target first instruction and the second instructions corresponding to the other N-1 first instructions, including: The first thread modifies the second instruction corresponding to the target first instruction and the second instructions corresponding to the other N-1 first instructions in accordance with the first preset order, and obtains N third instructions corresponding to the N first instructions respectively, and the second instruction sequence includes the N third instructions.

3. The method according to claim 2, characterized in that The first preset order is an order from the Nth first instruction to the 1st first instruction.

4. The method according to claim 1, wherein If the target first instruction is the Nth first instruction in the first instruction sequence; The first thread modifies the other N-1 first instructions included in the first instruction sequence, and obtains modified instructions corresponding to the other N-1 first instructions, including: The first thread modifies the other N-1 first instructions and obtains third instructions corresponding to the other N-1 first instructions respectively; The first thread obtains the second instruction sequence according to the second instruction corresponding to the target first instruction and the modified instructions corresponding to the other N-1 first instructions, including: The first thread modifies the second instruction corresponding to the target first instruction and obtains the third instruction corresponding to the target first instruction; The first thread obtains the second instruction sequence according to the third instructions corresponding to the other N-1 first instructions and the third instruction corresponding to the target first instruction, where the second instruction sequence includes N third instructions.

5. The method according to claim 4, characterized in that The first thread modifies the other N-1 first instructions to obtain third instructions corresponding to the other N-1 first instructions, including: The first thread modifies the other N-1 first instructions according to a second preset order, and obtains the third instructions corresponding to the other N-1 first instructions respectively, wherein the second preset order is the order from the Nth first instruction to the 1st first instruction, or the order from the 1st first instruction to the Nth first instruction.

6. The method according to any one of claims 1 to 5, characterized in that When the first thread determines to modify the first instruction sequence, before obtaining the first address of the target first instruction included in the first instruction sequence, the method further includes: Determining whether an assumption condition included in a monitoring statement corresponding to the first instruction sequence is established; If it is determined that the assumption condition is not met, the first thread determines to modify the first instruction sequence.

7. An instruction sequence atomic modification device, characterized in that: include: an acquisition module, configured to acquire a starting address corresponding to a target first instruction when determining to modify a first instruction sequence, wherein the first instruction sequence includes N first instructions, where N is a positive integer greater than 1, and the target first instruction is the first first instruction or the Nth first instruction included in the first instruction sequence; a modification module, configured to modify the target first instruction according to the first address corresponding to the target first instruction, and obtain a second instruction corresponding to the target first instruction; and modify the other N-1 first instructions included in the first instruction sequence, and obtain modified instructions corresponding to the other N-1 first instructions respectively; The first thread obtains a second instruction sequence according to the second instruction corresponding to the target first instruction and the modified instructions corresponding to the other N-1 first instructions; The second thread executes the second instruction corresponding to the target first instruction and then jumps to the first address corresponding to the first first instruction.

8. An instruction sequence atomic modification device, characterized in that: include: memory, processors, and computer program instructions; said memory storing said computer program instructions; The processor executes the computer program instructions to perform the instruction sequence atomic modification method according to any one of claims 1 to 6.

9. A readable storage medium, characterized in that include: program; When the program is executed by a processor, the method for atomically modifying an instruction sequence as claimed in any one of claims 1 to 6 is executed.

Images