Computing system and method for sharing device memories of different computing devices

Abstract

A computing system comprises: a host computing device having a system memory page table stored thereon, the system memory page table representing a mapping relationship between a virtual address and a system physical address, the host device physical address being a part of the system physical address; a slave computing device coupled with the host computing device through a data bus to enable data interaction therebetween, the slave computing device having a slave device memory page table stored thereon, the slave device memory page table comprising at least a part of the system memory page table, the part being requested and received by the slave computing device from the host computing device according to a data access request of a processing procedure run by the slave computing device, and comprising a mapping relationship between a virtual address of the data requested to be accessed and a slave device physical address; and a slave address mapping management unit configured to convert the requested virtual address into the slave device physical address based on the slave device memory page table to allow the slave processor to access a corresponding slave storage unit to assist the host processor to run the processing procedure.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a computing system and a method for sharing device memory of different computing devices in the computing system. Background Technology

[0002] With the diversification of memory types, the device memory (or main memory) configured in current computer server hosts (hereinafter referred to as hosts) is gradually becoming insufficient to meet the needs of different types of applications in terms of capacity, performance, and characteristics. Therefore, a variety of computing devices and systems have emerged. Some computing devices can operate independently of the host device, possessing their own main memory and computing or processing units, interconnected only with the host device via various buses. Such independent computing devices are generally referred to as "discrete computing devices." For example, graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) are examples of discrete computing devices. They can assist the host processor in performing various data processing and calculations, and can also support multiple independent virtual computers (hereinafter referred to as virtual machines) on the host device through physical device virtualization.

[0003] However, in existing computing systems with multiple discrete computing devices, the efficiency of collaborative data access to device memory between different computing devices is low. Therefore, it is necessary to provide an improved method for sharing device memory. Summary of the Invention

[0004] One object of this application is to provide a method for sharing device memory of different computing devices in a computing system.

[0005] According to some aspects of this application, a computing system is provided, comprising: a host computing device, the host computing device including: a host processor for running one or more processing processes; a host device memory including a plurality of host storage units addressable and accessible via respective host device physical addresses, and the host device memory storing a system memory page table representing a mapping relationship between virtual addresses and system physical addresses for each processing process, the host device physical address being a part of the system physical address; and a host address mapping management unit for managing the system memory page table and, based on the system memory page table, converting a requested virtual address into a host device physical address in response to a data access request from a processing process running on the host processor, thereby allowing the processing process to access the corresponding host storage unit; and a slave computing device coupled to the host computing device via a data bus to achieve data interaction therebetween, the slave computing device including: a slave processor, which can be invoked by the host processor to assist the host processing... The host computer runs the processing process; a slave device memory includes multiple slave storage units addressable and accessible via separate slave device physical addresses, which are also part of the system physical address; wherein the slave device memory stores a slave device memory page table, which includes at least a portion of the system memory page table, the portion of which is a mapping relationship between virtual addresses and system physical addresses for the processing process requested and received by the slave computing device from the host computing device based on data access requests from its running processing process, and the slave device memory page table includes a mapping relationship between virtual addresses and slave device physical addresses of the requested data; and a slave address mapping management unit, which, in response to the data access requests of the processing process, translates the requested virtual address into a slave device physical address based on the slave device memory page table, so as to allow the slave processor to access the corresponding slave storage unit to assist the host processor in running the processing process.

[0006] In some embodiments, the slave device memory page table is updated as the system memory page table is updated.

[0007] In some embodiments, the processing process is a virtual machine process, and the virtual address is a virtual machine physical address provided by the virtual machine process; wherein, the host device memory further stores a virtual machine memory page table representing the mapping relationship between virtual machine virtual addresses and virtual machine physical addresses, and the slave device memory page table includes the mapping relationship between virtual machine virtual addresses and slave device physical addresses.

[0008] In some embodiments, the mapping relationship between each virtual address and the system physical address in the slave device memory page table is associated with the corresponding processing process, and the slave address mapping management unit only allows each processing process to access the corresponding system physical address based on the mapping relationship between its associated virtual address and the system physical address.

[0009] In some embodiments, the mapping relationship between each virtual address and system physical address in the slave device memory page table is associated with the corresponding processing process and access permissions. The slave address mapping management unit only allows each processing process to access the corresponding system physical address based on its associated mapping relationship between virtual address and system physical address and access permissions.

[0010] In some embodiments, the data access request includes a process identifier indicating the processing process requesting access and a virtual address requesting access.

[0011] According to another aspect of this application, a method for sharing device memory of different computing devices in a computing system is also disclosed. The computing system includes a host computing device having host device memory and slave computing devices having slave device memory. The host computing device and the slave computing devices are coupled to the host computing device via a data bus to achieve data interaction therebetween. The method includes: storing a system memory page table in the host device memory representing a mapping relationship between virtual addresses and system physical addresses for each processing process, wherein the system physical addresses include host device physical addresses for addressing and accessing host memory units in the host device memory, and slave device physical addresses for addressing and accessing slave memory units in the slave device memory; and storing a system memory page table in the slave device memory... The system memory page table stores a slave device memory page table, which includes at least a portion of the system memory page table. This portion of the system memory page table represents the mapping relationship between virtual addresses and system physical addresses for a processing process, which the slave computing device requests and receives from the host computing device based on a data access request from its running processing process. The slave device memory page table also includes the mapping relationship between the virtual address and the slave device physical address of the requested data. In response to a data access request from a processing process running on the slave processor, the slave address mapping management unit of the slave computing device translates the requested virtual address into a slave device physical address based on the slave device memory page table, allowing the slave processor to access the corresponding slave memory unit to assist the host processor in running the processing process.

[0012] The computing system of this application can share the device memory of slave computing devices coupled via the system's data bus with the host computing device and the virtual machine program running on it, unifying the host device memory into the system's physical address space. The host computing device can also establish a virtual machine virtual address space corresponding to the virtual machine program to achieve data access. Simultaneously, slave processors on the slave computing devices can also access local device memory using a portion of the virtual addresses mirrored in the virtual machine virtual address space. This unified address space access capability improves the flexibility of data distribution across different device memories and simplifies programming complexity. Furthermore, slave computing devices can directly access slave device physical addresses using their locally mirrored virtual addresses without requiring translation from virtual addresses to slave device physical addresses by the host computing device, improving the performance of local memory access and ensuring full utilization of the computing power of the slave computing devices.

[0013] Furthermore, the address mapping management unit (MMU) used in the slave computing device of this application has relatively simple functional requirements. It only needs to complete three functions: page table request, page table storage, and page table translation. It does not require complete MMU management functions, resulting in lower implementation costs. Moreover, since the mirrored page tables and data are all local to the slave computing device, the performance is also better.

[0014] In this application, the management of adding and deleting mirrored page tables is actually completed by the software running on the host computing device and the hardware and software of the slave computing device in collaboration. The host computing device or the virtual machine program running on it can set the correct data access permissions according to its own data and process situation. This access permission will also be automatically mirrored to the slave computing device, thereby ensuring the security of the slave computing device's access to local data.

[0015] The above is an overview of this application, and there may be simplifications, generalizations, and omissions of details. Therefore, those skilled in the art should recognize that this section is merely illustrative and not intended to limit the scope of this application in any way. This overview section is neither intended to identify the key or essential features of the claimed subject matter nor to serve as an aid in determining the scope of the claimed subject matter. Attached Figure Description

[0016] The above and other features of this application will become more fully clear through the following description and appended claims, in conjunction with the accompanying drawings. It is understood that these drawings depict only a few embodiments of the application and should not be construed as limiting the scope of the application. The application will be described more clearly and in more detail through the use of the drawings.

[0017] Figure 1 A computing system according to an embodiment of this application is shown;

[0018] Figure 2 A method for sharing device memory of different computing devices in a computing system is shown according to one embodiment of this application;

[0019] Figure 3 An example of the mapping relationship between virtual addresses and system physical addresses according to an exemplary embodiment of this application is shown;

[0020] Figure 4 A computing system according to another embodiment of this application is shown. Detailed Implementation

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. In the drawings, similar symbols generally denote similar components unless the context otherwise requires. The illustrative embodiments described in the detailed description, drawings, and claims are not intended to be limiting. Other embodiments and variations may be employed without departing from the spirit or scope of the subject matter of this application. It will be understood that various different configurations, substitutions, combinations, and designs can be made to the various aspects of the general description and illustrated in the drawings of this application, all of which explicitly form part of the subject matter of this application.

[0022] Figure 1 A computing system 100 according to one embodiment of this application is shown. Figure 1The illustrated computing system 100 exemplarily includes a host computing device 102 and a slave computing device 104, both of which have data processing and storage capabilities. In some other embodiments, the computing system may also include more slave computing devices, which can access and process their local data under the control of the host computing device. A data bus 103 is used to couple the host computing device 102 and the slave computing device 104 to enable data interaction between them. In some embodiments, the data bus 103 may conform to various data bus standards, such as PCI (Peripheral Component Interconnect), PCIe (Peripheral Component Interconnect express, including PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4 and future PCIe standards), CCIX (Cache Coherent Interconnect for Accelerators), CXL (Compute Express Link), Gen-Z (Generation Z standard), or USB standard (Universal Serial Bus).

[0023] like Figure 1 As shown, the host computing device 102 includes a host processor 106, which can run one or more processing processes. In some embodiments, each processing process can be assigned a process identifier to uniquely identify the process, so that the host computing device 102 and the slave computing device 104 can distinguish different processing processes based on the process identifier. It is understood that each processing process is a dynamic running activity and process of a program on the computing system 100. In some cases, a processing process can terminate execution after satisfying the termination conditions specified by its corresponding program; subsequently, if the program is invoked and a new dynamic processing process is created, the new processing process can be assigned a process identifier different from the previous processing process. On the other hand, if the execution of a processing process does not satisfy the termination conditions specified by its corresponding program, the process identifier corresponding to the processing process can be retained for identification of the processing process. The host computing device 102 also includes a host device memory 108, which may include multiple host storage units that can be addressed and accessed through separate host device physical addresses. In some embodiments, the multiple host storage units can be configured as one or more storage arrays or storage modules.

[0024] Similarly, slave computing device 104 includes a slave processor 114 that can be invoked by host processor 106 to assist host processor 106 in running some processing processes. Slave computing device 104 also has slave device memory 116, which may include multiple slave memory units that can be addressed and accessed via separate slave device physical addresses. In some embodiments, the multiple slave memory units may be configured as one or more memory arrays or memory modules. In some embodiments, slave computing device 104 may be, for example, a graphics processing unit (GPU) device or an FPGA accelerator card for processing display or graphics data.

[0025] exist Figure 1 In the illustrated embodiment, to facilitate shared data storage, the host device physical address of the host device memory 108 and the slave device physical address of the slave device memory 116 can be uniformly addressed, thereby forming a uniformly addressed system physical address space. In other words, the host device physical address and the slave device physical address are each a part of the system physical address space. Thus, during process execution, the host computing device 102 and the slave computing device 104 can access the host device memory 108 or the slave device memory 116 through the uniformly addressed system physical address, without requiring inter-device physical address translation.

[0026] Typically, before running a processing process, the host computing device 102 generates a virtual address space consisting of virtual addresses for that processing process, and only allows the processing process to access these virtual addresses, not direct access to physical addresses. Therefore, the host device memory 108 may store a system memory page table 110 representing the mapping relationship between virtual addresses and system physical addresses for each processing process, and the host computing device 102 is also equipped with a host address mapping management unit (host MMU) 112. Thus, when a processing process running on the host processor 106 needs to access the host device memory 108, the host MMU 112 can, based on the system memory page table 110, respond to the data access request issued by the running processing process by converting the requested virtual address into a host device physical address, thereby allowing the processing process to access the corresponding host memory unit. It is understood that the host computing device 102 or the slave computing device 104 (described below) may run multiple processing processes; correspondingly, the system memory page table 110 may include the mapping relationship between virtual addresses and system physical addresses associated with each of these processing processes. Generally, different processing processes do not share virtual addresses.

[0027] Similarly, the slave device memory 116 may store a slave device memory page table 118 representing the mapping relationship between virtual addresses and slave device physical addresses associated with at least a portion of the processing processes, and the slave computing device 104 is also provided with a slave address mapping management unit (slave MMU) 120. The slave device memory page table 118 includes at least a portion of the system memory page table 110, and this portion is a mapping relationship between virtual addresses and system physical addresses included in a portion of the system memory page table 110, which is requested and received by the slave processor from the host computing device 102 according to data access requests of the processing processes it is running, and is associated with the processing processes. Specifically, when the host computing device 102 instructs the slave computing device 104 to assist in running the processing processes, the slave processor 114 may need to access data stored in the slave device memory 116. In some embodiments, the host computing device 102 may provide the slave computing device 104 with the virtual address of data stored in the slave device memory 116 that the slave processor 114 is required to access, so that the slave computing device 104 can passively generate a data access request based on the virtual address. In other embodiments, the slave computing device 104 may proactively determine, based on the needs of the processing process it will run, that certain data stored in the slave device memory 116 needs to be accessed, and then determine the virtual address of this data to be accessed, thereby further generating a data access request based on the virtual address. Accordingly, the slave computing device 104 can send a data access request to the host computing device 102, including a virtual address corresponding to the data that is actively or passively requested for access. Upon receiving the data access request, the host computing device 102 can identify the virtual address of the requested data and send the mapping relationship between the virtual address and the slave device's physical address in the system memory page table 110 to the slave computing device 104. Then, the slave computing device 104 can store the received mapping relationship between the virtual address and the slave device's physical address in the slave device memory page table 118 in the slave device memory 116. In this way, the slave MMU 120 can translate the requested virtual address into a slave device physical address based on the address mapping relationship included in the slave device memory page table 118, so as to allow the processing process running by the slave processor 114 to access the corresponding slave memory unit.

[0028] As can be seen, in the above embodiments, the computing system 100 uniformly allocates and manages the system physical address spaces of the host computing device 102 and the slave computing device 104 to store data, and utilizes the slave device memory page table 118 to essentially "mirror" or copy a portion of the address mapping relationships related to the data required by the slave processor 114 in the system memory page table 110. This avoids large-scale data transfer between devices during process execution, improving device computing efficiency. Furthermore, the slave device memory 116 only needs to dynamically store a portion of the relevant address mapping relationships according to the actual processing needs, which also improves the page table utilization efficiency and reduces resource consumption.

[0029] Figure 2 A method 200 for sharing device memory of different computing devices in a computing system is illustrated according to an embodiment of this application. In some embodiments, the method 200 may be provided by... Figure 1 The computing system 100 shown is used to implement this. Next, in conjunction with… Figure 1 and Figure 2 The method 200 will be further explained.

[0030] It should be noted that in the computing system 100, the slave computing device 104 can share its local slave device memory 116 with the host computing device 102 via the data bus 103. This makes the slave device memory 116 logically considered as part of the host computing device 102's memory, meaning it, together with the host device memory 110, constitutes the system storage space or system physical address space. Correspondingly, the system physical address includes the host device physical address used to address and access host storage units in the host device memory 108, and the slave device physical address used to address and access slave storage units in the slave device memory 116. Theoretically, both the host processor 106 and the slave processor 114 can access the corresponding storage units through the system physical address. However, in practice, it is usually necessary to establish a corresponding virtual address space for each running process, and the process accesses the corresponding system physical address through the virtual address in the corresponding virtual address space.

[0031] Based on this, the method includes step 202, storing a system memory page table 110 in the host device memory 108 of the host computing device 102, representing the mapping relationship between virtual addresses and system physical addresses corresponding to system physical addresses, wherein each processing process is allocated a corresponding set of virtual addresses. Specifically, the operating system and applications of the host computing device 102 can manage and allocate the physical address space of all device memories or a portion thereof in the computing system 100, thereby establishing the system memory page table 110 and storing it in the host device memory 108. Depending on changes in the running state of the processing process or other running conditions or circumstances, the mapping relationship between virtual addresses and system physical addresses included in the system memory page table 110 may change, for example, by adding, reducing, or replacing them. When a processing process running on the host computing device 102 needs to access the host device memory 108, the host processor 106 responds to the data access request issued by the processing process and, through the host MMU 112, translates the requested virtual address into a host device physical address based on the system memory page table 110, thereby allowing the processing process to access the target physical address in the host device memory 108.

[0032] In some cases, host computing device 102 may delegate some or all of the processing tasks to slave computing device 104, whereby the slave processor 114 assists in executing the relevant tasks. Accordingly, when host computing device 102 instructs slave computing device 104 to run a specific processing process, and the running processing process needs to access slave device memory 116, computing system 100 may create a slave device memory page table 118 and store the slave device memory page table 118 on slave device memory 116, as shown in step 204.

[0033] Specifically, the slave computing device 104 can send a data access request carrying a corresponding virtual address to the host computing device 102. After receiving the data access request, the host computing device 102 can identify the virtual address of the data to be accessed and send the mapping relationship between the virtual address and the slave device physical address included in the system memory page table 110 to the slave computing device 104. Thus, the slave computing device 104 can store the received mapping relationship between the virtual address and the slave device physical address in the slave device memory 116 as the slave device memory page table 118.

[0034] In some embodiments, one or more processing processes currently running on the slave processor 114 of the slave computing device 104 that are requesting data can each be assigned a unique process identifier, which may be uniformly assigned by the operating system. The virtual addresses are also uniformly assigned based on the processing processes; that is, a given processing process can only access one or more specific virtual addresses assigned by the system. Therefore, the mapping relationship between virtual addresses and system physical addresses stored in the system memory page table 110 can also be associated with each processing process, and each processing process can only access the virtual address associated with it. Figure 3 An example of a mapping relationship between virtual addresses and system physical addresses according to an exemplary embodiment of this application is shown. For example, the process identifier ID "001" is only associated with virtual addresses "0x00400000-0x0040FFFF", meaning that the processing process identified by ID "001" can only access the aforementioned virtual addresses to obtain the corresponding data. It can be seen that each virtual address-physical address mapping relationship is also associated with the identifier of the processing process, and optionally with pre-defined access permissions (e.g., read, write, or execute / run). It is understood that access permissions can be like a whitelist of permitted permissions, meaning that access operations outside the listed access permissions are not allowed, such as... Figure 3 As shown; access permissions can also be similar to a blacklist, meaning that access operations not listed are not allowed. Access permissions will be explained further below.

[0035] Thus, during the process of establishing the slave device memory page table 118 as shown in step 204, the slave computing device 104 can carry a process identifier in the data access request. Correspondingly, the host computing device 102 can first verify the process identifier during the response to the data access request, and determine whether to provide the requested address mapping relationship to the slave device memory 116 based on the identifier verification result. Specifically, the host computing device 102 can query the mapping relationship corresponding to the process identifier pre-stored in the system memory page table 110 based on the process identifier carried in the data access request (e.g., ...). Figure 3 (As shown in the example). If the process identifier is found in the pre-stored mapping, it can be confirmed that the processing process corresponding to the data access request has passed the verification. It can be understood that if the verification fails, that is, the processing process carrying the identifier does not have access rights to the virtual address corresponding to the identifier, then the host computing device 102 may not provide the requested address mapping to the slave computing device 104; conversely, if the identifier verification is successful, then the host computing device 102 provides the requested address mapping to the slave computing device 104, thereby storing the corresponding slave device memory page table 118 in the slave device memory 116.

[0036] It is understood that in some embodiments, since the slave device memory page table 118 is a mirror page table established based on the mapping relationship (or memory page mapping entry) dynamically requested from the host computing device 102 by the processing process running on the slave computing device 104, it is not a complete page table relative to the system physical address space, but only a partial temporary mirror of a portion or all of the slave device physical addresses in the system memory page table 110 concerning the slave device memory 116. This mirror page table forms a mapping relationship between the virtual addresses generated on the host computing device 102 side and the physical addresses of the slave device memory 116 on the slave computing device 104 side.

[0037] Next, in step 206, in response to a data access request from a processing process running on the slave processor 114, the slave address mapping management unit 120 of the slave computing device 104 translates the requested virtual address into a slave device physical address based on the slave device memory page table 118, so as to allow the slave processor 114 to access the corresponding slave memory unit to assist the host processor 106 in running the processing process.

[0038] It is understandable that the slave device memory 118 can store similar... Figure 3 The multiple address mapping relationships shown allow the slave MMU 120 to look up the corresponding slave device physical address based on the processing process indicated by a specific process identifier and its requested virtual address, and accordingly instruct the slave processor 114 to access that slave device physical address. Figure 3 In the example shown, each address mapping also includes corresponding access permissions, such as readable, writable, or executable. In this case, when the slave MMU 120 queries the slave device's physical address in response to a data access request provided by the slave processor 114, it can further verify whether the access permissions of the data access request are consistent with the access permissions included in the slave device's memory page table: if they are inconsistent, it means that the data access request is not valid, and therefore the response to the data access request can be restricted or prohibited, that is, the slave processor 114 is not allowed to access the slave device's memory 116 based on the request; only when they are consistent with the access permissions are access operations allowed to continue.

[0039] It is understood that as the computing system 100 operates, one or more address mappings in the system memory page table 110 may be updated, such as becoming invalid / reduced, replaced, or added. Specifically, when address mappings involving one or more slave device physical addresses in slave device memory 116 are updated due to management by the host process or the operating system itself, the host computing device 102 may send an address update message to the slave computing device 104, containing the changes in the relevant address mappings. Upon receiving this message, the slave computing device 104 updates one or more corresponding address mappings in the slave device memory page table 118 stored in the slave device memory 116 to maintain the mirror consistency of the two page tables. It is important to note that in some cases, the update synchronization process of the system memory page table 110 and the device memory page table 118 may not be timely enough, resulting in inconsistencies between the two. For example, while the slave computing device 104 is currently accessing a virtual address mapping, the corresponding mapping in the system memory page table 110 may be being updated, leading to inconsistencies and unpredictable results. In some embodiments, such problems can be avoided through certain error correction or verification mechanisms.

[0040] Similarly, one or more address mappings in the system memory page table 110 may be updated. For example, the range of virtual addresses accessible to a processing process changes, or the access permissions for a specified virtual address change. In this case, in some embodiments, the host computing device 102 can notify the slave computing device 104 of an update after the address mapping is updated, and send the updated address mapping to the slave computing device 104; accordingly, the corresponding mapping in the slave device's memory page table 118 can be adjusted or updated based on the received updated address mapping. In other embodiments, the host computing device 102 can periodically notify the slave computing device 104 of mapping updates; the higher the update frequency, the more accurate the mirroring of the page tables between the host computing device 102 and the slave computing device 104. In some embodiments, to avoid the problem of asynchronous page table updates, the slave computing device 104 can, after querying the mappings stored in the slave device's memory page table 118 and finding that a data access request lacks permission, request the host computing device 102 to confirm the aforementioned verification based on the mappings stored therein.

[0041] In short, the slave device memory page table can be updated along with the system memory page table. It can be understood that when mappings in the system memory page table that are unrelated to the slave device memory are updated or changed, the slave device memory page table may not need to be updated.

[0042] Figure 4A computing system 400 according to one embodiment of this application is shown. Compared to Figure 1 The computing system 100 shown, Figure 4 The computing system 400 shown runs a virtual machine process or program 432, which can create a virtual machine memory page table 434, which includes a mapping relationship between virtual machine virtual addresses and virtual machine physical addresses. The virtual machine memory page table 434 can be similarly stored in the host device memory 408.

[0043] For other processing processes of the non-virtual machine program 432 running on the computing system 400, when they need the slave processor 414 of the slave computing device 404 to assist in the execution of the process and access the slave device memory 416, the operation process is similar to Figure 1 The operations related to the slave computing device 404 in the computing system 100 shown will not be described in detail here. The following mainly describes the operations when the virtual machine program 432 needs to call the slave computing device 404 to execute related processing processes.

[0044] As mentioned earlier, the virtual machine program 432 establishes a virtual machine memory page table 434 that indicates the mapping relationship between virtual machine virtual addresses and virtual machine physical addresses. Therefore, when the virtual machine program 432 accesses host device memory or slave device memory, it needs to deal with two levels of page tables, namely the virtual machine memory page table 434 and the system memory page table 410. When the virtual machine program 432 needs to access data stored in host device memory or slave device memory, the host MMU 412 uses the two levels of page tables 434 and 410 to first convert the virtual machine virtual address corresponding to the requested data to a virtual machine physical address, and then further converts the virtual machine physical address (which is still a virtual address, not a system physical address pointing to host device memory 408 or slave device memory 416) to a system physical address. It can be understood that, depending on the data storage location, the converted system physical address may be a host device physical address or a slave device physical address.

[0045] In some cases, slave computing device 404 may assist virtual machine program 432 in executing processing procedures and needs to access data stored in slave device memory 416. In this case, virtual machine program 432 can send a notification to host computing device 402 and slave computing device 404, indicating that data stored in slave device memory 416 may be accessed. Accordingly, host MMU 412 identifies the slave device physical address associated with the virtual machine virtual address through two levels of page tables, thereby sending the address mapping relationship between the virtual machine virtual address and the slave device physical address to slave computing device 404. Upon receiving the address mapping relationship, slave computing device 404 stores it in slave device memory 416 as at least a part of slave device memory page table 418. Afterwards, slave computing device 404 can send a data access request, including the virtual machine virtual address, to host computing device 402 as needed. Thus, slave processor 414 can access the corresponding slave device physical address based on slave device memory page table 418. It can be seen that although the host computing device 402 includes two levels of page tables, the slave device memory page table 418 can include only one level of page table. That is, the mapping relationship between the virtual machine's virtual address and the slave device's physical address is based on the fact that the host computing device 402 includes two levels of page tables. Alternatively, the slave device memory page table 418 can also include two levels of page tables, similar to the structure and correspondence of the two levels of page tables 434 and 410.

[0046] The computing system of this application can share the device memory of slave computing devices coupled via the system's data bus with the host computing device and the virtual machine program running on it, unifying the host device memory into the system's physical address space. The host computing device can also establish a virtual machine virtual address space corresponding to the virtual machine program to achieve data access. Simultaneously, slave processors on the slave computing devices can also access local device memory using a portion of the virtual addresses mirrored in the virtual machine virtual address space. This unified address space access capability improves the flexibility of data distribution across different device memories and simplifies programming complexity. Furthermore, slave computing devices can directly access slave device physical addresses using their locally mirrored virtual addresses without requiring translation from virtual addresses to slave device physical addresses by the host computing device, improving the performance of local memory access and ensuring full utilization of the computing power of the slave computing devices.

[0047] Furthermore, the MMU module used in the slave computing device of this application has relatively simple functional requirements, only needing to complete three functions: page table request, page table storage, and page table translation. It does not require complete MMU management functions, resulting in lower implementation costs. Moreover, since the mirrored page tables and data are all local to the slave computing device, the performance is also better.

[0048] In this application, the management of adding and deleting mirrored page tables is actually completed by the software running on the host computing device and the hardware and software of the slave computing device in collaboration. The host computing device or the virtual machine program running on it can set the correct data access permissions according to its own data and process situation. This access permission will also be automatically mirrored to the slave computing device, thereby ensuring the security of the slave computing device's access to local data.

[0049] The computational system and method of this application can be used in many applications. The following example illustrates the application of the computational system and method of this application using the "vector similarity comparison query" subsystem commonly used in recommendation systems.

[0050] In recommender systems, image and text query systems, it is often necessary to vectorize large amounts of raw data (text, speech, images, user history information, etc.) to form a feature vector database representing the raw data. Since feature vector databases are often very large and difficult to query, an index file for the feature vector database needs to be created. This allows for comparison and searching between the feature vectors of the data to be queried and the feature vector index file during subsequent use of the vector database, thus obtaining the matching relationship between the input query data and the original data.

[0051] In existing recommender system servers, the creation and indexing of the vector database for raw data can be completed by the host computing device (e.g., a central processing unit) and stored in its memory. The host processor or virtual machine program accesses the vector index file through the host MMU and the memory page tables in the host computing device (indicating the mapping between physical and virtual addresses), without involving the use of slave computing devices. When query computations need to be performed using slave computing devices with local memory, such as GPUs, for example, for comparing and searching query vector distances, the slave computing device needs to request data from the host computing device. In response to this request, the current index data block in the host device's memory needs to be copied to the slave computing device's local memory for matching computation with the input query vector. Existing recommender system servers need to repeatedly request index data blocks for each query request, which impacts the overall system performance and power consumption.

[0052] However, the computing system of this application can share the device memory of different computing devices and allows the host computing device and the processing processes running on it (such as virtual machine programs) to directly access the local memory of the slave computing devices. The vector database of raw data can be directly written to the slave device memory during initialization, thereby establishing a unified address space for the host and slave computing devices. When it is necessary to call the slave computing device to query the input query vector, the slave processor of the slave computing device requests the relevant address mapping relationship of the system memory page table from the host computing device and stores it locally. Then, it can directly and quickly perform address mapping and access local data. This simplifies the system's data access process and improves computing performance.

[0053] In the example above, the program or process running on the host computing device can directly write the generated vector index file into the virtualized host device memory. This process only involves the host software, system memory page tables, and host device memory, without requiring synchronization with the slave computing device. It can be seen that the virtualization of the memory in the slave computing device does not affect the host computing device's normal access to the host device memory.

[0054] When a slave computing device performs computational queries based on a portion of its stored vector index file, it does not need to repeatedly request the host computing device to copy the index file to the slave device's memory. Instead, it can automatically query the locally mirrored slave device memory page table based on the data access requests, including virtual addresses, issued by the slave processor. If a corresponding page table entry is missing, the slave computing device's MMU can request the page table entry from the host computing device once and mirror it in the slave device's memory page table. This mirror remains valid until the computation task ends. Thus, when the slave processor accesses the virtual address again during the execution of its computation task, the slave computing device can directly use the "mirror" stored in the slave device's memory page table for local translation. Furthermore, since the slave device memory is virtualized at the slave computing device, it is transparent to the processing processes running on both the host and slave computing devices. Both use the same starting address (virtual address) of the vector index file to access the data index and perform computations. This process minimizes the communication overhead between the host and slave computing devices, improving the system's computational efficiency.

[0055] It should be noted that although the computing system and methods for sharing device memory of different computing devices in the computing system are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules.

[0056] Those skilled in the art can understand and implement other modifications to the disclosed embodiments by studying the specification, the disclosure, the drawings, and the appended claims. In the claims, the word "comprising" does not exclude other elements and steps, and the words "a" or "an" do not exclude a plurality. In practical applications of this application, a single part may perform the function of multiple technical features referenced in the claims. Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A computing system, characterized in that, include: The host computing device includes: The host processor is used to run one or more processing processes. A host device memory includes a plurality of host memory units addressable and accessible via respective host device physical addresses, and the host device memory stores a system memory page table representing a mapping between virtual addresses and system physical addresses for each processing process, wherein the host device physical addresses are a portion of the system physical addresses; and The host address mapping management unit is used to manage the system memory page table and, based on the system memory page table, respond to the data access requests of the processing process running on the host processor by converting the requested virtual address into the host device physical address, so as to allow the processing process running on the host processor to access the corresponding host storage unit. A slave computing device, which is coupled to the host computing device via a data bus to achieve data interaction between them, includes: A slave processor, which can be invoked by the host processor to assist the host processor in running the processing process; A slave device memory includes multiple slave memory units addressable and accessible via separate slave device physical addresses, which are also part of the system physical address. The slave device memory stores a slave device memory page table, which includes at least a portion of the system memory page table. This portion of the system memory page table represents a mapping between the virtual addresses and system physical addresses of the processing processes running on the slave processor, requested and received by the slave computing device from the host computing device based on data access requests from the processing processes running on the slave processor. The slave device memory page table also includes a mapping between the virtual addresses and slave device physical addresses of the requested data. The slave address mapping management unit is used to respond to data access requests from the processing process running by the slave processor, and to translate the requested virtual address into a slave device physical address based on the slave device memory page table, so as to allow the slave processor to access the corresponding slave memory unit to assist the host processor in running the processing process. The host address mapping management unit is further configured to manage the system memory page table, and in response to data access requests from processing processes running on the host processor, the host address mapping management unit translates the requested virtual address into a slave device physical address based on the system memory page table to allow the processing processes running on the host processor to access the corresponding slave memory unit; and in response to data access requests from processing processes running on the slave processor, the slave address mapping management unit translates the requested virtual address into a host device physical address based on the slave device memory page table to allow the processing processes running on the slave processor to access the corresponding host memory unit to assist the host processor in running its processing processes.

2. The computing system according to claim 1, characterized in that, The slave device memory page table is updated as the system memory page table is updated.

3. The computing system according to claim 1, characterized in that, The processing process running on the host processor is a virtual machine process, and the virtual address is the virtual machine physical address provided by the virtual machine process; wherein, the host device memory also stores a virtual machine memory page table representing the mapping relationship between virtual machine virtual addresses and virtual machine physical addresses, and the slave device memory page table includes the mapping relationship between virtual machine virtual addresses and slave device physical addresses.

4. The computing system according to claim 1, characterized in that, The mapping relationship between each virtual address and the system physical address in the slave device memory page table is associated with the corresponding processing process. The slave address mapping management unit only allows each processing process to access the corresponding system physical address based on its associated mapping relationship between virtual address and system physical address.

5. The computing system according to claim 4, characterized in that, The mapping relationship between each virtual address and the system physical address in the slave device memory page table is associated with the corresponding processing process and access permissions. The slave address mapping management unit only allows each processing process to access the corresponding system physical address based on its associated mapping relationship between virtual address and system physical address and access permissions.

6. The computing system according to claim 4 or 5, characterized in that, The data access request includes a process identifier that indicates the processing process requesting access and a virtual address that is requested to be accessed.

7. A method for sharing device memory of different computing devices in a computing system, characterized in that, The computing system includes a host computing device with host device memory and slave computing devices with slave device memory. The host computing device and the slave computing devices are coupled to the host computing device via a data bus to achieve data interaction between them. The method includes: The host device memory stores a system memory page table representing the mapping relationship between virtual addresses and system physical addresses for each processing process, wherein the system physical addresses include host device physical addresses for addressing and accessing host memory units in the host device memory, and slave device physical addresses for addressing and accessing slave memory units in the slave device memory. In response to a data access request from a processing process running on a host computing device, the host address mapping management unit of the host computing device converts the requested virtual address into a host device physical address or a slave device physical address based on the system memory page table, so as to allow the host computing device to access the corresponding host storage unit or slave storage unit. The slave device memory stores a slave device memory page table, which includes at least a portion of the system memory page table. This portion of the system memory page table represents the mapping between virtual addresses and system physical addresses of the processing processes running on the slave device, which the slave computing device requests and receives from the host computing device based on data access requests from its running processes. Furthermore, the slave device memory page table includes the mapping between the virtual addresses and slave device physical addresses of the requested data. In response to a data access request from a processing process running on a slave computing device, the slave address mapping management unit of the slave computing device converts the requested virtual address into a host device physical address or a slave device physical address based on the slave device memory page table, so as to allow the slave computing device to access the corresponding host storage unit or slave storage unit to assist the host computing device in running the processing process.

8. The method according to claim 7, characterized in that, The processing process running on the host processor is a virtual machine process, and the virtual address is the virtual machine physical address provided by the virtual machine process; wherein, the host device memory also stores a virtual machine memory page table representing the mapping relationship between virtual machine virtual addresses and virtual machine physical addresses, and the slave device memory page table includes the mapping relationship between virtual machine virtual addresses and slave device physical addresses.

9. The method according to claim 7, characterized in that, The mapping relationship between each virtual address and the system physical address in the slave device memory page table is associated with the corresponding processing process. The slave address mapping management unit only allows each processing process to access the corresponding system physical address based on its associated mapping relationship between virtual address and system physical address.

10. The method according to claim 9, characterized in that, The mapping relationship between each virtual address and the system physical address in the slave device memory page table is associated with the corresponding processing process and access permissions. The slave address mapping management unit only allows each processing process to access the corresponding system physical address based on its associated mapping relationship between virtual address and system physical address and access permissions.

11. The method according to claim 9 or 10, characterized in that, The data access request includes a process identifier that indicates the processing process requesting access and a virtual address that is requested to be accessed.

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