Adaptive impedance matching circuit of PHY chip and working method thereof

Abstract

The present invention relates to an adaptive impedance matching circuit of a PHY chip and a working method thereof. The output end of the transmitting end of the PHY chip is connected to a MAC chip interface through a transmission line. The PHY chip includes a variable impedance transmitting circuit, which transmits the output signal from the output end after passing through a main driver of the variable impedance, and the main driver adjusts the impedance value of the variable impedance under the action of a control signal sequence; an impedance matching detection circuit, which converts the signal of the output end and the impedance matching state of the transmission line into a count value under the action of an enable signal and a clock signal, and selects a control signal sequence according to the count value. The present invention detects the signal waveform of the output end of the transmitting end, obtains the control signal sequence in the best matching state to control and adjust the impedance value of the variable impedance of the transmitting end, realizes source end impedance matching, and enables the chip to adapt to transmission lines with different impedance values.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet chips, and in particular to an adaptive impedance matching circuit and a working method thereof. Background Art

[0002] In the current common Ethernet communication equipment, the PHY (Physical Layer) layer communication and the MAC (Media Access Control) layer communication are implemented using two independent chips. The commonly used communication protocols between the PHY chip and the MAC chip include MII (Media Independent Interface), RMII (Reduced Media Independent Interface), GMII (Gigabit Media Independent Interface) and RGMII (Reduced Gigabit Media Independent Interface), etc. Their communication medium is the microstrip transmission line on the PCB (Printed Circuit Board).

[0003] Figure 1 This is an example of PHY chip 1 sending RXC clock to MAC chip 2, where ZS is the equivalent output impedance of the transmitter Tx, ZL is the equivalent input impedance of the receiver Rx, and ZT is the characteristic impedance of the transmission line. In communication protocols such as MII, RMII, GMII, and RGMII, the equivalent input impedance ZL of the receiver Rx is often designed to be high impedance to meet the signal amplitude requirements reaching the receiver Rx, while at the transmitter Tx, ZS is equal to ZT to achieve source impedance matching to reduce reflections and standing waves in microstrip signal transmission. In many application scenarios, PCB boards are often developed before chips. In the prior art, the output impedance of the transmitter Tx circuit is usually designed to be a fixed value during the chip development process. When such chips are applied to devices with different characteristic impedance values ​​of microstrip transmission lines, the transceiver signals between the Ethernet PHY chip and the MAC chip interface will be negatively affected by impedance mismatch, which deteriorates the signal transmission quality between the PHY chip and the MAC chip. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide an adaptive impedance matching circuit of a PHY chip; an object of the present invention is also to provide a working method of the adaptive impedance matching circuit of a PHY chip.

[0005] The adaptive impedance matching circuit of the PHY chip, the output end of the transmitting end of the PHY chip is connected to the MAC chip interface through a transmission line, and the PHY chip includes:

[0006] A variable impedance transmission circuit, which transmits an output signal from the output end through a variable impedance main driver, wherein the main driver adjusts the impedance value of the variable impedance under the action of a control signal sequence;

[0007] The impedance matching detection circuit is connected to the output end of the variable impedance sending circuit, and converts the signal of the output end and the impedance matching state of the transmission line into a count value under the action of an enable signal and a clock signal, and selects the control signal sequence according to the count value.

[0008] The adaptive impedance matching circuit of the present invention, the main driver comprises:

[0009] N PMOS tube branches are controllably connected in parallel between the power supply voltage terminal and the output terminal, including N PMOS driving tubes and N PMOS switch tubes, each of the PMOS driving tubes is connected to a PMOS switch tube;

[0010] N NMOS tube branches are controllably connected in parallel between the output terminal and the ground terminal, including N NMOS driving tubes and N NMOS switch tubes, each of the NMOS driving tubes is connected to an NMOS switch tube;

[0011] The gates of each of the PMOS switch tubes and each of the NMOS switch tubes are connected to a control signal, the gate of the i-th NMOS switch tube is connected to the i-th control signal, the gate of the i-th PMOS switch tube is connected to the inverted signal of the i-th control signal, i∈[1,N], the 1st control signal connected to the gate of the 1st NMOS switch tube to the Nth control signal connected to the gate of the N-th NMOS switch tube constitute the control signal sequence.

[0012] The adaptive impedance matching circuit of the present invention, the variable impedance sending circuit also includes a pre-driving stage inverter, the input end of the pre-driving stage inverter is connected to the output signal, and the output end of the pre-driving stage inverter is connected to the gates of the PMOS driving tube and the NMOS driving tube.

[0013] The adaptive impedance matching circuit of the present invention,

[0014] The source terminal of each of the PMOS driving tubes is connected to the power supply voltage terminal, the drain terminal of the PMOS driving tube is connected to the source terminal of the PMOS switch tube, and the drain terminal of the PMOS switch tube is connected to the output terminal;

[0015] The drain terminal of each NMOS switch tube is connected to the output terminal, the source terminal of the NMOS switch tube is connected to the drain terminal of the NMOS driving tube, and the source terminal of the NMOS switch tube is connected to the ground terminal.

[0016] The adaptive impedance matching circuit of the present invention, the impedance matching detection circuit comprises:

[0017] A resistor voltage divider circuit, comprising a predetermined number of voltage divider resistors connected between the power supply voltage terminal and the ground terminal, wherein points where different voltage divider resistors are connected lead out a first reference voltage divider, a second reference voltage divider and a third reference voltage divider respectively;

[0018] A first comparator, for comparing the voltage at the output end with the first reference divided voltage to generate a first comparison signal;

[0019] A second comparator, for comparing the voltage at the output terminal with the second reference divided voltage to generate a second comparison signal;

[0020] An XOR gate performs an XOR operation on the first comparison signal and the second comparison signal to output an impedance matching detection signal.

[0021] The adaptive impedance matching circuit of the present invention, the impedance matching detection circuit comprises:

[0022] A first MOS transistor, controllably connected between a current source and a first reference node under the control of the impedance matching detection signal;

[0023] A first capacitor connected between the first reference node and a ground terminal;

[0024] A second MOS transistor, controllably connected between the first reference node and the ground terminal under the action of a first control signal;

[0025] a third comparator, for comparing the third reference divided voltage with the voltage of the first reference node to generate a third comparison signal;

[0026] a NOR gate, performing a NOR logic operation on the third comparison signal and the first control signal to generate a first logic signal;

[0027] An AND gate, performing an AND logic operation on the first logic signal and the clock signal to generate a second logic signal;

[0028] A counter, wherein a clock terminal of the counter is connected to the second logic signal, a trigger terminal is connected to an enable signal, and the counter outputs a count value.

[0029] The adaptive impedance matching circuit of the present invention comprises a first inverter, which connects the enable signal to the control end of the second MOS tube.

[0030] In the adaptive impedance matching circuit of the present invention, the transmission line is a microstrip transmission line, and the characteristic impedance of the transmission line is 50 ohms, or 75 ohms, or 100 ohms.

[0031] In the adaptive impedance matching circuit of the present invention, the output end of the PHY chip is a port for transmitting MII and / or RMII and / or GMII and / or RGMII signals.

[0032] The working method of the adaptive impedance matching circuit of the PHY chip includes the following steps:

[0033] Step S1, setting all control signal sequences consisting of the first control signal to the Nth control signal to zero;

[0034] Step S2, adding 1 to the control signal sequence,

[0035] Step S3, the output signal is sent outward through the output terminal of the PHY chip;

[0036] Step S4, enabling the impedance matching detection circuit through an enable signal, and recording the corresponding count value output by the counter;

[0037] Step S5, determining whether the control signal sequence is all 1, if all are 1, executing step S6, if not all are 1, repeating step S2;

[0038] Step S6, selecting a control signal sequence corresponding to a minimum count value from all count values ​​and sending it to the variable impedance sending circuit.

[0039] Beneficial effect: The present invention detects the signal waveform of the output end SIG_pad of the transmitting end TX, obtains the control signal sequence in the best matching state to control and adjust the impedance value of the variable impedance VZS of the transmitting end TX, realizes source end impedance matching, and enables the chip to adapt to transmission lines with different impedance values. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a connection diagram of a PHY chip sending an RXC clock to a MAC chip in the prior art;

[0041] Figure 2 is a schematic diagram of a PHY chip interface circuit of a specific embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of a variable impedance transmitting circuit of a specific embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of an impedance matching detection circuit of a specific embodiment of the present invention;

[0044] Figure 5 The present invention Figure 4 Waveform diagram of important nodes in the graph;

[0045] Figure 6 It is a flow chart of a working method of a specific embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0048] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0049] Reference Figure 2 , an adaptive impedance matching circuit of the PHY chip, an output end SIG_pad of the transmitting end TX of the PHY chip 1 is connected to the MAC chip interface through a transmission line, and the PHY chip 1 includes,

[0050] The variable impedance transmitting circuit 11 transmits an output signal SIG_tx from the output terminal SIG_pad through a main driver DR with a variable impedance VZS. The main driver DR is in a control signal sequence K <n:1>The impedance value of the variable impedance VZS is adjusted under the action of;

[0051] The impedance matching detection circuit 12 is connected to the output terminal SIG_pad of the variable impedance transmission circuit 11, and converts the signal of the output terminal SIG_pad and the impedance matching state of the transmission line into a count value under the action of an enable signal EN and a clock signal CLK, and selects the control signal sequence K according to the count value. <n:1>.

[0052] The present invention detects the signal waveform of the output end SIG_pad of the transmitting end TX, obtains the control signal sequence in the best matching state to control and adjust the impedance value of the variable impedance VZS of the transmitting end TX, realizes source end impedance matching, and enables the chip to adapt to transmission lines with different impedance values.

[0053] The adaptive impedance matching circuit of the present invention refers to Figure 3 , the main drive DR includes,

[0054] N PMOS tube branches are controllably connected in parallel between the power supply voltage terminal VDD and the output terminal SIG_pad, including N PMOS driving tubes and N PMOS switch tubes, and each PMOS driving tube is connected to a PMOS switch tube;

[0055] N NMOS tube branches are controllably connected in parallel between the output terminal SIG_pad and the ground terminal GND, including N NMOS driving tubes and N NMOS switch tubes, and each NMOS driving tube is connected to an NMOS switch tube;

[0056] The gates of each PMOS switch tube and each NMOS switch tube are connected to a control signal, the gate of the i-th NMOS switch tube is connected to the i-th control signal, the gate of the i-th PMOS switch tube is connected to the inverted signal of the i-th control signal, i∈[1,N], the first control signal connected to the gate of the first NMOS switch tube to the N-th control signal connected to the gate of the N-th NMOS switch tube constitutes a control signal sequence K <n:1>.

[0057] The adaptive impedance matching circuit of the present invention, the variable impedance sending circuit also includes

[0058] A pre-driving stage inverter INV_PDR, an input end of the pre-driving stage inverter INV_PDR is connected to the output signal SIG_tx, and an output end of the pre-driving stage inverter INV_PDR is connected to the gates of the PMOS driving tube and the NMOS driving tube.

[0059] The source terminal of each PMOS driving tube is connected to the power supply voltage terminal VDD, the drain terminal of the PMOS driving tube is connected to the source terminal of the PMOS switch tube, and the drain terminal of the PMOS switch tube is connected to the output terminal SIG_pad;

[0060] The drain terminal of each NMOS switch tube is connected to the output terminal SIG_pad, the source terminal of the NMOS switch tube is connected to the drain terminal of the NMOS driving tube, and the source terminal of the NMOS switch tube is connected to the ground terminal GND.

[0061] A conventional fixed impedance transmitting circuit comprises a PMOS driving tube and an NMOS driving tube connected to a power supply voltage and a ground terminal, and its output impedance is jointly determined by the size of the PMOS driving tube and the NMOS driving tube and the power supply voltage. Since the size of the PMOS driving tube and the NMOS driving tube has been completely determined during chip manufacturing, and the power supply voltage is also a fixed value in actual chip applications, the conventional fixed impedance transmitting circuit cannot adapt to transmission lines with a variety of different characteristic impedance values. The present invention arranges N PMOS driving tubes and N NMOS driving tubes, and the drain of each driving tube is connected to a switch tube. By changing the control signal sequence, the number of driving tubes actually connected to the circuit is selected, thereby achieving the purpose of adjusting the output impedance.

[0062] Combination Figure 3 , the N PMOS drive tubes are MP1, MP2, ..., MPN, the N PMOS switch tubes are MU1, MU2, ..., MUN, the N NMOS drive tubes are MN1, MN2, ..., MNN, the N NMOS switch tubes are MD1, MD2, ..., MDN, and the gate of the first NMOS switch tube MD1 is connected to the first control signal K <1> The gate of the first PMOS switch is connected to the inverted signal Kb of the first control signal. <1> The gate of the second NMOS switch tube MD2 is connected to the second control signal K <2> The gate of the second PMOS switch is connected to the inverted signal Kb of the second control signal. <2> The gate of the Nth NMOS switch tube MDN is connected to the Nth control signal K <n>The gate of the Nth PMOS switch is connected to the inverted signal Kb of the Nth control signal. <n>, the 1st control signal to the Nth control signal constitute a control signal sequence K <n:1>The inverted signal of the first control signal to the inverted signal of the Nth control signal constitutes an inverted control signal sequence Kb <n:1>,

[0063] The adaptive impedance matching circuit of the present invention refers to Figure 4 , the impedance matching detection circuit 12 includes,

[0064] The resistor voltage divider circuit includes a predetermined number of voltage divider resistors connected between a power supply voltage terminal VDD and a ground terminal GND, and the connection points between different voltage divider resistors respectively lead out a first reference divided voltage Vr_up, a second reference divided voltage Vr_dn and a third reference divided voltage Vr_md;

[0065] A first comparator CMP1 compares the signal at the output terminal SIG_pad with the first reference divided voltage Vr_up to generate a first comparison signal SU;

[0066] The second comparator CMP2 compares the signal at the output terminal SIG_pad with the second reference divided voltage Vr_dn to generate a second comparison signal SD;

[0067] The XOR gate XOR1 performs an XOR operation on the first comparison signal SU and the second comparison signal SD to output an impedance matching detection signal SO.

[0068] The impedance matching detection circuit 12 further includes:

[0069] The first MOS transistor M1 is controllably connected between the current source IB1 and the first reference node J1 under the control of the impedance matching detection signal SO;

[0070] A first capacitor C1 is connected between the first reference node J1 and the ground terminal GND;

[0071] The second MOS transistor M2 is controllably connected between the first reference node J1 and the ground terminal GND under the action of the first control signal;

[0072] A third comparator CMP3 compares the third reference divided voltage Vr_md with the voltage of the first reference node VC1 to generate a third comparison signal SM;

[0073] The NOR gate OR1 performs a NOR logic operation on the third comparison signal SM and the first control signal to generate a first logic signal;

[0074] AND gate AND1, performing an AND logic operation on the first logic signal and the clock signal CLK to generate a second logic signal CKC;

[0075] The counter 121 has a clock terminal CK connected to the second logic signal CKC, and a trigger terminal Connected to an enable signal EN, the counter 121 outputs a count value Nout;

[0076] The first inverter INV1 connects the enable signal EN to the control terminal of the second MOS transistor M2.

[0077] For the impedance matching detection circuit of the present invention in the case of poor matching, there is an undershoot or overshoot in the time-domain signal at the output terminal SIG_pad. At this time, the changes of the first comparison signal SU and the second comparison signal SD are almost synchronous, and the impedance matching detection signal SO output by the exclusive OR gate XOR is a signal with a length of 0; for the case of good matching, there is a sequential relationship between the transitions of the first comparison signal SU and the second comparison signal SD. The signal SO output after passing through the exclusive OR gate XOR for this time difference is a pulse signal. The first MOS transistor M1 conducts when the impedance matching detection signal SO is a pulse signal, and the current source IB1 charges the first capacitor C1. Combining Figure 4 and Figure 5 , taking the important node waveform diagram with the counter counting from 0 to 6 as an example, the enable signal EN controls the reset and start of the impedance matching detection circuit. When the enable signal EN = 0, the second MOS transistor M2 conducts, and the charges on the first capacitor C1 are all discharged to the ground terminal GND, and the voltage VC1 of the first reference node J1 is 0. When the enable signal EN = 1, it allows the current source IB1 to charge the first capacitor C1 through the first MOS transistor M1. The enable signal EN is also used to reset the counter 121 and control the input clock of the counter 121 at the same time. When the enable signal EN = 0, the counter 121 is reset to 0. When EN jumps from 0 to 1, the external clock CLK can be transmitted to the clock input terminal CK of the counter 121, and the counter 121 can count. The counting time of the counter 121 starting from 0 depends on how long it takes for the voltage VC1 of the first reference node J1 to reach the third reference voltage Vr_md. When VC1 < Vr_md, the counter 121 continuously receives the second logic signal CKC and counts. When the first capacitor C1 is gradually charged and the voltage VC1 of the first reference node J1 rises to the third reference voltage Vr_md, the counter 121 stops counting. At this time, the count value Nout of the counter 121 reflects the charging time. The larger the count value Nout, the longer the charging time, and the narrower the impedance matching detection signal SO; conversely, the smaller Nout, the shorter the charging time, and the wider the impedance matching detection signal SO. Therefore, the magnitude of the count value Nout equivalently reflects the quality of impedance matching.

[0078] Figure 4 The four voltage-dividing resistors R1, R2, R3, and R4 are connected between the power supply voltage terminal VDD and the ground terminal GND, the point where the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are connected leads to a first reference voltage-dividing resistor Vr_up, the point where the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4 are connected leads to a second reference voltage-dividing resistor Vr_dn, and the point where the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 are connected leads to a third reference voltage-dividing resistor Vr_md; preferably, the first reference voltage-dividing resistor Vr_up is VDD*2 / 5, the second reference voltage-dividing resistor Vr_dn is VDD*3 / 5, and the third reference voltage-dividing resistor Vr_md is VDD*1 / 2.

[0079] The input clock of the present invention is CLK, which is controlled by traversing the control signal sequence K <n:1>= all combinations of 00…0~11…1, the impedance matching detection circuit 12 judges the matching status of the transmitting end impedance and the transmission line impedance in turn, and selects the optimal control signal sequence K <n:1>The value is finally assigned to the variable impedance sending circuit to achieve the purpose of automatic impedance adjustment.

[0080] The transmission line of the present invention is a microstrip transmission line, and the characteristic impedance of the transmission line is 50 ohms, or 75 ohms, or 100 ohms. The output end of the PHY chip is a port for transmitting MII and / or RMII and / or GMII and / or RGMII signals.

[0081] Figure 6 The working method of the adaptive impedance matching circuit of the PHY chip of the present invention comprises the following steps:

[0082] Step S1, setting all control signal sequences consisting of the first control signal to the Nth control signal to zero;

[0083] Step S2, adding 1 to the control signal sequence.

[0084] Step S3, the output signal SIG_tx is sent outward through the output terminal SIG_pad of the PHY chip;

[0085] Step S4, enabling the impedance matching detection circuit through an enable signal, and recording the corresponding count value output by the counter;

[0086] Step S5, determining whether the control signal sequence is all 1, if all are 1, executing step S6, if not all are 1, repeating step S2;

[0087] Step S6, selecting a control signal sequence with the smallest count value from all count values ​​and sending it to the variable impedance sending circuit.

[0088] The variable impedance transmission circuit and the impedance matching detection circuit of the present invention cooperate with each other. After starting, the control signal sequence K <n:1>Set to 00…0, and then perform the addition operation of the thermometer code, that is, let the control signal sequence K <n:1>=00…1, the output signal SIG_tx sends the signal outward through the output terminal SIG_pad of the PHY chip; the impedance matching detection circuit is enabled through the enable signal, allowing the counter to start counting, recording the corresponding count value Nout output by the counter, and judging the control signal sequence K <n:1>Is it equal to 11…1? If not, repeat step S2. When the control signal sequence K <n:1>When it is equal to 11…1, the control signal sequence K has been completed.<N:1> After traversing all the numerical combinations, the control signal sequence that minimizes the count value Nout is found and assigned to the variable impedance transmission circuit as the output impedance control value in the best matching state. The present invention can adaptively match microstrip transmission lines with different characteristic impedances and optimize the signal transmission quality between the PHY chip and the MAC chip.

[0089] Through the description and drawings, typical embodiments of the specific structures of the specific implementation methods are given, and other transformations can be made based on the spirit of the present invention. Although the above invention proposes the existing preferred embodiments, these contents are not intended to be limiting.

[0090] For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications of the true intent and scope of the present invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to still be within the intent and scope of the present invention. < / n> < / n>

Claims

1. The adaptive impedance matching circuit of the PHY chip is characterized by: The output end of the transmitting end of the PHY chip is connected to the MAC chip interface through a transmission line, and the PHY chip includes: A variable impedance transmission circuit, which transmits an output signal from the output end through a variable impedance main driver, wherein the main driver adjusts the impedance value of the variable impedance under the action of a control signal sequence; an impedance matching detection circuit connected to the output end of the variable impedance transmission circuit, converting the signal of the output end and the impedance matching state of the transmission line into a count value under the action of an enable signal and a clock signal, and selecting the control signal sequence according to the count value; The impedance matching detection circuit comprises: A resistor voltage divider circuit, comprising a predetermined number of voltage divider resistors connected between a power supply voltage terminal and a ground terminal, wherein points where different voltage divider resistors are connected lead out a first reference voltage divider, a second reference voltage divider and a third reference voltage divider respectively; A first comparator, for comparing the voltage at the output end with the first reference divided voltage to generate a first comparison signal; A second comparator, for comparing the voltage at the output terminal with the second reference divided voltage to generate a second comparison signal; An XOR gate, performing an XOR operation on the first comparison signal and the second comparison signal to output an impedance matching detection signal; A first MOS transistor, controllably connected between a current source and a first reference node under the control of the impedance matching detection signal; A first capacitor connected between the first reference node and a ground terminal; A second MOS transistor, controllably connected between the first reference node and the ground terminal under the action of a first control signal; a third comparator, for comparing the third reference divided voltage with the voltage of the first reference node to generate a third comparison signal; a NOR gate, performing a NOR logic operation on the third comparison signal and the first control signal to generate a first logic signal; An AND gate, performing an AND logic operation on the first logic signal and the clock signal to generate a second logic signal; A counter, wherein a clock terminal of the counter is connected to the second logic signal, a trigger terminal is connected to an enable signal, and the counter outputs the count value.

2. The adaptive impedance matching circuit according to claim 1, characterized in that: The main driver comprises: N PMOS tube branches, controllably connected in parallel between the power supply voltage terminal and the output terminal, including N PMOS driving tubes and N PMOS switch tubes, each of the PMOS driving tubes being connected to one of the PMOS switch tubes; N NMOS tube branches, controllably connected in parallel between the output terminal and the ground terminal, including N NMOS driving tubes and N NMOS switch tubes, each of the NMOS driving tubes being connected to one of the NMOS switch tubes; The gates of each of the PMOS switch tubes and each of the NMOS switch tubes are connected to a control signal, the gate of the i-th NMOS switch tube is connected to the i-th control signal, the gate of the i-th PMOS switch tube is connected to the inverted signal of the i-th control signal, i∈[1,N], the 1st control signal connected to the gate of the 1st NMOS switch tube to the Nth control signal connected to the gate of the N-th NMOS switch tube constitute the control signal sequence.

3. The adaptive impedance matching circuit according to claim 2, characterized in that: The variable impedance sending circuit also includes a pre-driving stage inverter, an input end of the pre-driving stage inverter is connected to the output signal, and an output end of the pre-driving stage inverter is connected to the gates of the PMOS driving tube and the NMOS driving tube.

4. The adaptive impedance matching circuit according to claim 2, characterized in that: The source terminal of each of the PMOS driving tubes is connected to the power supply voltage terminal, the drain terminal of the PMOS driving tube is connected to the source terminal of the PMOS switch tube, and the drain terminal of the PMOS switch tube is connected to the output terminal; The drain terminal of each NMOS switch tube is connected to the output terminal, the source terminal of the NMOS switch tube is connected to the drain terminal of the NMOS driving tube, and the source terminal of the NMOS switch tube is connected to the ground terminal.

5. The adaptive impedance matching circuit according to claim 1, characterized in that: A first inverter is included, connecting the enable signal to the control end of the second MOS tube.

6. The adaptive impedance matching circuit according to claim 1, characterized in that: The transmission line is a microstrip transmission line, and the characteristic impedance of the transmission line is 50 ohms, or 75 ohms, or 100 ohms.

7. The adaptive impedance matching circuit according to claim 1, characterized in that: The output end of the PHY chip is a port for transmitting MII and / or RMII and / or GMII and / or RGMII signals.

8. A working method of an adaptive impedance matching circuit of a PHY chip, characterized in that: The adaptive impedance matching circuit for the PHY chip according to any one of claims 1 to 7 comprises the following steps: Step S1, setting all control signal sequences consisting of the first control signal to the Nth control signal to zero; Step S2, adding 1 to the control signal sequence, Step S3, the output signal is sent outward through the output terminal of the PHY chip; Step S4, enabling the impedance matching detection circuit through an enable signal, and recording the corresponding count value output by the counter; Step S5, determining whether the control signal sequence is all 1, if all are 1, executing step S6, if not all are 1, repeating step S2; Step S6, selecting a control signal sequence corresponding to a minimum count value from all count values ​​and sending it to the variable impedance sending circuit.

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