Page buffer and semiconductor memory device including the same

Abstract

The present technology relates to a page buffer and a semiconductor memory device including the same. A page buffer includes: a bit line selector configured to connect a bit line of a memory cell array to a sensing node; a precharger configured to precharge a potential of the sensing node to a first level; and a latch component configured to sense data by detecting the time when the potential of the sensing node decreases from the first level to a second level.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a page buffer and a semiconductor memory device including the same. Background Art

[0002] A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices are roughly divided into volatile memory devices and nonvolatile memory devices.

[0003] A volatile memory device is a memory device in which the stored data is lost when the power supply is cut off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non-volatile memory device is a memory device that retains the stored data even if the power supply is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is roughly divided into NOR type and NAND type. Summary of the invention

[0004] A page buffer according to an embodiment of the present disclosure includes: a bit line selector configured to connect a bit line of a memory cell array to a sensing node; a precharger configured to precharge a potential of the sensing node to a first level; and a latch component configured to sense data by detecting the time when the potential of the sensing node decreases from the first level to the second level.

[0005] A semiconductor memory device according to an embodiment of the present disclosure includes: a memory block having a plurality of memory cells programmed to an erase state and a plurality of programmed states; a voltage generating circuit configured to generate a read voltage to be applied to a word line of the memory block during a read operation; and a read / write circuit connected to a bit line of the memory block and configured to latch data by sensing a potential level of a sensing node based on a cell current of the memory cell during a read operation.

[0006] A semiconductor memory device according to an embodiment of the present disclosure includes: a memory block having a plurality of memory cells programmed to an erase state and a plurality of programming states; a voltage generating circuit configured to generate a read voltage to be applied to a word line of the memory block during a read operation; and a page buffer connected to a bit line of the memory block, configured to precharge a potential of a sensing node connected to the bit line to a first level during a read operation, and latch data by detecting a time when a programming state of a selected memory cell among a plurality of memory cells connected to the bit line decreases from a first level to a second level based on the sensing node. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 is an example Figure 1 A diagram of a semiconductor memory device included in a memory device.

[0009] Figure 3 is a diagram illustrating a three-dimensional storage block.

[0010] Figure 4 It is a specific example Figure 3 A circuit diagram of any one of the memory blocks shown.

[0011] Figure 5 is an example Figure 4 Circuit diagram of the memory string shown.

[0012] Figure 6 is an example Figure 2 Diagram of the page buffer.

[0013] Figure 7 is a threshold voltage distribution diagram illustrating an erase state, multiple program states, and a read voltage.

[0014] Figure 8 is a graph illustrating cell currents for an erased state and multiple programmed states.

[0015] Fig. 9 is an example Figure 6 FIG. 1 is a diagram of a first implementation of a latch assembly.

[0016] Fig.10 is a diagram illustrating a control signal generator according to the first embodiment.

[0017] Fig.11 is an example Fig. 9 A waveform diagram of the signals showing the operation of the latch component.

[0018] Fig.12 It is an example from Fig. 9 A diagram of the data values ​​output by the latch component is shown.

[0019] Fig.13 is an example Figure 6 FIG. 1 is a diagram of a second embodiment of a latch assembly.

[0020] Fig.14 It is a diagram illustrating a second embodiment of the control signal generator.

[0021] Fig.15 is an example Fig.13 A waveform diagram of the signals showing the operation of the latch component.

[0022] Fig.16 It is an example from Fig.13 A diagram of the data values ​​output by the latch component is shown.

[0023] Fig.17 is a diagram illustrating another embodiment of a memory system.

[0024] Fig.18 is a diagram illustrating another embodiment of a memory system.

[0025] Fig.19 is a diagram illustrating another embodiment of a memory system.

[0026] Fig. 20 is a diagram illustrating another embodiment of a memory system. DETAILED DESCRIPTION

[0027] The specific structural or functional description of the embodiments according to the concept disclosed in this specification or application is only exemplified for describing the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms, and the description is not limited to the embodiments described in this specification or application.

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily carry out the technical spirit of the present disclosure.

[0029] Embodiments of the present disclosure provide a page buffer capable of performing a read operation on a plurality of program states in a state where one read voltage is applied to a word line during a read operation, and a semiconductor memory device including the same.

[0030] According to the present technology, a read operation for a plurality of program states can be performed in a state where one read voltage is applied to a word line during a read operation, thereby reducing a read operation time.

[0031] Figure 1is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0032] Reference Figure 1 , the memory system 1000 may include a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 may include a plurality of semiconductor memory devices 100. The plurality of semiconductor memory devices 100 may be divided into a plurality of groups. Although the host 1300 is shown and described as being included in the memory system 1000 in the embodiments of the present disclosure, the memory system 1000 may be configured to include only the controller 1200 and the memory device 1100, and the host may be configured to be disposed outside the memory system 1000.

[0033] exist Figure 1 In the embodiment, the plurality of groups GR1 to GRn of the memory device 1100 communicate with the controller 1200 through the first channel CH1 to the nth channel CHn, respectively. Figure 2 Each semiconductor memory device 100 is described.

[0034] Each of the groups GR1 to GRn may be configured to communicate with the controller 1200 through one common channel. The controller 1200 may be configured to control the plurality of semiconductor memory devices 100 of the memory device 1100 through the plurality of channels CH1 to CHn.

[0035] The controller 1200 may be connected between the host 1300 and the memory device 1100. The controller 1200 may be configured to access the memory device 1100 in response to a request from the host 1300. For example, the controller 1200 may be configured to control a read operation, a program operation, an erase operation, and a background operation of the memory device 1100 in response to a host command Host_CMD received from the host 1300. During a program operation, the host 1300 may send an address ADD and data DATA to be programmed together with the host command Host_CMD, and during a read operation, the host 1300 may send an address ADD together with the host command Host_CMD. During a program operation, the controller 1200 may send a command corresponding to a program operation and data DATA to be programmed to the memory device 1100. During a read operation, the controller 1200 may send a command corresponding to a read operation to the memory device 1100, may receive the read data DATA from the memory device 1100, and may send the received data DATA to the host 1300. The controller 1200 may be configured to provide an interface between the memory device 1100 and the host 1300. The controller 1200 may be configured to drive firmware for controlling the memory device 1100.

[0036] The host 1300 may include a portable electronic device such as a computer, a PDA, a PMP, an MP3 player, a camera, a camcorder, or a mobile phone. The host 1300 may request a program operation, a read operation, an erase operation, etc. of the memory system 1000 through a host command Host_CMD. The host 1300 may send a host command Host_CMD, data DATA, and an address ADD corresponding to a program operation to the controller 1200 for a program operation of the memory device 1100, and may send a host command Host_CMD and an address ADD corresponding to a read operation to the controller 1200 for a read operation. At this time, the address ADD may be a logical address (logical address block) of the data.

[0037] The controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device. As an exemplary embodiment, the controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device to constitute a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device to constitute a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or Micro MMC), an SD card (SD, Mini SD, Micro SD or SDHC), and a Universal Flash Device (UFS).

[0038] As another example, the memory system 1000 is provided as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, and a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

[0039] As an exemplary embodiment, the memory device 1100 or the memory system 1000 may be installed as various types of packages. For example, the memory device 1100 or the memory system 1000 may be packaged or installed in a method such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic lead chip carrier (PLCC), a plastic dual in-line package (PDIP), a wafer in a waffle package, a wafer form wafer, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline (SOIC), a shrink small outline package (SSOP), a thin small outline (TSOP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), or a wafer-level processing stacked package (WSP).

[0040] Figure 2 is an example Figure 1 A diagram of a semiconductor memory device included in a memory device.

[0041] Reference Figure 2 , the semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic 140, and a voltage generation circuit 150. The address decoder 120, the read / write circuit 130, and the voltage generation circuit 150 may be defined as a peripheral circuit 160 that performs a read operation on the memory cell array 110.

[0042] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 120 via word lines WL. The plurality of memory blocks BLK1 to BLKz may be connected to the read-write circuit 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. As an embodiment, the plurality of memory cells are nonvolatile memory cells. A plurality of memory cells connected to one word line among the plurality of memory cells may be defined as one page. That is, the memory cell array 110 may be composed of a plurality of pages.

[0043] Each of the plurality of memory blocks BLK1 to BLKz of the memory cell array 110 may include a plurality of memory strings. Each of the plurality of memory strings may include a drain select transistor, a plurality of memory cells, and a source select transistor connected in series between a bit line and a source line. In addition, each of the plurality of memory strings may include a pass transistor between a source select transistor and a memory cell, a pass transistor between a drain select transistor and a memory cell, and may also include a gate transistor between the memory cells. A detailed description of the memory cell array 110 will be described later.

[0044] Each of the plurality of memory cells may store a plurality of data bits, such as a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).

[0045] The address decoder 120 is connected to the memory cell array 110 through the word lines WL. The address decoder 120 may be configured to operate in response to the address decoder control signal AD_signals generated in the control logic 140. The address decoder 120 may receive the address ADDR through an input / output buffer (not shown) inside the semiconductor memory device 100.

[0046] The address decoder 120 can decode the row address in the received address ADDR, and can apply multiple operating voltages including a program voltage Vpgm, a read voltage Vread, a pass voltage Vpass and a verification voltage Vverify generated by the voltage generation circuit 150 to multiple memory cells of the memory cell array 110 based on the decoded row address.

[0047] The address decoder 120 may be configured to decode the column address in the received address ADDR and may send the decoded column address Yi to the read / write circuit 130 .

[0048] The address ADDR received during a program operation or a read operation may include a block address, a row address, and a column address. The address decoder 120 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 120 and may be provided to the read / write circuit 130.

[0049] The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

[0050] The read / write circuit 130 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may be connected to the memory cell array 110 through the bit lines BL1 to BLm. During a read operation or a verification operation, the plurality of page buffers PB1 to PBm may perform a data sensing operation that senses the programming state of the memory cells connected to the bit lines BL1 to BLm. During the data sensing operation, each of the plurality of page buffers PB1 to PBm may latch data based on the cell current of the selected memory cell connected to the corresponding bit line. For example, each of the plurality of page buffers PB1 to PBm may check the time when the sensing node precharged to the first level decreases to the second level based on the cell current of the selected memory cell connected to the corresponding bit line, and may latch a data value corresponding to the checked time. For example, each of the plurality of page buffers PB1 to PBm may latch data corresponding to the potential level of the sensing node at each of the plurality of set time points. At this time, a read voltage may be applied to the word line connected to the selected memory cell.

[0051] The read and write circuit 130 may operate in response to the page buffer control signal PB_signals output from the control logic 140 .

[0052] As an exemplary embodiment, the read / write circuit 130 may include a page buffer (or a page register), a column selection circuit, and the like.

[0053] The control logic 140 may be connected to the address decoder 120, the read / write circuit 130, and the voltage generating circuit 150. The control logic 140 may receive a command CMD through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 may be configured to control the overall operation of the semiconductor memory device 100 in response to the command CMD. For example, the control logic 140 may receive a command CMD corresponding to a programming operation, and may generate and output an address decoder control signal AD_signals for controlling the address decoder 120, a page buffer control signal PB_signals for controlling the read / write circuit 130, and a voltage generating circuit control signal VG_signals for controlling the voltage generating circuit 150 in response to the received command CMD. In addition, the control logic 140 may receive a command CMD corresponding to a read operation, and may generate and output an address decoder control signal AD_signals for controlling the address decoder 120, a page buffer control signal PB_signals for controlling the read / write circuit 130, and a voltage generating circuit control signal VG_signals for controlling the voltage generating circuit 150 in response to the received command CMD.

[0054] During a program operation, the voltage generation circuit 150 may generate a program voltage Vpgm, a pass voltage Vpass, and a verification voltage Vverify based on a voltage generation circuit control signal VG_signals output from the control logic 140, and may output the program voltage Vpgm, the pass voltage Vpass, and the verification voltage Vverify to the address decoder 120. In addition, during a read operation, the voltage generation circuit 150 may generate a read voltage Vread and a pass voltage Vpass based on a voltage generation circuit control signal VG_signals output from the control logic 140, and may output one of the read voltage Vread and the pass voltage Vpass to the address decoder 120.

[0055] According to an embodiment of the present disclosure, the voltage generation circuit 150 may output a read voltage during a read operation of a memory cell storing a plurality of data bits.

[0056] Figure 3 is a diagram illustrating a three-dimensional storage block.

[0057] Reference Figure 3 , the three-dimensional memory blocks BLK1 to BLKz may be arranged to be spaced apart from each other along the direction Y in which the bit lines BL1 to BLm extend. For example, the first to z-th memory blocks BLK1 to BLKz may be arranged to be spaced apart from each other along the second direction Y and include a plurality of memory cells stacked along the third direction Z. Figure 4 and Figure 5 The first to z-th memory blocks BLK1 to BLKz are described in detail.

[0058] Figure 4 It is a specific example Figure 3 A circuit diagram of any one of the memory blocks shown.

[0059] Figure 5 is an example Figure 4 Circuit diagram of the memory string shown.

[0060] Reference Figure 4 and Figure 5 , each memory string ST may be connected between the bit lines BL1 to BLm and the source line SL. The memory string ST connected between the first bit line BL1 and the source line SL is described as an example.

[0061] The memory string ST may include a source selection transistor SST, memory cells F1 to Fn (n is a positive integer) and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. The gates of the source selection transistors SST included in different memory strings ST connected to different bit lines BL1 to BLm may be connected to a first source selection line SSL0 and a second source selection line SSL1. For example, source selection transistors adjacent to each other in the second direction Y among the source selection transistors SST may be connected to the same source selection line. For example, assuming that the source selection transistors SST are arranged in sequence along the second direction Y, the gates of the source selection transistors SST arranged in the first direction X and included in different strings ST from the first source selection transistor SST and the gates of the source selection transistors SST arranged in the first direction X and included in different strings ST from the second source selection transistor SST may be connected to the first source selection line SSL0. In addition, gates of source selection transistors SST arranged in the first direction X and included in different strings ST from the third source selection transistor SST and gates of source selection transistors SST arranged in the first direction X and included in different strings ST from the fourth source selection transistor SST may be connected to the second source selection line SSL1.

[0062] Gates of the memory cells F1 to Fn may be connected to the word lines WL1 to WLn, and a gate of the drain select transistor DST may be connected to any one of the first to fourth drain select lines DSL0 to DSL3 .

[0063] The gates of the transistors arranged in the first direction X among the drain selection transistors DST may be commonly connected to the same drain selection line (e.g., DSL0), but the transistors arranged in the second direction Y may be connected to different drain selection lines DSL1 to DSL3. For example, assuming that the drain selection transistors DST are sequentially arranged along the second direction Y, the gates of the drain selection transistors DST arranged in the first direction X and included in different strings ST from the first drain selection transistor DST may be connected to the first drain selection line DSL0. The drain selection transistors DST arranged in the second direction Y starting from the drain selection transistor DST connected to the first drain selection line DSL0 may be sequentially connected to the second drain selection line DSL1 to the fourth drain selection line DSL3. Therefore, the memory string ST connected to the selected drain selection line may be selected within the selected memory block, and the memory strings ST connected to the remaining unselected drain selection lines may not be selected.

[0064] The memory cells connected to the same word line may form a page PG. Here, a page refers to a physical page. For example, among the strings ST connected to the first bit line BL1 to the mth bit line BLm, a group of memory cells connected to the same word line in the first direction X is called a page PG. For example, among the first memory cells F1 connected to the first word line WL1, the memory cells arranged along the first direction X may form a page PG. The cells among the first memory cells F1 arranged in the second direction Y and connected to the first word line WL1 in common may be divided into different pages. Therefore, when the first drain selection line DSL0 is the selected drain selection line and the first word line WL1 is the selected word line, among the multiple page PGs connected to the first word line WL1, the page connected to the first drain selection line DSL0 may become the selected page. The page connected to the first word line WL1 in common but connected to the unselected second drain selection line DSL1 to the fourth drain selection line DSL3 may become an unselected page.

[0065] In the drawings, one string ST includes one source selection transistor SST and one drain selection transistor DST, but according to the semiconductor memory device, one string ST may include multiple source selection transistors SST and multiple drain selection transistors DST. In addition, according to the memory device, a dummy cell may be included between the source transistor SST, the memory cells F1 to Fn, and the drain selection transistor DST. The dummy cell does not store user data like the normal memory cells F1 to Fn, but can be used to improve the electrical characteristics of each string ST. However, the dummy cell is not an important configuration in the present embodiment, and therefore, its detailed description is omitted.

[0066] Figure 6 is an example Figure 2 Diagram of the page buffer.

[0067] Figure 2 The plurality of page buffers PB1 to PBm shown may be configured similarly to one another, and for ease of description, reference is made to Figure 6 The page buffer PB1 will be described.

[0068] Reference Figure 6 , the page buffer PB1 may include a bit line selector 131 , a sensor 132 , a precharger 133 , a latch component 134 , and a data output circuit 135 .

[0069] The bit line selector 131 may be connected between the corresponding bit line BL1 and the sensor 132 , and may electrically connect the corresponding bit line BL1 and the sensor 132 during a read operation.

[0070] The sensor 132 may be connected between the bit line selector 131 and the sensing node SO. The sensor 132 may connect the sensing node SO to the bit line BL1 connected through the bit line selector 131 during a read operation, and may evaluate the sensing node SO based on the current amount of the bit line BL1. For example, the sensor 132 may reduce the potential of the sensing node SO precharged to the first level to the second level based on the current amount of the bit line BL1, and as the current amount of the bit line BL1 increases, the time for the potential to be reduced to the second level may be reduced. That is, during a read operation, the sensing node SO may be reduced from the first level to the second level based on the cell current of the selected memory cell connected to the bit line BL1. In addition, as the cell current amount of the selected memory cell increases, the time for the potential of the sensing node SO to be reduced from the first level to the second level may be reduced, and as the cell current amount decreases, the time for the potential of the sensing node SO to be reduced from the first level to the second level may be increased.

[0071] During a read operation, the precharger 133 may be connected to the sensing node SO, may precharge the bit line BL1 to a set level through the sensor 132 and the bit line selector 131 , and may precharge the sensing node SO to a first level.

[0072] The latch component 134 may be connected to the sensing node SO, and may latch data by sensing a potential level of the sensing node SO every predetermined time.

[0073] The data output circuit 135 can be connected to the output terminal Q of the latch component 134.<m;1> and a bit output line BITOUT which is an output terminal of the page buffer PB1. The data output circuit 135 may receive the data latched in the latch component 134 and may output the data to the bit output line BITOUT.

[0074] Figure 7 is a threshold voltage distribution diagram illustrating an erase state, multiple program states, and a read voltage.

[0075] Figure 8 is a graph illustrating cell currents for an erased state and multiple programmed states.

[0076] In the embodiments of the present disclosure, the description Figure 5 The case where the plurality of memory cells F1 to Fn are MLCs is shown as an example.

[0077] Reference Figure 7 and Figure 8 , Figure 5The plurality of memory cells F1 to Fn shown may be programmed into an erase state E and a plurality of program states PV1 to PV3. The erase state E and the plurality of program states PV1 to PV3 may have different threshold voltage distributions. Figure 7 As shown, the threshold voltage distribution of the program state PV1 may be higher than the threshold voltage of the erase state E, and the threshold voltage distribution of the program state PV2 may be higher than the threshold voltage of the program state PV1. In addition, the threshold voltage distribution of the program state PV3 may be higher than the threshold voltage of the program state PV2.

[0078] When a read voltage Vread is applied to the word lines of the plurality of memory cells F1 to Fn during a read operation, the memory cells corresponding to the erase state E and the program states PV1 and PV2 may be turned on, and the memory cells corresponding to the program state PV3 may be turned off. Figure 8 As shown, when a read voltage Vread is applied to a word line, the cell current amounts of a plurality of memory cells F1 to Fn may vary based on the corresponding erase state E and a plurality of programming states PV1 to PV3. For example, the cell current of the memory cell corresponding to the erase state E may be the largest, and the cell current of the memory cell corresponding to the programming state PV3 may be the smallest. In addition, the cell current of the memory cell corresponding to the programming state PV1 may be smaller than the cell current of the memory cell corresponding to the erase state E, and may be larger than the cell current of the memory cell corresponding to the programming state PV2. The cell current of the memory cell corresponding to the programming state PV2 may be smaller than the cell current of the memory cell corresponding to the programming state PV1, and may be larger than the cell current of the memory cell corresponding to the programming state PV3.

[0079] As described above, when the same read voltage Vread is applied to the word line, the cell current of the plurality of memory cells F1 to Fn programmed to the erase state E and the plurality of programming states PV1 to PV3 may be different based on the erase state E and the plurality of programming states PV1 to PV3. Therefore, during a read operation, when the bit line connected to the selected memory cell and the sensing node in the page buffer are electrically connected, the time for the potential of the sensing node precharged to the first level to decrease to the second level is changed based on the cell current of the selected memory cell. For example, as the cell current increases, the time for the potential of the sensing node to decrease from the first level to the second level may decrease, and as the cell current decreases, the time for the potential of the sensing node to decrease from the first level to the second level may increase.

[0080] Fig. 9 is an example Figure 6 FIG. 1 is a diagram of a first implementation of a latch assembly.

[0081] Reference Fig. 9, the latch component 134 may include a plurality of latch stages 134A to 134D. Figure 2 The number of latch stages 134A to 134D included in the latch component 134 is adjusted according to the number of data bits that can be stored in the memory cells included in the memory cell array 110. For example, when the memory cells are MLC, the latch component 134 may include three latch stages, and when the memory cells are TLC, the latch component 134 may include seven latch stages. In addition, when the memory cells are QLC, the latch component 134 may include fifteen latch stages.

[0082] The latch stage 134A may include a first transistor T1 , a first inverter IV1 , a second inverter IV2 , and a second transistor T2 .

[0083] The first transistor T1 may be connected between the sensing node SO and the first node ND1, and may be turned on or off in response to the first latch signal PLS1. The first inverter IV1 and the second inverter IV2 may be connected in reverse parallel between the first node ND1 and the second node ND2. That is, the first inverter IV1 and the second inverter IV2 may be configured as a latch between the first node ND1 and the second node ND2. The second transistor T2 may be connected between the second node ND2 and the output terminal Q <1> and can be turned on or off in response to a data output signal DO.

[0084] The first transistor T1 may transmit the first data D1 corresponding to the potential of the sensing node SO to the first node ND1 in response to the first latch signal PLS1. The first inverter IV1 and the second inverter IV2 may receive and latch the first data D1, invert the first data D1, and transmit the inverted first data to the second transistor T2. The second transistor T2 may output the first data D1 to the output terminal Q in response to the data output signal DO. <1> The inverted first data is output.

[0085] For example, when the sensing node SO is at the first level as the precharge level, the first transistor T1 may transmit the first data D1 having the first level of potential to the first node ND1 in response to the first latch signal PLS1. The first inverter IV1 and the second inverter IV2 may receive the first data D1 having the first level of potential and may control the first node ND1 to a logic high level and the second node ND2 to a logic low level. The second transistor T2 may transmit the first data D1 having the first level of potential to the first node ND1 in response to the data output signal DO. <1> The inverted first data of a logic low level is output.

[0086] For example, when the sensing node SO is discharged to the second level, the first transistor T1 may transmit the first data D1 having the second level of potential to the first node ND1 in response to the first latch signal PLS1. The first inverter IV1 and the second inverter IV2 may receive the first data D1 having the second level of potential and may control the first node ND1 to a logic low level and the second node ND2 to a logic high level. The second transistor T2 may transmit the first data D1 having the second level of potential to the first node ND1 in response to the data output signal DO. <1> The inverted first data of a logic high level is output.

[0087] The latch stage 134B may include a third transistor T3 , a third inverter IV3 , a fourth inverter IV4 , and a fourth transistor T4 .

[0088] The third transistor T3 may be connected between the sensing node SO and the third node ND3, and may be turned on or off in response to the second latch signal PLS2. The third inverter IV3 and the fourth inverter IV4 may be connected in reverse parallel between the third node ND3 and the fourth node ND4. That is, the third inverter IV3 and the fourth inverter IV4 may be configured as a latch between the third node ND3 and the fourth node ND4. The fourth transistor T4 may be connected between the fourth node ND4 and the output terminal Q. <2> and can be turned on or off in response to a data output signal DO.

[0089] Since the operation of the latch stage 134B is similar to that of the latch stage 134A, a detailed description thereof is omitted.

[0090] The latch stage 134C may include a fifth transistor T5 , a fifth inverter IV5 , a sixth inverter IV6 , and a sixth transistor T6 .

[0091] The fifth transistor T5 may be connected between the sensing node SO and the fifth node ND5, and may be turned on or off in response to the third latch signal PLS3. The fifth inverter IV5 and the sixth inverter IV6 may be connected in reverse parallel between the fifth node ND5 and the sixth node ND6. That is, the fifth inverter IV5 and the sixth inverter IV6 may be configured as a latch between the fifth node ND5 and the sixth node ND6. The sixth transistor T6 may be connected between the sixth node ND6 and the output terminal Q <3> and can be turned on or off in response to a data output signal DO.

[0092] Since the operation of the latch stage 134C is similar to that of the latch stage 134A, a detailed description thereof is omitted.

[0093] The latch stage 134D may include a seventh transistor T7, a seventh inverter IV7, an eighth inverter IV8, and an eighth transistor T8.

[0094] The seventh transistor T7 may be connected between the sensing node SO and the seventh node ND7, and may be turned on or off in response to the mth latch signal PLSm. The seventh inverter IV7 and the eighth inverter IV8 may be connected in reverse parallel between the seventh node ND7 and the eighth node ND8. That is, the seventh inverter IV7 and the eighth inverter IV8 may be configured as a latch between the seventh node ND7 and the eighth node ND8. The eighth transistor T8 may be connected between the eighth node ND8 and the output terminal Q <m>and can be turned on or off in response to a data output signal DO.

[0095] Since the operation of the latch stage 134D is similar to that of the latch stage 134A, a detailed description thereof is omitted.

[0096] Fig.10 is a diagram illustrating a control signal generator according to the first embodiment.

[0097] The control signal generator 141 may generate the first to m-th latch signals PLS1 to PLSm in response to the clock signal CLK that flips at a predetermined cycle and may output the first to m-th latch signals PLS1 to PLSm. Each of the first to m-th latch signals PLS1 to PLSm may have an activation period that is activated during a predetermined time. The first to m-th latch signals PLS1 to PLSm may be activated sequentially.

[0098] In response to the clock signal CLK, the control signal generator 141 may generate and output a data output signal DO activated during a predetermined time after a last activated latch signal (ie, an mth latch signal PLSm) among the first to mth latch signals PLS1 to PLSm is activated.

[0099] The control signal generator 141 may include Figure 2 and configured in the control logic 140.

[0100] Fig.11 is an example Fig. 9 A waveform diagram of the signals showing the operation of the latch component.

[0101] Fig.12 It is an example from Fig. 9 A diagram of the data values ​​output by the latch component is shown.

[0102] Refer to the following Figures 2 to 12 A read operation of the semiconductor memory device according to the embodiment of the present disclosure is described.

[0103] In an embodiment of the present disclosure, a memory cell connected to a selected word line is described as an MLC programmed to an erase state E and a plurality of program states PV1 to PV3 and Fig. 9 The latch component 134 may include an example of three latch stages (eg, 134A, 134B, and 134C).

[0104] During a read operation, the voltage generation circuit 150 may generate a read voltage Vread and a pass voltage Vpass based on a voltage generation circuit control signal VG_signals output from the control logic 140, and may output a read voltage Vread and a pass voltage Vpass to the address decoder 120. The address decoder 120 may apply the read voltage Vread generated by the voltage generation circuit 150 to a selected word line (e.g., WL1) of a selected memory block (e.g., BLK1). The address decoder 120 may apply the pass voltage Vpass generated by the voltage generation circuit 150 to unselected word lines (e.g., WL2 to WLn) of the selected memory block (e.g., BLK1).

[0105] The read voltage Vread generated by the voltage generating circuit 150 may be lower than Figure 7 The threshold voltage of the programming state PV3 having the highest threshold voltage distribution among the erased state E and the plurality of programming states PV1 to PV3 shown, and may be higher than the threshold voltage of the programming state PV2 adjacent to the programming state PV3 having the highest threshold voltage distribution. For example, the read voltage Vread may be an intermediate voltage value of the two programming states PV2 and PV3 having the relatively highest threshold voltage distribution among the erased state E and the plurality of programming states PV1 to PV3. In more detail, the read voltage Vread may be an intermediate voltage value of the threshold voltage values ​​of the majority of the memory cells among the memory cells corresponding to the programming state PV2 and the threshold voltage values ​​of the majority of the memory cells among the memory cells corresponding to the programming state PV3.

[0106] As another embodiment, the read voltage Vread may be a voltage higher than a threshold voltage of a program state PV3 having a highest threshold voltage distribution among the erase state E and a plurality of program states PV1 to PV3 .

[0107] The plurality of page buffers PB1 to PBm of the read and write circuit 130 may sense the program states of the memory cells F1 connected to the selected word line WL1 through the bit lines BL1 to BLm.

[0108] Since the plurality of page buffers PB1 to PBm perform the sensing operation in a similar method to one another, an operation in which the page buffer PB1 senses a program state of a memory cell connected to a corresponding bit line BL1 is described as an example as follows.

[0109] The precharger 133 may precharge the bit line BL1 to a precharge level through the sensor 132 and the bit line selector 131. In addition, the precharger 133 may precharge the sensing node SO to a first level VH.

[0110] When a read voltage Vread is applied to the selected word line WL1, a cell current flowing through the bit line BL1 may be generated based on the programming state of the memory cell F1 connected to the bit line BL1. For example, when the memory cell F1 is in the erase state E, the cell current may be the largest, and when the memory cell F1 is in the programming state PV3, the cell current may be the smallest.

[0111] The bit line selector 131 and the sensor 132 may electrically connect the bit line BL1 and the sensing node SO, and may evaluate the sensing node SO based on the cell current of the memory cell F1. That is, the cell current corresponding to the programming state of the memory cell F1 may flow through the bit line BL1. The sensing node SO connected to the bit line BL1 may decrease from the first level VH to the second level based on the cell current, and the time for the sensing node SO to decrease from the first level VH to the second level VL may be adjusted based on the magnitude of the cell current. As a result, the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be adjusted based on the programming state of the memory cell.

[0112] For example, when the selected memory cell F1 is in the erase state E having the lowest threshold voltage distribution, the cell current of the bit line BL1 may be the largest, and the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be the shortest. For example, when the selected memory cell F1 is in the erase state E, the potential of the sensing node SO may be discharged to the second level VL within the first period.

[0113] For example, when the selected memory cell F1 is in the programming state PV1 having a threshold voltage distribution higher than that of the erase state E, the cell current of the bit line BL1 may be smaller than the cell current corresponding to the erase state E, and the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be longer than the time corresponding to the erase state E. For example, when the selected memory cell F1 is in the programming state P1, the potential of the sensing node SO may be discharged to the second level VL within the second period.

[0114] For example, when the selected memory cell F1 is in the programming state PV2 having a threshold voltage distribution higher than that of the programming state PV1, the cell current of the bit line BL1 may be less than the cell current corresponding to the programming state PV1, and the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be longer than the time corresponding to the programming state PV1. For example, when the selected memory cell F1 is in the programming state P2, the potential of the sensing node SO may be discharged to the second level VL within the third period.

[0115] For example, when the selected memory cell F1 is in the program state PV3 having the highest threshold voltage distribution, the cell current of the bit line BL1 may be minimum.

[0116] The control signal generator 141 may generate the first to third latch signals PLS1 to PLS3 in response to the clock signal CLK that flips at a predetermined cycle and may output the first to third latch signals PLS1 to PLS3. Each of the first to third latch signals PLS1 to PLS3 may have an activation period that is activated during a predetermined time. The first to third latch signals PLS1 to PLS3 may be activated sequentially.

[0117] For example, the first latch signal PLS1 may be activated during a predetermined time from a time point when the potential level of the sensing node SO decreases from the first level VH to the second level VL by the memory cell in the erase state E to a time point before the potential level of the sensing node SO decreases from the first level VH to the second level VL by the memory cell in the program state PV1. For example, the first latch signal PLS1 may be activated during a predetermined time within the first period.

[0118] For example, the second latch signal PLS2 may be activated during a predetermined time from a time point when the potential level of the sensing node SO decreases from the first level VH to the second level VL by the memory cells in the programming state PV1 to a time point before the potential level of the sensing node SO decreases from the first level VH to the second level VL by the memory cells in the programming state PV2. For example, the second latch signal PLS2 may be activated during a predetermined time within the second period.

[0119] For example, the third latch signal PLS3 may be activated during a predetermined time after the time point when the potential level of the sensing node SO decreases from the first level VH to the second level VL by the memory cell of the programming state PV2. For example, the third latch signal PLS3 may be activated during a predetermined time within the third period.

[0120] The plurality of respective latch stages 134A to 134C of the latch component 134 may sequentially latch data in response to corresponding first to third latch signals PLS1 to PLS3 .

[0121] For example, in response to the first latch signal PLS1, the latch stage 134A may latch the first data D1 corresponding to the potential of the sensing node SO from a time point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cells in the erase state E to a time point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cells in the program state PV1. That is, the latch stage 134A may latch the first data D1 corresponding to the potential of the sensing node SO in the first period.

[0122] For example, in response to the second latch signal PLS2, the latch stage 134B may latch the second data D2 corresponding to the potential of the sensing node SO from the time point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cells in the programming state PV1 to the time point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cells in the programming state PV2. That is, the latch stage 134B may latch the second data D2 corresponding to the potential of the sensing node SO in the second period.

[0123] For example, in response to the third latch signal PLS3, the latch stage 134C may latch the third data D3 corresponding to the potential of the sensing node SO after a time point at which the potential level of the sensing node SO decreases from the first level VH to the second level VL by the memory cells in the programming state PV2. That is, the latch stage 134C may latch the third data D3 corresponding to the potential of the sensing node SO within the third period.

[0124] Each of the plurality of latch stages 134A to 134C of the latch component 134 may output latched data to an output terminal Q<3;1> in response to a data output signal DO.

[0125] For example, when the selected memory cell F1 connected to the bit line BL1 is in the erase state E, the sensing node SO can be reduced to the second level V in the first period to the third period. Therefore, the plurality of latch stages 134A, 134B, and 134C can latch the first data D1 to the third data D3 of the logic low level, and can output the first data to the third data inverted to the logic high level to the output terminal Q<3;1>. That is, each of the output terminals Q<3;1> can output "1" data corresponding to the logic high level.

[0126] For example, when the selected memory cell F1 connected to the bit line BL1 is in the programming state PV1, the sensing node SO may not reach the second level VL in the first period, and the sensing node SO may decrease to the second level VL in the second and third periods. Therefore, the latch stage 134A may latch the first data D1 of the logic high level, and the latch stages 134B and 134C may latch the second data D2 and the third data D3 of the logic low level. Therefore, the output terminal Q <1> "0" data corresponding to a logic low level can be output, and the output terminal Q <2> and Q <3> Outputs "1" data corresponding to a logic high level.

[0127] For example, when the selected memory cell F1 connected to the bit line BL1 is in the programming state PV2, the sensing node SO may not reach the second level VL in the first period and the second period, and the sensing node SO may decrease to the second level VL in the third period. Therefore, the corresponding latch stages 134A and 134B latch the first data D1 and the second data D2 of the logic high level, and the latch stage 134C may latch the third data D3 of the logic low level. Therefore, the output terminal Q <1> and Q <2> Each of the output terminals Q can output "0" data corresponding to a logic low level, and the output terminal Q <3> "1" data corresponding to a logic high level can be output.

[0128] For example, when the selected memory cell F1 connected to the bit line BL1 is in the programming state PV3, the sensing node SO may not be lowered to the second level VL in the first period to the third period. Therefore, the plurality of latch stages 134A, 134B, and 134C may latch the first data D1 to the third data D3 of the logic high level, and may output the first data to the third data inverted to the logic low level to the output terminal Q<3;1>. That is, each of the output terminals Q<3;1> may output "0" data corresponding to the logic low level.

[0129] The data output circuit 135 may receive data from the output terminal Q<3;1>, and may output MSB data and LSB data as bit read data DATA to a bit output line BITOUT based on the received data.

[0130] As described above, according to the embodiments of the present disclosure, during a read operation of a memory cell storing a plurality of data bits, in a state where one read voltage is applied to a word line, the programming state of the memory cell can be sensed by sensing the time point at which the sensing node SO is reduced to the second level. Therefore, the operation speed of the read operation can be increased, and the area of ​​a circuit for generating a read voltage can be reduced by using only one read voltage instead of a plurality of read voltages.

[0131] In the above embodiment, the read voltage Vread applied to the selected word line may be lower than the threshold voltage of the program state PV3 having the relatively highest threshold voltage distribution among the erase state E and the plurality of program states PV1 to PV3, as shown in FIG. Figure 7 As shown, and may be higher than the threshold voltage of a program state PV2 adjacent to a program state PV3 having the highest threshold voltage distribution.

[0132] In another embodiment, the read voltage Vread may be a voltage higher than the threshold voltage of the programming state PV3 having the highest threshold voltage distribution among the erase state E and the plurality of programming states PV1 to PV3. During the read operation, according to another embodiment, when a read voltage Vread higher than the threshold voltage of the programming state PV3 is applied to the selected word line, the bit lines corresponding to the memory cells programmed to the erase state E and the plurality of programming states PV1 to PV3 may have different cell current amounts. Therefore, the time at which the potential level of the sensing node SO decreases from the first level to the second level may vary based on the programming state of the memory cell. The latch component 134 may latch data corresponding to the potential level of the sensing node SO at a plurality of set time points to sense the programming state of the memory cell.

[0133] Fig.13 is an example Figure 6 FIG. 1 is a diagram of a second embodiment of a latch assembly.

[0134] Reference Fig.13 , the latch component 134 may include a plurality of latch stages 134E to 134H. Figure 2 The number of latch stages 134E to 134H included in the latch component 134 is adjusted according to the number of data bits that can be stored in the memory cells included in the memory cell array 110. For example, when the memory cells are MLC, the latch component 134 may include three latch stages, and when the memory cells are TLC, the latch component 134 may include seven latch stages. In addition, when the memory cells are QLC, the latch component 134 may include fifteen latch stages.

[0135] Each of the plurality of latch stages 134E to 134H may be constituted by a D flip-flop.

[0136] The latch stage 134E may latch data corresponding to the potential level of the sensing node SO in response to a rising edge of the inverted latch signal PLS, and may output the data to the output terminal Q in response to a falling edge of the latch signal PLS. <1> Outputs the latched data.

[0137] The latch stage 134F may latch the output terminal Q in response to the rising edge of the inverted latch signal PLS. <1> The received data can be output to the output terminal Q in response to the falling edge of the latch signal PLS. <2> Outputs the latched data.

[0138] The latch stage 134G can latch the output terminal Q in response to the rising edge of the inverted latch signal PLS. <2> The received data can be output to the output terminal Q in response to the falling edge of the latch signal PLS. <3> Outputs the latched data.

[0139] The latch stage 134H can latch the output terminal Q in response to the rising edge of the inverted latch signal PLS. <m-1>The received data can be output to the output terminal Q in response to the falling edge of the latch signal PLS. <m>Outputs the latched data.

[0140] For example, the latch stage 134E may latch data corresponding to the potential of the sensing node SO in response to a first rising edge of the latch signal PLS, and may output data to the output terminal Q in response to a first falling edge of the latch signal PLS. <1> Outputs the latched data.

[0141] The latch stage 134E may latch new data corresponding to the potential of the sense node SO in response to the second rising edge of the latch signal PLS, and the latch stage 134F may latch the new data from the output terminal Q in response to the second rising edge of the latch signal PLS. <1> That is, the latch stage 134F may latch the data output from the latch stage 134E in response to the second rising edge. The latch stage 134E may output the data to the output terminal Q in response to the second falling edge of the latch signal PLS. <1> The latched data is outputted, and the latch stage 134F may output the latched data to the output terminal Q in response to the second falling edge of the latch signal PLS. <2> Outputs the latched data.

[0142] The latch stage 134E may latch new data corresponding to the potential of the sensing node SO in response to the third rising edge of the latch signal PLS, and the latch stage 134F may latch the new data from the output terminal Q in response to the third rising edge of the latch signal PLS. <1> The received data, and the latch stage 134G can latch the data from the output terminal Q in response to the third rising edge of the latch signal PLS. <2> The latch stage 134E may output the received data to the output terminal Q in response to the third falling edge of the latch signal PLS. <1> The latch stage 134F may output the latched data to the output terminal Q in response to the third falling edge of the latch signal PLS. <2> The latched data is outputted, and the latch stage 134G may output the latched data to the output terminal Q in response to the third falling edge of the latch signal PLS. <3> Outputs the latched data.

[0143] As described above, each time the latch signal PLS is flipped, the plurality of latch stages 134E to 134H of the latch component 134 may latch data corresponding to the potential of the sensing node SO and may transmit the data latched during the previous flip of the latch signal PLS to the next latch stage.

[0144] Fig.14 It is a diagram illustrating a second embodiment of the control signal generator.

[0145] Reference Fig.14 The control signal generator 142 may generate and output a latch signal PLS that is flipped multiple times in response to the flipped clock signal CLK. The control signal generator 142 may include Figure 2 and configured in the control logic 140.

[0146] The timing of a rising edge when the latch signal PLS transitions from a low level to a high level and the timing of a falling edge when the latch signal PLS transitions from a high level to a low level may be set based on the cell current amount corresponding to the erase state and each of the plurality of program states.

[0147] Fig.15 is an example Fig.13 A waveform diagram of the signals showing the operation of the latch component.

[0148] Fig.16 It is an example from Fig.13 A diagram of the data values ​​output by the latch component is shown.

[0149] Refer to the following Figure 8 and Figures 13 to 16 A read operation of a semiconductor memory device according to an embodiment of the present disclosure will be described.

[0150] In an embodiment of the present disclosure, it is described that the memory cells connected to one selected word line may be MLCs programmed to an erase state E and a plurality of program states PV1 to PV3 and Fig.13 The latch component 134 may include an example of three latch stages (eg, 134E, 134F, and 134G).

[0151] During a read operation, the voltage generation circuit 150 may generate a read voltage Vread and a pass voltage Vpass based on a voltage generation circuit control signal VG_signals output from the control logic 140, and may output a read voltage Vread and a pass voltage Vpass to the address decoder 120. The address decoder 120 may apply the read voltage Vread generated by the voltage generation circuit 150 to a selected word line (e.g., WL1) of a selected memory block (e.g., BLK1). The address decoder 120 may apply the pass voltage Vpass generated by the voltage generation circuit 150 to unselected word lines (e.g., WL2 to WLn) of the selected memory block (e.g., BLK1).

[0152] The read voltage Vread generated by the voltage generating circuit 150 may be lower than the threshold voltage of the program state PV3 having the highest threshold voltage distribution among the erase state E and the plurality of program states PV1 to PV3, as shown in FIG. Figure 7 As shown, and may be higher than the threshold voltage of the programming state PV2 adjacent to the programming state PV3 having the highest threshold voltage distribution. For example, the read voltage Vread may be an intermediate voltage value of two programming states PV2 and PV3 having a relatively highest threshold voltage distribution among the erase state E and the plurality of programming states PV1 to PV3. In more detail, the read voltage Vread may be an intermediate voltage value of the threshold voltage values ​​of most memory cells among the memory cells corresponding to the programming state PV2 and the threshold voltage values ​​of most memory cells among the memory cells corresponding to the programming state PV3.

[0153] As another embodiment, the read voltage Vread may be a voltage higher than a threshold voltage of a program state PV3 having a highest threshold voltage distribution among the erase state E and a plurality of program states PV1 to PV3 .

[0154] The plurality of page buffers PB1 to PBm of the read and write circuit 130 may sense the program states of the memory cells F1 connected to the selected word line WL1 through the bit lines BL1 to BLm.

[0155] Since the plurality of page buffers PB1 to PBm perform sensing operations in a similar method to one another, an operation in which the page buffer PB1 senses a program state of a memory cell connected to a corresponding bit line BL1 is described as follows as an example.

[0156] The precharger 133 may precharge the bit line BL1 to a precharge level through the sensor 132 and the bit line selector 131. In addition, the precharger 133 may precharge the sensing node SO to a first level VH.

[0157] When a read voltage Vread is applied to the selected word line WL1, a cell current flowing through the bit line BL1 may be generated based on the programming state of the memory cell F1 connected to the bit line BL1. For example, when the memory cell F1 is in the erase state E, the cell current may be the largest, and when the memory cell F1 is in the programming state PV3, the cell current may be the smallest.

[0158] The bit line selector 131 and the sensor 132 may electrically connect the bit line BL1 to the sensing node SO, and may evaluate the sensing node SO based on the cell current of the memory cell F1. That is, a cell current corresponding to the programming state of the memory cell F1 may flow through the bit line BL1. The sensing node SO connected to the bit line BL1 may decrease from a first level VH to a second level VL based on the cell current, and the time for the sensing node SO to decrease from the first level VH to the second level VL may be adjusted based on the magnitude of the cell current. As a result, the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be adjusted based on the programming state of the memory cell.

[0159] For example, when the selected memory cell F1 is in the erase state E having the lowest threshold voltage distribution, the cell current of the bit line BL1 may be the largest, and the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be the shortest. For example, when the selected memory cell F1 is in the erase state E, the potential of the sensing node SO may be discharged to the second level VL within the first period.

[0160] For example, when the selected memory cell F1 is in the programming state PV1 having a threshold voltage distribution higher than that of the erase state E, the cell current of the bit line BL1 may be smaller than the cell current corresponding to the erase state E, and the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be longer than the time corresponding to the erase state E. For example, when the selected memory cell F1 is in the programming state P1, the potential of the sensing node SO may be discharged to the second level VL within the second period.

[0161] For example, when the selected memory cell F1 is in the programming state PV2 having a threshold voltage distribution higher than that of the programming state PV1, the cell current of the bit line BL1 may be less than the cell current corresponding to the programming state PV1, and the time for the potential of the sensing node SO to decrease from the first level VH to the second level VL may be longer than the time corresponding to the programming state PV1. For example, when the selected memory cell F1 is in the programming state P2, the potential of the sensing node SO may be discharged to the second level VL within the third period.

[0162] For example, when the selected memory cell F1 is in the program state PV3 having the highest threshold voltage distribution, the cell current of the bit line BL1 may be minimum.

[0163] The control signal generator 142 may generate a latch signal PLS that is inverted multiple times in response to a clock signal CLK that is inverted at a predetermined cycle and may output the latch signal PLS that is inverted multiple times.

[0164] For example, the first inversion period of the latch signal PLS may be included in the first period, which is a period from the time point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell in the erase state E to the time point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell in the program state PV1. That is, the first rising edge and falling edge of the latch signal PLS may be included in the first period.

[0165] For example, the second inversion period of the latch signal PLS may be included in the second period, and the second period is a period from the time point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell in the programming state PV1 to the time point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell in the programming state PV2. That is, the second rising edge and falling edge of the latch signal PLS may be included in the second period.

[0166] For example, the third inversion period of the latch signal PLS may be included in the third period, which is a period after the time point at which the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV2. That is, the third rising edge and falling edge of the latch signal PLS may be included in the third period.

[0167] The timing of the rising and falling edges of the latch signal PLS may be set based on the cell current corresponding to the erase state E and each of the plurality of program states PV1 to PV3. Figure 6 The sensing node of sets the timing of the rising edge and the timing of the falling edge of the latch signal PLS based on a time point when the cell current corresponding to each of the erase state and the plurality of program states decreases from the first level VH as the precharge level to the second level VL.

[0168] Each of the plurality of latch stages 134E to 134G of the latch component 134 may latch data in response to a latch signal PLS.

[0169] For example, in the first period when the latch signal PLS is first flipped, the latch stage 134E may latch data corresponding to the potential of the sensing node SO in response to the rising edge of the latch signal PLS. For example, when the memory cell F1 is in the erase state E, the latch stage 134E may latch "0" data corresponding to the potential of the sensing node SO reduced to the second level VL. The latch stage 134E may output data to the output terminal Q in response to the falling edge of the latch signal PLS. <1> The latched "0" data is output. For example, when the memory cell F1 is in any one of the programming states PV1, PV2, and PV3, the latch stage 134E may latch the "1" data corresponding to the potential of the sensing node SO higher than the second level VL. The latch stage 134E may output the latched "0" data to the output terminal Q in response to the falling edge of the latch signal PLS. <1> Outputs the latched "1" data.

[0170] In the second period in which the latch signal PLS is flipped for the second time, the latch stage 134F may receive and latch the data output from the latch stage 134E in response to the rising edge of the latch signal PLS, and the latch stage 134E may latch the data corresponding to the potential of the sensing node SO. For example, when the memory cell F1 is in the erase state E or the programming state PV1, the latch stage 134E may latch the "0" data corresponding to the potential of the sensing node SO reduced to the second level VL. For example, when the memory cell F1 is in any one of the programming states PV2 and PV3, the latch stage 134E may latch the "1" data corresponding to the potential of the sensing node SO higher than the second level VL.

[0171] The latch stage 134E may respond to the falling edge of the latch signal PLS to the output terminal Q <1> The latch stage 134F can output the latched data to the output terminal Q in response to the falling edge of the latch signal PLS. <2> Outputs the latched data.

[0172] In the third period in which the latch signal PLS is flipped for the third time, the latch stage 134G may receive and latch the data output from the latch stage 134F in response to the rising edge of the latch signal PLS, and the latch stage 134F may receive and latch the data output from the latch stage 134E in response to the rising edge of the latch signal PLS, and the latch stage 134E may latch the data corresponding to the potential of the sensing node SO. For example, when the memory cell F1 is in the erase state E, the programming state PV1, or the programming state PV2, the latch stage 134E may latch the "0" data corresponding to the potential of the sensing node SO reduced to the second level LV. For example, when the memory cell F1 is in the programming state PV3, the latch stage 134E may latch the data "1" corresponding to the potential of the sensing node SO higher than the second level LV.

[0173] The latch stage 134E may respond to the falling edge of the latch signal PLS to the output terminal Q <1> The latch stage 134F can output the latched data to the output terminal Q in response to the falling edge of the latch signal PLS. <2> The latch stage 134G can output the latched data to the output terminal Q in response to the falling edge of the latch signal PLS. <3> Outputs the latched data.

[0174] The data output circuit 135 may receive data from the output terminal Q<3;1>, and may output MSB data and LSB data as bit read data DATA to a bit output line BITOUT based on the received data.

[0175] As described above, according to the embodiments of the present disclosure, during the read operation of a memory cell in which a plurality of data bits are stored, in a state where one read voltage is applied to a word line, the programming state of the memory cell can be sensed by sensing the time point at which the sensing node SO is reduced to the second level. Therefore, the operation speed of the read operation can be increased, and the area of ​​the circuit for generating the read voltage can be reduced by using only one read voltage instead of a plurality of read voltages.

[0176] Fig.17 is a diagram illustrating another embodiment of a memory system.

[0177] Reference Fig.17 , the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 may control data access operations of the memory device 1100, such as a program operation, an erase operation, or a read operation, under the control of the processor 3100.

[0178] Data programmed in the memory device 1100 may be output through the display 3200 under the control of the memory controller 1200 .

[0179] The radio transceiver 3300 can send and receive radio signals through the antenna ANT. For example, the radio transceiver 3300 can convert the radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and send the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 can program the signal processed by the processor 3100 to the memory device 1100. In addition, the radio transceiver 3300 can convert the signal output from the processor 3100 into a radio signal and output the converted radio signal to an external device through the antenna ANT. The input device 3400 can be a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device, a keypad, or a keyboard such as a touch pad or a computer mouse. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 1200 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output through the display 3200 .

[0180] According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100, and may also be implemented as a chip separate from the processor 3100. Figure 1 The illustrated example of controller 1200 implements a memory controller 1200 .

[0181] Fig.18 is a diagram illustrating another embodiment of a memory system.

[0182] Reference Fig.18 , the memory system 40000 may be implemented as a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0183] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation of the memory device 1100 .

[0184] The processor 4100 may output data stored in the memory device 1100 through the display 4300 based on data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0185] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the memory controller 1200. According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or may be implemented as a chip separate from the processor 4100. Figure 1 The illustrated example of controller 1200 implements a memory controller 1200 .

[0186] Fig.19 is a diagram illustrating another embodiment of a memory system.

[0187] Reference Fig.19 , the memory system 50000 may be implemented as an image processing device, for example, a digital camera, a portable phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet PC provided with a digital camera.

[0188] The memory system 50000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation (eg, a program operation, an erase operation, or a read operation) of the memory device 1100 .

[0189] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The converted digital signal may be sent to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signal may be output through the display 5300, or may be stored in the memory device 1100 through the memory controller 1200. In addition, under the control of the processor 5100 or the memory controller 1200, the data stored in the memory device 1100 may be output through the display 5300.

[0190] According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 5100, or may be implemented as a chip separate from the processor 5100. Figure 1 The illustrated example of controller 1200 implements a memory controller 1200 .

[0191] Fig. 20 is a diagram illustrating another embodiment of a memory system.

[0192] Reference Fig. 20 The memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0193] The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to an embodiment, the card interface 7100 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto. Figure 1 The illustrated example of controller 1200 implements a memory controller 1200 .

[0194] The card interface 7100 may interface data exchange between the host 60000 and the memory controller 1200 based on the protocol of the host 60000. According to an embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0195] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box, the interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0196] Although the present disclosure has been described with reference to limited embodiments and drawings, the present disclosure is not limited to the above-described embodiments, and those skilled in the art to which the present disclosure pertains may make various changes and modifications based on the disclosed description.

[0197] CROSS-REFERENCE TO RELATED APPLICATIONS

[0198] This application claims the priority of Korean Patent Application No. 10-2020-0128216 filed on October 5, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.< / m> < / m>

Claims

1. A page buffer, comprising: a bit line selector connecting a bit line of the memory cell array to a sensing node; a precharger, the precharger precharging the potential of the sensing node to a first level; as well as a latch component that senses data by detecting a time when the potential of the sensing node decreases from the first level to a second level, Wherein, the latch component comprises: a first latch stage that latches data corresponding to the potential of the sensing node in response to a rising edge of a latch signal and outputs the latched data to a first output terminal in response to a falling edge of the latch signal; a second latch stage that latches data received from the first output terminal in response to the rising edge of the latch signal and outputs the latched data to a second output terminal in response to the falling edge; and A third latch stage latches the data received from the second output terminal in response to the rising edge of the latch signal and outputs the latched data to a third output terminal in response to the falling edge.

2. The page buffer according to claim 1, further comprising: A data output circuit receives data output from a plurality of output terminals of the latch component and outputs the data to an external device.

3. The page buffer according to claim 1, wherein: Each of the first latch stage, the second latch stage, and the third latch stage latches the data corresponding to the potential of the sensing node in response to the latch signal flipped a plurality of times.

4. The page buffer according to claim 1, wherein: Each of the first latch stage, the second latch stage, and the third latch stage is constituted by a D flip-flop.

5. A semiconductor memory device, the semiconductor memory device comprising: a memory block having a plurality of memory cells programmed into an erased state and a plurality of programmed states; a voltage generating circuit that generates a read voltage to be applied to a word line of the memory block during a read operation; as well as a read / write circuit connected to a plurality of bit lines of the memory block and latching data by sensing a potential level of a sense node based on cell currents of the plurality of memory cells during the read operation, The read / write circuit includes a plurality of page buffers respectively connected to the plurality of bit lines. Each of the plurality of page buffers comprises: A bit line selector connecting any one of the plurality of bit lines and the sensing node; a precharger configured to precharge a potential of the sensing node to a first level; and a latch component that senses the data by detecting a time when the potential of the sensing node decreases from the first level to a second level, and Wherein, the latch component comprises: a first latch stage that latches data corresponding to the potential of the sensing node in response to a rising edge of a latch signal and outputs the latched data to a first output terminal in response to a falling edge of the latch signal; a second latch stage that latches data received from the first output terminal in response to the rising edge of the latch signal and outputs the latched data to a second output terminal in response to the falling edge; and A third latch stage latches the data received from the second output terminal in response to the rising edge of the latch signal and outputs the latched data to a third output terminal in response to the falling edge.

6. The semiconductor memory device according to claim 5, wherein: In a state where the one read voltage is applied during the read operation, the cell currents of the plurality of memory cells vary based on the erase state and the plurality of program states.

7. The semiconductor memory device according to claim 5, wherein: The read voltage is lower than a threshold voltage of a program state having a highest threshold voltage distribution among the erase state and the plurality of program states.

8. The semiconductor memory device according to claim 5, wherein: The read voltage is an intermediate voltage value of two program states having a relatively highest threshold voltage distribution among the erase state and the plurality of program states.

9. The semiconductor memory device according to claim 8, wherein: The read voltage is an intermediate voltage value between a first threshold voltage value of most memory cells among the memory cells corresponding to a first programming state of the two programming states and a second threshold voltage value of most memory cells among the memory cells corresponding to a second programming state of the two programming states.

10. The semiconductor memory device according to claim 5, wherein: Each of the plurality of page buffers further includes a data output circuit which receives data output from the plurality of output terminals of the latch component and outputs the data to an external device.

11. The semiconductor memory device according to claim 5, wherein: Each of the first latch stage, the second latch stage, and the third latch stage latches the data corresponding to the potential of the sensing node in response to the latch signal flipped a plurality of times.

12. The semiconductor memory device according to claim 5, wherein: Each of the first latch stage, the second latch stage, and the third latch stage is constituted by a D flip-flop.

13. A semiconductor memory device, the semiconductor memory device comprising: a memory block having a plurality of memory cells programmed into an erased state and a plurality of programmed states; a voltage generating circuit that generates a read voltage to be applied to a word line of the memory block during a read operation; as well as a page buffer connected to a bit line of the memory block, precharging a potential of a sense node connected to the bit line to a first level during the read operation, and latching data by detecting a time when the sense node decreases from the first level to a second level based on a programming state of a selected memory cell among the plurality of memory cells connected to the bit line, Wherein, the page buffer comprises: a bit line selector connecting the bit line and the sensing node; a precharger configured to precharge a potential of the sensing node to a first level; and a latch component that senses the data by detecting a time when the potential of the sensing node decreases from the first level to a second level, and Wherein, the latch component comprises: a first latch stage that latches data corresponding to the potential of the sensing node in response to a rising edge of a latch signal and outputs the latched data to a first output terminal in response to a falling edge of the latch signal; a second latch stage that latches data received from the first output terminal in response to the rising edge of the latch signal and outputs the latched data to a second output terminal in response to the falling edge; and A third latch stage latches the data received from the second output terminal in response to the rising edge of the latch signal and outputs the latched data to a third output terminal in response to the falling edge.

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