Memory with improved command / address bus utilization

Abstract

Memory devices and systems with improved command / address bus utilization are disclosed herein. In one embodiment, a memory device includes a plurality of external command / address terminals and a command decoder. The plurality of external command / address terminals are configured to receive a command as a corresponding plurality of command / address bits. A first set of command / address bits indicates a read or write operation. A second set of command / address bits indicates whether to perform a refresh operation. The memory device is configured to perform a read or write operation to a portion of a memory array in response to the first set of command / address bits. The memory device is further configured to perform the refresh operation to refresh at least one memory bank of the memory array in response to the second set of command / address bits when the second set of command / address bits indicates that the refresh operation should be performed.

Description

Technical Field

[0001] This disclosure relates to memory systems, apparatuses, and associated methods. In particular, this disclosure relates to memory apparatuses having an improved command / address bus. Background Technology

[0002] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, including static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), as well as other types of memory, may require an external power source to maintain its data. In contrast, non-volatile memory retains its stored data even without an external power supply. Non-volatile memory can be used in a wide variety of technologies, including flash memory (such as NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), as well as other types of memory. Improving memory devices can generally include increasing memory cell density, increasing read / write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. Summary of the Invention

[0003] One aspect of this disclosure relates to a memory device comprising: a memory array including a plurality of memory banks; a plurality of external command / address terminals configured to receive commands as corresponding to a plurality of command / address bits, wherein a first set of command / address bits indicates a read or write operation and a second set of command / address bits indicates whether a refresh operation should be performed; and a command decoder configured to decode the commands by monitoring the plurality of command / address bits, wherein the memory device is configured to perform the read or write operation on a portion of the memory array in response to the first set of command / address bits of the command, and wherein the memory device is configured to perform a refresh operation to refresh at least one of the plurality of memory banks in response to the second set of command / address bits of the command when the second set of command / address bits indicates that the refresh command should be performed.

[0004] Another aspect of this disclosure relates to a method comprising: receiving commands as a plurality of command / address bits via corresponding plurality of external command / address terminals of a memory device, wherein a first set of command / address bits indicates a read or write operation and a second set of command / address bits indicates whether a refresh operation is to be performed; performing the read or write operation on a portion of a memory array of the memory device in response to the first set of command / address bits of the command; and performing the refresh operation to refresh at least one memory bank of the memory device when the second set of command / address bits indicates that the refresh operation should be performed in response to the command.

[0005] Another aspect of this disclosure relates to a memory system comprising: a memory controller and / or a host device; and a memory device communicating with the memory controller and / or the host device via one or more command / address buses, wherein the memory device includes: a plurality of external command / address terminals connected to the one or more command / address buses and configured to receive commands via the one or more command / address buses from the memory controller and / or from the host device as corresponding to a plurality of command / address bits; and a command decoder configured to decode the commands by monitoring the corresponding plurality of command / address bits, wherein: a first set of command / address bits indicates a read or write operation and a second set of command / address bits indicates whether a refresh operation is performed; the memory controller and / or the host device is configured to embed a refresh command into the command using the second set of command / address bits of the command; and the command decoder is further configured to determine, at least in part, whether a refresh operation is performed in response to the command in addition to performing the read or write operation, based on the second set of command / address bits of the command. Attached Figure Description

[0006] Many aspects of this disclosure can be better understood with reference to the accompanying drawings. The components in the drawings are not necessarily to scale. Rather, the focus should be on clearly illustrating the principles of this disclosure. The drawings should not be construed as limiting this disclosure to the specific embodiments depicted, but are merely for explanation and understanding.

[0007] Figure 1 This is a block diagram schematically illustrating a memory system configured according to various embodiments of the present technology.

[0008] Figure 2A This is a timing diagram of the refresh all memory command (REFab) according to various embodiments of the present technology.

[0009] Figure 2BThis is a timing diagram of refresh single memory bank commands (REFsb) according to various embodiments of the present technology.

[0010] Figure 3 This is a timing diagram illustrating bus utilization when a read command, a precharge command, and a refresh single memory bank (REFsb) command are issued according to various embodiments of the present technology.

[0011] Figure 4 This is a timing diagram illustrating bus utilization when a Read Automatic Precharge + Refresh (ReadAPR) command is issued according to various embodiments of the present technology.

[0012] Figure 5 This is a timing diagram illustrating bus utilization when write commands, precharge commands, and refresh single memory bank (REFsb) commands are issued according to various embodiments of the present technology.

[0013] Figure 6 This is a timing diagram illustrating bus utilization when a Write Automatic Precharge + Refresh (WriteAPR) command is issued according to various embodiments of the present technology.

[0014] Figure 7 This is a flowchart illustrating routines for configuring memory devices and / or memory systems according to various embodiments of the present technology.

[0015] Figure 8 This is a schematic diagram of a system comprising a memory device configured according to various embodiments of the present technology. Detailed Implementation

[0016] For example, a DRAM device's memory device utilizes refresh operations to protect data from damage caused by factors such as charge leakage or other effects that can degrade data over time. Typically, the memory device performs a refresh operation in response to receiving a refresh command (e.g., from the memory controller and / or from the host device). One such refresh command is a Refresh All Banks Command (REFab). In response to receiving a Refresh All Banks Command (REFab), the memory device continues to perform several refresh operations to refresh all memory banks of its memory array within time period tRFC1. Because all memory banks of the memory array are refreshed in response to receiving the Refresh All Banks Command (REFab), the memory device locks the entire memory array for the entire duration of time period tRFC1, meaning that the memory banks of the memory device are inaccessible for reading or writing data and / or for other operations during time period tRFC1. Therefore, whenever the memory device receives and executes a Refresh All Banks Command (REFab), the total time available for reading and writing data to the memory array of the memory device is reduced.

[0017] In some embodiments, a Refresh Single Bank Command (REFsb) can be used instead of a Refresh All Banks Command (REFab). In response to receiving a Refresh Single Bank Command (REFsb), the memory device continues to perform one or more refresh operations (e.g., automatic refresh and / or row hammer refresh) on only one memory bank in the memory array (e.g., the memory bank specified in the Refresh Single Bank Command (REFsb) or specified by a counter of the memory device). Therefore, the memory device locks only one memory bank within a time period tRFCsb, which is shorter than the time period tRFC1 of the Refresh All Banks Command (REFab). Additionally, the other memory banks in the memory array remain unlocked and are available for reading or writing data and / or for other operations when the memory device executes the Refresh Single Bank Command (REFsb).

[0018] This means that multiple Refresh Single Bank Commands (REFsb) are needed to refresh each memory bank in the memory array. For example, sixteen Refresh Single Bank Commands (REFsb) are needed to refresh a memory array containing a total of sixteen memory banks. Therefore, using Refresh Single Bank Commands (REFsb) to refresh each memory bank in the memory array consumes more command / address bus bandwidth than using a single Refresh All Banks Command (REFab).

[0019] The memory devices and systems of this technology address this problem by embedding a Refresh Single Bank Command (REFsb) and / or other refresh commands into one or more other commands (e.g., read, write, and / or other commands) issued to and / or received by the memory device. For example, the Refresh Single Bank Command (REFsb) may be issued to the memory device after a read or write command. Continuing this example, the command / address bits of the read or write command may be used in some embodiments to indicate whether the memory device executes the Refresh Single Bank Command (REFsb) and / or other refresh commands after executing a read or write command. In this way, by embedding the refresh command into other commands transmitted via the command / address bus, the memory system of this technology can issue refresh commands and / or the memory device of this technology can receive refresh commands, while minimizing and / or reducing the consumption of command / address bus bandwidth.

[0020] Those skilled in the art will understand that this technology may have additional embodiments, and may be implemented without the need for further reference below. Figures 1 to 8The present invention is practiced in accordance with several details of the described embodiments. In the embodiments described below, memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the present invention may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive and other storage media, including non-volatile flash (e.g., NAND and / or NOR) storage media.

[0021] As used herein, the term "refresh" refers to various maintenance operations that can be performed on one or more memory cells of a memory device configured according to various embodiments of the present technology. In some embodiments, the term "refresh" may refer to maintenance operations performed on one or more memory cells to maintain their data. For example, in the context of DRAM and other memory devices, the term "refresh" may refer to reading data from one or more memory cells and rewriting data to one or more memory cells to increase the charge stored on one or more memory cells to improve charge leakage and prevent data loss. In these and other embodiments, the term "refresh" may refer to reading data from one or more memory cells and rewriting data to one or more memory cells that are in an inverted or other data state (e.g., high to low or low to high) to improve hysteresis, material depolarization, imprinting and / or wear effects or the like. In these and other embodiments, the term "refresh" may refer to other maintenance operations, such as reading data from one or more memory cells and rewriting data to one or more memory cells at another / other memory location.

[0022] In the embodiments described below, for clarity and understanding, the memory devices and systems are primarily described in the context of embedding a refresh single bank command (REFsb) into other commands issued to and / or received by the memory device. However, this disclosure is not limited thereto. Those skilled in the art will recognize that all or a subset of the techniques disclosed herein can be implemented in the context of embedding other refresh commands (e.g., refresh all bank command (REFab), fine-grained refresh commands, and / or other refresh commands) into other commands issued to and / or received by the memory device, and such implementations fall within the scope of this technology.

[0023] Figure 1This is a block diagram schematically illustrating a memory system 190 configured according to various embodiments of the present technology. The memory system 190 may include a memory device 100 (e.g., an individual memory die, multiple memory dies, etc.) that can be connected to any of or components of several electronic devices capable of using memory for temporary or permanent storage of information. For example, the memory device 100 may be operatively connected to a memory controller 101 (via interface 119) and / or a host device 108 (e.g., via interface 116 and / or via memory controller 101 and interface 117). The host device 108 operatively connected to the memory device 100 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or components thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device 108 may be a networking device (e.g., a switch, router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, equipment, a toy, or any of several other products. In one embodiment, host device 108 may be directly connected to memory device 100, but in other embodiments, host device 108 may be indirectly connected to memory device 100 (e.g., via a network connection or through an intermediary device, such as memory controller 101).

[0024] The memory device 100 may receive multiple signals (e.g., from the memory controller 101 and / or from the host device 108). In this regard, the memory device 100 may employ multiple external terminals, including command and address terminals respectively coupled to the command / address bus and the address bus to receive command signal CMD and address signal ADDR. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, and power supply terminals VDD, VSS, and VDDQ.

[0025] The power supply terminals of memory device 100 may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to internal voltage generator circuit 170. Internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. Internal potential VPP may be used in line decoder 140, internal potentials VOD and VARY may be used in sense amplifiers included in memory array 150 of memory device 100, and internal potential VPERI may be used in many other circuit blocks.

[0026] A power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output (IO) circuit 160 together with the power supply potential VSS. In an embodiment of this technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of this technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used in the IO circuit 160 so that power supply noise generated by the IO circuit 160 does not propagate to other circuit blocks.

[0027] The clock terminal and digital clock terminal can be supplied with external clock signals and complementary external clock signals. External clock signals CK, CKF, WCK, and WCKF can be supplied to clock input circuit 120. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0028] An input buffer included in clock input circuit 120 can receive an external clock signal. For example, when enabled by the CKE signal from command decoder 115, the input buffer can receive CK and CKF signals and WCK and WCKF signals. Clock input circuit 120 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase and frequency controlled internal clock signals based on the internal clock signal ICLK received from command decoder 115 and the clock enable signal CKE. For example, internal clock circuit 130 may include a clock path ( Figure 1(Not shown), it receives the internal clock signal ICLK and provides various clock signals (not shown) to the command decoder 115. The internal clock circuit 130 can further provide input / output (IO) clock signals. The IO clock signals can be supplied to the IO circuit 160 and can be used as timing signals to determine the output timing for reading data and the input timing for writing data. The IO clock signals can be provided at multiple clock frequencies, so that data can be output from and input to the memory device 100 at different data rates. Higher clock frequencies may be required when high memory speed is desired. Lower clock frequencies may be required when low power consumption is desired. The internal clock signal ICLK can also be supplied to the timing generator 135, and thus, various internal clock signals can be generated that can be used by the command decoder 115, the column decoder 145, and / or other components of the memory device 100.

[0029] Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in multiple memory regions, and each memory region may include multiple word lines (WL), multiple bit lines (BL), and multiple memory cells arranged at the intersections of word lines and bit lines. In some embodiments, a memory region may be one or more memory banks or another arrangement of memory cells (e.g., half a memory bank, a subarray within a memory bank, etc.). In these and other embodiments, the memory regions of memory array 150 may be arranged in one or more groups (e.g., one or more groups of memory banks, one or more logical memory ranks, or dies, etc.). The memory cells in memory array 150 may include any of several different memory media types (including capacitive, magnetoresistive, ferroelectric, phase-change, or similar). The selection of word lines WL may be performed by row decoder 140, and the selection of bit lines BL may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may in turn be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) (which may function as a switch). The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0030] Command and address terminals can be supplied with address signals and bank address signals from outside the memory device 100 (e.g., from the memory controller 101 and / or the host device 108) via command and address buses (e.g., via interfaces 116, 117, and / or 119), respectively. The address signals and bank address signals supplied to the address terminals can be transmitted to the address decoder 110 via command / address input circuitry 105. Address decoder 110 can receive address signals and supply the decoded row address signal (XADD) to row decoder 140, and the decoded column address signal (YADD) to column decoder 145. Address decoder 110 can also extract the bank address signal (BADD) and supply it to both row decoder 140 and column decoder 145.

[0031] Command and address terminals may be supplied with command signal CMD, address signal ADDR, and chip select signal CS (e.g., from memory controller 101 and / or host device 108). Command signals may represent various memory commands (e.g., access commands, which may include read, write, and refresh commands). The select signal CS can be used to select memory device 100 in response to commands and addresses provided to the command and address terminals. When a valid CS signal is provided to memory device 100, commands and addresses can be decoded, and memory operations can be performed. Command signal CMD may be provided as internal command signal ICMD to command decoder 115 via command / address input circuitry 105. Command decoder 115 may include circuitry for decoding internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Internal command signals may also include output and input activation commands, such as timing commands CMDCK (not shown) to command decoder 115.

[0032] Command decoder 115 may further include one or more registers 118 for tracking various counts or values ​​(e.g., counts of refresh commands received by memory device 100 or counts of self-refresh operations performed by memory device 100) and / or for storing various operating conditions for memory device 100 to perform specific functions, features, and modes (refresh mode, test mode, etc.). Thus, in some embodiments, register 118 (or a subset of register 118) may be referred to as a mode register. For example, memory device 100 can be placed in refresh mode by programming specific bits of register 118.

[0033] When a read command is issued and the row and column addresses are supplied in a timely manner along with the read command, read data can be read from the memory cells specified by these row and column addresses in memory array 150. The read command can be received by command decoder 115, which can provide internal commands to I / O circuitry 160, so that read data can be output from data terminals DQ, RDQS, DBI, and DMI via read / write (RW) amplifier 155 and I / O circuitry 160 according to the RDQS clock signal. The read data can be provided at a time defined by read delay information RL, which can be programmed in memory device 100 (e.g., in mode register 118). Read delay information RL can be defined based on the clock cycles of the CK clock signal. For example, read delay information RL can be the number of clock cycles of the CK signal after the read command is received by memory device 100 when the associated read data is provided.

[0034] When a write command is issued and the row and column addresses are supplied in time along with the command, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by the command decoder 115, which can provide an internal command to the I / O circuit 160, allowing the write data to be received by the data receiver in the I / O circuit 160 and supplied to the memory array 150 via the I / O circuit 160 and RW amplifier 155. The write data can be written to the memory cell specified by the row and column addresses. The write data can be supplied to the data terminals at a time defined by the write delay WL information. The write delay WL information can be programmed into the memory device 100 (e.g., in the mode register 118). The write delay WL information can be defined according to the clock cycle of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0035] As described herein, memory array 150 can be refreshed or maintained to prevent data loss due to charge leakage or imprinting effects. As described herein, a refresh operation can be initiated by memory system 190 (e.g., by host device 108, memory controller 101, and / or memory device 100) and may include accessing one or more rows (e.g., WL) and discharging the cells of the accessed row to the corresponding SAMP. When the row is open (e.g., when the accessed WL is energized), the SAMP can compare the voltage caused by the discharged cell with a reference. The SAMP can then write the logic value (e.g., charge the cell) back to the nominal value of the given logic state. In some cases, this write-back process can increase the cell charge to improve the discharge problem discussed above. In other cases, the write-back process can reverse the data state of the cell (e.g., from high to low or from low to high) to improve hysteresis, material depolarization, or the like. Other refresh schemes or methods may also be employed.

[0036] In one method, memory device 100 may be configured to simultaneously refresh memory cells in the same row of each memory bank of memory array 150. In another method, memory device 100 may be configured to sequentially refresh memory cells in the same row of each memory bank of memory array 150. In yet another method, memory device 100 may further include circuitry (e.g., one or more registers, latches, embedded memories, counters, etc.) configured to track row (e.g., word line) addresses, each corresponding to one of the memory banks in memory array 150. In this method, memory device 100 is not restricted to refreshing the same row in each memory bank of memory array 150 before refreshing another row in one of the memory banks.

[0037] Regardless of the refresh method, memory device 100 can be configured to refresh memory cells in memory array 150 within a given refresh rate or time window (e.g., 32ms, 28ms, 25ms, 23ms, 21ms, 18ms, 16ms, 8ms, etc.) (referred to as tREF). In these embodiments, memory system 190 (e.g., memory controller 101, host device 108, and / or memory device 100) can be configured to supply refresh commands to memory device 100 according to a specified minimum tREF. For example, memory system 190 can be configured to supply one or more refresh commands to memory device 100 at least every 7.8μs, such that a suitable minimum of 4000 refresh commands are supplied to memory device 100 within a 32ms time window.

[0038] As explained above, an example of a refresh command is the Refresh All Banks command (REFab). In response to receiving the Refresh All Banks command (REFab), memory device 100 performs several refresh operations (e.g., one or more automatic refresh operations and / or one or more row hammer refresh (RHR) operations) to refresh all memory banks of memory array 150. Figure 2A This is a timing diagram 210 showing commands sent to and / or received by the memory device 100 via the command / address bus according to various embodiments of the present technology. Specifically, Figure 2A This means that when memory device 100 receives a Refresh All Banks command (REFab), memory device 100 locks the entire memory array 150 for the duration tRFC1. In other words, when memory device 100 receives the Refresh All Banks command (REFab), the memory banks of memory array 150 cannot be used for reading or writing data and / or for other operations until the duration tRFC1 has elapsed. Therefore, whenever memory device 100 receives and executes the Refresh All Banks command (REFab), the total time that memory array 150 of memory device 100 can be used for reading and writing data and / or other operations is reduced. After the duration tRFC1 has elapsed, memory device 100 unlocks memory array 150 and can continue to receive other commands CMD All BK and / or execute other commands CMD All BK on any of the memory banks of memory array 150.

[0039] Another example of a refresh command is a refresh single bank command (REFsb). In response to receiving a refresh single bank command (REFsb), memory device 100 performs one or more refresh operations (e.g., one or more auto refresh operations and / or one or more RHR operations) on only one memory bank in memory array 150 (e.g., the memory bank specified in the refresh single bank command (REFsb) or specified by a counter of memory device 100). Figure 2B This is a timing diagram 215 showing commands sent to and / or received by the memory device 100 via the command / address bus according to various embodiments of the present technology. Specifically, Figure 2B The memory device 100 receives a refresh single memory bank command (REFsb B0). In response to the command, the memory device 100 locks memory bank B0 of the memory array 150 for a period tRECsb and continues to perform one or more refresh operations on memory bank B0 only until the period tRECsb expires. As shown, the period tRECsb is significantly shorter in duration than Figure 2ADuring the period tRFCsb, other memory banks of memory array 150 (e.g., memory banks B1, B2, and B3) remain unlocked (e.g., available for reading or writing data and / or for other operations), meaning that memory device 100 can receive other commands (e.g., command CMD B1, B2, B3) and / or execute said other commands on other memory banks of memory array 150. After the period tRFCsb has elapsed, memory device 100 unlocks memory bank B0 and can continue to receive other commands CMD All BK and / or execute other commands CMD All BK on any of the memory banks of memory array 150.

[0040] In some embodiments, instead of or in place of the refresh all memory bank command (REFab), a refresh single memory bank command (REFsb) may be used (e.g., to keep at least a portion of memory array 150 available for reading or writing data and / or for other operations when memory device 100 refreshes one or more memory banks of memory array 150). That is, multiple refresh single memory bank commands (REFsb) are required to refresh multiple memory banks of memory array 150. For example, sixteen refresh single memory bank commands (REFsb) are required to refresh a memory array comprising a total of sixteen memory banks. Therefore, using multiple refresh single memory bank commands (REFsb) to refresh all or even some memory banks of memory array 150 can consume more command / address bus bandwidth than using a single refresh all memory bank command (REFab).

[0041] To address this issue, memory system 190 may embed a refresh single bank command (REFsb) and / or other refresh commands into one or more other commands (e.g., read, write, and / or other commands) issued to and / or received by memory device 100 via the command / address bus. For example, a refresh single bank command (REFsb) and / or another refresh command may be issued to memory device 100 after a read command. Figure 3 This is a timing diagram 320 illustrating the command / address bus utilization under this example according to various embodiments of the present technology. As shown, an activation command (ACT) is sent to and / or received by memory device 100, followed by a read command (Read). Once data is read from memory array 150, a precharge command (Pre) is sent to and / or received by memory device 100 to precharge all or part of memory array 150 for a refresh operation performed by memory device 100 in response to receiving a subsequent refresh command (e.g., a refresh single bank command (REFsb)).

[0042] Figure 4 This is a timing diagram 420 illustrating the command / address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded in a read command (Read) or a read auto-precharge command (Read AP) according to various embodiments of the present technology. As shown, an activation command (ACT) is sent to and / or received by memory device 100, followed by a read auto-precharge + refresh command (Read APR). A first set (e.g., one or more) of command / address bits of the read auto-precharge + refresh command (Read APR) indicates a read operation and / or a precharge operation, and a second set (e.g., one or more) of command / address bits of the read auto-precharge + refresh command (Read APR) indicates a refresh operation. The first set of command / address bits may be the same as or different from the second set of command / address bits. In response to the first set of command / address bits of the read auto-precharge + refresh command (Read APR), memory device 100 continues to read data from memory array 150 and / or precharge all or part of memory array 150. In response to the second set of command / address bits of the Read Automatic Precharge + Refresh command (Read APR), the memory device 100 continues to perform one or more refresh operations on all or part of the memory array 150. In other words, assuming embedded in Figure 4 The refresh command in the Read Automatic Precharge + Refresh command (Read APR) is a refresh single-bank command (REFsb) for memory bank B0 of memory array 150. Then, memory device 100 continues to execute... Figure 3 The same sequence of operations is described, but two fewer commands are transmitted via the command / address bus. Therefore, by embedding refresh commands (e.g., a refresh single-bank command (REFsb) or another refresh command) into read commands or read auto-precharge commands (Read AP), memory system 190 reduces the amount of command / address bus bandwidth used to refresh one or more memory banks of memory array 150. In this way, memory system 190 can issue (and / or memory device 100 can receive) a refresh single-bank command (REFsb) to refresh the memory banks of memory array 150, while keeping other memory banks of memory array 150 available for reading or writing data and / or for other operations, while minimizing and / or reducing command / address bus bandwidth consumption.

[0043] As another example, a refresh single bank command (REFsb) and / or another refresh command may be issued to memory device 100 after a write command. Figure 5This is a timing diagram 520 illustrating the command / address bus utilization under this example according to various embodiments of the present technology. As shown, an activation command (ACT) is sent to and / or received by memory device 100, followed by a write command (Write). Once data is written to memory array 150, a precharge command (Pre) is sent to and / or received by memory device 100 to precharge all or part of memory array 150 for a refresh operation performed by memory device 100 in response to receiving a subsequent refresh command (e.g., a refresh single bank command (REFsb)).

[0044] Figure 6 This is a timing diagram 620 illustrating the command / address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded in a write command or a write auto-precharge command (Write AP) according to various embodiments of the present technology. As shown, an activation command (ACT) is sent to and / or received by memory device 100, followed by a write auto-precharge + refresh command (Write AP). A first set (e.g., one or more) of command / address bits of the write auto-precharge + refresh command indicates a write operation and / or a precharge operation, and a second set (e.g., one or more) of command / address bits of the write auto-precharge + refresh command (Write AP) indicates a refresh operation. The first set of command / address bits may be the same as or different from the second set of command / address bits. In response to the first set of command / address bits of the write auto-precharge + refresh command (Write AP), memory device 100 continues to write data to memory array 150 and / or precharge all or part of memory array 150. In response to the second set of command / address bits of the Write Automatic Precharge + Refresh command (WriteAPR), the memory device 100 continues to perform one or more refresh operations on all or part of the memory array 150. In other words, assuming embedded in Figure 6 The refresh command in the Write Automatic Precharge + Refresh command (Write APR) is a refresh single-bank command (REFsb) for memory bank B0 of memory array 150. Then, memory device 100 continues to execute... Figure 5The same sequence of operations is described, but two fewer commands are transmitted via the command / address bus. Therefore, by embedding refresh commands (e.g., a refresh single-bank command (REFsb) or another refresh command) into write commands or write auto-precharge commands (Write AP), memory system 190 reduces the amount of command / address bus bandwidth used to refresh one or more memory banks of memory array 150. In this way, memory system 190 can issue (and / or memory device 100 can receive) a refresh single-bank command (REFsb) to refresh the memory banks of memory array 150, while keeping other memory banks of memory array 150 available for reading or writing data and / or for other operations, while minimizing and / or reducing command / address bus bandwidth consumption.

[0045] In some embodiments, the memory system 190 may use command / address bits of other commands to embed refresh commands into other commands. For example, one or more command / address bits of a Read command, a Read AP command, a Write command, and / or a Write AP command may be used to indicate whether the memory device 100 performs a refresh operation (e.g., refresh a single memory bank operation and / or another refresh operation) after performing a Read operation, a Read AP operation, a Write operation, and / or a Write AP operation. Table 1 below illustrates one possibility of embedding refresh commands into other commands using command / address bits (e.g., command / address bit 12) of other commands transmitted to and / or received by the memory device 100:

[0046]

[0047] Table 1

[0048] Referring to Table 1 above as an example, the memory device 100 can monitor the command / address bit 12 of a read command, read auto-precharge command (Read AP), write command, and / or write auto-precharge command (Write AP) received via the command / address bus. When the command / address bit 12 is asserted, the memory device can execute a refresh command after executing the corresponding read command, read auto-precharge command (Read AP), write command, and / or write auto-precharge command (Write AP). In other words, the memory device 100 can execute a read auto-precharge + refresh command (Read APR) or a write auto-precharge + refresh command (Write APR) when the command / address bit 12 is asserted. On the other hand, when the command / address bit 12 is not asserted, the memory device 100 can execute the original command (e.g., read command, read auto-precharge command (Read AP), write command, and / or write auto-precharge command (Write AP)) received via the command / address bus.

[0049] In some embodiments, the features described above can be enabled or disabled. As an example, a mode register can be used to enable or disable embedding a refresh command into a read command (READ). When enabled, memory device 100 can monitor command / address bit 12 of a read command (READ) to determine whether a refresh operation should be performed after a read operation, as described above. When disabled, memory device 100 can perform only a read operation in response to a read command (READ), regardless of whether command / address bit 12 is asserted.

[0050] Those skilled in the art will recognize that Table 1 above only illustrates four possible commands into which the memory system 190 can embed refresh commands. That is, those skilled in the art should understand that the memory system 190 can embed refresh commands into commands other than or replacing the Read command, Read AP command, Write command, and Write AP command (e.g., any other command that does not use all command / address bits). For example, the memory system 190 can embed refresh commands into precharge commands and / or into various mode register commands (e.g., mode register read commands, mode register write commands, mode register erase commands, etc.). Such other commands fall within the scope of this art.

[0051] Furthermore, those skilled in the art will recognize that one or more other command / address bits, besides or replacing command / address bit 12 in the examples provided in Table 1, can be used to embed a refresh command into other commands. In addition, those skilled in the art should recognize that, compared to the examples provided in Table 1 above, a refresh command can be embedded into another command by not asserting (as opposed to asserting) the corresponding command / address bit or by various combinations of asserting / not asserting command / address bits.

[0052] In some embodiments, one or more commands (e.g., a read command (READ) or a write command (WRITE)) may be embedded in a refresh command. For example, a read command (READ) or a write command (WRITE) may be embedded in a refresh single memory bank command (REFsb). Continuing this example, a first set (e.g., one or more) of command / address bits of the refresh command may indicate a refresh single memory bank operation, and a second set (e.g., one or more) of command / address bits of the refresh command may indicate a read or write operation. The first set of command / address bits may be the same as or different from the second set of command / address bits. In response to the first set of command / address bits of the refresh command, the memory device 100 continues to perform refresh operations on the memory banks or groups of memory banks of the memory array 150. Once the memory device or die has completed the refresh operation, the memory device or die may reopen the same memory row and may continue to read data or write data to the memory array 150. Reopening the same memory row after the refresh operation is completed avoids the memory controller 101 needing to issue another activation command (ACT) after the refresh operation is completed but before the read or write operation is performed.

[0053] Figure 7 This is a flowchart illustrating routine 780 configured in various embodiments of the present technology for a memory device and / or memory system. In some embodiments, routine 780 may be executed at least in part by the memory device, a memory controller operatively connected to the memory device, and / or a host device operatively connected to the memory controller and / or the memory device. For example, one or more steps of routine 780 may be implemented at least in part by components of the memory device, such as command / address input circuitry, command decoder, row decoder, column decoder, memory array, memory row, memory bank, and / or group of memory banks. In these and other embodiments, all or a subset of the steps of routine 780 may be executed by other components of the memory device, components of the memory controller, components of the host device, and / or other components of the memory system containing the memory device.

[0054] Routine 780 can be initiated at block 781 by receiving a command via the command / address bus as a plurality of command / address bits (e.g., as 14 command / address bits or another number of command / address bits). In some embodiments, the first set of command / address bits may indicate a read operation, a read operation and a precharge operation (Read AP), a write operation, and / or a write operation and a precharge operation (Write AP). In these and other embodiments, the first set of command / address bits may indicate another operation, such as a precharge operation (Pre) or a mode register operation. In these and other embodiments, a second set of command / address bits (e.g., one or more refresh command / address bits) may indicate whether a refresh operation (e.g., refresh a single memory bank operation, refresh all memory banks operation, fine-grained refresh operation, etc.) is performed. Each of the plurality of command / address bits is asserted or not asserted.

[0055] In block 782, routine 780 monitors multiple command / address bits of a command received at block 781 via the command / address bus. For example, routine 780 may monitor a first set of command / address bits of a command received at block 781 and determine that the first set of command / address bits indicates a read operation. In this embodiment, routine 780 may continue to block 783 to perform the read operation. In these and other embodiments, routine 780 may monitor a second set of command / address bits to determine whether to perform a refresh operation (e.g., in addition to the operation indicated by the first set of command / address bits). For example, routine 780 may determine whether command / address bits in the second set of command / address bits are asserted or not asserted. Continuing this example, when one or more command / address bits in the second set of command / address bits are not asserted, routine 780 may determine that no refresh operation is performed. On the other hand, when one or more command / address bits in the second set of command / address bits are asserted, routine 780 may determine that a refresh operation is performed.

[0056] In block 783, routine 780 executes the command received in block 781 with or without a refresh operation, depending on the state of the second set of command / address bits monitored at block 782. Continuing the example above, when the second set of command / address bits does not indicate that a refresh operation should be performed, routine 780 performs only a read operation at block 783. On the other hand, when the second set of command / address bits indicates that a refresh operation should be performed, routine 780 performs a refresh operation (e.g., after a read operation). In some embodiments, routine 780 performs a precharge operation after executing the operation indicated by the first set of command / address bits but before performing the refresh operation.

[0057] Although the steps of routine 780 are discussed and explained in a specific order, by Figure 7The method described in routine 780 is not limited thereto. In other embodiments, the method may be performed in a different order. In these and other embodiments, any of the steps of routine 780 may be performed before, during, and / or after any of the other steps of routine 780. Furthermore, those skilled in the art will readily recognize that the described method may be modified while remaining within these and other embodiments of the present technology. For example, in some embodiments, steps may be omitted and / or repeated. Figure 7 The routine 780 described herein may include one or more steps. In these and other embodiments, one or more steps of routine 780 may be combined to form one or more other routines of the memory device.

[0058] Figure 8 This is a schematic diagram of a system including a memory device according to an embodiment of the present technology. (See above reference) Figures 1 to 7 Any of the aforementioned memory devices can be incorporated into any of a multitude of larger and / or more complex systems, a representative example being... Figure 8 The system 890 is schematically shown in the diagram. System 890 may include a semiconductor device assembly 800, a power supply 892, a driver 894, a processor 896, and / or other subsystems and components 898. The semiconductor device assembly 800 may include components generally similar to those described in the reference above. Figures 1 to 7 The described memory device features characteristics and may therefore include various features for authenticating memory contents. The resulting system 890 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 890 may include (without limitation) handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, equipment, and other products. Components of system 890 may be housed in a single component or distributed across multiple interconnected components (e.g., via a communication network). Components of system 890 may also include remote devices and any of a wide variety of computer-readable media.

[0059] in conclusion

[0060] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed herein. Although specific embodiments and examples of this technology have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of this technology. For example, although steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may also be combined to provide other embodiments.

[0061] As should be understood from the foregoing, specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the present technology. If any material incorporated herein by reference conflicts with this disclosure, this disclosure shall prevail. Where the context permits, singular or plural items may also contain plural or singular items respectively. Furthermore, unless the word “or” is explicitly limited to meaning a single item excluded from other items when referring to a list of two or more items, its use in this list should be interpreted as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Where the context permits, singular or plural items may also contain plural or singular items respectively. Furthermore, as used herein, the phrase “and / or” in “A and / or” means A alone, B alone, and both A and B. Additionally, the use of the terms “comprising,” “including,” “having,” and “possessing” throughout the document means including at least the described features such that no larger number of identical features and / or other features of additional types are excluded.

[0062] It should also be understood from the foregoing that various modifications can be made without departing from the present technology. For example, the various components of the present technology can be further divided into sub-components, or the various components and functions of the present technology can be combined and / or integrated. Furthermore, although advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A memory device, comprising: a memory array including a plurality of memory banks; a plurality of external command / address terminals configured to receive a plurality of command / address bits, wherein a first set of command / address bits of the plurality of command / address bits indicates a read or write operation and a second set of command / address bits of the plurality of command / address bits indicates whether to perform a refresh operation, wherein the first set of command / address bits and the second set of command / address bits are received simultaneously or in one communication; and a command decoder configured to decode the plurality of command / address bits, wherein the memory device is configured to perform the read or write operation on a portion of the memory array in response to the first set of command / address bits, and wherein the memory device is configured to perform the refresh operation to refresh at least one memory bank of the plurality of memory banks in response to the second set of command / address bits when the second set of command / address bits indicates that the refresh operation should be performed.

2. The memory device of claim 1, wherein the memory device is configured to perform the refresh operation after performing the read or write operation.

3. The memory device of claim 1, wherein the second set of command / address bits indicates that the memory device is to perform the refresh operation after performing the read or write operation when a command / address bit in the second set of command / address bits is asserted.

4. The memory device of claim 1, wherein the second set of command / address bits indicates that the memory device is to perform the refresh operation after performing the read or write operation when a command / address bit in the second set of command / address bits is not asserted.

5. The memory device of claim 1, wherein the read or write operation is a read operation, a read operation and a precharge operation, a write operation, or a write operation and a precharge operation.

6. The memory device of claim 1, wherein the refresh operation is a refresh single bank operation, a refresh all banks operation, or a fine-grained refresh operation.

7. The memory device of claim 1, wherein when the second set of command / address bits indicates that the refresh operation should be performed, the memory device is configured to perform a precharge operation after performing the read or write operation but before performing the refresh operation.

8. The memory device of claim 1, wherein the memory device is a single memory die.

9. The memory device of claim 1, wherein the memory device is a dynamic random access memory (DRAM) device.

10. A method performed at a memory device, comprising: receiving a plurality of command / address bits via a corresponding plurality of external command / address terminals of the memory device, wherein a first set of command / address bits of the plurality of command / address bits indicates a read or write operation and a second set of command / address bits of the plurality of command / address bits indicates whether to perform a refresh operation, wherein the first set of command / address bits and the second set of command / address bits are received simultaneously or in one communication; performing the read or write operation on a portion of a memory array of the memory device in response to the first set of command / address bits; and performing the refresh operation to refresh at least one memory bank of the memory device in response to the second set of command / address bits when the second set of command / address bits indicates that the refresh operation should be performed.

11. The method of claim 10, wherein the method comprises performing the read or write operation without performing the refresh operation when the second set of command / address bits indicates that the refresh operation should not be performed.

12. The method of claim 10, wherein performing the refresh operation includes performing the refresh operation after performing the read or write operation.

13. The method of claim 10, wherein performing the refresh operation includes performing the refresh operation after determining that a command / address bit in the second set of command / address bits is asserted.

14. The method of claim 10, wherein performing the refresh operation includes performing the refresh operation after determining that a command / address bit in the second set of command / address bits is not asserted.

15. The method of claim 10, wherein performing the refresh operation includes refreshing all or a subset of memory banks included in the memory array of the memory device.

16. The method of claim 10, further comprising performing a pre-charge operation after performing the read or write operation but before performing the refresh operation.

17. A memory system comprising: a memory controller and / or a host device; and a memory device in communication with the memory controller and / or the host device via one or more command / address buses, wherein the memory device includes: a plurality of external command / address terminals connected to the one or more command / address buses and configured to receive a plurality of command / address bits from the memory controller and / or from the host device via the one or more command / address buses, and a command decoder configured to decode the plurality of command / address bits, wherein: a first set of command / address bits of the plurality of command / address bits indicates a read or write operation and a second set of command / address bits of the plurality of command / address bits indicates whether to perform a refresh operation, the first set of command / address bits and the second set of command / address bits are received simultaneously or in one communication, the memory controller and / or the host device is configured to embed a refresh command into the second set of command / address bits, and the command decoder is further configured to determine whether to perform the refresh operation in addition to performing the read or write operation based at least in part on the second set of command / address bits.

18. The memory system of claim 17, wherein the memory device is configured to perform the read or write operation without performing the refresh operation when the command decoder determines not to perform the refresh operation based at least in part on the second set of command / address bits.

19. The memory system of claim 17, wherein the memory device is configured to perform the refresh operation after performing the read or write operation when the command decoder determines to perform the refresh operation based at least in part on the second set of command / address bits.

20. The memory system of claim 17, wherein: the read or write operation is a read operation, a read operation and a precharge operation, a write operation, or a write operation and a precharge operation; and the refresh command is a refresh single bank operation, a refresh all banks operation, or a fine grain refresh operation.

21. The memory system of claim 17, wherein the command decoder is configured to determine to perform the refresh operation based at least in part on the second set of command / address bits when the second set of command / address bits is indicative of a refresh command.

22. The memory system of claim 17, wherein the command decoder is configured to determine to perform the refresh operation based at least in part on the second set of command / address bits when the second set of command / address bits is indicative of a refresh command and a bank address.

23. The memory system of claim 17, wherein the command decoder is configured to determine to perform the refresh operation based at least in part on the second set of command / address bits when the second set of command / address bits is indicative of a refresh command and a bank address and a row address.

24. The memory system of claim 17, wherein the command decoder is configured to determine to perform the

Images