Baseband chip cache structure read-write control method and baseband chip cache structure

Abstract

The application belongs to the technical field of power line carrier communication, and particularly relates to a baseband chip cache structure read-write control method and a baseband chip cache structure, which comprises the following steps: receiving communication message data and caching the communication message data to multiple bank cache units; if the communication message data is leading data, reading the leading data from the multiple bank cache units until the leading data is read completely; according to the bank sequence number where the read-write pointer of the current multiple bank cache unit accessed is located, dividing the multiple bank cache units into a shared cache module and a circular cache module containing unread communication message data; the circular cache module is used for circularly storing subsequent communication message data; the shared cache module is used for read-write access by external modules; and the shared cache module and the circular cache module are controlled to be read-write accessed respectively. Thus, the application solves the problems of large baseband chip cache memory, large power consumption and poor performance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power line carrier communication, and particularly relates to a baseband chip cache structure read-write control method and a baseband chip cache structure. BACKGROUND

[0002] Power line communication (PLC) technology is a kind of communication technology for transmitting data and signals by using power lines. The modulation mode commonly used by the power line communication is OFDM, i.e. orthogonal frequency division multiplexing. In the process of transmission, the data is modulated and loaded on the current by using the modulation technology, and then transmitted on the power line. The receiving end extracts the modulated signal by using a filter, performs frame synchronization detection and demodulation, and restores the original signal.

[0003] The PLC physical layer communication message is generally composed of a preamble data part, a frame control data part and a payload data part. In the receiving end, the baseband communication chip uses the preamble data to detect the frame synchronization. Meanwhile, the preamble data needs to be buffered for a sufficient length to perform the frequency offset estimation and channel estimation functions, so as to better perform the frequency offset compensation and channel compensation, and achieve better communication performance. The baseband chip receiving buffer needs to be used for the results of data processing of the channel estimation module and the data decoding module and the like under the condition of meeting the above functions, and the buffered data is large. In the face of this problem, the conventional method is to increase the overall hardware area of the baseband chip to ensure that there is a large enough buffer. However, after the hardware area is increased, the hardware device is increased, resulting in large overall hardware overhead of the baseband chip. On the other hand, in the prior art, the frame synchronization module data needs to be read from the receiving buffer RAM unit to obtain the communication message data; or before the data is filtered and down-sampled in the front-stage filtering data path, the data is synchronized to a higher frequency module working clock by the ADC clock, at this time, the data can be directly input to the frame synchronization module after being filtered and down-sampled. These two methods either increase the frequent reading of the RAM or increase the working frequency of the front-stage, resulting in large power consumption. In summary, the large amount of buffer read-write data is chaotic, the receiving data flow is complex, the chip power consumption is further increased, the performance is decreased, and the optimization of the area, power consumption and performance cannot be achieved. SUMMARY

[0004] The application aims to provide a baseband chip cache structure read-write control method and a baseband chip cache structure, so as to solve the problems of large baseband chip cache memory, large power consumption and poor performance in the prior art.

[0005] To solve the above technical problems, the technical solution provided by the application and the beneficial effects corresponding to the technical solution are as follows:

[0006] The baseband chip cache structure read-write control method provided by the application comprises the following steps:

[0007] 1) receiving communication message data, and buffering to a plurality of bank cache units;

[0008] 2) judging whether the communication message data is preamble data, and if the communication message data is preamble data, reading the preamble data from the plurality of bank cache units until the preamble data is read completely;

[0009] 3) after the preamble data is read completely, obtaining read and write pointers of the plurality of bank cache units currently accessed and bank sequence numbers where the read and write pointers are located;

[0010] 4) according to the bank sequence numbers where the read and write pointers are located, dividing the plurality of bank cache units into a shared cache module and a circular cache module containing unread communication message data; the circular cache module is used for circularly storing subsequent communication message data; and the shared cache module is used for read and write access by external modules;

[0011] 5) controlling the shared cache module to be read and written by external modules; and controlling the circular cache module to buffer subsequent communication message data and read the subsequent communication message data.

[0012] The above technical solution has the following beneficial effects: the communication message data received is buffered to the plurality of bank cache units, and when preamble data is detected, the preamble data in the buffered communication message data is read. After the preamble signal in the communication message data is read completely, the plurality of bank cache units are divided into a shared cache module and a circular cache module containing unread communication message data; wherein the unread communication message data is still stored in the circular cache module, ensuring the integrity of the data. The preamble data part in the communication message data is buffered to the entire plurality of bank cache units, to ensure that the preamble data part is long enough; after frame synchronization, frequency offset estimation and channel estimation are performed by using the preamble data, the plurality of bank cache units are divided into two parts, wherein the circular cache module is used for storing subsequent frame control data part and payload data part, and the shared cache module is used for read and write access by external modules, so that the area and power consumption of the baseband chip are effectively reduced while the excellent communication receiving performance is maintained, under the condition that the sufficient cache space is ensured.

[0013] Further, the plurality of bank cache units are divided in the following manner in step 4):

[0014] The multi-bank cache unit caches data in ascending order of bank serial numbers before being divided; the starting bank serial number of the circular cache module is determined according to the bank serial number where the read pointer is located; the starting bank serial number of the circular cache module is less than or equal to the bank serial number where the read pointer is located; the ending bank serial number of the circular cache module is greater than or equal to the bank serial number where the read pointer is located; and the remaining bank blocks in the multi-bank cache unit except the circular cache module are shared cache modules.

[0015] Further, the communication message data is data after baseband chip clock domain synchronization.

[0016] Further, the reading and writing data of the shared cache module and the circular cache module in step 5) respectively include:

[0017] Mapping each bank in the shared cache module to an external cache access interface to obtain a mapping relationship; and performing writing and reading of the shared cache module according to the mapping relationship and an enable mask share_mask of the shared cache module;

[0018] Performing reading and writing access of the circular cache module according to a read enable mask loop_rd_mask and a write enable mask loop_wr_mask of the circular cache module.

[0019] Further, the enable mask share_mask of the shared cache module is determined by the following formula in step 5):

[0020] share_mask = (M1 << share_bank_sid) | (share_bank_sid > N? (M1 >> (AN - share_bank_sid)): 0)

[0021] M1 = (1 << SN) - 1

[0022] Wherein, SN is the number of banks of the shared cache module, share_bank_sid is the starting bank serial number of the shared cache module, AN is the total number of banks of the multi-bank cache unit, and N is the number of banks of the circular cache module.

[0023] Further, the read enable mask of the circular cache module is determined by the following method:

[0024] loop_rd_mask = rd_req << loop_bank_rid

[0025] The write enable mask of the circular cache module is determined by the following method:

[0026] loop_wr_mask = wr_req << loop_bank_wid

[0027] Wherein, the rd_req is current read-write request signal, the wr_req is write request signal, the loop_bank_rid is the bank serial number corresponding to the read address in the loop cache module when reading data in a loop, and the loop_bank_wid is the bank serial number corresponding to the write address in the loop cache module when writing data in a loop.

[0028] Further, if loop_bank_wid < AN, then loop_bank_wid = loop_wadr % L + bank_rid.

[0029] If loop_bank_wid ≥ AN, then loop_bank_wid = loop_bank_wid - AN.

[0030] If loop_bank_rid < AN, then loop_bank_rid = loop_radr % L + bank_rid.

[0031] If loop_bank_rid ≥ AN, then loop_bank_rid = loop_bank_rid - AN.

[0032] Wherein, the loop_wadr is the write pointer corresponding to writing data in a loop of the loop cache module, the bank_rid is the bank serial number corresponding to the read address in the loop cache module, and L is the bank memory depth; the loop_radr is the read pointer corresponding to reading data in a loop of the loop cache module, and the bank_rid is the bank serial number corresponding to the read pointer accessed by the multi-bank cache unit when receiving a shared cache signal.

[0033] The application provides a baseband chip cache structure, which comprises a receiving state control unit, a loop cache management module and a multi-bank cache unit.

[0034] The receiving state control unit is used for outputting received communication message data, so as to judge whether the communication message data is leading data.

[0035] The cyclic cache management module is configured to cache the received communication message data to the multi-bank cache unit, and read the preamble data from the multi-bank cache unit until the reading of the preamble data is completed, in the case that the communication message data is the preamble data; after the reading of the preamble data is completed, the read and write pointers of the current multi-bank cache unit and the bank serial number where the read and write pointers are located are obtained; according to the bank serial number where the read and write pointers are located, the multi-bank cache unit is divided into a shared cache module and a cyclic cache module containing unread communication message data; the shared cache module is controlled to be read and written by an external module; and the cyclic cache module is controlled to cache subsequent communication message data and the subsequent communication message data after being read.

[0036] The multi-bank cache unit is configured to store the communication message data, and after being divided, the cyclic cache module is configured to cyclically store the subsequent communication message data; and the shared cache module is configured to be read and written by an external module.

[0037] Further, the structure further comprises an asynchronous FIFO cache unit, which is configured to synchronize the original communication message data to a baseband working clock domain to obtain the communication message data, and send the communication message data to the receiving state control unit and the cyclic cache management module.

[0038] Further, the cyclic cache management module maps each bank in the shared cache module to an external cache access interface, so as to enable each cache access interface to access the shared cache module. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a whole hardware structure schematic diagram of a baseband chip cache structure of the present application;

[0040] Figure 2 is a cache structure working state diagram in an embodiment of the baseband chip cache structure of the present application;

[0041] Figure 3 is a cache structure division schematic diagram in an embodiment of the baseband chip cache structure of the present application. DETAILED DESCRIPTION

[0042] The application aims to provide a baseband chip cache structure read-write control method, which effectively reduces the area and power consumption of the baseband chip while maintaining excellent communication receiving performance. The control method caches the received communication message data to the main storage, i.e. a multi-bank cache unit composed of multiple RAMs, and the multi-bank cache unit performs read-write access in a cyclic manner. After detecting the preamble data, the preamble data in the cached communication message data is read out for frequency offset estimation and channel estimation by an external module. When the multi-bank cache unit receives data to a certain state, the cyclic cache management module divides the multi-bank cache unit into two parts, a small part of the cache unit continues the previous cyclic access, and the other large part of the cache unit is released for external shared access.

[0043] In order to make the purpose, technical scheme and advantages of the application more clear and obvious, the application is further described in detail below in combination with the drawings and examples.

[0044] A baseband chip cache structure embodiment:

[0045] A baseband chip cache structure embodiment of the application, as a whole, Figure 1 as shown, comprises an asynchronous FIFO cache unit, a receiving state control unit, a cyclic cache management module and a multi-bank cache unit.

[0046] The input data of the cache structure generally comes from the filtering down-sampling circuit, and the working clock frequency is the baseband input ADC clock frequency. The asynchronous FIFO cache unit is responsible for synchronizing the input data to the baseband working clock frequency to obtain the communication message data; the communication message data is directly output to the external frame synchronization module through the receiving state control unit, and is written into the multi-bank cache unit through the cyclic cache management module. The input data of the frame synchronization module of the application directly comes from the small FIFO unit, and does not need to read a large area of storage, thereby reducing power consumption.

[0047] The multi-bank cache unit is used to cache the source data (communication message data) in the baseband receiving communication process and share the storage for processing data by external modules. Before frame synchronization, the communication message data is always written in a cyclic mode, sequentially from bank0 to bank13, and then cyclically back to bank0, sequentially reciprocating, as shown in the initial cyclic structure in Figure 3 .

[0048] The receiving state control unit is used to divide the working state of the current cache structure, serve the data access of the external corresponding module according to the working state, and output the received communication message data, which is used to judge whether the communication message data is preamble data.

[0049] Specifically, the working state of the receiving state control unit is as shown inFigure 2 As shown, the receiving buffer idle state, frame synchronization state, frequency offset estimation state, channel estimation state, and symbol data decoding state are divided. In each state, the buffer structure serves each corresponding module outside, including the frame synchronization module, the frequency offset estimation module, the channel estimation module, and the symbol decoding module. The circular buffer management module is used to control the storage and reading of the multi-bank buffer unit. In particular, the circular buffer management module divides the multi-bank buffer unit into two parts after the channel estimation state ends, a small part (circular buffer module) continues the previous circular access structure, that is, it continues to be used to buffer the communication message data, especially the subsequent frame control data part and the payload data part; the other large part (shared buffer module) is released for reading and writing access by other modules in the external receiving process.

[0050] The main working process of the buffer structure is as follows: after the external frame synchronization module searches for the preamble signal and gives the frame synchronization signal, the circular buffer management module provides the multi-bank memory bank to the external frequency offset estimation module. After the frequency offset estimation is completed, the preamble data is also provided to the external channel estimation module. After the channel estimation is completed, the circular buffer management module provides the OFDM symbol data after the preamble to the external symbol decoding module. After receiving enough decoded symbol data, the buffer structure returns to the idle state again. As can be seen, after the frame synchronization state, the multi-bank buffer unit receives input data on one side and outputs data for use by external modules on the other side, that is, reading and writing are performed simultaneously.

[0051] The reading and writing control process of the buffer structure is as follows:

[0052] Step 1: receive the communication message data through the asynchronous FIFO buffer unit, one way through the receiving state control unit to output directly to the external frame synchronization module, and the other way through the circular buffer management module to buffer to the multi-bank buffer unit.

[0053] Step 2: when the external frame synchronization module detects the preamble signal, the preamble data is read from the multi-bank buffer unit through the circular buffer management module until the preamble data is read, for frequency offset estimation and channel estimation.

[0054] Step 3: divide the multi-bank buffer unit, a part of which is used to continue buffering the communication message data, and a part of which is used to share for access by external modules.

[0055] In the embodiment of the present application, the working state of the cache structure is divided into two parts after the channel estimation is finished, by the circular cache management module. One part with small area stores the bank to continue the previous circular read-write mode, and the other part with large area releases the circular bank for the system external module to read and write, thereby reducing the overall hardware area and power consumption of the baseband chip. The specific division process is as follows:

[0056] Step 301: At the moment when the channel estimation is finished, that is, at the moment when the bank is to be cut for sharing, record the read pointer and the write pointer of the recent circular cache access, which are identified as radr and wadr respectively, and the bank sequence number where the read and write pointers are located, which are identified as bank_rid and bank_wid respectively, such as Figure 3 As shown in the example, bank_rid=4 and bank_wid=9.

[0057] Specifically, the starting bank sequence number of the circular cache module is determined according to the bank sequence number where the read pointer is located; the starting bank sequence number of the circular cache module is less than or equal to the bank sequence number where the read pointer is located; the ending bank sequence number of the circular cache module is greater than or equal to the bank sequence number where the read pointer is located; and the remaining bank blocks in the multi-bank cache unit except the circular cache module are the shared cache module.

[0058] In the embodiment, the bank sequence number where the read pointer is located is taken as the starting bank sequence number of the circular cache module, and the sequence number of the bank where the read pointer is located plus N is taken as the starting sequence number of the shared cache module.

[0059] Step 302: Set the number of shared banks (also referred to as shared cache module) as SN, the number of all banks as AN, and the number of secondary circular caches (also referred to as circular cache module) as N, such as Figure 3 As shown in the example, SN=8, AN=14, and N=6. The starting bank sequence number of the shared cache obtained from step 301 is set as share_bank_sid, and share_bank_sid=rd_bank_id+N. If the calculated share_bank_sid is greater than or equal to AN, AN needs to be subtracted, such as Figure 3 For example, share_bank_sid=10. At the same time, the number of cached data is obtained and identified as has_num, such as Figure 3 As shown in the example, the shadow part of the read-write pointer.

[0060] Step 303: Obtain the read pointer and the write pointer of the cut secondary circular memory and the update mechanism thereof.

[0061] The read pointer and the write pointer of the secondary loop cache are marked as loop_radr and loop_wadr, respectively. As shown in Figure 3 The depth of a bank memory in the embodiment is 1024, and the value of loop_radr at the end of the channel estimation is radr%1024. The loop_radr is incremented with the read access request signal until it is equal to N x 1024, and then it is incremented from 0 again. Similarly, the initial value of loop_wadr is radr%1024+has_num, and the loop_wadr is incremented with the write access request signal until it is equal to N x 1024, and then it is incremented from 0 again.

[0062] Step 304: Obtain the bank sequence number corresponding to the read and write pointers of the secondary loop memory and the updating mechanism thereof.

[0063] According to the loop_radr and loop_wadr obtained in step 303 and the bank_rid in step 301, the bank sequence number corresponding to the read and write addresses in the secondary loop cache is obtained, and the read and write bank sequences are marked as loop_bank_rid and loop_bank_wid, respectively. The loop_bank_rid can be expressed as: loop_bank_rid=loop_radr%1024+bank_rid. If the loop_bank_rid is greater than or equal to AN, the loop_bank_rid is updated as loop_bank_rid-AN.

[0064] Similarly, the loop_bank_wid can be expressed as: loop_bank_wid=loop_wadr%1024+bank_rid. If the loop_bank_wid is greater than or equal to AN, the loop_bank_wid is updated as loop_bank_wid-AN.

[0065] Step 305: Obtain the read and write enable masks of the bank being accessed in the secondary loop and the enable masks of the shared cache banks.

[0066] The read and write enable masks of the bank being accessed in the secondary loop cache are marked as loop_rd_mask and loop_wr_mask, respectively. Let the current read and write request signals be rd_req and wr_req, respectively. Then, loop_rd_mask=rd_req<<loop_bank_rid, and loop_wr_mask=wr_req<<loop_bank_wid.

[0067] As shown in Figure 3For example, if the secondary circular cache is reading from bank4 and writing to bank9, the bank read / write enable mask of the secondary circular cache can be represented in binary as: loop_rd_mask = `b0000_0000_0100_00`, loop_wr_mask = `b0000_1000_0000_00`; Simultaneously, the enable mask of the shared cache bank is obtained, denoted as share_mask, which can be logically represented as:

[0068] M1=(1< <SN)-1

[0069] share_mask = (M1<<share_bank_sid)|(share_bank_sid> N? (M1>>(AN-share_bank_sid)):0);

[0070] like Figure 3 As shown in the example, the binary representation of share_mask is: share_mask=`b1111_0000_0011_11.

[0071] Step 4: Map the shared cache bank blocks to the external shared cache access interfaces one-to-one. Based on the mapping relationship and the shared cache read / write enable mask, perform read / write operations on the shared cache and drive the corresponding external shared access read data interface. Simultaneously, the secondary loop cache body (secondary loop cache) undergoes access control according to its bank's read / write enable mask and read / write address.

[0072] like Figure 3 For example, from left to right, the shared cache's bank blocks are mapped sequentially to external cache access ports. For instance, bank0, bank1, bank2, and bank3 correspond to external access ports 0-3, and bank10, bank11, bank12, and bank13 correspond to external access ports 4-7. Writes and reads to the relevant shared cache are performed based on the mapping relationship and the `share_mask`. Additionally, for the double-loop cache, read and write access control is performed according to `loop_rd_mask` and `loop_wr_mask`.

[0073] The cache structure of this invention only accesses the necessary storage bank during data reception, resulting in lower power consumption compared to a single large storage block. Furthermore, by releasing and sharing the storage space occupied by the large amount of preamble data stored in the receive cache for read and write access by external modules, the system's hardware area is reduced, power consumption is simultaneously decreased, and excellent receiving performance is maintained.

[0074] When the next communication message data arrives, the data in the shared cache is completely read, and the data in the secondary loop cache is also completely read, at which time the cache structure is in a receiving cache idle state. At this time, the shared cache and the secondary loop cache are recombined into a complete multi-bank cache unit, which is still sequentially cached from bank0 to bank13 to ensure that there is enough space to cache the preamble data in the communication message data.

[0075] A baseband chip cache structure read-write control method embodiment:

[0076] The baseband chip cache structure read-write control method embodiment of the application comprises the following steps: 1) receiving communication message data and caching the data into a multi-bank cache unit; 2) judging whether the communication message data is preamble data, and if the communication message data is preamble data, reading the preamble data from the multi-bank cache unit until the preamble data is completely read; 3) after the preamble data is completely read, obtaining the read and write pointers of the current multi-bank cache unit and the bank sequence number where the read and write pointers are located; 4) according to the bank sequence number where the read and write pointers are located, dividing the multi-bank cache unit into a shared cache module and a loop cache module containing unread communication message data; the loop cache module is used to cyclically store subsequent communication message data; the shared cache module is used for external module read and write access; 5) controlling the shared cache module to be read and written by the external module; and controlling the loop cache module to cache subsequent communication message data and read the subsequent communication message data. The read-write control process of the method and the cache structure in the baseband chip cache structure embodiment is consistent, and the read-write control process has been described in detail in the baseband chip cache structure embodiment, and thus is not described again here.

Claims

1. A method for controlling the read / write operation of a baseband chip cache structure, characterized in that: Includes the following steps: 1) Receive communication message data and buffer it in a multi-bank buffer unit; 2) Determine whether the communication message data is preamble data. If the communication message data is preamble data, read the preamble data from the multi-bank buffer unit until the preamble data has been read. 3) After the preceding data is read, obtain the read and write pointers of the currently accessed multi-bank cache unit and the bank sequence number where the read and write pointers are located; 4) Based on the bank sequence number where the read and write pointers are located, the multi-bank cache unit is divided into a shared cache module and a circular cache module containing unread communication message data; the circular cache module is used to cyclically store subsequent communication message data; the shared cache module is used for external modules to read and write access. 5) Control the shared cache module to be read and written by external modules, map each bank in the shared cache module to the external cache access interface to obtain the mapping relationship; perform writing and reading of the shared cache module according to the mapping relationship and the shared cache module's enable mask share_mask; control the circular cache module to cache subsequent communication message data and read subsequent communication message data, and perform read and write access of the circular cache module according to the circular cache module's read enable mask loop_rd_mask and write enable mask loop_wr_mask.

2. The baseband chip cache structure read / write control method according to claim 1, characterized in that: Step 4) uses the following method to divide the multi-bank cache units: Before being partitioned, the multi-bank cache unit caches data in ascending order of bank sequence number; the starting bank sequence number of the circular cache module is determined based on the bank sequence number where the read pointer is located; the starting bank sequence number of the circular cache module is less than or equal to the bank sequence number where the read pointer is located; the ending bank sequence number of the circular cache module is greater than or equal to the bank sequence number where the read pointer is located; the remaining bank blocks in the multi-bank cache unit, excluding the circular cache module, are shared cache modules.

3. The baseband chip cache structure read / write control method according to claim 1, characterized in that: The communication message data is the data after synchronization with the baseband chip clock domain.

4. The baseband chip cache structure read / write control method according to any one of claims 1 to 3, characterized in that: Step 1) is to receive communication message data through the asynchronous FIFO buffer unit.

5. The baseband chip cache structure read / write control method according to claim 4, characterized in that: In step 5), the enable mask share_mask of the shared cache module is determined using the following formula: share_mask=(M1<<share_bank_sid)|(share_bank_sid> N?(M1>>(AN-share_bank_sid)):0) M1=(1 << SN)-1 Where SN is the number of banks in the shared cache module, share_bank_sid is the starting bank sequence number of the shared cache module, AN is the total number of banks in the multi-bank cache unit, and N is the number of banks in the circular cache module.

6. The baseband chip cache structure read / write control method according to claim 4, characterized in that: The read enable mask for the circular cache module is determined using the following method: loop_rd_mask= rd_req << loop_bank_rid The write enable mask for the circular cache module is determined using the following method: loop_wr_mask= wr_req << loop_bank_wid Where rd_req is the current read / write request signal, wr_req is the write request signal, loop_bank_rid is the bank sequence number corresponding to the read address when reading data in the loop buffer module, and loop_bank_wid is the bank sequence number corresponding to the write address when writing data in the loop buffer module.

7. The baseband chip cache structure read / write control method according to claim 6, characterized in that: If loop_bank_wid <AN, then loop_bank_wid = loop_wadr % L + bank_rid; If loop_bank_wid ≥AN, then loop_bank_wid= loop_bank_wid – AN; If loop_bank_rid <AN, then loop_bank_rid = loop_radr % L + bank_rid; If loop_bank_rid ≥AN, then loop_bank_rid=loop_bank_rid – AN; Where loop_wadr is the write pointer corresponding to the circular write of data in the circular cache module, bank_rid is the bank sequence number corresponding to the read address in the circular cache module, and L is the bank storage depth; loop_radr is the read pointer corresponding to the circular read of data in the circular cache module, and bank_rid is the bank sequence number corresponding to the read pointer of the accessed multi-bank cache unit when the shared cache signal is received.

8. A baseband chip cache structure, characterized in that: The structure includes a receive status control unit, a circular buffer management module, and a multi-bank buffer unit; The receiving status control unit is used to output the received communication message data to determine whether the communication message data is preamble data; The circular buffer management module is used to buffer the received communication message data into the multi-bank buffer unit, and is also used to read the preamble data from the multi-bank buffer unit when the communication message data is preamble data, until the preamble data has been read. After the preceding data is read, obtain the read and write pointers of the currently accessed multi-bank cache unit and the bank sequence number where the read and write pointers are located; based on the bank sequence number where the read and write pointers are located, divide the multi-bank cache unit into a shared cache module and a circular cache module containing unread communication message data; control the shared cache module to be read and written by external modules, map each bank in the shared cache module to the external cache access interface to obtain the mapping relationship; write and read the shared cache module according to the mapping relationship and the shared cache module's enable mask share_mask; control the circular cache module to cache subsequent communication message data and the read subsequent communication message data, and perform read and write access to the circular cache module according to the circular cache module's read enable mask loop_rd_mask and write enable mask loop_wr_mask; The multi-bank cache unit is used to store communication message data, and after being divided, the circular cache module is used to cyclically store subsequent communication message data; the shared cache module is used for external modules to read and write access.

9. The baseband chip cache structure according to claim 8, characterized in that: The structure also includes an asynchronous FIFO buffer unit, which is used to synchronize the original communication message data to the baseband working clock domain, obtain the communication message data, and send the communication message data to the receiving status control unit and the circular buffer management module.

10. The baseband chip cache structure according to claim 8 or 9, characterized in that: The circular cache management module maps each bank in the shared cache module to an external cache access interface, so that each cache access interface can access the shared cache module separately.

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