Method for forming semiconductor structure and mask

Abstract

A method for forming a semiconductor structure and a mask plate, the method comprising: providing a substrate including a target layer; forming a core material layer on the substrate, the core material layer including a first region and a second region surrounding the first region; ion doping the core material layer in the second region to increase etching resistance of the core material layer, the core material layer in the second region serving as an etching resistant layer, and the core material layer in the first region serving as a core layer; forming a first trench along a first direction through at least part of the core material layer in the first region, the core material layer in the first region remaining on both sides of the first trench in a second direction; forming a side wall on a sidewall of the first trench, the side wall enclosing a first recess; removing the core layer to form a second recess; and etching the target layer under the first recess and the second recess using the etching resistant layer and the side wall as a mask to form a target pattern.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure and a photomask. Background Technology

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of interconnects in each chip) gradually increases, the geometric size (i.e. the smallest component size that can be produced by process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, with the continuous shrinking of technology nodes, improving the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure and a mask, which further compresses the pitch between target patterns.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a target layer for forming a target pattern; forming a core material layer on the substrate, the core material layer including a first region for forming a core layer and a second region surrounding the first region for forming an etch-resistant layer; ion-doping the core material layer in the second region to improve the etch resistance of the core material layer, wherein the ion-doped core material layer in the second region serves as the etch-resistant layer, and the ion-undoped core material layer in the first region serves as the core layer; forming a first trench penetrating at least a portion of the core material layer in the first region along a first direction, wherein a second direction is perpendicular to the first direction, and in the second direction, portions of the core material layer in the first region are retained on both sides of the first trench; forming sidewalls on the sidewalls of the first trench, such that the sidewalls enclose a first groove; after ion doping and forming the sidewalls, removing the core layer, and forming a second groove located on both sides of the first groove in the etch-resistant layer; using the etch-resistant layer and the sidewalls as masks, etching the target layer below the first groove and the second groove to form a target pattern.

[0007] Optionally, in the step of forming the first trench, the first trench includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; along the first direction, the first trench penetrates the core material layer of the first region; or, along the first direction, the first trench penetrates the core material layer of the first region, and either or both of the first sidewall and the second sidewall extend into the core material layer of an adjacent second region; in the step of removing the core layer, the second grooves are spaced apart.

[0008] Optionally, in the step of forming the first trench, the first trench includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; the first sidewall of the first trench is located in the first region, and there is a gap between the first sidewall and the boundary on the same side of the first region; the second sidewall of the first trench is flush with the boundary on the same side of the first region, or the second sidewall of the first trench is located in an adjacent second region; in the step of removing the core layer, the second groove is connected at the location of the first sidewall.

[0009] Optionally, in the step of forming the first trench, the first trench is located in the core material layer of the first region, and in the first direction, there is a gap between the sidewall of the first trench and the boundary on the same side of the first region; in the step of removing the core layer, the second groove surrounds the first groove.

[0010] Optionally, the core material layer in the second region is ion-doped after the core material layer is formed and before the first trench is formed; or, the core material layer in the second region is ion-doped after the first trench is formed and before the sidewall is formed; or, the core material layer in the second region is ion-doped after the sidewall is formed and before the core layer is removed.

[0011] Optionally, the core material layer may be made of one or more of the following: amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbonitride.

[0012] Optionally, the ions used for ion doping include one or more of boron ions, phosphorus ions, and argon ions.

[0013] Optionally, an ion implantation process can be used to ion-dope the core material layer in the second region.

[0014] Optionally, the step of ion doping the core material layer in the second region includes: forming a masking layer on the core material layer in the first region, the masking layer exposing the second region; using the masking layer as a mask to ion dope the core material layer; and removing the masking layer.

[0015] Optionally, the step of forming the first trench includes: forming a mask layer on the core material layer, the mask layer having a mask opening extending along a first direction; on a projection plane parallel to the substrate, the first region spans the mask opening along a second direction; using the mask layer as a mask, removing the core material layer below the mask opening to form the first trench; and removing the mask layer.

[0016] Optionally, using the mask layer as a mask, a dry etching process is employed to remove the core material layer below the mask opening.

[0017] Optionally, the etching selectivity ratio between the core layer and the etch-resistant layer is at least 20:1.

[0018] Optionally, the number of first regions is multiple and arranged along a second direction, and the multiple first regions are independent of each other; the method of forming the semiconductor structure further includes: after forming the core material layer and before forming the sidewalls, forming a second trench that penetrates the core material layer located between the first regions along the second direction; in the step of forming the sidewalls, the sidewalls are also formed on the sidewalls of the second trench, and the sidewalls located on the sidewalls of the second trench form a third groove; using the anti-etching layer and the sidewalls as masks, etching the first groove, the second groove, and the target layer below the third groove to form a target pattern.

[0019] Optionally, the process for removing the core layer includes a wet etching process.

[0020] Optionally, the target layer is a dielectric layer; the target pattern is an interconnect trench; the method for forming the semiconductor structure further includes: forming metal interconnects in the interconnect trench after forming the interconnect trench.

[0021] Accordingly, embodiments of the present invention also provide a photomask for forming a semiconductor structure, the semiconductor structure comprising: a substrate, including a target layer for forming a target pattern; a core material layer located on the substrate, including a first region for forming the core layer and a second region surrounding the first region for forming an etch-resistant layer, the etch-resistant layer having a higher etch resistance than the core layer; the photomask comprising: a first photomask including a first pattern, the first pattern being used to form a first trench penetrating at least a portion of the core material layer in a first direction, the direction perpendicular to the first direction being a second direction, the first pattern being configured such that, in the second direction, a portion of the core material layer of the first region is retained on both sides of the first trench; and a second photomask cooperating with the first photomask, the second photomask including a second pattern, the second pattern being used to form the core layer located in the first region.

[0022] Optionally, the first trench includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; the first pattern is configured such that the first trench penetrates the core material layer of the first region along a first direction; or, the first trench penetrates the core material layer of the first region along a first direction, and either or both of the first sidewall and the second sidewall extend into the core material layer of the adjacent second region.

[0023] Optionally, the first trench includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; the first pattern is configured such that: the first sidewall of the first trench is located in the first region, and there is a gap between the first sidewall and the boundary on the same side of the first region; the second sidewall of the first trench is flush with the boundary on the same side of the first region, or the second sidewall of the first trench is located in an adjacent second region.

[0024] Optionally, the first pattern is configured such that the first trench is located in the core material layer of the first region, and in the first direction, the sidewall of the first trench is spaced apart from the boundary of the first region on the same side.

[0025] Optionally, the first mask is used to form a mask layer; the first trench is formed by etching the core material layer using the mask layer as a substrate; the second mask is used to form a shielding layer located in the first region; the anti-etching layer is formed by ion doping the core material layer in the second region using the shielding layer as a mask, wherein the ion doping is adapted to improve the etching resistance of the core material layer, and the undoped core material layer located in the first region serves as the core layer.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0027] In the semiconductor structure formation method provided by this invention, the core material layer in the second region is ion-doped to form an etch-resistant layer in the second region and a core layer in the first region. In the step of forming the first trench, a portion of the core material layer of the first region is retained on both sides of the first trench in the second direction; that is, the first region spans the first trench along the second direction. Then, sidewalls are formed on the sidewalls of the first trench, forming a first groove. In the step of removing the core layer, the formed second groove is located on both sides of the first groove, and the first and second grooves are isolated by the sidewalls. In this invention, compared to the second groove, the first region has a larger size. This design easily meets the requirements of photolithography processes. Furthermore, the portion of the first region excluding the area overlapping with the first trench is used to define the shape and size of the second groove. By superimposing the pattern of the first region and the pattern of the first trench, the second groove can achieve a smaller size. The space between the second groove and the first groove is defined by the thickness of the sidewall. The minimum design spacing between the first groove and the second groove is easily met. This allows for smaller critical dimensions of the target pattern and further compression of the pitch between the target patterns without changing the limits of the photolithography process, thus meeting the requirements of high density and high integration of integrated circuits. Moreover, it requires minimal modification to existing processes, has low process complexity, and is highly photolithography-friendly. Attached Figure Description

[0028] Figures 1 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0029] Figures 13 to 16 This is a top view of each step in another embodiment of the method for forming a semiconductor structure according to the present invention;

[0030] Figures 17 to 20 This is a top view of each step in another embodiment of the method for forming a semiconductor structure according to the present invention;

[0031] Figures 21 to 25 This is a top view of each step in another embodiment of the method for forming a semiconductor structure according to the present invention;

[0032] Figure 26 This is a schematic diagram of a semiconductor structure without the mask processing of the present invention;

[0033] Figure 27 This is a schematic diagram of the structure of a mask plate according to an embodiment of the present invention;

[0034] Figure 28 It is to utilize Figure 27 A schematic diagram of a photomask used to process a semiconductor structure;

[0035] Figure 29 This is a schematic diagram of another embodiment of the photomask of the present invention;

[0036] Figure 30 It is to utilize Figure 29 A schematic diagram of a photomask used to process a semiconductor structure.

[0037] Figure 31 This is a schematic diagram of the structure of another embodiment of the photomask of the present invention;

[0038] Figure 32 It is to utilize Figure 31 A schematic diagram of a photomask used to process a semiconductor structure. Detailed Implementation

[0039] As the background technology shows, with the continuous shrinking of technology nodes, improving the matching degree between the pattern formed on the wafer and the target pattern has become a challenge.

[0040] To address the aforementioned technical problem, this invention provides a method for forming a semiconductor structure. The method involves ion doping a core material layer in a second region to form an etch-resistant layer in the second region and a core layer in the first region. In the step of forming a first trench, a portion of the core material layer of the first region is retained on both sides of the first trench in the second direction. That is, the first region spans the first trench along the second direction. Then, sidewalls are formed on the sidewalls of the first trench, creating a first groove. In the step of removing the core layer, the formed second groove is located on both sides of the first groove, and the first and second grooves are isolated by the sidewalls. In this invention, compared to the second groove, the first region… The region has a large size, which easily meets the requirements of photolithography process conditions. Moreover, the portion of the first region excluding the area overlapping with the first trench is used to define the shape and size of the second groove. By superimposing the pattern of the first region and the pattern of the first trench, the second groove can achieve a smaller size. The interval between the second groove and the first groove is defined by the thickness of the sidewall. The minimum design interval between the first groove and the second groove is easily met. Thus, without changing the limits of photolithography process, it is beneficial to achieve a smaller critical size of the target pattern and further compress the pitch between the target patterns to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires little modification to existing processes, has low process complexity, and is highly photolithography friendly.

[0041] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 1 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0042] refer to Figure 1 , Figure 1 'a' is the top view. Figure 1 b is Figure 1 A cross-sectional view along the yy secant line, providing a base 200, including a target layer 100 for forming the target pattern.

[0043] The substrate 200 provides a platform for the process technology. The target layer 100 is a film layer to be patterned to form a target pattern. The target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a FinFET, a channel stack in a Gate All-Around-Apart (GAA) transistor or a Forksheet transistor, a hard mask (HM) layer, etc.

[0044] In this embodiment, the target layer 100 is a dielectric layer, and the target pattern is an interconnect trench. The dielectric layer is subsequently patterned to form multiple interconnect trenches, and then metal interconnects are formed within these interconnect trenches. The dielectric layer is used to achieve electrical isolation between the metal interconnects. Therefore, the dielectric layer is an intermetallic dielectric (IMD) layer. The material of the dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0045] Semiconductor devices such as transistors and capacitors can be formed in the substrate 200, and functional structures such as resistive structures and conductive structures can also be formed in the substrate 200. In this embodiment, the substrate 200 also includes a substrate 110 located at the bottom of the target layer 100. As an example, the substrate 110 is a silicon substrate.

[0046] In this embodiment, the substrate 200 further includes a hard mask material layer 115 located on the target layer 100. Subsequently, the hard mask material layer 115 is patterned to form a hard mask layer, and then the target layer 100 is patterned using the hard mask layer as a mask. This improves the process stability and pattern transfer accuracy of the patterned target layer 100.

[0047] The hard mask material layer 115 is selected from materials that have etching selectivity with the target layer 100. The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon carbonitride. As an example, the material of the hard mask material layer 115 is titanium nitride.

[0048] In specific processes, depending on actual process requirements, a stress buffer layer can be provided between the hard mask material layer 115 and the target layer 100. Furthermore, an etching stop layer can be provided between the hard mask material layer 115 and the stress buffer layer, and also on the hard mask material layer 115. The descriptions of the stress buffer layer and the etching stop layer will not be repeated in this embodiment.

[0049] Continue to refer to Figure 1 A core material layer 120 is formed on the substrate 200. The core material layer 120 includes a first region 120a for forming the core layer and a second region 120b surrounding the first region 120a for forming an etch-resistant layer.

[0050] Subsequently, the core material layer 120 in the second region 120b is ion-doped to form an etch-resistant layer, and the remaining core material layer 120 in the first region 120a serves as the core layer.

[0051] The core material layer 120 is made of one or more of the following materials: amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the core material layer 120 is made of amorphous silicon.

[0052] It should be noted that, in this embodiment, only one first region 120a is shown for ease of illustration and explanation. However, the shape, position, and number of the first region 120a are not limited to this. For example, in other embodiments, the number of the first regions may be multiple and arranged along the second direction, with the multiple first regions being independent of each other.

[0053] refer to Figures 2 to 4 The core material layer 120 in the second region 120b is ion-doped to improve the etching resistance of the core material layer 120. The ion-doped core material layer 120 in the second region 120b serves as an anti-etching layer 130, and the undoped core material layer 120 in the first region 120a serves as a core layer 140.

[0054] After forming a first trench that penetrates at least a portion of the first region 120a along a first direction, the remaining core material layer 120 of the first region 120a (i.e., the core layer 140) is used to occupy space for forming a second groove. The etching resist layer 130 is used as a mask for subsequent patterning of the target layer 100.

[0055] Subsequent processes also include: forming sidewalls on the sidewalls of the first trench, so that the sidewalls enclose the first groove.

[0056] In this embodiment, the core material layer 120 is ion-doped to form an etch-resistant layer 130 and a core layer 140, thereby achieving patterning of the core material layer 120. Ion doping is suitable for improving the etch resistance of the core material layer 120, so that the etch resistance of the etch-resistant layer 130 is greater than that of the core layer 140. There is a high etch selectivity between the core layer 140 and the etch-resistant layer 130. In the subsequent step of removing the core layer 140 to form the second groove, it is not easy to cause erroneous etching of the etch-resistant layer 130, which helps to reduce the probability of double etching of the first groove, thereby ensuring the pattern accuracy of the first groove. Moreover, the etch-resistant layer 130 can be retained as a mask for the patterning target layer 100.

[0057] In this embodiment, the anti-etching layer 130 surrounds the core layer 140.

[0058] In this embodiment, the ions used to ion-dopat the core material layer 120 of the second region 120b include one or more of boron ions, phosphorus ions, and argon ions.

[0059] In this embodiment, the etching selectivity ratio between the core layer 140 and the anti-etching layer 130 is at least 20:1. The high etching selectivity ratio between the core layer 140 and the anti-etching layer 130 is beneficial to significantly reduce the probability of the subsequent process of removing the core layer 140 causing mis-etching of the anti-etching layer 130.

[0060] As an example, the core material layer 120 of the second region 120b is ion-doped after the core material layer 120 is formed and before the first trench is formed. However, the step of ion-doping the core material layer 120 of the second region 120b is not limited to this.

[0061] In other embodiments, the core material layer of the second region may be ion-doped after the first trench is formed and before the sidewalls are formed. In still other embodiments, the core material layer of the second region may be ion-doped after the sidewalls are formed and before the core layer is removed.

[0062] In this embodiment, the step of ion doping the core material layer 120 of the second region 120b includes:

[0063] like Figure 2 As shown, Figure 2 'a' is the top view. Figure 2 b is Figure 2A cross-sectional view along the yy secant line shows a masking layer 150 formed on the core material layer 120 of the first region 120a, exposing the second region 120b. The masking layer 150 serves as a mask for ion doping of the core material layer 120, and correspondingly defines the shape and position of the core layer 140 and the etch-resistant layer 130.

[0064] In this embodiment, the occlusion layer 150 includes a first planarization layer 151 and a first patterning layer 152.

[0065] The first planarization layer 151 provides a flat surface for forming the first patterning layer 152, thereby improving the accuracy of pattern transfer. In this embodiment, the material of the first planarization layer 151 is spin-on carbon (SOC). The first patterning layer 152 serves as an etching mask for forming the first planarization layer 151, and the first patterning layer 152 correspondingly defines the shape and position of the core layer 140 and the resist layer 130. In this embodiment, the material of the first patterning layer 152 is photoresist.

[0066] like Figure 3 As shown, Figure 3 'a' is the top view. Figure 3 b is Figure 3 a) A cross-sectional view along the yy secant line, using the shielding layer 150 as a mask, shows the core material layer 120 being ion-doped. In this embodiment, an ion implantation process is used to ion-dopate the core material layer 120 in the second region 120b.

[0067] like Figure 4 As shown, Figure 4 'a' is the top view. Figure 4 b is Figure 4 A cross-sectional view along the yy secant line, showing the removal of the masking layer 150. In this embodiment, one or both of an ashing process and a wet adhesive removal process are used to remove the masking layer 150.

[0068] refer to Figures 5 to 8 Formed along the first direction (e.g.) Figure 7 A first trench 180 (as shown in the X direction in a) penetrates at least part of the core material layer 120 of the first region 120a, and the direction perpendicular to the first direction is the second direction (as shown in the X direction in a). Figure 7 (as shown in the Y direction in b), in the second direction, the core material layer 120 of the first region 120a is retained on both sides of the first trench 180.

[0069] In the second direction, the core material layer 120 of the first region 120a is retained on both sides of the first trench 120. That is, the first region 120a spans the first trench 180 in the second direction. Then, a sidewall is formed on the sidewall of the first trench 180, so that the sidewall surrounds the first groove. In the subsequent step of removing the core layer 140 to form the second groove, the second groove is located on both sides of the first groove, and the first groove and the second groove are isolated by the sidewall.

[0070] In this embodiment, compared with the second groove, the first region 120a has a larger size, which is easier to meet the requirements of photolithography process conditions. Moreover, the portion of the first region 120a that overlaps with the first groove 180 is used to define the shape and size of the second groove. Thus, by superimposing the pattern of the first region 120a and the pattern of the first groove 180, the second groove can achieve a smaller size. The space between the second groove and the first groove is defined by the thickness of the sidewall. The minimum design spacing between the first groove and the second groove is easy to meet. Therefore, without changing the limits of photolithography process, it is beneficial to achieve a smaller critical size of the target pattern and further compress the pitch between the target patterns to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires little modification to the existing process, has low process complexity, and is highly photolithography friendly.

[0071] In this embodiment, after ion doping, a first trench 180 is formed. Therefore, the first trench 180 penetrates at least a portion of the core layer 140 along a first direction, and in the second direction, portions of the core layer 140 are retained on both sides of the first trench 180.

[0072] In this embodiment, the first trench 180 includes a first sidewall 181 along the second direction and a second sidewall 182 opposite to and parallel to the first sidewall 181.

[0073] Along the first direction, the first trench 180 penetrates the core material layer 120 of the first region 120a; or, along the first direction, the first trench 180 penetrates the core material layer 120 of the first region 120a, and either or both of the first sidewall 181 and the second sidewall 182 extend into the core material layer 120 of the adjacent second region 120b.

[0074] Therefore, in this embodiment, after the first trench 180 is formed, the core material layers 120 of the first regions 120a on both sides of the first trench 180 are spaced apart. Specifically, the core layers 140 on both sides of the first trench 180 are spaced apart, so that the second grooves formed after the core layers 140 are subsequently removed are spaced apart.

[0075] As an example, along the first direction, the first trench 180 penetrates the core material layer 120 of the first region 120a, and both the first sidewall 181 and the second sidewall 182 extend into the core material layer 120 of the adjacent second region 120b. That is, along the first direction, the end of the first trench 180 protrudes beyond the sacrificial layer first region 120a. After the core layer 140 is subsequently removed to form the second groove, along the first direction, the end of the first groove correspondingly protrudes beyond the second groove.

[0076] It should be noted that, in this embodiment, for ease of illustration and explanation, only one first region 120a and a first trench 180 penetrating at least a portion of the core material layer 120 of the first region 120a along a first direction are shown. In the second direction, portions of the core material layer 120 of the first region 120a are retained on both sides of the first trench 180. However, the shape, position, and number of the first region 120a, as well as its positional relationship with the first trench 180, are not limited to this.

[0077] As an example, there may be multiple first regions arranged along a second direction, with each of the first regions being independent of the others. The first trench may be formed only in the core material layer of a portion of the first regions, while the first trench may not be formed in the core material layer of the remaining first regions. In other embodiments, depending on actual design requirements, the first trench may be formed in all of the first regions.

[0078] It should also be noted that, in this embodiment, for ease of illustration and explanation, only the first region 120a, the second region 120b, and the first groove 180 are shown; other graphic structures surrounding the first region 120a are not shown. It should be understood that in actual manufacturing processes, the first region 120a and the first groove 180 may not be independent graphics. Depending on design requirements, other graphic structures may be provided around the first region 120a, for example: Figure 8 As shown, along the second direction, a second groove 185 may also be formed on one or both sides of the first region 120a. In the subsequent step of forming a sidewall on the sidewall of the first groove 180, the sidewall is also formed on the sidewall of the second groove 185. The sidewall located on the sidewall of the second groove 185 can form a third groove, which is also used to define the shape of the target shape.

[0079] In this embodiment, the step of forming the first trench 180 includes:

[0080] like Figure 5 As shown, Figure 5 'a' is the top view. Figure 5 b is Figure 5 A cross-sectional view along the yy secant line shows a mask layer 160 formed on the core material layer 120. The mask layer 160 has a secant line along a first direction (e.g., ...). Figure 5 A mask opening 170 extending in the X direction (as shown in a); on a projection plane parallel to the substrate 200, the first region 120a extends along the second direction (as shown in a diagram). Figure 5 (as shown in the Y direction in b) spans the mask opening 170.

[0081] The mask layer 160 serves as an etching mask for forming the first trench. The mask opening 170 defines the shape and location of the first trench. In this embodiment, the material of the mask layer 160 is photoresist.

[0082] In this embodiment, before forming the mask layer 160, the forming method further includes: forming a second planarization layer 161 on the core material layer 120; and forming an anti-reflection coating 162 on the second planarization layer 161.

[0083] The second planarization layer 161 is used to provide a flat top surface for forming the mask layer 160. In this embodiment, the material of the second planarization layer 161 is spin-coated carbon.

[0084] The anti-reflective coating 162 is used to reduce the reflection effect during exposure. In this embodiment, the material of the anti-reflective coating 162 is BARC (Bottom Anti-reflective coating).

[0085] like Figure 6 As shown, Figure 6 'a' is the top view. Figure 6 b is Figure 6 a. A cross-sectional view along the yy secant line, using the mask layer 160 as a mask, the core material layer 120 below the mask opening 170 is removed to form the first trench 180.

[0086] In this embodiment, the mask layer 160 is used as a mask, and a dry etching process (e.g., anisotropic dry etching process) is used to remove the core material layer 120 below the mask opening 170, thereby improving the accuracy of pattern transfer and the cross-sectional morphology quality of the first trench 180.

[0087] like Figure 7 As shown, Figure 7 'a' is the top view. Figure 7 b is Figure 7 a. A cross-sectional view along the yy secant line, showing the removal of the mask layer 160. In this embodiment, one or both of the ashing process and the wet stripping process are used to remove the mask layer 160.

[0088] In the step of removing the mask layer 160, the anti-reflective coating 162 and the second planarization layer 161 are also removed.

[0089] refer to Figure 9 , Figure 9 'a' is the top view. Figure 9 b is Figure 9 A cross-sectional view along the yy secant line shows a sidewall 190 formed on the sidewall of the first groove 180, such that the sidewall 190 surrounds the first groove 210.

[0090] The first groove 210 is used to define a portion of the target graphic. In this embodiment, the shape and position of the first groove 210 are defined by the first trench 180 and the sidewall 190, which helps to make the first groove 210 have a smaller size, and the first groove 210 is isolated from the core layer 120 by the sidewall 190.

[0091] The sidewall 190 is made of a material that is etch-selective with the core layer 140, the anti-etching layer 130 and the target layer 100. The material of the sidewall 190 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon carbide, aluminum oxide and amorphous silicon.

[0092] In this embodiment, the step of forming the sidewall 190 includes: forming a sidewall material layer (not shown) that conformally covers the top surface of the core layer 140 and the anti-etching layer 130, as well as the bottom and sidewall of the first trench 180; removing the sidewall material layer located on the top surface of the core layer 140 and the anti-etching layer 130, as well as the bottom of the first trench 180, and using the remaining sidewall material layer located on the sidewall of the first trench 180 as the sidewall 190.

[0093] In this embodiment, the sidewall material layer is formed by atomic layer deposition, which helps to improve the thickness uniformity of the sidewall material layer and makes it easier to precisely control the thickness of the sidewall material layer.

[0094] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to remove the sidewall material layer located on the top surface of the core layer 140 and the anti-etching layer 130, as well as the bottom of the first trench 180.

[0095] refer to Figure 10 , Figure 10 'a' is the top view. Figure 10 b is Figure 10 A cross-sectional view along the yy secant line shows that after ion doping and forming the sidewalls 190, the core layer 140 is removed, and a second groove 220 is formed in the etch-resistant layer 130 on both sides of the first groove 210.

[0096] The second groove 220 and the first groove 210 together define the shape of the target graphic.

[0097] After removing the core layer 140, the second groove 220 and the first groove 210 are separated by the side wall 190, which helps to ensure that the second groove 220 and the first groove 210 meet the design minimum spacing.

[0098] In this embodiment, the core layer 140 and the anti-etching layer 130 have a high etching selectivity ratio, so that in the step of removing the core layer 140 to form the second groove 220, it is not easy to cause double etching to the first groove 210, thereby reducing the process risk and ensuring the pattern accuracy of the first groove 210.

[0099] In this embodiment, after the second groove 220 is formed, along the first direction, the end of the first groove 210 protrudes out of the second groove 220, the second groove 220 is located on both sides of the first groove 210, and the second grooves 220 are spaced apart.

[0100] The process for removing the core layer 140 includes one or both of wet etching and dry etching. As an example, a wet etching process is used to remove the core layer 140. In this embodiment, the etching solution for the wet etching process includes TMAH solution (tetramethylammonium hydroxide solution), SC1 solution, or SC2 solution. SC1 solution refers to a mixed solution of NH4OH and H2O2, and SC2 solution refers to a mixed solution of HCl and H2O2.

[0101] refer to Figure 11 , Figure 11 'a' is the top view. Figure 11 b is Figure 11 A cross-sectional view along the yy secant line shows the target layer 100 below the first groove 210 and the second groove 220 being etched using the anti-etching layer 130 and the sidewall 190 as a mask to form the target pattern 230.

[0102] As described above, by superimposing the pattern of the first region 120a and the pattern of the first trench 180, the pattern of the second groove 220 is defined. Consequently, the second groove 220 can achieve a smaller size, and the minimum design spacing between the second groove 220 and the first groove 210 is easily met. Thus, without changing the limits of the photolithography process, it is beneficial to achieve a smaller critical size of the target pattern 230 and further compress the pitch between the target patterns 230 to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires little modification to the existing process, has low process complexity, and is highly photolithography friendly. It is beneficial to improve the matching degree between the target pattern 230 and the design pattern, as well as improve the pattern accuracy of the target pattern 230.

[0103] In this embodiment, the target layer 100 is a dielectric layer. Therefore, using the etch-resistant layer 130 and the sidewall 190 as masks, the dielectric layer beneath the first groove 210 and the second groove 220 is etched to form interconnect trenches 30. The target pattern 230 is the interconnect trench 30, which provides space for forming metal interconnects.

[0104] Specifically, in this embodiment, the hard mask material layer 115 below the first groove 210 and the second groove 220 is etched using the anti-etching layer 130 and the sidewall 190 as masks to form a hard mask layer 105; the dielectric layer is patterned using the hard mask layer 105 as a mask to form the interconnect trench 30.

[0105] In this embodiment, during the step of etching the target layer 100 below the first groove 210 and the second groove 220, the anti-etching layer 130 and the sidewall 190 also have a portion of their thickness consumed.

[0106] refer to Figure 12 , Figure 12 'a' is the top view. Figure 12 b is Figure 12 A cross-sectional view along the yy secant line. The method of forming the interconnection trench 30 also includes: forming a metal interconnection line 240 in the interconnection trench 30 after forming the interconnection trench 30.

[0107] In this embodiment, the interconnect trenches 30 can achieve smaller critical dimensions, and the pitch between the interconnect trenches 30 is further compressed. Therefore, it is beneficial to further compress the pitch of the metal interconnects 240 to meet the requirements of high density and high integration of integrated circuits. Moreover, the interconnect trenches 30 are easy to meet the minimum design spacing and the pattern accuracy of the interconnect trenches 30 is high. This is beneficial to meet the minimum design spacing between the metal interconnects 240 and improve the pattern accuracy of the metal interconnects 240, thereby improving the performance of the semiconductor structure.

[0108] The metal interconnect 240 is used to realize the electrical connection between the semiconductor structure and external circuits or other interconnect structures. In this embodiment, the material of the metal interconnect 240 is copper. In other embodiments, the material of the metal interconnect can also be conductive materials such as cobalt, tungsten, and aluminum. In this embodiment, in the step of forming the metal interconnect 240, the resist layer 130, the sidewall 190, and the hard mask layer 105 are also removed to prepare for subsequent processes.

[0109] Figures 13 to 16 This is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiment will not be repeated here. The differences between this embodiment and the previous embodiment are:

[0110] refer to Figure 13 Ion doping is performed on the core material layer (not shown in the figure) in the second region (not indicated) to improve the etching resistance of the core material layer. The core material layer doped with ions in the second region serves as the etching resistance layer 330, and the core material layer without ions in the first region serves as the core layer 340.

[0111] As an example, the ion doping is performed before the formation of the first trench.

[0112] refer to Figure 14 Formed along the first direction (e.g.) Figure 14 The first trench 380 (as shown in the X direction) penetrates at least part of the core material layer of the first region, and the direction perpendicular to the first direction is the second direction (as shown in the X direction). Figure 14 (As shown in the Y direction), in the second direction, the core material layer of the first region is retained on both sides of the first trench 380.

[0113] In this embodiment, after the ion doping is performed, the first trench 380 is formed. Therefore, the first trench 380 penetrates at least a portion of the core layer 340 along a first direction, and in a second direction, portions of the core layer 340 are retained on both sides of the first trench 380.

[0114] The first trench 380 includes a first sidewall 381 along a second direction and a second sidewall 382 opposite to and parallel to the first sidewall 381. In this embodiment, the first sidewall 381 of the first trench 380 is located in the first region, and there is a gap between the first sidewall 381 and the boundary on the same side of the first region; the second sidewall 382 of the first trench 380 is flush with the boundary on the same side of the first region, or the second sidewall 382 of the first trench 380 is located in an adjacent second region.

[0115] Specifically, in this embodiment, the first sidewall 381 of the first trench 380 is located in the core layer 340, and there is a gap between the first sidewall 381 and the sidewall on the same side of the core layer 340; the second sidewall 382 of the first trench 380 is flush with the sidewall on the same side of the core layer 340, or the second sidewall 382 of the first trench 380 is located in the adjacent anti-etching layer 330.

[0116] As an example, the first sidewall 381 of the first trench 380 is located in the core layer 340, and there is a gap between the first sidewall 381 and the sidewall on the same side of the core layer 340, and the second sidewall 382 of the first trench 380 is located in the adjacent anti-etching layer 330.

[0117] refer to Figure 15A sidewall 390 is formed on the sidewall of the first groove 380, so that the sidewall 390 surrounds the first groove 310.

[0118] refer to Figure 16 After ion doping and forming the sidewalls 390, the core layer 340 is removed, and a second groove 320 is formed in the etch-resistant layer 330 on both sides of the first groove 310.

[0119] In the step of removing the core layer 340, the second groove 320 is connected at the position of the first sidewall 381. The second groove 320 correspondingly exposes the sidewall of the first sidewall 381.

[0120] Therefore, in this embodiment, the second groove 320 not only extends along the first direction, but the second groove 320 located outside the first sidewall 381 also extends along the second direction. Thus, by superimposing the core layer 340 pattern and the first groove 380 pattern, the pattern of the second groove 320 is a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern. Moreover, compared with using the pattern of the photomask to realize the two-dimensional pattern, this embodiment is beneficial to reducing the process difficulty and increasing the photolithography process window.

[0121] In this embodiment, the target layer is a dielectric layer. Subsequently, using the etch-resistant layer 330 and the sidewall 390 as masks, the dielectric layer beneath the first groove 310 and the second groove 320 is etched to form interconnect trenches. These interconnect trenches provide spatial locations for forming metal interconnects. Accordingly, the metal interconnects corresponding to the position of the second groove 320 extend not only in the first direction but also along the second direction, thereby enabling two-dimensional winding. This improves the graphic design and layout freedom of the metal interconnects and enhances their connectivity.

[0122] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0123] Figures 17 to 20 This is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure according to the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:

[0124] refer to Figure 17 The core material layer in the second region is ion-doped to improve the etching resistance of the core material layer. The ion-doped core material layer in the second region serves as the etching-resistant layer 430, and the undoped core material layer in the first region serves as the core layer 440.

[0125] As an example, the ion doping is performed before the formation of the first trench.

[0126] refer to Figure 18 A first trench 480 is formed that penetrates at least a portion of the core material layer of the first region along a first direction. The direction perpendicular to the first direction is a second direction. In the second direction, a portion of the core material layer of the first region is retained on both sides of the first trench 480.

[0127] The first trench 480 is located in the core material layer of the first region, and in the first direction, there is a gap between the sidewall of the first trench 480 and the boundary on the same side of the first region.

[0128] Specifically, the first trench 480 is located in the core layer 440, and in the first direction, there is a gap between the sidewall of the first trench 480 and the sidewall of the core layer 440 on the same side. Moreover, in the second direction, a portion of the core material layer of the first region is retained on both sides of the first trench 480, that is, in the second direction, there is also a gap between the sidewall of the first trench 480 and the sidewall of the core layer 440 on the same side.

[0129] Therefore, in this embodiment, after the first trench 480 is formed, the remaining core layer 440 surrounds the first trench 480.

[0130] refer to Figure 19 A sidewall 490 is formed on the sidewall of the first groove 480, so that the sidewall 490 surrounds the first groove 410.

[0131] refer to Figure 20 After ion doping and forming the sidewalls 490, the core layer 440 is removed, and a second groove 420 is formed in the etch-resistant layer 430 on both sides of the first groove 410.

[0132] In this embodiment, during the step of removing the core layer 440, the second groove 420 surrounds the first groove 410. The second groove 420 correspondingly surrounds the sidewall of the sidewall 490, and is an annular groove.

[0133] Therefore, in this embodiment, the second groove 420 extends not only along the first direction but also along the second direction. By superimposing the core layer 440 pattern and the first groove 480 pattern, the pattern of the second groove 420 is a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern. Moreover, compared with using the pattern of the photomask to realize the two-dimensional pattern, this embodiment is beneficial to reducing the process difficulty and increasing the photolithography process window.

[0134] In this embodiment, the target layer (not shown) is a dielectric layer. Subsequently, using the etch-resistant layer 430 and the sidewall 490 as masks, the dielectric layer below the first groove 410 and the second groove 420 is etched to form interconnect trenches. The interconnect trenches are used to provide space for forming metal interconnects.

[0135] Correspondingly, the metal interconnect line corresponding to the position of the second groove 420 not only extends in the first direction, but also extends along the second direction, thereby enabling two-dimensional winding, which is beneficial to improving the graphic design and layout freedom of the metal interconnect line, and also beneficial to improving the interconnection capability of the metal interconnect line.

[0136] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0137] Figures 21 to 25 This is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure according to the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:

[0138] like Figure 21 As shown, a core material layer 12 is formed on the substrate. The core material layer 12 includes a first region 12a for forming the core layer and a second region 12b surrounding the first region 12a for forming an anti-etching layer. There are multiple first regions 12a arranged along a second direction, and the multiple first regions 12a are independent of each other.

[0139] It should be noted that the shape, position, arrangement and quantity of the first region 12a in this embodiment are only examples, and the shape, position and quantity and arrangement of the first region 12a in this embodiment are not limited to this.

[0140] like Figure 22 As shown, the core material layer 12 in the second region 12b is ion-doped to improve the etching resistance of the core material layer 12. The ion-doped core material layer 12 in the second region 12b serves as the etching-resistant layer 13, and the undoped core material layer 12 in the first region 12a serves as the core layer 14.

[0141] like Figure 23 As shown, a first trench 15 is formed that penetrates at least a portion of the core material layer 12 of the first region 12a along a first direction. The direction perpendicular to the first direction is a second direction. In the second direction, a portion of the core material layer 12 of the first region 12a is retained on both sides of the first trench 15.

[0142] As an example, after ion doping, the first trench 15 is formed, and correspondingly, the first trench 15 penetrates at least a portion of the core layer 14 in a first direction, and in a second direction, portions of the etch-resistant layer 13 are retained on both sides of the first trench 15.

[0143] As an example, the first trench 15 may be formed only in a portion of the core material layers 12 of the first region 12a, while the first trench 15 may not be formed in the remaining portion of the core material layers 12 of the first region 12a.

[0144] In other embodiments, the first trench may be formed in all of the first regions, depending on the actual design requirements.

[0145] like Figure 23 As shown, the method for forming the semiconductor structure further includes: after forming the core material layer 12 and before forming the sidewalls, forming a second trench 16 that penetrates the core material layer 12 located between the first regions 12a along the second direction.

[0146] As an example, after ion doping, the second trench 16 is formed, and correspondingly, the second trench 16 penetrates the etch-resistant layer 13 located between the core layers 14 along the second direction.

[0147] It should be noted that the second groove 16 and the first groove 15 can be formed in the same step or in different steps. In this embodiment, the specific steps for forming the first groove 15 and the second groove 16 are not limited.

[0148] like Figure 24 As shown, a sidewall 17 is formed on the sidewall of the first groove 15, so that the sidewall 17 surrounds the first groove 21.

[0149] In this embodiment, during the step of forming the sidewall 17, the sidewall 17 is also formed on the sidewall of the second groove 16, and the sidewall 17 located on the sidewall of the second groove 16 forms a third groove 23.

[0150] Accordingly, the core layer 14 is subsequently removed to form a second groove. The second groove, the first groove 15, and the third groove 23 are arranged along a second direction, and adjacent grooves are isolated from each other by the sidewall 17. The third groove 23 is also used to define the shape of the target graphic.

[0151] like Figure 25 As shown, the core layer 14 is removed, and a second groove 22 is formed in the anti-etching layer 13 on both sides of the first groove 21.

[0152] The first groove 21, the second groove 22, and the third groove 23 are used together to define the target pattern. Accordingly, the target layer below the first groove 21, the second groove 22, and the third groove 23 is etched using the anti-etching layer 13 and the sidewall 17 as a mask to form the target pattern.

[0153] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0154] Accordingly, the present invention also provides a photomask for forming semiconductor structures. Figure 26 This is a schematic diagram of a semiconductor structure according to an embodiment that has not been processed using the photomask of the present invention. Figure 27 This is a schematic diagram of the structure of a mask plate according to an embodiment of the present invention; Figure 28 It is to utilize Figure 27 This is a schematic diagram illustrating how a photomask is used to process a semiconductor structure. Among them, Figure 27 a is a schematic diagram of an embodiment of the first mask plate 601 of the present invention. Figure 27 b is a schematic diagram of an embodiment of the second mask plate 602 of the present invention.

[0155] like Figure 26 As shown, Figure 26 'a' is the top view. Figure 26 b is Figure 26 A cross-sectional view along the yy secant line shows that the semiconductor structure includes: a substrate 500, including a target layer 510 for forming a target pattern; and a core material layer 520 located on the substrate 500, including a first region I for forming a core layer and a second region II surrounding the first region I for forming an etch-resistant layer, wherein the etch-resistant layer has a greater etch resistance than the core layer.

[0156] The target layer 510 is the film layer to be patterned to form a target pattern. The target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor, a channel stack in a fully enclosed gate transistor or a fork gate transistor, a hard mask layer, etc.

[0157] In this embodiment, the target layer 510 is a dielectric layer, the target pattern is an interconnect trench, the interconnect trench provides space for forming metal interconnects, and the dielectric layer accordingly realizes electrical isolation between metal interconnects.

[0158] The etching resistance of the anti-etching layer is greater than that of the core layer. After the semiconductor structure is processed using the mask in this embodiment, the remaining anti-etching layer is used as a mask for the patterning target layer 510. Subsequently, the core layer needs to be removed to form corresponding grooves. The grooves are used to define part of the target pattern.

[0159] refer to Figures 27 to 28 The photomask includes: a first photomask 601, including a first pattern 610, the first pattern 610 being used to form along a first direction (e.g., Figure 28 The first trench (shown in the X direction) penetrates at least part of the core material layer 520 of the first region II, and the direction perpendicular to the first direction is the second direction (as shown in the X direction). Figure 28 (As shown in the Y direction), the first pattern 610 is configured such that, in the second direction, a portion of the core material layer of the first region I is retained on both sides of the first trench; the second mask 602 cooperates with the first mask 601, and the second mask 602 includes a second pattern 620, which is used to form the core layer located in the first region I.

[0160] The first pattern 610 is configured such that, in the second direction, a portion of the core material layer of the first region I is retained on both sides of the first trench. The second pattern 620 is used to form the core layer located in the first region I. Therefore, after processing the semiconductor structure using the mask provided in this embodiment, the pattern of the core layer spans the pattern of the first trench, and the portion of the first region I excluding the area overlapping with the first trench is used to define the shape and size of the groove. Thus, by superimposing the first mask 601 pattern and the second mask 602 pattern in this embodiment, the groove can achieve a smaller size. This allows for smaller critical dimensions of the target pattern and further compression of the pitch between target patterns without changing the limits of the photolithography process, in order to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires minimal modification to existing processes, has low process complexity, and is highly photolithography-friendly.

[0161] In this embodiment, the first mask 601 is used as a mask for etching the core material layer 520. Specifically, the first mask 601 is used to form a mask layer; the first trench is formed by etching the core material layer 520 using the mask layer.

[0162] In this embodiment, the second mask 602 is used as a mask for ion doping the core material layer 520 of the second region II. Specifically, the second mask 602 is used to form a shielding layer located in the first region; the etch-resistant layer is formed by ion doping the core material layer 520 of the second region using the shielding layer as a mask. The ion doping is suitable for improving the etch resistance of the core material layer, and the undoped core material layer located in the first region serves as the core layer.

[0163] The ion doping is adapted to improve the etching resistance of the core material layer 520, so that after ion doping of the core material layer 520 using the shielding layer formed by the second mask 602 as a mask, the etching resistance of the core material layer 520 (i.e., the etching-resistant layer) in the second region II is correspondingly greater than that of the core material layer 520 (i.e., the core layer) in the first region I. The core layer is used to occupy space for forming the groove.

[0164] In this embodiment, the photolithography process is a positive photolithography process. The first pattern 610 is a light-receiving pattern, and the second pattern 620 is a light-shielding pattern. Correspondingly, when the photoresist is exposed and developed using the first mask 601, an opening pattern corresponding to the first pattern 610 is formed in the photoresist layer on the wafer; when the photoresist is exposed and developed using the second mask 602, a blocking pattern corresponding to the second pattern 620 is formed in the photoresist layer on the wafer.

[0165] In other embodiments, the photolithography process can also be a negative photolithography process, where the first pattern is a light-shielding pattern and the second pattern is a light-receiving pattern. Accordingly, an opening pattern corresponding to the first pattern and a blocking pattern corresponding to the second pattern 620 can also be formed in the photoresist layer on the wafer.

[0166] It should be noted that, for ease of illustration and explanation, only one second pattern 620 is shown in the second mask 602 in this embodiment. However, the shape, number, and position of the second pattern 620 are not limited to this. In other embodiments, the pattern of the second mask is flexibly adjusted according to the actual shape, number, and position of the first region. For example, when there are multiple first regions arranged along the second direction, and the multiple first regions are independent of each other, the number of second patterns is correspondingly multiple and arranged along the second direction.

[0167] It should also be noted that, depending on the actual semiconductor structure required, the second mask 602 may also have other patterned structures. For example, a pattern for forming the second trench. For a specific description of the second trench, please refer to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0168] Furthermore, in other embodiments, when there are multiple second patterns, the patterns of the first mask can be flexibly adjusted accordingly. For example, the number of first patterns in the first mask may also be multiple, and they may correspond to the second patterns in the second mask; or, for another example, the first patterns in the first mask may correspond only to a portion of the second patterns in the second mask.

[0169] In this embodiment, the first trench includes a first sidewall along the second direction and a second sidewall opposite to and parallel to the first sidewall; the first pattern 610 is configured such that the first trench penetrates the core material layer 520 of the first region I along the first direction; or, the first trench penetrates the core material layer 520 of the first region I along the first direction, and either or both of the first sidewall and the second sidewall extend into the core material layer 520 of the adjacent second region II.

[0170] Accordingly, after processing the semiconductor structure using the mask in this embodiment, in the second direction, the core layers located on both sides of the first trench are separated by the first trench.

[0171] Figure 29 This is a schematic diagram of another embodiment of the photomask of the present invention. Figure 30 It is to utilize Figure 29 This is a schematic diagram illustrating how a photomask is used to process a semiconductor structure. Among them, Figure 29 a is a schematic diagram of the first mask 701. Figure 29 b is a schematic diagram of the second mask 702. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:

[0172] The first trench includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall. The first pattern 710 is configured such that the first sidewall of the first trench is located in the first region, and there is a gap between the first sidewall and the boundary of the first region on the same side; the second sidewall of the first trench is flush with the boundary of the first region on the same side, or the second sidewall of the first trench is located in an adjacent second region. Sidewalls are typically also formed on the sidewalls of the first trench, so that the sidewalls enclose the first groove.

[0173] Therefore, after forming the first trench using the first mask 701 and forming the core layer and resist layer by ion doping the core material layer 730 using the second mask 702, the core layer is connected at the position of the first sidewall. Correspondingly, in the step of removing the core layer, the formed second groove is connected at the position of the first sidewall, so that the second groove not only extends along the first direction, but also the second groove located outside the first sidewall extends along the second direction. Thus, by superimposing the patterns of the first mask 701 and the second mask 702, the pattern of the second groove is a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern. In addition, compared with realizing a two-dimensional pattern using the pattern of the photomask, this embodiment is beneficial to reducing the process difficulty and increasing the photolithography process window.

[0174] Figure 31This is a schematic diagram of another embodiment of the photomask of the present invention. Figure 32 It is to utilize Figure 31 This is a schematic diagram illustrating how a photomask is used to process a semiconductor structure. Among them, Figure 31 a is a schematic diagram of the first mask 801. Figure 31 b is a schematic diagram of the second mask 802. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:

[0175] The first pattern 810 is configured such that the first trench is located in the core material layer 830 of the first region, and in the first direction, there is a gap between the sidewall of the first trench and the boundary on the same side of the first region. Sidewalls are typically also formed on the sidewalls of the first trench, so that the sidewalls enclose the first groove.

[0176] Therefore, after forming the first trench using the first mask 801 and the core layer and resist layer using the second mask 801, the core layer surrounds the first trench. Correspondingly, in the step of removing the core layer, the formed second groove surrounds the first groove, so that the second groove extends not only along the first direction but also along the second direction. Thus, by superimposing the patterns of the first mask 801 and the second mask 802, the pattern of the second groove is a two-dimensional pattern, which helps to improve the design freedom of the target pattern.

[0177] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, including a target layer for forming a target pattern; forming a core material layer on the substrate, the core material layer including a first region for forming a core layer, and a second region surrounding the first region for forming an etch-resistant layer; ion-doping the core material layer of the second region, adapted to increase the etch-resistance of the core material layer, the core material layer of the second region doped with ions serving as the etch-resistant layer, and the core material layer of the first region not doped with ions serving as the core layer; forming a first trench through at least part of the core material layer of the first region in a first direction, a direction perpendicular to the first direction being a second direction, in the second direction, the core material layer of the first region remaining on both sides of the first trench; forming a side wall on the sidewall of the first trench, so that the side wall encloses a first groove; after the ion-doping and the formation of the side wall, removing the core layer to form a second groove on both sides of the first groove in the etch-resistant layer; using the etch-resistant layer and the side wall as a mask, etching the target layer under the first groove and the second groove to form the target pattern; in the step of forming the first trench, the first trench is in the core material layer of the first region, and in the first direction, the sidewall of the first trench has a spacing between the boundary on the same side of the first region; in the step of removing the core layer, the second groove surrounds the first groove.

2. The method of forming a semiconductor structure of claim 1, wherein, in the step of forming the first trench, the first trench includes a first sidewall in the second direction, and a second sidewall opposite to the first sidewall and parallel to the first sidewall; in the first direction, the first trench penetrates the core material layer of the first region; alternatively, in the first direction, the first trench penetrates the core material layer of the first region, and either one or both of the first sidewall and the second sidewall further extends into the core material layer of the adjacent second region; in the step of removing the core layer, the second grooves are spaced apart.

3. The method of forming a semiconductor structure of claim 1, wherein, in the step of forming the first trench, the first trench includes a first sidewall in the second direction, and a second sidewall opposite to the first sidewall and parallel to the first sidewall; the first sidewall of the first trench is in the first region, and the first sidewall has a spacing between the boundary on the same side of the first region; the second sidewall of the first trench is flush with the boundary on the same side of the first region, or the second sidewall of the first trench is in the adjacent second region; in the step of removing the core layer, the second grooves are connected at the position of the first sidewall.

4. The method of forming a semiconductor structure of claim 1, wherein, after the formation of the core material layer, and before the formation of the first trench, ion-doping the core material layer of the second region; alternatively, after the formation of the first trench, and before the formation of the side wall, ion-doping the core material layer of the second region; Alternatively, after forming the side wall and before removing the core layer, the core material layer of the second region is ion doped.

5. The method of forming a semiconductor structure of claim 1, wherein, The material of the core material layer includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbon nitride, and silicon carbon oxynitride.

6. The method of forming a semiconductor structure of claim 1, wherein, The ion for ion doping includes one or more of boron ion, phosphorus ion, and argon ion.

7. The method of forming a semiconductor structure of claim 1, wherein, The core material layer of the second region is ion doped by using an ion implantation process.

8. The method of forming a semiconductor structure of claim 1, wherein, The step of ion doping the core material layer of the second region includes: forming a shielding layer on the core material layer of the first region, the shielding layer exposing the second region; using the shielding layer as a mask, ion doping the core material layer; and removing the shielding layer.

9. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the first trench includes: forming a mask layer on the core material layer, the mask layer having a mask opening extending in a first direction; in a projection plane parallel to the substrate, the first region crossing the mask opening in a second direction; using the mask layer as a mask, removing the core material layer under the mask opening to form the first trench; and removing the mask layer.

10. The method of forming a semiconductor structure of claim 9, wherein, The core material layer under the mask opening is removed by using a dry etching process with the mask layer as a mask.

11. The method of forming a semiconductor structure of claim 1, wherein, The etching selectivity ratio between the core layer and the etching-resistant layer is at least 20:

1.

12. The method of forming a semiconductor structure of claim 1, wherein, The number of the first regions is multiple and the multiple first regions are arranged along the second direction; The method for forming the semiconductor structure further includes: after forming the core material layer and before forming the side wall, forming a second trench through the core material layer between the first regions along the second direction; In the step of forming the side wall, the side wall is also formed on the sidewall of the second trench, and the side wall on the sidewall of the second trench encloses a third recess. The target layer is etched under the first recess, the second recess, and the third recess using the etching-resistant layer and the side wall as a mask to form a target pattern.

13. The method of forming a semiconductor structure of claim 1, wherein, The process of removing the core layer includes a wet etching process.

14. The method of forming a semiconductor structure of claim 1, wherein, The target layer is a dielectric layer; and the target pattern is an interconnection trench. The method for forming the semiconductor structure further includes: after forming the interconnection trench, forming a metal interconnection line in the interconnection trench.

15. A mask for forming a semiconductor structure, the semiconductor structure comprising: A substrate includes a target layer for forming a target pattern; A core material layer on the substrate includes a first region for forming a core layer and a second region surrounding the first region for forming an etching-resistant layer, the etching-resistant layer having a higher etching resistance than the core layer; The mask includes: A first mask includes a first pattern for forming a first trench through at least part of the core material layer of the first region along a first direction, a direction perpendicular to the first direction being a second direction, the first pattern being arranged such that, in the second direction, both sides of the first trench are left with part of the core material layer of the first region. A second mask, cooperating with the first mask, the second mask comprising a second pattern, the second pattern being used to form the core layer in the first region; The first pattern is configured such that the first trench is located in the core material layer in the first region, and in the first direction, the first trench has a spacing between the side wall and the boundary on the same side of the first region.

16. The mask of claim 15, wherein, The first trench comprises a first side wall along the second direction, and a second side wall opposite to the first side wall and parallel to the first side wall; The first pattern is configured such that the first trench penetrates the core material layer in the first region along the first direction; or, the first trench penetrates the core material layer in the first region along the first direction, and any one or both of the first side wall and the second side wall further extends into the core material layer in the adjacent second region.

17. The mask of claim 15, wherein, The first trench comprises a first side wall along the second direction, and a second side wall opposite to the first side wall and parallel to the first side wall; The first pattern is configured such that the first side wall of the first trench is located in the first region, and the first side wall has a spacing between the first side wall and the boundary on the same side of the first region; the second side wall of the first trench is flush with the boundary on the same side of the first region, or the second side wall of the first trench is located in the adjacent second region.

18. The mask of claim 15, wherein, The first mask is used to form a mask layer; the first trench is formed by etching the core material layer with the mask layer as a mask; The second mask is used to form a shielding layer in the first region; The etching-resistant layer is formed by ion doping the core material layer in the second region with the shielding layer as a mask, the ion doping being suitable for improving the etching resistance of the core material layer, and the core material layer in the first region without ion doping serving as the core layer.

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