Semiconductor element, semiconductor assembly and method for producing the same

Abstract

The present disclosure provides a semiconductor element, a semiconductor assembly and a method of manufacturing the semiconductor assembly. The semiconductor element includes a substrate, a conductive feature in the substrate, an insulating liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature has first, second and third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension, which is greater than the first critical dimension. The third block is interposed between the first and second blocks and has a plurality of varying third critical dimensions.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. Official Application No. 17 / 077,842, filed October 22, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to the conductivity characteristics of a semiconductor element and a method for fabricating the same. In particular, this disclosure provides a conductivity characteristic of a semiconductor element and semiconductor assembly having non-uniform critical dimensions and a method for fabricating the same. Background Technology

[0003] Since the invention of integrated circuits, the semiconductor industry has experienced sustained rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from repeated reductions in the smallest feature size, allowing more components to be integrated into a given chip area.

[0004] These improvements in integration are essentially two-dimensional (2D) because the volume occupied by the integrated components is essentially located on the surface of the semiconductor wafer. Significant improvements in lithography have led to significant improvements in the formation of 2D integrated circuits. However, due to the reduction in component size, the contact area between the multiple conductive pads and bumps of the integrated components is reduced, making delamination of the bumps and conductive pads more likely. This negatively impacts the electrical performance and reliability of the semiconductor device.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a conductive feature, an insulating pad, and a main component. The conductive feature is disposed in the substrate and includes a first block, a second block, and a third block. The first block has a uniform first critical size, and the second block has a uniform second critical size, the second critical size being larger than the first critical size. The third block is interposed between the first block and the second block and has a plurality of varying third critical sizes. The insulating pad covers a portion of the conductive feature; and the main component is disposed in the substrate and around the first block.

[0007] In some embodiments, the third critical size of the third block gradually increases at locations with increasing distance from the first block and gradually decreases at locations with increasing distance from the second block.

[0008] In some embodiments, the first block of the conductive feature has a first height, the second block of the conductive feature has a second height, and the third block of the conductive feature has a third height, wherein the second height is greater than the first height and the third height is less than the first height.

[0009] Another embodiment of this disclosure provides a semiconductor assembly. The semiconductor assembly includes a first semiconductor element, a second semiconductor element, a conductive feature, and an insulating pad. The first semiconductor element includes a conductive pad; and the second semiconductor element is vertically stacked on the first semiconductor element. The conductive feature passes through the second semiconductor element and includes a first block and a second block with different critical dimensions. The first block contacts the conductive pad and has a first critical dimension; and the second block is connected to the first block and has a second critical dimension larger than the first critical dimension. The insulating pad is interposed between the second semiconductor element and the conductive feature.

[0010] In some embodiments, the conductive feature further includes a third block, interposed between the first block and the second block, and having a plurality of varying third critical dimensions.

[0011] In some embodiments, the third critical dimension of the third block of the conductive feature gradually increases at locations with increasing distance from the first block and gradually decreases at locations with increasing distance from the second block.

[0012] In some embodiments, the second semiconductor element includes a substrate, a plurality of main components, and an isolation layer. The main components are disposed in the substrate and around the first block; and the isolation layer encapsulates the main components. A portion of the first block, the second block, and the third block of the conductive feature are located in the substrate, and another portion of the first block of the conductive feature extends through the isolation layer.

[0013] In some embodiments, the portion of the first block of the conductive feature located in the substrate has a first height, the second block of the conductive feature has a second height, and the third block of the conductive feature has a third height, wherein the second height is greater than the first height and the third height is less than the first height.

[0014] In some embodiments, the sum of the first height and the third height is less than the second height.

[0015] In some embodiments, the semiconductor component further includes a passivation layer covering the substrate, wherein a portion of the second block of the conductive feature is surrounded by the passivation layer.

[0016] In some embodiments, the semiconductor component further includes a bonding layer sandwiched between the first semiconductor element and the second semiconductor element, wherein the first block of the conductive feature passes through the bonding layer to contact the conductive pad.

[0017] Another embodiment of this disclosure provides a method for fabricating a semiconductor component. The method includes bonding a first semiconductor element and a second semiconductor element together; performing a first cyclic process to create a plurality of first recesses in a substrate of the second semiconductor element, the first recesses being interconnected, wherein the first recesses have a first width; performing a second cyclic process to create a plurality of second recesses via the first recesses, the second recesses being interconnected, wherein the second recesses have a second width smaller than the first width; forming an insulating pad on portions of the substrate exposed via the first and second recesses; and depositing a conductive material in the first and second recesses coated with the insulating pad.

[0018] In some embodiments, the first depression is generated by the first cycle process of alternating a deposition step and an etching step, and the second depression is generated by a sequence including a first deposition step, a second deposition step and an etching step.

[0019] In some embodiments, the time duration of the etching step for etching the substrate in the second cycle process is shorter than the time duration of the etching step for etching the substrate in the first cycle process.

[0020] In some embodiments, the fabrication method further includes performing a removal process on the substrate to remove a fan-shaped pattern generated during each etching step of the first and second cycle processes, thereby forming a trench through the substrate, the trench having a non-uniform width.

[0021] In some embodiments, a portion of the substrate exposed by the trench includes a first vertical surface, a second vertical surface, and an inclined surface, the inclined surface connecting the first vertical surface and the second vertical surface.

[0022] In some embodiments, the fabrication method further includes: depositing a passivation layer on the second semiconductor device; and generating an opening in the passivation layer prior to performing the first cycle process; wherein the substrate is etched through the opening to generate the first and second recesses.

[0023] In some embodiments, the bonding of the first semiconductor element and the second semiconductor element includes: depositing a plurality of dielectric films on the first semiconductor element and the second semiconductor element respectively; mounting the second semiconductor element onto the first semiconductor element to make the dielectric films contact; and performing an annealing process to melt the dielectric films, thereby forming a bonding layer for connecting the first and second semiconductor elements; wherein, prior to forming the insulating pad, a portion of the bonding layer below the first and second recesses is removed to expose the conductive pad.

[0024] In some embodiments, the first cycle process is performed until the substrate is etched to a selected depth, and the second cycle process is completed once the connected first and second recesses have passed through the substrate, wherein the second recess has a default depth that is less than the selected depth.

[0025] Because the architecture of the semiconductor component and the semiconductor element reduces the footprint of the conductive feature in the vicinity of each main component, the area utilization of the substrate on which the conductive feature is disposed is increased.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 A cross-sectional schematic diagram of an electronic system illustrating some embodiments of the present disclosure is shown.

[0029] Figure 2A cross-sectional schematic diagram illustrating some embodiments of the present disclosure is shown.

[0030] Figure 3 A schematic flowchart illustrating a method for fabricating a semiconductor component according to some embodiments of this disclosure is provided.

[0031] Figures 4 to 30 The following are schematic cross-sectional views illustrating the intermediate stages of fabricating a semiconductor component according to some embodiments of this disclosure.

[0032] The reference numerals in the attached figures are explained as follows:

[0033] 10: Electronic Systems

[0034] 20: Semiconductor Components

[0035] 60: Semiconductor components

[0036] 100: Circuit board

[0037] 102: Bump

[0038] 210: First semiconductor element

[0039] 220: Base

[0040] 230: Main components

[0041] 240: Isolation layer

[0042] 242: Upper surface

[0043] 250: Conductive pad

[0044] 252: Top surface

[0045] 300: Trench

[0046] 310: Second semiconductor element

[0047] 320: Base

[0048] 321: Thinning the substrate

[0049] 3212: Surface

[0050] 322: Base

[0051] 330: Main components

[0052] 332: Base

[0053] 340: Isolation layer

[0054] 400: Bonding layer

[0055] 402: Hole

[0056] 410: Dielectric film

[0057] 420: Dielectric film

[0058] 450: Passivation layer

[0059] 451: Opening

[0060] 452: Passivation layer

[0061] 500: Conductivity characteristics

[0062] 502: Block 1

[0063] 504: Block 2

[0064] 506: Block 3

[0065] 510: Conductive materials

[0066] 520: Insulating film

[0067] 522: Insulating gasket

[0068] 530: Diffusion barrier membrane

[0069] 534: Diffusion barrier membrane

[0070] 610: Base

[0071] 6102: Upper surface

[0072] 620: Main Components

[0073] 630: Conductivity characteristics

[0074] 632: Block 1

[0075] 634: Second Block

[0076] 636: Third Block

[0077] 640: Insulation layer

[0078] 700: Preparation method

[0079] 800: Light mask

[0080] 802: Window

[0081] 810: Sacrificial membrane

[0082] 812: Horizontal section

[0083] 814: Vertical section

[0084] 820: Sacrificial membrane

[0085] 830: Sacrificial membrane

[0086] 840: First sacrificial membrane

[0087] 850: Sacrificial membrane

[0088] 860: Sacrificial membrane

[0089] 3222a: First depression

[0090] 3222b: First depression

[0091] 3222c: First depression

[0092] 3222d: First depression

[0093] 3224a: Second depression

[0094] 3224b: Second depression

[0095] 3224c: Second depression

[0096] 3332: First vertical surface

[0097] 3334: Second vertical surface

[0098] 3336: Inclined surface

[0099] 6322: Perpendicular to surrounding surface

[0100] 6342: Perpendicular to surrounding surface

[0101] 6362: Tilt surrounding surface

[0102] CD1: First critical size

[0103] CD2: Second critical size

[0104] CD3: Third critical size

[0105] CDa: Predetermined critical size

[0106] H: Preset height

[0107] H1: First Height

[0108] H2: Second Altitude

[0109] H3: Third Height

[0110] S702: Steps

[0111] S704: Steps

[0112] S706: Steps

[0113] S708: Steps

[0114] S710: Steps

[0115] S712: Steps

[0116] S714: Steps

[0117] S716: Steps

[0118] S718: Steps

[0119] S720: Steps

[0120] S722: Steps

[0121] S724: Steps

[0122] Ta: Original thickness

[0123] Tb: Thickness

[0124] Tx: Thickness

[0125] Ty: Thickness

[0126] T1: First thickness

[0127] T2: Second thickness

[0128] W: Preset width

[0129] W1: First width

[0130] W2: Second width Detailed Implementation

[0131] The embodiments or examples of this disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0132] It should be understood that while the terms "first," "second," "third," etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the "first element," "component," "region," "layer," or "section" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0133] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, the terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0134] Figure 1 A cross-sectional schematic diagram illustrating some embodiments of an electronic system 10 of this disclosure is shown. Please refer to... Figure 1 The electronic system 10 has a circuit board 100 and a semiconductor component 20, the semiconductor component 20 being electrically coupled to the circuit board 100 via at least one bump 102. The bump 102 serves as a plurality of input / output (I / O) connection points to electrically connect the semiconductor component 20 to a plurality of external devices, the external devices including a central processing unit (CPU) and a graphics processing unit (GPU) mounted on the circuit board 100.

[0135] Semiconductor component 20 includes a first semiconductor element 210 and a second semiconductor element 310, and a conductive feature 500. The first semiconductor element 210 and the second semiconductor element 310 are vertically stacked in a front-to-front configuration. The conductive feature 500 passes through the second semiconductor element 310 to electrically couple the first semiconductor element 210 to the bump 102, and thus to the circuit board 100. The first semiconductor element 210 and the second semiconductor element 310 can be manufactured using the same manufacturing process. For example, the first semiconductor element 210 and the second semiconductor element 310 can form a memory stack. Alternatively, the first semiconductor element 210 and the second semiconductor element 310 can be manufactured using different manufacturing processes. For example, one of the first semiconductor element 210 and the second semiconductor element 310 can be a memory element, while the other of the first semiconductor element 210 and the second semiconductor element 310 can be a processor, an image sensor, or an application-specific integrated circuit (ASIC) element.

[0136] The first semiconductor element 210 is bonded to the second semiconductor element 310 via a bonding layer 400, which contains an insulating material. In particular, the first and second semiconductor elements 210 and 310 are bonded using a dielectric-to-dielectric bonding process, such as an oxide fusion bonding process.

[0137] The conductive feature 500 passes through not only the second semiconductor element 310 but also the bonding layer 400. The conductive feature 500 may comprise aluminum or an aluminum alloy. Alternatively, the conductive feature 500 may comprise copper or a copper alloy, having a resistance lower than that of aluminum. The conductive feature 500 may include a first block 502, a second block 504, and a third block 506; the first block 502 has a uniform first critical size CD1; the second block 504 has a uniform second critical size CD2; the third block 506 is interposed between the first block 502 and the second block 504 and has a varying third critical size CD3. The first critical size CD1 is smaller than the second critical size CD2; the third critical size CD3 gradually increases at positions with increasing distance from the first block 502 and gradually decreases at positions with increasing distance from the second block 504. In some embodiments, when viewed in cross-sectional view, the first and second blocks 502 and 504 of the conductive feature 500 have rectangular shapes, and the third block 506 of the conductive feature 500 has a trapezoidal shape. The first block 502, the second block 504, and the third block 506 of the conductive feature 500 can be integrally formed.

[0138] The first semiconductor element 210 includes a substrate 220, an isolation layer 240, and a conductive pad 250; the isolation layer 240 encapsulates the substrate 220; the conductive pad 250 is surrounded by the isolation layer 240. The conductive pad 250 has a predetermined critical size CDa, which is larger than a second critical size CD2 of the second block 504 of the conductive feature 500. After the first and second semiconductor elements 210 and 310 are assembled, the isolation layer 240 serves as a contact bonding layer 400.

[0139] The second semiconductor element 310 has a substrate 322, a plurality of main components 330, and an isolation layer 340; the main components 330 are disposed on or within the substrate 322; the isolation layer 340 encapsulates the substrate 322 and the main components 330. After the first and second semiconductor elements 210 and 310 are assembled, the isolation layer 340 is a contact bonding layer 400. In some embodiments, the substrate 322 of the second semiconductor element 310 is covered with a passivation layer 452, wherein a portion of the second block 504 of the conductive feature 500 is surrounded by the passivation layer 452, and this portion of the second block 504 of the conductive feature 500 is away from the first block 502.

[0140] like Figure 1As shown, a portion of the first block 502 passes through the isolation layer 340 and the bonding layer 400 of the second semiconductor element 310, and another portion of the first block 502, having a first height H1, is located in the substrate 322 of the second semiconductor element 310. In some embodiments, the first height H1 is greater than 1 μm. Furthermore, the second block 504 in the substrate 322 has a second height H2, and the third block 506 has a third height, where the second height H2 is greater than the first height H1, and the third height H3 is less than the first height H1.

[0141] The semiconductor assembly 20 also includes an insulating pad 522 sandwiched between the second semiconductor element 310 and the conductive feature 500 to separate the conductive feature 500 from the second semiconductor element 310, thereby allowing the metal contained in the conductive feature 500 to diffuse into the substrate 322 of the second semiconductor element 310. In some embodiments, the insulating pad 522 may also be interposed between the bonding layer 400 and the conductive feature 500, and between the passivation layer 452 and the conductive feature 500.

[0142] The semiconductor component 20 may further include a diffusion barrier film 534 disposed between the conductive feature 500 and the insulating pad 522, and between the conductive pad 250 and the conductive feature 500. In other words, the conductive feature 500 is surrounded by the diffusion barrier film 534, which has a uniform thickness. The diffusion barrier film 534 comprises a plurality of refractory metals (e.g., tantalum and titanium). In some embodiments, the diffusion barrier film 534 functions as an adhesive layer to prevent the conductive feature 500 from flaking or spalling from the insulating layer 522. The conductive feature 500 and the diffusion barrier film 534 serve as an electrical interconnect between the conductive pad 250 and the bump 102.

[0143] Typically, the main component 330 near the conductive feature 500 suffers severe performance degradation due to the stress caused by the conductive feature 500. To minimize this performance variation, a keep-out zone (KOZ) is imposed around the conductive feature 500, in which the main component 330 cannot be placed. The larger the KOZ, the lower the area utilization for manufacturing the main component 330. To improve the utilization of the substrate 322 of the second semiconductor element 320, the conductive feature 500 extends through it. The first block 502 of the conductive feature 500 near the main component 330 is designed to have a minimum critical size, while the second block 504 of the conductive feature 500 away from the main component 330 can have a preset (default) critical size sufficient to facilitate the engagement of the bump 102.

[0144] Figure 2 The diagram illustrates a cross-sectional view of a semiconductor element 60 according to some embodiments of the present disclosure. The semiconductor element 60 has a substrate 610, at least one main component 620, a conductive feature 630, and an insulating layer 640, wherein the at least one main component 620, the conductive feature 630, and the insulating layer 640 are located within the substrate 610. The substrate 610 is a semiconductor substrate, such as a bulk silicon substrate, but may contain other semiconductor materials, such as group III, group IV, and / or group V elements. The main component 620 may include a transistor, a capacitor, or the like, and is formed within the substrate 610 and connected to an upper surface 6102 of the substrate 610. In some embodiments, the main component 620 may include a recessed access transistor formed within the substrate 610 during multiple front-end-of-line (FEOL) processes.

[0145] The conductive feature 630 penetrating the substrate 610 includes a first block 632, a second block 634, and a third block 636. The first block 632 has a uniform first critical size CD1; the second block 634 has a uniform second critical size CD2, which is different from the first critical size CD1; and the third block 636 has a varying third critical size CD3, wherein the third block 636 connects the second block 634 to the first block 632. Specifically, the first critical size CD1 is smaller than the second critical size CD2, and the third critical size CD3 gradually increases with increasing distance from the first block 632 and gradually decreases with increasing distance from the second block 634. That is, the first and second blocks 632 and 634 have perpendicular peripheral surfaces 6322 and 6342, respectively, and the third block 636 has an inclined peripheral surface 6362.

[0146] In some embodiments, the first block 632 of the conductive feature 630 has a first height H1. Furthermore, the second block 634 of the conductive feature 630 has a second height H2, and the third block 636 has a third height H3, where the second height H2 is greater than the first height H1, and the third height H3 is less than the first height H1. In some embodiments, the main component 620 may have a preset height H, which is less than the first height H1. For example, the first height H1 is greater than 1 μm. The conductive feature 630 with non-uniform critical dimensions can increase the utilization rate of the substrate 610. In some embodiments, a via lastprocess can be used to provide the conductive feature 630.

[0147] The insulating pad 640 covers the surrounding surfaces 6322, 6342, and 6362 of the conductive feature 630, thereby preventing the metal contained in the conductive feature 630 from diffusing into the substrate 610. The insulating pad 640, having a uniform thickness, may include a silicon-containing dielectric, such as silicon dioxide or silicon nitride. For example, the insulating pad 640 may be fabricated using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes.

[0148] Figure 3 A schematic flowchart illustrating a method 700 for fabricating a semiconductor component 20 according to some embodiments of this disclosure is shown. Figures 4 to 30 This disclosure illustrates cross-sectional schematic diagrams of various intermediate stages in the fabrication of the semiconductor component 20 according to some embodiments, corresponding to... Figure 3 The flowchart. In the following discussion, as... Figures 4 to 30 The manufacturing stages shown are for reference as follows: Figure 3 The processing steps shown are explained.

[0149] Please refer to Figure 4 ,in accordance with Figure 3In step S702, a first semiconductor element 210 and a second semiconductor element 310 are provided, and dielectric films 410 and 420 are respectively formed on the first and second semiconductor elements 210 and 310. The first semiconductor element 210 has a substrate 220, a plurality of main components 230, an isolation layer 240, and a conductive pad 250; the main components 230 are disposed in the substrate 220; the isolation layer 240 covers the substrate 220 and the main components 230; the conductive pad 250 is disposed in the isolation layer 240. The conductive pad 250 may have an uppermost surface 252 that is coplanar with an upper surface 242 of the isolation layer 240, and the dielectric film 410 covers the isolation layer 240 and the conductive pad 250. The second semiconductor element 310 has a substrate 320, a plurality of main components 330, and an isolation layer 340; the main components 330 are disposed on or in the substrate 320; the isolation layer 340 covers the substrate 320 and the main components 330. For example, the dielectric films 410 and 420 are fabricated by depositing a dielectric material on the semiconductor elements 210 and 310 respectively using a CVD process, the dielectric material comprising an oxide-based material.

[0150] Substrates 220 and 320 may comprise silicon. Additionally, substrates 220 and 320 may comprise other elemental semiconductor materials, such as germanium. In some embodiments, substrates 220 and 320 may comprise a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrates 220 and 320 may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. Substrates 220 and 320 may comprise various doped regions (not shown), which may be doped with p-type dopant and / or n-type dopant, where the p-type dopant is, for example, boron, and the n-type dopant is, for example, phosphorus or arsenic. In some embodiments, multiple insulating features, such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS), may be introduced into the substrate 220 / 320 to define and insulate various principal components 230 / 330, which are located in or on the substrate 220 / 320.

[0151] The main components 230 and 330 may include multiple active components and multiple passive components, such as transistors and / or diodes, and passive components such as capacitors, resistors, or the like. The main components 230 and 330 are fabricated using various processes, including deposition, etching, implantation, photolithography, annealing, and / or other applicable processes. The main component 230 may be electrically connected to the conductive pad 250 via a conductive feature (not shown) embedded in the isolation layer 240, and its fabrication technology includes various existing damascene processes. Furthermore, for example, the main components 230 / 330 may be interconnected to form a logic element, a memory element, an input / output element, a system-on-chip element, other suitable types of elements, or combinations thereof. In some embodiments, during the front-end-of-line (FEOL) process, the main components 230 and 330 may be formed in the substrates 220 and 320, respectively. During the back-end-of-line (BEOL) process, the isolation layers 240 / 340 and the conductive pad 250 may be formed on the substrates 220 / 320.

[0152] Please refer to Figure 5 The second semiconductor element 310 is flipped so that the dielectric films 410 and 420 can face each other and be aligned with each other. In some embodiments, multiple planarization processes may be performed on the dielectric films 410 and 420 before the first and second semiconductor elements 210 and 310 are aligned to produce an acceptable topology.

[0153] Please refer to Figure 6 ,in accordance with Figure 3Step S704 involves bonding the first and second semiconductor elements 210 and 310. After the second semiconductor element 310 is bonded to the first semiconductor element 210, the dielectric film 410 of the first semiconductor element 210 directly contacts the dielectric film 420 covering the second semiconductor element 310. After the surfaces of the dielectric films 410 and 420 come into contact, heat and force are applied to melt the dielectric films 410 and 420, thereby forming a bonding layer 400. In some embodiments, the strength of the fusion bond between the dielectric films 410 and 420 can be enhanced by exposing the first and second semiconductor elements 210 and 310 to an annealing process, wherein the first and second semiconductor elements 210 and 310 are respectively coated with dielectric films 410 and 420. Furthermore, the dielectric film 410 coated on the first semiconductor element 210 has a first thickness T1, and the dielectric film 420 covering the second semiconductor element 310 has a second thickness T2; and the first thickness T1 is greater than the second thickness T2, thereby reducing the stress applied to the first semiconductor element 210 during the melting of the dielectric films 410 and 420.

[0154] Next, based on Figure 3 In step S706, a thinning process is performed on the substrate 320 of the second semiconductor element 310 to reduce its thickness. The substrate 320 is formed from... Figure 4 The original thickness Ta shown is thinned to a thickness Tb of approximately 30 to 50 micrometers. For example, the original thickness Ta of substrate 320 is approximately 775 micrometers. Thinning substrate 320 reduces the processing time for forming at least one conductive feature as described below. The thinning process can be implemented using suitable techniques, such as grinding, polishing, and / or chemical etching. In some embodiments, a carrier wafer (not shown) may be provided to support the bonded first and second semiconductor elements 210, 310 during the thinning of substrate 320. The carrier wafer may be a blank glass carrier, a blank ceramic carrier, or the like, and may be reused so that it can be reused after removal. That is, the carrier wafer can be reused; for example, the carrier wafer can repeatedly perform step S706 to fabricate multiple intermediate structures.

[0155] Please refer to Figure 7 ,in accordance with Figure 3In step S708, a passivation layer 450 is formed to cover the thinned substrate 321. The fabrication technique for the passivation layer 450, having a uniform thickness, includes depositing a dielectric material on a surface 3212 of the thinned substrate 321. The fabrication technique for the passivation layer 450, which includes a silicon-containing material, includes a spin coating process, a CVD process, or other suitable processes for forming the dielectric material, such as silicon dioxide or silicon nitride. In some embodiments, after the dielectric material deposition, a planarization process may be optionally performed to produce an acceptable planar topology.

[0156] After the passivation layer 450 is formed, a photoresist mask 800 is provided on the passivation layer 450, the photoresist mask 800 having at least one window 802. The fabrication technique of the photoresist mask 800 includes: (1) conformally coating a photosensitive material on the passivation layer 450; (2) exposing a portion of the photosensitive material to radiation (not shown); (3) performing a post-exposure baking process; and (4) developing the photosensitive material; thereby forming the window 802, which defines the pattern etched through the passivation layer 450.

[0157] Please refer to Figure 7 and Figure 8 ,in accordance with Figure 3 In step S710, the passivation layer 450 is etched through window 802 to form an opening 451, which exposes a portion of the thinned substrate 321. Accordingly, a retained passivation layer 452 is formed, which is a portion of the thinned substrate 321 exposed on the conductive pad 250. For example, the passivation layer 450 can be anisotropically dry etched through the window using a reactive ion etching (RIE) process to create an opening 451, such that a predetermined width W in window 802 is maintained within the opening 451.

[0158] Next, a thin substrate 321 is etched using multiple cycle processes to create a trench 300, which has a non-uniform width. Specifically, a first cycle process (e.g., alternating deposition and etching steps) is used. Figure 3 Step S712) to remove a portion of the thinned substrate 321, and a second cycle process (such as) utilizing an alternating sequence of deposition, etching, and etch steps. Figure 3 Step S712) in the process of removing another part of the thinned substrate 321. Figure 3 Steps S712 and S714 together result in a deep, high aspect ratio trench 300 that penetrates the thinned substrate 321.

[0159] The first cycle process begins as follows: Figure 9 exemplified. like Figure 9 As shown, a sacrificial film 810 is formed on the photoresist mask 800 and in the openings 451 and windows 802 to cover the thinned substrate 321, the passivation layer 450, and the photoresist mask 800. The sacrificial film 810 has a topology that follows the configuration of each exposed portion of the thinned substrate 321, the passivation layer 450, and the photoresist mask 800. Figure 9 As shown, the sacrificial film 810 may include a plurality of horizontal portions 812 and one or more vertical portions 814. The horizontal portions 812 cover the thinned substrate 321 and the photoresist mask 800, while the one or more vertical portions 814 are coated on portions of the passivation layer 450 exposed through the opening 451 and portions of the photoresist mask 800 exposed through the window 802. The sacrificial film 810 can be deposited using a plasma deposition process that uses a gas selected from the group consisting of trifluoromethane (CHF3), tetrafluoroethane (C2F4), hexafluoroethane (C2F6), difluoroethane (C2H2F2), octofluorocyclobutane (C4F8), and mixtures thereof.

[0160] Next, an etching step is performed to at least remove the sacrificial film 810 from the thinned substrate 321 (e.g., Figure 10 Some portions of the thinned substrate 321 and the remaining sacrificial spacers (as shown) are exposed to the remaining sacrificial spacers. Figure 11 (As shown) is a part of this. Accordingly, a first recess 3222a is formed. The etching step is a plasma etching step, preferably in which accelerated ions advance toward the stacked first and second semiconductor elements 210, 310, thus obtaining the activation energy required for the chemical reaction in the etching step. In particular, the required plasma is generated from an etching gas by a high-frequency discharge or a microwave discharge, wherein the etching gas is derived from fluorine compounds, such as sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), and trifluoroamine (NF3).

[0161] It is worth noting that during the formation of the sacrificial film 810, etching of portions of the sacrificial film 810 and the thinned substrate 321 is performed in situ. As used herein, the term "in-situ" is used to describe steps or processes performed while the bonded first and second semiconductor elements 210, 310 are held within a processing system (e.g., a system including a load-locking chamber, a transfer chamber, a processing chamber, or any other fluid-coupled chamber), and where, for example, the processing chamber allows the bonded first and second semiconductor elements 210, 310 to be held under vacuum conditions. Therefore, the term "in-situ" can also generally be used to refer to steps or processes where the bonded first and second semiconductor elements 210, 310 are not exposed to an external environment (e.g., outside the processing system). In some embodiments, for example, the processing chamber may be a reactive etching chamber configured to generate a plasma by coupling a radio frequency (RF) electromagnetic field to a gas therein.

[0162] Please refer to Figure 9 and Figure 10 Because the fluorine-based gas used to etch the silicon substrate 321 is a less-effective etchant for the sacrificial film 810, the sacrificial film 810 can be etched anisotropically. Accordingly, the horizontal portion 812 of the sacrificial film 810 is removed, while the vertical portion 814 of the sacrificial film 810 remains on the passivation layer 452 and the sidewalls of the photoresist mask 800.

[0163] Please refer to Figure 10 and Figure 11 The remaining sacrificial spacer (e.g., the vertical portion 814 of the sacrificial film 810) is used as a mask to etch the thinned substrate 321. Due to the statistical distribution of the velocities of multiple free radicals in the plasma and the associated effects of forming volatile adsorbates, a lateral etching is accompanied by a vertical etching of the semiconductor material in the thinned substrate 321, which results in one or more undercuts in the etched substrate 322. Accordingly, the first recess 3222a may have a first width W1, and the first width W1 is greater than that in the case of... Figure 8 The preset width W in the window 802 of the light-blocking mask 800 shown.

[0164] Finish Figure 10 and Figure 11 In the etching step, the etching gas in the processing chamber is extracted from the processing chamber, and the deposition gas flows into the processing chamber to form another sacrificial film 820, as... Figure 12As shown. The deposition is formed by ionization of multiple ions; these ions are accelerated toward the stacked first and second semiconductor elements 210, 310 to deposit a sacrificial film 820 on the photoresist mask 800, the remaining sacrificial spacers, and a portion of the substrate 322 exposed through the first groove 3222a. Due to the statistical distribution of free radical velocities in the plasma, the sacrificial film 820 is a contiguous film.

[0165] Please refer to Figure 13 and Figure 14 After the sacrificial membrane 820 was deposited, it was carried out again. Figure 10 and Figure 11 The etching step. The duration of this etching step, used to etch some portions of the sacrificial film 820 and the substrate 322, can be the same as that used to etch such... Figure 10 and Figure 11 The duration of the sacrificial film 810 and some portions of the thinned substrate 321 shown. More specifically, in Figure 13 In the middle, it is anisotropic etching, such as Figure 12 The sacrificial membrane 820 is shown to expose a portion of the substrate 322. Next, in Figure 14 In the process, the substrate 322 is etched via the remaining sacrificial film 822 to create another first recess 3222b in the substrate 322, the first recess 3222b being connected to the first recess 3222a.

[0166] After the first depression 3222b is formed, as Figure 15 As shown, it can be repeated. Figure 12 The deposition process involves using a sacrificial film 830 to cover a portion of the substrate 322 exposed by the first recess 3222b. For example... Figure 12 As shown, the process parameters for depositing sacrificial film 830 are approximately the same as those for depositing sacrificial film 820.

[0167] like Figure 16 As shown, the etching and deposition steps in the first cycle process are repeated sequentially on the stack of the first and second semiconductor elements 210, 310 until the substrate 322 is etched to a selected depth D1. Each repetition of the etching and deposition steps extends the trench downward to increase a chamber volume. In some embodiments, the first cycle process may produce four first recesses 3222a to 3222d.

[0168] After the first cycle process is completed, a second cycle process is performed to extend the trench and penetrate the substrate 322. The second cycle process includes a first deposition step, a second deposition step, and an etching step in sequence.

[0169] The initial stage of the second cycle process is illustrated in Figure 17 .like Figure 17 As shown, a first deposition step is performed to form a first sacrificial film 840 to at least cover a portion of the substrate 322 exposed through the first to fourth recesses 3222a to 3222d. The sacrificial film 840 located at the fourth recess 3222a and in contact with the substrate 322 may have a thickness Tx. It is worth noting that the process parameters for depositing the sacrificial film 840 may be substantially the same as those for depositing the sacrificial films 810 / 820.

[0170] Please refer to Figure 18 A second deposition step is performed to... Figure 17 The sacrificial film 840 shown is grown from thickness Tx to a desired thickness Ty, thereby forming another sacrificial film 850. The duration of the second deposition step may be the same as or different from the duration of the first cycle process.

[0171] After the second deposition step is completed, an etching step is performed to etch some portions of the sacrificial film 850 (e.g., Figure 19 (as shown) and some portions of the substrate 322 exposed by etching through the remaining sacrificial film 852 (as shown) Figure 20 As shown). Accordingly, a second recess 3224a is created. The second recess 3224a may have a second width W2, and the second width W2 is smaller than the first width W1 of the first recess 322a (e.g., as shown). Figure 11 (As shown). It is worth noting that the duration of the etching step in the second cycle process for etching substrate 322 is shorter than the duration of the etching step in the first cycle process for etching substrates 321 / 322. Furthermore, the duration of the etching process in the second cycle process for etching sacrificial film 850 and some portions of substrate 322 may be the same as the duration of the etching process in the first cycle process for etching sacrificial films 810 / 820 / 830 and substrates 321 / 322.

[0172] The etching step is complete, as follows: Figure 21 As shown, the first deposition step is repeated to deposit the same type of sacrificial material, thereby forming another sacrificial film 860 on at least a portion of the substrate 322 exposed by the second recess 3224a. Next, as... Figure 23 As shown, repeat the second deposition step (as shown). Figure 22 (As shown) and an etching step sequence to create another second groove 3224b, whereby the first deposition step is used to define an area etched into the substrate 322, and the etching step is used to remove the sacrificial film 870 and some portions of the substrate 322 formed during the second deposition step. Figure 24As shown, the first deposition step, the second deposition step, and the etching step are repeated in sequence to etch the substrate 322 until the isolation layer 340 of the second semiconductor element 310 is exposed. Accordingly, a trench 300 is formed. In some embodiments, the second cycle process may produce second recesses 3224a to 3224c in the substrate 322, and the second recesses 3224a to 3224c are interconnected. It is worth noting that the formation of the second recesses 3224a to 3224c can be performed in situ during the formation of the first recesses 3222a to 3222d.

[0173] like Figure 24 As shown, the selected depth D1 for forming the first recesses 3222a to 3222d is determined by the preset depth D2 for forming the second recesses 3224a to 3224c. Specifically, the trench 300 formed by the first recesses 3222a to 3222d and the second recesses 3224a to 3224c is used to form a conductive feature as described below; therefore, the preset depth D2 is designed to prevent the main component 330 from suffering severe performance degradation due to the conductive feature.

[0174] After the second cycle is completed, a cleaning process is performed to remove any remaining sacrificial film. For example, a wet cleaning process is used to clean the stack of the first and second semiconductor devices 210, 310. Figure 24 As shown, the undercut produced by the etching steps in the first and second cycle processes makes the trench 300 a steep-sided hole. That is, the inner surface of the substrate 322, which intersects with the trench 300, has a scalloped pattern. Typically, it is difficult to uniformly form a desired thin film on the inner wall of a substrate 322 with a scalloped pattern, limiting the yield and reliability of the semiconductor device. Therefore, as... Figure 25 As shown, a removal process can be performed to planarize (i.e., smooth) the inner wall of the substrate 322. In some embodiments, for example, the technique for fabricating the fan-shaped pattern includes a reactive ion etching (RIE) process. After the removal process, the inner surface of the substrate 322 may include three segments: a first vertical surface 3332, a second vertical surface 3334, and an inclined surface 3336, wherein the inclined surface 3336 is connected to the first vertical surface 3332 and the second vertical surface 3334.

[0175] Please refer to Figure 26 ,in accordance with Figure 3In step S716, a portion of the isolation layer 340 and a portion of the bonding layer 400 of the second semiconductor element 310 located below the trench 300 are sequentially removed to expose the conductive pad 250 of the first semiconductor element 210. This forms a hole 402. For example, at least one RIE process is used to anisotropically dry etch the isolation layer 340 and the bonding layer 400. It should be understood that the etching process can use various etchants, selected according to the materials of the isolation layer 340 and the bonding layer 400, to sequentially etch the isolation layer 340 and the bonding layer 400. In some embodiments, during the etching of some portions of the isolation layer 340 and the bonding layer 400, a significant amount of photoresist mask 800 may be consumed. The photoresist mask 800 is used to protect the passivation layer 452 from damage during the etching steps in the first and second cycle processes. Residue of the photoresist mask 800 can then be removed using, for example, an ashing process or a stripping process. The wet stripping process is used to chemically alter the photoresist mask 800 so that it no longer adheres to the passivation layer 452.

[0176] Please refer to Figure 27 ,in accordance with Figure 3 In step S718, an insulating film 520 is deposited in the opening 451, trench 300, and via 402. The insulating film 520 is a conformal layer having a configuration that follows the configuration of some exposed portions of the passivation layer 452, the substrate 322 of the second semiconductor element 310, the bonding layer 400, and the conductive pad 250 of the first semiconductor element 210. For example, the insulating film 520 comprises an oxide, nitride, oxynitride, or high-k material and can be deposited using a CVD process, an ALD process, or the like. In some embodiments, the insulating film 520 and the bonding layer 400 may comprise the same material, but this disclosure is not limited thereto.

[0177] Please refer to Figure 27 and Figure 28 ,in accordance with Figure 3 In step S720, a portion of the insulating film 520 is removed to expose the conductive pad 250. In step S720, an anisotropic etching process is used to remove the horizontal portion of the insulating film 520, while the vertical portion 522 of the insulating film 520 remains in situ, thereby forming at least one insulating pad. The chemical properties of the anisotropic etching process are selective for the material of the insulating film 520. Therefore, during the etching of the horizontal portion of the insulating film 520, a significant amount of passivation layer 452 material is not removed.

[0178] Please refer to Figure 29 ,in accordance with Figure 3In step S722, a diffusion barrier film 530 is deposited on the exposed portions of the conductive pad 250, passivation layer 452, and insulating liner 522. The diffusion barrier film 530, having a substantially uniform thickness, covers the conductive pad 250, passivation layer 452, and insulating liner 522. To ensure step coverage, for example, a PVD process or an ALD process can be used to form the diffusion barrier film 530. The diffusion barrier layer 530 can be a single-layer structure or a multilayer structure, comprising one or more refractory metals, refractory metal nitrides, or refractory metal silicon nitrides.

[0179] Please refer to Figure 30 ,in accordance with Figure 3 In step S724, a conductive material 510 is deposited to fill the openings 451, trenches 300, and pores 402. The conductive material 510 is conformally and uniformly deposited on the diffusion barrier film 530 until the openings 452, trenches 300, and pores 402 are completely filled. The diffusion barrier film 530 is used to prevent the conductive material 510 from flaking or spalling from the insulating pad 522. The conductive material 510 may include metals such as copper, tungsten, aluminum, silver, gold, indium, or the like. The insulating pad 522 is used to separate the conductive material 510 from the substrate 322, thereby preventing the conductive material 510 from diffusing into the substrate 320. The conductive material 510 can be deposited using a CVD process, a PVD process, an ALD process, or other suitable processes.

[0180] Next, a planarization process is performed to remove the conductive material 510 and diffusion barrier film 530 that overflowed from the openings 451, trenches 300, and openings 402. Finally, the fully formed... Figure 1 The semiconductor component 20 shown exposes a passivation layer 452 and forms as shown. Figure 1 The conductive feature 500 is shown. The planarization process may include a chemical mechanical polishing (CMP) process and / or a wet etching process.

[0181] In summary, the architecture of the semiconductor component 20 or semiconductor element 60 includes conductive components 500 / 630, which encompass first blocks 502 / 632 and second blocks 504 / 634. The first blocks 502 / 632 have a minimum critical size near the main component, and the second blocks 504 / 634 have a maximum critical size away from the main component. Therefore, the area utilization of the substrate 322 / 610 disposed on the conductive features 500 / 630 is increased.

[0182] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a conductive feature, an insulating pad, and a main component. The conductive feature is disposed in the substrate and includes a first block, a second block, and a third block. The first block has a uniform first critical size, and the second block has a uniform second critical size, the second critical size being larger than the first critical size. The third block is interposed between the first block and the second block and has a plurality of varying third critical sizes. The insulating pad covers a portion of the conductive feature; and the main component is disposed in the substrate and around the first block.

[0183] Another embodiment of this disclosure provides a semiconductor assembly. The semiconductor assembly includes a first semiconductor element, a second semiconductor element, a conductive feature, and an insulating pad. The first semiconductor element includes a conductive pad; and the second semiconductor element is vertically stacked on the first semiconductor element. The conductive feature passes through the second semiconductor element and includes a first block and a second block with different critical dimensions. The first block contacts the conductive pad and has a first critical dimension; and the second block is connected to the first block and has a second critical dimension larger than the first critical dimension. The insulating pad is interposed between the second semiconductor element and the conductive feature.

[0184] Another embodiment of this disclosure provides a method for fabricating a semiconductor component. The method includes bonding a first semiconductor element and a second semiconductor element together; performing a first cyclic process to create a plurality of first recesses in a substrate of the second semiconductor element, the first recesses being interconnected, wherein the first recesses have a first width; performing a second cyclic process to create a plurality of second recesses via the first recesses, the second recesses being interconnected, wherein the second recesses have a second width smaller than the first width; forming an insulating pad on portions of the substrate exposed via the first and second recesses; and depositing a conductive material in the first and second recesses coated with the insulating pad.

[0185] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0186] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One base; A conductive feature is disposed in the substrate and includes: A first block having a uniform first critical size; A second block having a uniform second critical size, the second critical size being larger than the first critical size; and A third block is inserted between the first block and the second block and has a plurality of varying third critical dimensions, wherein the third block has an inclined surrounding surface, and wherein the third critical dimensions of the third block gradually increase at positions with increasing distance from the first block and gradually decrease at positions with increasing distance from the second block. An insulating pad covers one or more of the conductive feature; and A main component is disposed in the base and around the first block.

2. The semiconductor device of claim 1, wherein the first block of the conductive feature has a first height, the second block of the conductive feature has a second height, the third block of the conductive feature has a third height, the second height is greater than the first height, and the third height is less than the first height.

3. A semiconductor component, comprising: A first semiconductor element, including a conductive pad; A second semiconductor element is vertically stacked on top of the first semiconductor element; A conductive feature, passing through the second semiconductor element, includes: A first block, in contact with the conductive pad and having a first critical dimension; as well as A second block, connected to the first block, and having a second critical size, the second critical size being larger than the first critical size; A third block, interposed between the first block and the second block, and having a plurality of varying third critical dimensions, wherein the third block has an inclined surrounding surface, and wherein the third critical dimensions of the third block gradually increase at positions with increasing distance from the first block and gradually decrease at positions with increasing distance from the second block; and An insulating pad is inserted between the second semiconductor element and the conductive feature.

4. The semiconductor component of claim 3, wherein the third critical dimension of the third block of the conductive feature gradually increases at positions with increasing distance from the first block and gradually decreases at positions with increasing distance from the second block.

5. The semiconductor assembly of claim 4, wherein the second semiconductor element comprises: One base; Multiple main components are disposed in the base and around the first block; as well as An isolation layer encapsulates the main components; A portion of the first block, the second block, and the third block of the conductive feature are located in the substrate, and another portion of the first block of the conductive feature passes through the isolation layer.

6. The semiconductor component of claim 5, wherein the first block of the conductive feature located in the substrate has a first height, the second block of the conductive feature has a second height, the third block of the conductive feature has a third height, and the second height is greater than the first height, and the third height is less than the first height.

7. The semiconductor component of claim 6, wherein the total of the first height and the third height is less than the second height.

8. The semiconductor component of claim 5 further includes a passivation layer covering the substrate, wherein a portion of the second block of the conductive feature is surrounded by the passivation layer.

9. The semiconductor assembly of claim 8, further comprising a bonding layer sandwiched between the first semiconductor element and the second semiconductor element, wherein the first block of the conductive feature passes through the bonding layer to contact the conductive pad.

10. A method for fabricating a semiconductor component, comprising: A first semiconductor element and a second semiconductor element are bonded together, wherein the first semiconductor element includes a conductive pad; A first cycle process is performed to generate a plurality of first recesses in a substrate of the second semiconductor device, the first recesses being interconnected, wherein the first recesses have a first width; A second cycle process is performed to generate a plurality of second recesses via the first recess, the second recesses being interconnected, wherein the second recesses have a second width that is smaller than the first width; An insulating pad is formed on some portions of the substrate exposed via the first and second recesses; A conductive material is deposited in the first and second recesses where the insulating pad is coated; as well as A removal process is performed on the substrate to remove a fan-shaped pattern generated during each etching step of the first cycle process and the second cycle process, thereby forming a trench through the substrate, the trench having a non-uniform width. The portion of the substrate exposed by the trench includes a first vertical surface, a second vertical surface, and an inclined surface, the inclined surface connecting the first vertical surface and the second vertical surface.

11. The preparation method of claim 10, wherein the first depression is generated by the first cycle process of alternating a deposition step and an etching step, and the second depression is generated by a sequence including a first deposition step, a second deposition step and an etching step.

12. The preparation method of claim 11, wherein the duration of the etching step for etching the substrate in the second cycle process is less than the duration of the etching step for etching the substrate in the first cycle process.

13. The preparation method of claim 11, wherein the etching step of the first cycle process comprises: Remove some horizontal portions of a sacrificial film formed during this deposition step; as well as Remove the portion of the substrate exposed by the remaining sacrificial membrane.

14. The preparation method according to claim 10, further comprising: A passivation layer is deposited on the second semiconductor device; as well as Before performing the first cycle process, an opening is created in the passivation layer; The substrate is etched through the opening to create the first and second recesses.

15. The preparation method of claim 10, wherein the bonding of the first semiconductor element and the second semiconductor element comprises: Multiple dielectric films are deposited on the first semiconductor element and the second semiconductor element, respectively; The second semiconductor element is mounted onto the first semiconductor element so that the dielectric film contacts it. as well as An annealing process is performed to melt the dielectric film, thereby forming a bonding layer for connecting the first and second semiconductor elements; Specifically, before forming the insulating liner, a portion of the bonding layer beneath the first and second recesses is removed to expose the conductive pad.

16. The fabrication method of claim 10, wherein the first cycle process is performed until the substrate is etched to a selected depth, and the second cycle process is completed once the connected first and second recesses have passed through the substrate, wherein the second recess has a preset depth, the preset depth being less than the selected depth.

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