Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The semiconductor structure includes: a substrate; a gate structure located on the substrate; source / drain doped layers located within the substrate on both sides of the gate structure; an interlayer dielectric layer located on the exposed substrate of the gate structure, the interlayer dielectric layer covering the source / drain doped layers; a contact hole penetrating the interlayer dielectric layers on both sides of the gate structure, the bottom of the contact hole exposing the source / drain doped layers; a bottom source / drain plug located in the contact hole and electrically connected to the source / drain doped layers; a sidewall layer located between the sidewall of the bottom source / drain plug and the sidewall of the contact hole, the top of the sidewall layer being lower than the top of the bottom source / drain plug, the interlayer dielectric layer, the sidewall layer, and the bottom source / drain plug forming an opening; and a sealing layer covering the top of the bottom source / drain plug, the sidewall of the bottom source / drain plug exposed in the opening, and the top of the opening. Acidic solutions are less likely to penetrate into the sealing layer and affect the bottom source / drain plug, reducing the probability of forming pores in the bottom source / drain plug, thereby improving the structural performance of the semiconductor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; source / drain doped layers located within the substrate on both sides of the gate structure; an interlayer dielectric layer located on the exposed substrate of the gate structure, the interlayer dielectric layer covering the source / drain doped layers; a contact hole penetrating the interlayer dielectric layers on both sides of the gate structure, the bottom of the contact hole exposing the source / drain doped layers; a bottom source / drain plug located in the contact hole and electrically connected to the source / drain doped layers; a sidewall layer located between the sidewall of the bottom source / drain plug and the sidewall of the contact hole, the top of the sidewall layer being lower than the top of the bottom source / drain plug, the interlayer dielectric layer, the sidewall layer, and the bottom source / drain plug forming an opening; and a sealing layer covering the top of the bottom source / drain plug, the sidewall of the bottom source / drain plug exposed by the opening, and the top of the opening.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, an interlayer dielectric layer is formed on the exposed substrate of the gate structure, the interlayer dielectric layer covering the source and drain doped layers; etching the interlayer dielectric layer on both sides of the gate structure to form contact holes exposing the source and drain doped layers in the interlayer dielectric layer; forming a sidewall layer on the sidewall of the contact holes; forming a bottom source and drain plug in the contact holes after forming the sidewall layer; etching the sidewall layer to form an opening surrounded by the interlayer dielectric layer, the sidewall layer and the bottom source and drain plug; and forming a sealing layer at the bottom of the opening, the top of the bottom source and drain plug and the sidewall of the bottom source and drain plug exposed by the opening.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a semiconductor structure in which a sidewall layer is provided between the sidewall of a bottom source / drain plug and the sidewall of a contact hole. The top of the sidewall layer is lower than the top of the bottom source / drain plug. The interlayer dielectric layer, the sidewall layer, and the bottom source / drain plug form an opening. A sealing layer covers the top of the bottom source / drain plug, the sidewall of the bottom source / drain plug exposed by the opening, and the top of the opening. Therefore, compared with a solution that only provides a planar sealing layer on the top of the bottom source / drain plug, when the sealing layer on the top of the bottom source / drain plug is subsequently removed to expose the top of the bottom source / drain plug, the sealing layer located on the sidewall of the bottom source / drain plug protects its sidewall, thereby reducing the probability of damage to the bottom source / drain plug via its sidewall (e.g., etching solution is less likely to contact the bottom source / drain plug via the interface between the sealing layer and the sidewall of the contact hole). Correspondingly, the probability of forming pore defects in the bottom source / drain plug is reduced, thereby improving the structural performance of the semiconductor.

[0009] This invention provides a method for forming a semiconductor structure. After forming a contact hole exposing the source / drain doped layer in an interlayer dielectric layer, before forming a bottom source / drain plug in the contact hole, a sidewall layer is formed on the sidewall of the contact hole. After forming the bottom source / drain plug, the sidewall layer is etched to form an opening surrounded by the interlayer dielectric layer, the sidewall layer, and the bottom source / drain plug. Then, a sealing layer is formed at the bottom of the opening, the top of the bottom source / drain plug, and the sidewall of the bottom source / drain plug exposed by the opening. This invention, through the formation of an opening and the formation of a sealing layer on the top and sidewalls of the bottom source / drain plug, as well as at the bottom of the opening, covering the sidewalls of the bottom source / drain plug, provides a protective effect on the sidewalls of the bottom source / drain plug during subsequent removal of the sealing layer from the top of the plug. This reduces the probability of damage to the bottom source / drain plug via its sidewalls (e.g., etching solution is less likely to contact the plug via the interface between the sealing layer and the contact hole sidewalls). Consequently, it reduces the probability of forming pore defects in the bottom source / drain plug, thereby improving the structural performance of the semiconductor. Attached Figure Description

[0010] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figures 4 to 13 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0012] Figures 14 to 15 This is a schematic diagram of the structure corresponding to the second embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one method for forming a semiconductor structure as an example. Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1The substrate is provided, including a substrate 10 and a fin 11 protruding from the substrate 10. A gate structure 12 is formed on the substrate 10 across the fin 11. The gate structure 12 covers a portion of the top and a portion of the sidewalls of the fin 11. A gate cap layer 14 is formed on the top of the gate structure 12. Sidewalls 13 are formed on the sidewalls of the gate structure 12. Source and drain doped layers 16 are formed in the substrate on both sides of the gate structure 12. An interlayer dielectric layer 15 is formed on the substrate exposed by the gate structure 12. Contact holes 20 are formed in the interlayer dielectric layer 15 between the gate structures 12 to expose the source and drain doped layers 16.

[0015] refer to Figure 2 A bottom source / drain plug 17 is formed on top of the source / drain doped layer 16, and the top of the bottom source / drain plug 17 is lower than the top of the interlayer dielectric layer 15.

[0016] refer to Figure 3 A sealing layer 18 is formed on the bottom source drain plug 17, and the sealing layer 18 covers the sidewall of the interlayer medium layer 15.

[0017] Research has revealed that during the formation of the sealing layer 18 on top of the bottom source / drain plug 17, it is difficult to ensure a complete seal between the sidewall of the sealing layer 18 and the sidewall of the contact hole 20. In other words, it is difficult to guarantee that the sealing layer 18 can completely seal the bottom source / drain plug 17, and gaps are easily formed between the sealing layer 18 and the sidewall of the contact hole 20 (e.g., Figure 3 As shown in the dashed box, during the subsequent process of forming the top source / drain plug on the top of the bottom source / drain plug 17, acidic solution can easily penetrate into the bottom source / drain plug 17 through the gap, thereby increasing the probability of damage to the bottom source / drain plug 17. For example, it increases the probability of forming void defects in the bottom source / drain plug 17, which can easily lead to a decrease in the performance of the semiconductor structure.

[0018] To address the aforementioned technical problem, embodiments of the present invention provide a method for fabricating a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, source / drain doped layers are formed in the substrate on both sides of the gate structure, and an interlayer dielectric layer is formed on the exposed substrate of the gate structure, the interlayer dielectric layer covering the source / drain doped layers; etching the interlayer dielectric layers on both sides of the gate structure to form contact holes exposing the source / drain doped layers in the interlayer dielectric layers; forming a sidewall layer on the sidewall of the contact holes; forming a bottom source / drain plug in the contact holes after forming the sidewall layer; etching the sidewall layer to form an opening surrounded by the interlayer dielectric layer, the sidewall layer, and the bottom source / drain plug; and forming a sealing layer at the bottom of the opening, the top of the bottom source / drain plug, and the sidewall of the bottom source / drain plug exposed by the opening.

[0019] In the embodiment of the present invention, after forming a contact hole exposing the source / drain doped layer in the interlayer dielectric layer, before forming the bottom source / drain plug in the contact hole, a sidewall layer is formed on the sidewall of the contact hole, and after forming the bottom source / drain plug, the sidewall layer is etched to form an opening surrounded by the interlayer dielectric layer, the sidewall layer and the bottom source / drain plug, and then a sealing layer is formed at the bottom of the opening, the top of the bottom source / drain plug and the sidewall of the bottom source / drain plug exposed by the opening. This invention, through the formation of an opening and the formation of a sealing layer on the top and sidewalls of the bottom source / drain plug, as well as at the bottom of the opening, covering the sidewalls of the bottom source / drain plug, provides a protective effect on the sidewalls of the bottom source / drain plug during subsequent removal of the sealing layer from the top of the plug. This reduces the probability of damage to the bottom source / drain plug via its sidewalls (e.g., etching solution is less likely to contact the plug via the interface between the sealing layer and the contact hole sidewalls). Consequently, it reduces the probability of forming pore defects in the bottom source / drain plug, thereby improving the structural performance of the semiconductor.

[0020] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figures 4 to 12 A schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0022] refer to Figure 4 A substrate is provided, on which a gate structure 102 is formed. Source and drain doped layers 106 are formed in the substrate on both sides of the gate structure 102. An interlayer dielectric layer 105 is formed on the exposed substrate of the gate structure 102, and the interlayer dielectric layer 105 covers the source and drain doped layers 106.

[0023] The substrate is used to provide a process platform for subsequent process manufacturing.

[0024] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0025] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, which is silicon.

[0026] In this embodiment, when the device is in operation, the gate structure 102 is used to control the opening or closing of the conductive channel.

[0027] In this embodiment, the gate structure 102 is located on the substrate 100, and the gate structure 102 spans the fin 101 and covers part of the top and part of the sidewall of the fin 101.

[0028] In this embodiment, the gate structure 102 is a metal gate structure, which includes a high-k gate dielectric layer 1021, a work function layer 1023 on the high-k gate dielectric layer 1021, and a gate electrode layer 1022 on the work function layer 1023.

[0029] The high-k gate dielectric layer 1021 is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 1021 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0030] The work function layer 1023 is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer 1022 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer 1022 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0031] The gate electrode layer 1022 is used to bring out the electrical properties of the gate structure 102. In this embodiment, the material of the gate electrode layer 105 is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0032] In this embodiment, a gate cap layer 104 is formed on the top of the gate structure 102.

[0033] When a bottom source / drain plug is subsequently formed on top of the source / drain doped layer 106, the gate cap layer 104 is used to protect the top of the gate structure 102 from damage. Furthermore, forming a top source / drain plug on the bottom source / drain plug helps to reduce the probability of a short circuit between the top source / drain plug and the gate structure 102.

[0034] In this embodiment, the material of the gate cap layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0035] In this embodiment, the source / drain doped layer 106 is located in the fins 101 on both sides of the gate structure 102.

[0036] When the semiconductor structure is in operation, the source / drain doped layer 106 provides stress to the channel below the gate structure 102, thereby increasing the carrier migration rate.

[0037] Specifically, adjacent gate structures 102 share a source / drain doped layer 106.

[0038] When forming an NMOS transistor, the source / drain doped layer 106 includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the source / drain doped layer 106 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0039] Continue to refer to Figure 4 In this embodiment, a sidewall 103 is also formed on the sidewall of the gate structure 102.

[0040] Sidewall 103 defines the formation region of source / drain doped layer 106 and also protects the sidewalls of gate structure 102. Sidewall 103 can be a single-layer structure or a multilayer structure, and the material of sidewall 103 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, sidewall 103 is a single-layer structure, and the material of sidewall 103 is silicon oxide.

[0041] The interlayer dielectric layer 105 is used to isolate adjacent devices.

[0042] The interlayer dielectric layer 105 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the interlayer dielectric layer 105 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 105.

[0043] refer to Figure 5The interlayer dielectric layer 105 on both sides of the gate structure 102 is etched to form a contact hole 135 in the interlayer dielectric layer 105 that exposes the source and drain doped layer 106.

[0044] The contact hole 135 provides space for the subsequent formation of the sidewall layer and source / drain plug.

[0045] In this embodiment, the interlayer dielectric layer 105 on both sides of the gate structure 102 is etched using a dry etching process.

[0046] As an example, the sidewall of the contact hole 135 exposes the interlayer dielectric layer 105. In other embodiments, the sidewall of the contact hole may also expose the sidewall.

[0047] refer to Figures 6 to 7 A sidewall layer 131 is formed on the sidewall of the contact hole 135.

[0048] Subsequently, the sidewall layer 131 is etched to form an opening surrounded by the interlayer dielectric layer 105, the sidewall layer 131, and the bottom source / drain plug.

[0049] The sidewall layer 131 is subsequently etched to form an opening surrounded by the interlayer dielectric layer 105, the sidewall layer 131, and the bottom source / drain plug. Therefore, by forming the opening through the sidewall layer 131, the linewidth of the opening can be adjusted to meet the process requirements by adjusting the thickness of the sidewall layer 131, thus providing greater process flexibility.

[0050] In this embodiment, the step of forming the sidewall layer 131 includes: as follows Figure 6 As shown, a padding material layer 107 is formed on the top of the interlayer dielectric layer 105, and on the sidewalls and bottom of the contact hole 135; as Figure 7 As shown, the padding material layer 107 located at the top of the interlayer dielectric layer 105 and at the bottom of the contact hole 135 is removed, and the remaining padding material layer 107 on the sidewall of the contact hole 135 is retained as the sidewall layer 131.

[0051] In this embodiment, by first removing the pad material layer 107 located at the bottom of the contact hole 135, the sidewall layer 131 is exposed to the source / drain doped layer 106, thereby preparing for the subsequent formation of the bottom source / drain plug that electrically connects to the source / drain doped layer 106.

[0052] In this embodiment, the process for forming the sidewall layer 131 includes atomic layer deposition.

[0053] Specifically, the padding material layer 107 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the padding material layer 107, enabling it to conformally cover the top and sidewalls of the interlayer dielectric layer 105, as well as the bottom of the contact hole 135. Furthermore, ALD offers good gap-filling performance and step coverage, correspondingly enhancing the conformal coverage capability of the padding material layer 107. In other embodiments, the padding material layer can also be formed using chemical vapor deposition (CVD).

[0054] In this embodiment, a dry etching process is used to remove the top of the interlayer dielectric layer 105 and the pad material layer 107 located at the bottom of the contact hole 135.

[0055] It should be noted that the thickness of the sidewall layer 131 should not be too large or too small. If the thickness of the sidewall layer 131 is too large, it will easily occupy too much space for the subsequent formation of the bottom source / drain plug; if the thickness of the sidewall layer 131 is too small, it will easily lead to an excessively small opening, and correspondingly, an excessively small thickness of the sealing layer formed within the opening. This results in an excessively small thickness of the sealing layer subsequently formed on the sidewall of the bottom source / drain plug, making it easier for the etching solution to contact the bottom source / drain plug through the interface between the sealing layer and the sidewall of the interlayer dielectric layer 105, increasing the probability of forming pore defects in the bottom source / drain plug, thereby reducing the performance of the semiconductor. Therefore, in this embodiment, the thickness of the sidewall layer 131 is 2 nanometers to 4 nanometers along the direction perpendicular to the sidewall of the contact hole 135. For example, the thickness of the sidewall layer 131 is 2.5 nanometers, 3 nanometers, or 3.5 nanometers.

[0056] In this embodiment, the material of the sidewall layer 131 includes amorphous silicon or silicon nitride.

[0057] It should be noted that, in the subsequent process of removing the sidewall layer using a wet etching process, under the same etching selectivity ratio between the sidewall layer 131 and the bottom source / drain plug, the amorphous silicon or silicon nitride is removed at a faster rate, thereby improving the efficiency of the process and reducing the process cost.

[0058] Continue to refer to Figure 7 It should be noted that after the sidewall layer 131 is formed on the sidewall of the contact hole 135, a barrier adhesion layer 109 is formed on the sidewall of the sidewall layer 131.

[0059] The barrier adhesion layer 109 reduces the probability of metal ions in the bottom source / drain plug 108 diffusing to other layers and increases the adhesion between the bottom source / drain plug 108 and the sidewall layer 131 during the subsequent formation of the bottom source / drain plug 108.

[0060] In this embodiment, the material of the barrier adhesion layer 109 includes one or both of Ti and TiN.

[0061] In this embodiment, the barrier adhesion layer 109 is formed by a deposition process. In the step of forming the barrier adhesion layer 109, the barrier adhesion layer 109 conformally covers the bottom of the contact hole 135, the sidewall of the sidewall layer 131, and the top of the interlayer dielectric layer 105 and the gate structure 102.

[0062] In this embodiment, after forming the barrier adhesion layer 109, the method further includes: removing the barrier adhesion layer 109 located at the bottom of the contact hole 135 and the top of the interlayer dielectric layer 105 and the gate structure 102, thereby exposing the source / drain doped layer 106. Correspondingly, after forming the bottom source / drain plug in the contact hole 135, the bottom source / drain plug is in direct contact with the source / drain doped layer 106, thereby improving the electrical connection effect between the bottom source / drain plug and the source / drain doped layer 106.

[0063] It should be noted that in other embodiments, the barrier adhesion layer may not be etched, and the barrier adhesion layer located on top of the interlayer dielectric layer and the gate structure may be removed during the subsequent formation of the bottom source / drain plug in the contact hole.

[0064] refer to Figure 8 After the sidewall layer 131 is formed, a bottom source drain plug 108 is formed in the contact hole 135.

[0065] In this embodiment, the bottom source / drain plug 108 is in contact with the source / drain doped layer 106 to enable electrical connection between the source / drain doped layer 106 and external circuits or other interconnection structures.

[0066] Specifically, the steps of forming the bottom source / drain plug 108 include: filling the contact hole 135 with a conductive material, the conductive material covering the barrier adhesion layer 109; performing a planarization treatment on the conductive material (e.g., chemical mechanical polishing) to remove the conductive material above the top of the gate cap layer 104, and using the remaining conductive material in the contact hole 135 as the bottom source / drain plug 108.

[0067] During the planarization process of the conductive material, the interlayer dielectric layer 105 and the barrier adhesion layer 109 above the top of the gate cap layer 104 are also removed.

[0068] Specifically, the material of the bottom source / drain plug 108 includes one or more of Cu, Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the bottom source / drain plug 108 includes Co. Co has stable chemical properties, mature formation process, and simple operation, which helps to reduce the process difficulty of semiconductor structures and improve the formation efficiency of semiconductor structures.

[0069] refer to Figure 10 The sidewall layer 131 is etched to form an opening 110 surrounded by the interlayer dielectric layer 105, the sidewall layer 131 and the bottom source / drain plug 108.

[0070] The opening 110 provides space for the subsequent formation of the sealing layer. The opening 110 exposes a portion of the sidewall of the bottom source / drain plug 108, thereby allowing the sealing layer to cover the sidewall of the bottom source / drain plug 108.

[0071] In this embodiment, the step of forming the opening 110 includes: etching the sidewall layer 131 using a wet etching process.

[0072] It should be noted that, compared with the dry etching process, the wet etching process causes less damage to the bottom source / drain plug 108 during the etching of the sidewall layer 131.

[0073] In this embodiment, only the sidewall layer 131 is etched during the formation of the opening 110.

[0074] In other embodiments, during the etching of the sidewall layer, the barrier adhesion layer is also etched. Accordingly, the opening is surrounded by the interlayer dielectric layer, the sidewall layer, the barrier adhesion layer, and the bottom source / drain plug, thereby increasing the space of the opening to facilitate the subsequent formation of a sealing layer.

[0075] In this embodiment, during the step of forming the opening 110, the etching selectivity ratio between the sidewall layer 131 and the bottom source / drain plug 108 is greater than 2:1, thereby reducing damage to the bottom source / drain plug 108.

[0076] Specifically, the etching selectivity ratio refers to the relative etching rate between the sidewall layer 131 and the bottom source / drain plug 108 under the same etching process conditions. In this embodiment, during the wet etching of the sidewall layer 131, only a portion of the sidewall layer 131 needs to be etched away, and the bottom source / drain plug 108 needs to be retained. Therefore, in this embodiment, the etching selectivity ratio between the sidewall layer 131 and the bottom source / drain plug 108 is greater than 2:1.

[0077] Continue to refer to Figure 9In this embodiment, before forming the opening 110, the method further includes: back etching the bottom source drain plug 108 and the sidewall layer 131 so that the top of the remaining bottom source drain plug 108 and the sidewall layer 131 is lower than the top of the contact hole 135.

[0078] Specifically, by making the top of the remaining bottom source drain plug 108 and the sidewall layer 131 lower than the top of the contact hole 135, space is provided for the subsequent formation of a top source drain plug on top of the bottom source drain plug 108.

[0079] In this embodiment, a dry etching process is used to etch back a portion of the thickness of the bottom source / drain plug 108 and the sidewall layer 131, which makes it easier to control the amount of etching and helps to improve the flatness of the top surface of the remaining bottom source / drain plug 108 and the sidewall layer 131.

[0080] refer to Figure 11 A sealing layer 111 is formed at the bottom of the opening 110, the top of the bottom source drain plug 108, and the sidewall of the bottom source drain plug 108 exposed by the opening 110.

[0081] The sealing layer 111 protects the sidewalls of the bottom source / drain plug 108, thereby reducing the probability that the etching solution will come into contact with the bottom source / drain plug 108 through the interface between the sealing layer 111 and the sidewalls of the interlayer dielectric layer 105. Consequently, it reduces the probability of forming pore defects in the bottom source / drain plug 108, thereby improving the structural performance of the semiconductor.

[0082] By forming a sealing layer 111 on the top and sidewalls of the bottom source / drain plug 108 and at the bottom of the opening 110, the sealing layer 111 covers the sidewalls of the bottom source / drain plug 108. Therefore, compared to a solution where a sealing layer with a planar structure is formed only on the top of the bottom source / drain plug 108, when the sealing layer 111 on the top of the bottom source / drain plug 108 is subsequently removed to expose the top of the bottom source / drain plug 108, the sealing layer 111 located on the sidewalls of the bottom source / drain plug 108 protects its sidewalls, thereby reducing the probability of damage to the bottom source / drain plug 108 via its sidewalls (e.g., the etching solution is less likely to come into contact with the bottom source / drain plug 108 via the interface between the sealing layer 111 and the sidewalls of the interlayer dielectric layer 105). Consequently, the probability of forming pore defects in the bottom source / drain plug 108 is reduced, thereby improving the structural performance of the semiconductor.

[0083] In this embodiment, during the step of forming the sealing layer 111, the top of the sealing layer 111 is lower than the top of the contact hole 135.

[0084] The top of the sealing layer 111 is lower than the top of the contact hole 135, thereby providing space for the subsequent formation of a top source drain plug on top of the bottom source drain plug 108.

[0085] It should be noted that the step of forming the sealing layer 111 includes: forming a sealing material layer (not shown) covering the bottom source drain plug 108 in the contact hole 135, the sealing material layer also filling the opening 110; etching back a portion of the thickness of the sealing material layer, the remaining sealing material layer serving as the sealing layer 111.

[0086] In this embodiment, the sealing material layer is formed using a chemical vapor deposition process.

[0087] In this embodiment, a dry etching process is used to etch back a portion of the thickness of the sealing material layer.

[0088] It should be noted that the thickness of the sealing layer 111 located on top of the bottom source / drain plug 108 should not be too large or too small. If the thickness of the sealing layer 111 on top of the bottom source / drain plug 108 is too large, it will easily occupy too much space for the subsequent formation of the top source / drain plug, thus affecting the performance of the semiconductor. If the thickness of the sealing layer 111 on top of the bottom source / drain plug 108 is too small, the etching solution will easily come into contact with the bottom source / drain plug 108 through the interface between the sealing layer 111 and the sidewall of the interlayer dielectric layer 105, increasing the probability of forming pore defects in the bottom source / drain plug 108, thereby reducing the performance of the semiconductor. Therefore, in this embodiment, the thickness of the sealing layer 111 located on top of the bottom source / drain plug 108 is 1.5 nanometers to 4 nanometers.

[0089] In this embodiment, the material of the sealing layer 111 includes one or two of titanium nitride, titanium, tantalum nitride, and tantalum.

[0090] It should be noted that the titanium nitride, titanium, tantalum nitride, and tantalum are all insoluble in water and are not easily corroded by acidic or alkaline solutions.

[0091] refer to Figures 12 to 13 After forming the sealing layer 111, the forming method further includes: removing the sealing layer 111 from the top of the bottom source drain plug 108 to expose the top of the bottom source drain plug 108; and forming a top source drain plug 113 on the exposed top of the bottom source drain plug 108.

[0092] The top source / drain plug 113 and the bottom source / drain plug 108 constitute a source / drain plug, thereby enabling the bottom source / drain plug 108 to be electrically connected to other interconnect structures or external circuits.

[0093] In this embodiment, an anisotropic dry etching process is used to remove the sealing layer 111 on top of the bottom source / drain plug 108. The dry etching process has anisotropic etching characteristics, good control over the etching profile, and is beneficial to improving the removal efficiency of the sealing layer 111.

[0094] It should be noted that after the sealing layer 111 on the top of the bottom source / drain plug 108 is removed by an anisotropic dry etching process, a wet cleaning step will be performed immediately afterward, in which an acidic solution will be used.

[0095] Specifically, the step of forming the top source / drain plug 113 includes: filling the top of the exposed bottom source / drain plug 108 with a conductive material layer (not shown), the conductive material layer also covering the top of the interlayer dielectric layer 105 and the gate cap layer 104; using the top of the interlayer dielectric layer 105 as the stop position, planarizing the conductive material layer, and the remaining conductive material layer on the top of the bottom source / drain plug 108 serves as the top source / drain plug 113.

[0096] The specific description of the top source drain plug 113 will not be repeated here in this embodiment.

[0097] refer to Figures 14 to 15 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention.

[0098] The similarities between the embodiments of the present invention and the first embodiment will not be repeated here. The differences between the embodiments of the present invention and the first embodiment are as follows:

[0099] refer to Figure 14 In this embodiment, the step of forming a sidewall layer 209 on the sidewall of the contact hole 235 includes: forming a barrier adhesion layer on the sidewall of the contact hole 235, the barrier adhesion layer serving as the sidewall layer 209.

[0100] By using a barrier adhesion layer to form the sidewall layer 209, the formation method eliminates the need to form an additional film layer to create the opening, thus simplifying the process steps.

[0101] During the subsequent formation of the bottom source / drain plug, the sidewall layer 209 reduces the probability of metal ions in the bottom source / drain plug diffusing to other layers and increases the adhesion between the bottom source / drain plug and the interlayer dielectric layer 205.

[0102] The material of the sidewall layer 209 includes one or both of Ti and TiN.

[0103] In this embodiment, the process for forming the sidewall layer 209 includes atomic layer deposition.

[0104] Accordingly, in this embodiment, after the barrier adhesion layer is formed, the barrier adhesion layer conformally covers the bottom and sidewall of the contact hole 235 and the top of the interlayer medium layer 205, wherein the barrier adhesion layer located on the sidewall of the contact hole 235 serves as the sidewall layer 209.

[0105] Accordingly, forming the barrier adhesion layer further includes: removing the barrier adhesion layer located at the bottom of the contact hole 235 and the top of the interlayer medium layer, and retaining the sidewall layer 209 located on the sidewall of the contact hole 235.

[0106] refer to Figure 15 In this embodiment, after forming the sidewall layer 209, the method further includes: forming a bottom source / drain plug 208 within the contact hole 235; etching the sidewall layer 209 to form an opening surrounded by the interlayer dielectric layer 205, the sidewall layer 209, and the bottom source / drain plug 208; forming a sealing layer 207 at the bottom of the opening, the top of the bottom source / drain plug 208, and the sidewall of the bottom source / drain plug 208 exposed by the opening; removing the sealing layer 207 from the top of the bottom source / drain plug 208 to expose the top of the bottom source / drain plug 208; and forming a top source / drain plug on the exposed top of the bottom source / drain plug 208.

[0107] The steps following the formation of the sidewall layer 209 are the same as those in the first embodiment, and will not be repeated here.

[0108] The similarities between the embodiments of the present invention and the first embodiment will not be repeated here.

[0109] Accordingly, embodiments of the present invention also provide a semiconductor structure. (See reference...) Figure 13 The diagram shows a schematic diagram of the first embodiment of the semiconductor structure of the present invention.

[0110] The semiconductor structure includes: a substrate; a gate structure 102 located on the substrate; source / drain doped layers 106 located within the substrate on both sides of the gate structure 102; an interlayer dielectric layer 105 located on the exposed substrate of the gate structure 102, the interlayer dielectric layer 105 covering the source / drain doped layers 106; a contact hole 135 penetrating the interlayer dielectric layer 105 on both sides of the gate structure 102, the bottom of the contact hole 135 exposing the source / drain doped layers 106; and a bottom source / drain plug 108 located within the contact hole 106. 35 is electrically connected to the source / drain doped layer 106; a sidewall layer 131 is located between the sidewall of the bottom source / drain plug 108 and the sidewall of the contact hole 135, the top of the sidewall layer 131 is lower than the top of the bottom source / drain plug 108, and the interlayer dielectric layer 105, the sidewall layer 131 and the bottom source / drain plug 108 form an opening; a sealing layer 111 covers the top of the bottom source / drain plug 108, the sidewall of the bottom source / drain plug 108 exposed by the opening 110, and the top of the opening 110.

[0111] The sealing layer 111 covers the top of the bottom source / drain plug 108, the sidewall of the bottom source / drain plug 108 exposed by the opening 110, and the top of the opening 110. Therefore, compared with the scheme of providing a sealing layer with a planar structure only on the top of the bottom source / drain plug 108, when the sealing layer 111 on the top of the bottom source / drain plug 108 is subsequently removed to expose the top of the bottom source / drain plug 108, the sealing layer 111 located on the sidewall of the bottom source / drain plug 108 protects its sidewall, thereby reducing the probability of damage to the bottom source / drain plug 108 via the sidewall of the bottom source / drain plug 108 (e.g., the etching solution is less likely to come into contact with the bottom source / drain plug 108 via the interface between the sealing layer 111 and the sidewall of the interlayer dielectric layer 105). Correspondingly, the probability of forming pore defects in the bottom source / drain plug 108 is reduced, thereby improving the structural performance of the semiconductor.

[0112] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0113] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, which is silicon.

[0114] In this embodiment, when the device is in operation, the gate structure 102 is used to control the opening or closing of the conductive channel.

[0115] In this embodiment, the gate structure 102 is located on the substrate 100, and the gate structure 102 spans the fin 101 and covers part of the top and part of the sidewall of the fin 101.

[0116] In this embodiment, the gate structure 102 is a metal gate structure, which includes a high-k gate dielectric layer 1021, a work function layer 1023 on the high-k gate dielectric layer 1021, and a gate electrode layer 1022 on the work function layer 1023.

[0117] It should be noted that the semiconductor structure further includes a gate cap layer 104, located on top of the gate structure 102. The gate cap layer 104 is used to protect the top of the gate structure 102 from damage.

[0118] In this embodiment, the material of the gate cap layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0119] In this embodiment, the source / drain doped layer 106 is located in the substrate on both sides of the gate structure 102.

[0120] When the semiconductor structure is operating, the source / drain doped layer 106 provides stress to the channel beneath the gate structure 102, thereby improving the carrier mobility. Specifically, adjacent gate structures 102 share a single source / drain doped layer 106. When the semiconductor structure is an NMOS transistor, the source / drain doped layer 106 includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC, and it provides tensile stress to the channel region of the NMOS transistor, thus improving the carrier mobility. The N-type ions are P-ions, As-ions, or Sb-ions. When the conductor structure is a PMOS transistor, the source / drain doped layer 106 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe, and it provides compressive stress to the channel region of the PMOS transistor, thus improving the carrier mobility. The P-type ions are B-ions, Ga-ions, or In-ions.

[0121] The semiconductor structure further includes a sidewall 103 located on the sidewall of the gate structure 102.

[0122] The sidewall 103 defines the formation region of the source / drain doped layer 106 and also protects the sidewalls of the gate structure 102. The sidewall 103 can be a single-layer structure or a multilayer structure, and the material of the sidewall 103 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 103 is a single-layer structure, and the material of the sidewall 103 is silicon oxide.

[0123] In this embodiment, the interlayer dielectric layer 105 is located on the exposed substrate of the gate structure 102, and the interlayer dielectric layer 105 covers the source and drain doped layer 106.

[0124] The interlayer dielectric layer 105 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the interlayer dielectric layer 105 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 105.

[0125] In this embodiment, the contact hole 135 penetrates the interlayer dielectric layer 105 on both sides of the gate structure 102, and the bottom of the contact hole 135 exposes the source / drain doped layer 106.

[0126] The contact hole 135 provides space for the formation of the sidewall layer 131 and the bottom source / drain plug 108.

[0127] In this embodiment, the bottom source / drain plug 108 is located in the contact hole 135 and electrically connected to the source / drain doped layer 106. The bottom source / drain plug 108 contacts the source / drain doped layer 106, enabling electrical connection between the source / drain doped layer 106 and external circuits or other interconnect structures. Specifically, the material of the bottom source / drain plug 108 includes one or more of Cu, Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the bottom source / drain plug 108 includes Co. Co has stable chemical properties, a mature formation process, and is simple to operate, which helps to reduce the process difficulty of semiconductor structures and improve the formation efficiency of semiconductor structures.

[0128] In this embodiment, the top of the bottom source / drain plug 108 is lower than the top of the contact hole 135. The fact that the top of the bottom source / drain plug 108 is lower than the top of the contact hole 135 provides space for forming a top source / drain plug on the top of the bottom source / drain plug 108.

[0129] In this embodiment, the sidewall layer 131 is located between the sidewall of the bottom source / drain plug 108 and the sidewall of the contact hole 135. The top of the sidewall layer 131 is lower than the top of the bottom source / drain plug 108. The interlayer dielectric layer 105, the sidewall layer 131 and the bottom source / drain plug 108 form an opening 110.

[0130] The opening 110 can be formed by the sidewall layer 131.

[0131] The opening 110 provides space for the formation of the sealing layer 111. The opening 110 exposes a portion of the sidewall of the bottom source / drain plug 108, thereby allowing the sealing layer 111 to cover the sidewall of the bottom source / drain plug 108.

[0132] It should be noted that the thickness of the sidewall layer 131 should not be too large or too small. If the thickness of the sidewall layer 131 is too large, it will easily occupy too much space for forming the bottom source / drain plug 108; if the thickness of the sidewall layer 131 is too small, the linewidth of the opening will easily be too small, which will correspondingly lead to the thickness of the sealing layer 111 formed in the opening being too small. Consequently, the thickness of the sealing layer 111 located on the sidewall of the bottom source / drain plug will be too small, and the etching solution will easily come into contact with the bottom source / drain plug 108 through the interface between the sealing layer 111 and the sidewall of the interlayer dielectric layer 105, increasing the probability of forming pore defects in the bottom source / drain plug 108, thereby reducing the performance of the semiconductor. Therefore, in this embodiment, the thickness of the sidewall layer 131 along the direction perpendicular to the sidewall of the contact hole 135 is 2 nanometers to 4 nanometers.

[0133] In this embodiment, the material of the sidewall layer 131 includes amorphous silicon or silicon nitride.

[0134] It should be noted that during the formation of the semiconductor structure, a wet etching process is used to etch the sidewall layer 131 to form an opening. During the wet etching process of the sidewall layer 131, when the etching selectivity between the sidewall layer 131 and the bottom source / drain plug 108 is constant, the amorphous silicon or silicon nitride is removed at a faster rate, thereby improving the efficiency of the process and reducing the process cost.

[0135] In this embodiment, the sealing layer 111 covers the top of the bottom source drain plug 108, the side wall of the bottom source drain plug 108 exposed by the opening 110, and the top of the opening 110.

[0136] In this embodiment, the sealing layer 111 fills the opening 110.

[0137] By filling the opening 110 with the sealing layer 111, the sealing layer 111 located on the side wall of the bottom source drain plug 108 becomes thicker, thereby further improving the protective effect of the sealing layer 111 on the bottom source drain plug 108, and further reducing the probability of damage to the bottom source drain plug 108 via the side wall of the bottom source drain plug 108.

[0138] In this embodiment, the top of the sealing layer 111 is lower than the top of the contact hole 135. The lower top of the sealing layer 111 provides space for the subsequent formation of a top source drain plug on top of the bottom source drain plug 108.

[0139] It should be noted that the thickness of the sealing layer 111 located on top of the bottom source / drain plug 108 should not be too large or too small. If the thickness of the sealing layer 111 on top of the bottom source / drain plug 108 is too large, it will easily occupy too much space for the subsequent formation of the top source / drain plug, thus affecting the performance of the semiconductor. If the thickness of the sealing layer 111 on top of the bottom source / drain plug 108 is too small, the etching solution will easily come into contact with the bottom source / drain plug 108 through the interface between the sealing layer 111 and the sidewall of the interlayer dielectric layer 105, increasing the probability of forming pore defects in the bottom source / drain plug 108, thereby reducing the performance of the semiconductor. Therefore, in this embodiment, the thickness of the sealing layer 111 on top of the bottom source / drain plug 108 is 1.5 nanometers to 4 nanometers.

[0140] In this embodiment, the conductor structure further includes a barrier adhesion layer 109, located between the sidewall layer 131 and the bottom source / drain plug 108, and covering the sidewall of the bottom source / drain plug 108.

[0141] The barrier adhesion layer 109 reduces the probability of metal ions in the bottom source / drain plug 108 diffusing into other film layers (e.g., interlayer dielectric layer 105) and increases the adhesion between the bottom source / drain plug 108 and the sidewall layer 131.

[0142] In this embodiment, the material of the barrier adhesion layer 109 includes one or both of Ti and TiN.

[0143] In this embodiment, the top of the barrier adhesion layer 109 and the top of the bottom source drain plug 108 are flush.

[0144] In other embodiments, the top of the barrier adhesion layer may be lower than the top of the bottom source / drain plug. Accordingly, the opening is surrounded by the interlayer dielectric layer, the sidewall layer, the barrier adhesion layer and the bottom source / drain plug, thereby increasing the process window for forming the sealing layer in the opening. When the sealing layer fills the opening, it is beneficial to further increase the thickness of the sealing layer located on the sidewall of the bottom source / drain plug.

[0145] In this embodiment, the semiconductor structure further includes a top source / drain plug 113 located at the top of the bottom source / drain plug 108, the top source / drain plug 113 penetrating the sealing layer 111 and connected to the top of the bottom source / drain plug 108.

[0146] The top source / drain plug 113 and the bottom source / drain plug 108 constitute a source / drain plug, thereby enabling the bottom source / drain plug 108 to be electrically connected to other interconnect structures or external circuits.

[0147] The specific description of the top source drain plug 113 will not be repeated here in this embodiment.

[0148] The semiconductor structure can be formed using the formation method described in the first embodiment, or it can be formed using other formation methods. For a detailed description of the semiconductor structure in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0149] refer to Figure 15 The diagram shows a schematic representation of another embodiment of the semiconductor structure of the present invention.

[0150] The similarities between the embodiments of the present invention and the first embodiment will not be repeated here. The differences between the embodiments of the present invention and the first embodiment are as follows:

[0151] The sidewall layer 207 is a barrier adhesion layer.

[0152] By using a barrier adhesion layer as the sidewall layer 207, no additional film layer is needed to form the opening, thus simplifying the process structure.

[0153] The sidewall layer 207 reduces the probability of metal ions in the bottom source / drain plug 208 diffusing into other film layers and increases the adhesion between the bottom source / drain plug 208 and the interlayer dielectric layer 205.

[0154] The material of the sidewall layer 207 includes one or both of Ti and TiN.

[0155] The semiconductor structure can be formed using the formation method described in the second embodiment, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0156] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A gate structure is located on the substrate; Source and drain doped layers are located within the substrate on both sides of the gate structure; An interlayer dielectric layer is located on the exposed substrate of the gate structure, and the interlayer dielectric layer covers the source and drain doped layers; A contact hole penetrates the interlayer dielectric layer on both sides of the gate structure, and the bottom of the contact hole exposes the source / drain doped layer; The bottom source / drain plug is located in the contact hole and is electrically connected to the source / drain doped layer; A sidewall layer is located between the sidewall of the bottom source / drain plug and the sidewall of the contact hole. The top of the sidewall layer is lower than the top of the bottom source / drain plug. The interlayer dielectric layer, the sidewall layer, and the bottom source / drain plug form an opening. A sealing layer covers the sidewall of the bottom source drain plug exposed by the opening and the top of the opening, and exposes the top of the bottom source drain plug.

2. The semiconductor structure as described in claim 1, characterized in that, The top of the bottom source drain plug is lower than the top of the contact hole; The top of the sealing layer is lower than the top of the contact hole.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, The sealing layer fills the opening.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a barrier adhesion layer located between the sidewall layer and the bottom source / drain plug, and covering the sidewall of the bottom source / drain plug, the top of the barrier adhesion layer being flush with the top of the bottom source / drain plug, and the sealing layer covering the sidewall of the barrier adhesion layer; or, The semiconductor structure further includes a barrier adhesion layer located between the sidewall layer and the bottom source / drain plug, and covering the sidewall of the bottom source / drain plug, wherein the top of the barrier adhesion layer is lower than the top of the bottom source / drain plug.

5. The semiconductor structure as described in claim 4, characterized in that, The top of the barrier adhesion layer is lower than the top of the bottom source / drain plug, and the opening is formed by the interlayer dielectric layer, the sidewall layer, the barrier adhesion layer and the bottom source / drain plug.

6. The semiconductor structure as described in claim 1, characterized in that, The sidewall layer is a barrier adhesion layer.

7. The semiconductor structure as described in claim 1, characterized in that, The thickness of the sealing layer located on top of the bottom source drain plug is 1.5 nanometers to 4 nanometers.

8. The semiconductor structure as described in claim 1, characterized in that, Along a direction perpendicular to the sidewall of the contact hole, the thickness of the sidewall layer is 2 nanometers to 4 nanometers.

9. The semiconductor structure as claimed in claim 1, characterized in that, The sidewall layer is made of amorphous silicon or silicon nitride.

10. The semiconductor structure as described in claim 1 or 2, characterized in that, The semiconductor structure further includes a top source / drain plug located on top of the bottom source / drain plug, the top source / drain plug penetrating the sealing layer and connected to the top of the bottom source / drain plug.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a gate structure is formed, and source / drain doped layers are formed in the substrate on both sides of the gate structure. An interlayer dielectric layer is formed on the exposed substrate of the gate structure, and the interlayer dielectric layer covers the source / drain doped layers. The interlayer dielectric layer on both sides of the gate structure is etched to form contact holes in the interlayer dielectric layer that expose the source and drain doped layers; A sidewall layer is formed on the sidewall of the contact hole; After the sidewall layer is formed, a bottom source / drain plug is formed inside the contact hole; The sidewall layer is etched to form an opening surrounded by the interlayer dielectric layer, the sidewall layer, and the bottom source / drain plug; A sealing layer is formed at the bottom of the opening, the top of the bottom source / drain plug, and the sidewall of the bottom source / drain plug exposed by the opening.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the sidewall layer includes: forming a padding material layer on top of the interlayer dielectric layer, and on the sidewalls and bottom of the contact hole; Remove the gasket material layer located at the top of the interlayer dielectric layer and at the bottom of the contact hole, and retain the remaining gasket material layer on the sidewall of the contact hole as a sidewall layer.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before forming the opening, the process further includes: re-etching the bottom source / drain plug and sidewall layer so that the top of the remaining bottom source / drain plug and sidewall layer is lower than the top of the contact hole; In the step of forming the sealing layer, the top of the sealing layer is lower than the top of the contact hole.

14. The method for forming a semiconductor structure as described in claim 11 or 13, characterized in that, The step of forming the sealing layer includes: forming a sealing material layer covering the bottom source / drain plug in the contact hole, the sealing material layer also filling the opening; etching back a portion of the thickness of the sealing material layer, the remaining sealing material layer serving as the sealing layer.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, The forming method further includes: after forming the sidewall layer on the sidewall of the contact hole, forming a barrier adhesion layer on the sidewall of the sidewall layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, During the etching of the sidewall layer, the barrier adhesion layer is also etched, and the opening is formed by the interlayer dielectric layer, the sidewall layer, the barrier adhesion layer and the bottom source / drain plug.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming a sidewall layer on the sidewall of the contact hole includes: forming a barrier adhesion layer on the sidewall of the contact hole, the barrier adhesion layer serving as the sidewall layer.

18. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process for forming the sidewall layer includes atomic layer deposition.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the opening includes etching the sidewall layer using a wet etching process.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the opening, the etching selectivity ratio between the sidewall layer and the bottom source / drain plug is greater than 2:

1.

21. The method for forming a semiconductor structure as described in claim 11 or 13, characterized in that, After forming the sealing layer, the forming method further includes: removing the sealing layer from the top of the bottom source / drain plug to expose the top of the bottom source / drain plug; and forming a top source / drain plug on the exposed top of the bottom source / drain plug.

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