Dynamic random access memory and method of forming the same

Abstract

A dynamic random access memory and a forming method thereof, wherein the method comprises: forming a first wafer, the first wafer having a storage area and a plurality of peripheral capacitor areas outside the storage area, one peripheral capacitor area comprising a plurality of peripheral capacitors, the storage area comprising a plurality of storage banks, each storage bank comprising a plurality of memory groups, the plurality of memory groups being arranged in an array along a first direction and a second direction, each memory group comprising a plurality of memory cells, each memory cell comprising a storage capacitor; forming a second wafer, the second wafer having a logic circuit area, the logic circuit area comprising a plurality of first peripheral areas and a second peripheral area, the plurality of first peripheral areas being arranged in an array along the first direction and the second direction; bonding the first wafer and the second wafer, and electrically connecting one of the first peripheral areas and one of the memory groups, thereby improving the integration level of the chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a dynamic random access memory and a method for forming the same. Background Technology

[0002] With the rapid development of technology, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory. Because of its fast access speed, DRAM is often used as a cache.

[0003] Dynamic Random Access Memory (DRAM) mainly consists of two parts: the peripheral circuitry and the memory array (core). A basic memory cell in DRAM consists of a storage transistor and a storage capacitor, while a memory array consists of multiple memory cells. With the continuous development of integrated circuit manufacturing technology, more chips can be integrated into each wafer, necessitating the introduction of new structural layouts to further reduce chip size and increase chip density.

[0004] In conclusion, existing dynamic random access memory (DRAM) still needs improvement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a dynamic random access memory and a method for forming the same, so as to reduce chip size and thereby increase chip density.

[0006] To address the aforementioned technical problems, the present invention provides a dynamic random access memory (DRAM), comprising: a first wafer having a storage region and a plurality of peripheral capacitor regions outside the storage region, each peripheral capacitor region including a plurality of peripheral capacitors; the storage region including a plurality of storage repositories, each storage repositories including a plurality of memory groups, the plurality of memory groups being arranged in an array along a first direction and a second direction; each memory group including a plurality of memory cells, each memory cell including a storage capacitor; and a second wafer bonded to the first wafer, the second wafer having a logic circuit region including a plurality of first peripheral regions and a second peripheral region, the plurality of first peripheral regions being arranged in an array along the first direction and the second direction; one first peripheral region being electrically connected to one of the memory groups and controlling the memory group.

[0007] Optionally, the plurality of storage cells are arranged in an array along the first and second directions, and the structure of each storage capacitor is the same as the structure of each peripheral capacitor.

[0008] Optionally, each memory cell further includes a transistor, a bit line, and a word line, wherein the drain region of the transistor is connected to the bit line, and the memory capacitor is electrically connected to the source region of the transistor; the first wafer has a plurality of heavily doped regions, and a plurality of peripheral capacitors in a peripheral capacitor region are electrically connected to one of the heavily doped regions.

[0009] Optionally, the storage capacitor includes a first electrode layer, a second electrode layer, and a first dielectric layer located between the first electrode layer and the second electrode layer.

[0010] Optionally, the peripheral capacitors within a peripheral capacitor region are divided into several capacitor groups, with the peripheral capacitors in each capacitor group connected in parallel and the capacitor groups connected in series.

[0011] Optionally, the peripheral capacitor includes a third electrode layer, a fourth electrode layer, and a second dielectric layer located between the third electrode layer and the fourth electrode layer.

[0012] Optionally, the third electrode layer of one of the peripheral capacitors and the fourth electrode layer of the other peripheral capacitor are electrically connected to realize the series connection of the two peripheral capacitors.

[0013] Optionally, each of the first peripheral regions includes a decoder and driver region and a sensor amplifier region.

[0014] Accordingly, the present invention also provides a method for forming the aforementioned dynamic random access memory, comprising: a method for forming a dynamic random access memory, characterized in that it comprises: forming a first wafer, the first wafer having a storage region and a plurality of peripheral capacitor regions located outside the storage region, each peripheral capacitor region including a plurality of peripheral capacitors, the storage region including a plurality of storage repositories, each storage repositories including a plurality of memory groups, the plurality of memory groups being arranged in an array along a first direction and a second direction, each memory group including a plurality of storage cells, each storage cell including a storage capacitor; forming a second wafer, the second wafer having a logic circuit region, the logic circuit region including a plurality of first peripheral regions and a second peripheral region, the plurality of first peripheral regions being arranged in an array along the first direction and the second direction; bonding the first wafer and the second wafer, and electrically connecting one of the first peripheral regions to one of the memory groups.

[0015] Optionally, the plurality of storage cells are arranged in an array along the first and second directions, and the structure of each storage capacitor is the same as the structure of each peripheral capacitor.

[0016] Optionally, each memory cell further includes a transistor, a bit line, and a word line, wherein the drain region of the transistor is connected to the bit line, and the storage capacitor is electrically connected to the source region of the transistor.

[0017] Optionally, the method for forming the first wafer includes: providing a substrate, the substrate including a first region and a second region; forming a plurality of transistors in the first region; forming a plurality of heavily doped regions in the second region; and after forming the plurality of transistors and the plurality of heavily doped regions, forming a plurality of storage capacitors and a plurality of peripheral capacitor regions on the surface of the substrate, wherein a plurality of peripheral capacitors in a peripheral capacitor region are electrically connected to a heavily doped region.

[0018] Optionally, the method for forming the heavily doped region includes: forming a first mask layer on the surface of the first region; using the first mask layer as a mask, implanting first dopant ions into the second region to form the heavily doped region in the second region.

[0019] Optionally, the first region has a well region, and the active region of the transistor is located in the well region; the method of forming the well region includes: forming a second mask layer on the surface of the second region before forming the transistor; using the second mask layer as a mask, implanting second doped ions into the first region to form the well region.

[0020] Optionally, a first isolation layer is provided between the active regions of adjacent transistors; and a second isolation layer is provided between the plurality of heavily doped regions.

[0021] Optionally, the method for forming the active region, the first isolation layer, and the second isolation layer includes: forming a third mask layer on the surface of the second region; using the third mask layer as a mask, etching the first region to form a first groove between the plurality of active regions and adjacent active regions; after forming the first groove, removing the third mask layer; and after removing the third mask layer, forming the first isolation layer in the first groove.

[0022] Optionally, the substrate has a first side and a second side facing each other; the storage capacitor is located on the side of the transistor facing the first side, the bit line is located on the side of the transistor facing the second side, and the peripheral capacitor and the storage capacitor are located on the same side of the substrate.

[0023] Optionally, the storage capacitor includes a first electrode layer, a second electrode layer, and a first dielectric layer located between the first electrode layer and the second electrode layer, wherein the second electrode layer is located away from the first surface relative to the first electrode layer; the peripheral capacitor includes a third electrode layer, a fourth electrode layer, and a second dielectric layer located between the third electrode layer and the fourth electrode layer, wherein the fourth electrode layer is located away from the first surface relative to the three electrode layers.

[0024] Optionally, the first dielectric layer may have a planar or U-shaped shape; the second dielectric layer may have a planar or U-shaped shape.

[0025] Optionally, after forming the plurality of storage capacitors and the peripheral capacitor region, the method further includes: forming a first metal layer electrically connected to the second electrode layer, and a first electrical plug electrically connected to the first metal layer, the first electrical plug being led out from the second surface of the substrate; forming a second metal layer electrically connected to the bit line, and a second electrical plug electrically connected to the second metal layer, the second electrical plug being led out from the second surface of the substrate; forming a third metal layer electrically connected to the fourth electrode layer, and a third electrical plug electrically connected to the third metal layer, the third electrical plug being led out from the second surface of the substrate; forming a fourth metal layer electrically connected to the heavily doped region, and a fourth electrical plug electrically connected to the fourth metal layer, the fourth electrical plug being led out from the second surface of the substrate.

[0026] Optionally, after forming the third and fourth electrical plugs, a plurality of electrical interconnects are also formed, which electrically connect the third metal layer of one peripheral capacitor to the fourth metal layer of another peripheral capacitor.

[0027] Optionally, each of the first peripheral regions includes a decoder and driver region and a sensor amplifier region.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] In the dynamic random access memory provided by this invention, several peripheral capacitor regions and storage regions are placed on a first wafer, and a second wafer with logic circuit regions is bonded to the first wafer. On one hand, the peripheral capacitor regions do not occupy chip area in the logic circuit region; therefore, more functional circuit regions can be integrated in the logic circuit region, improving the chip's integration level. On the other hand, the peripheral capacitor regions and storage capacitors can be formed in the same process, which helps reduce process steps.

[0030] Furthermore, the peripheral capacitors within a peripheral capacitor region are divided into several capacitor groups. The peripheral capacitors within each capacitor group are connected in parallel, and the capacitor groups are connected in series. This avoids the problem of all peripheral capacitors failing due to the failure of a single peripheral capacitor or a fault in a certain peripheral capacitor circuit. At the same time, the number of peripheral capacitors connected in series or in parallel can be adjusted according to actual needs to obtain different overall circuit capacitance values.

[0031] Furthermore, the first wafer has several heavily doped regions, and several peripheral capacitors in a peripheral capacitor region are electrically connected to one of the heavily doped regions. The heavily doped regions are used to adjust the contact between the peripheral capacitors and the substrate from a metal-semiconductor contact to an ohmic contact, thereby reducing the contact resistance between the peripheral capacitors and the substrate. Attached Figure Description

[0032] Figure 1This is a schematic diagram of a dynamic random access memory in one embodiment;

[0033] Figure 2 This is a schematic diagram of a dynamic random access memory in another embodiment;

[0034] Figure 3 This is a schematic diagram of a dynamic random access memory in one embodiment of the present invention;

[0035] Figure 4 This is a circuit diagram of several peripheral capacitors in one embodiment of the present invention;

[0036] Figures 5 to 9 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory according to an embodiment of the present invention. Detailed Implementation

[0037] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0038] As described in the background section, existing dynamic random access memories (DRAMs) still need improvement. This will now be analyzed and explained in conjunction with specific embodiments.

[0039] Figure 1 This is a schematic diagram of a dynamic random access memory in one embodiment.

[0040] Please refer to Figure 1 It includes: a storage bank 10 arranged in 4 rows and 2 columns and peripheral circuitry 20 located between two adjacent rows of storage banks 10. Each storage bank 10 includes a plurality of memory groups 101, and a driver 102, a row address decoder 103, a column address decoder 104, a sensor amplifier 105, and peripheral capacitors 106 located around the plurality of memory groups 101. Each memory group 101 includes a plurality of memory cells (not shown in the figure) arranged in an array along a first direction X1 and a second direction Y1. The plurality of memory groups 101 are arranged in an array along the first direction X1 and the second direction Y1.

[0041] Dynamic random access memory (DRAM) chips typically include a storage area (storage unit 10) and a CMOS circuit area excluding the storage area. The CMOS circuit area (including the peripheral circuitry 20) is used to implement various logic circuit functions. The storage area refers to the arrayed storage cells used for data storage. In this embodiment, the storage area and the CMOS circuit area are distributed on the same wafer, occupying a large chip area, which is not conducive to improving chip density.

[0042] Figure 2 This is a schematic diagram of a dynamic random access memory in another embodiment.

[0043] Please refer to Figure 2 The wafer comprises: a first wafer A, having a CMOS circuit region within the first wafer A, the CMOS circuit region including a plurality of first peripheral regions 201 and a second peripheral region 202, the second peripheral region 202 having peripheral capacitors 2021, the plurality of first peripheral regions 201 being arranged in an array along a first direction X2 and a second direction Y2, each first peripheral region 201 including a driver & address decoder region 2011 and a sensor amplifier region 2012; and a second wafer B bonded to the first wafer A, having a storage region within the second wafer B, the storage region including a plurality of storage repositories 203, each storage repositories 203 including a plurality of memory groups 2031, the plurality of memory groups 2031 being arranged in an array along a first direction X2 and a second direction Y2, and the second wafer B having dummy cells 204 corresponding to the positions of the second peripheral region 202.

[0044] In this embodiment, by placing the CMOS circuit area and the memory area on two wafers and then bonding the two wafers, the chip area is significantly reduced. However, the area of ​​the peripheral capacitor 201 accounts for approximately 5% of the total area of ​​the CMOS circuit area chip, which is still not conducive to chip integration.

[0045] To address the aforementioned technical problems, the present invention provides a dynamic random access memory (DRAM) in which several peripheral capacitor regions and a storage region are placed on a first wafer, and a second wafer with a logic circuit region is bonded to the first wafer. On one hand, the peripheral capacitor regions do not occupy chip area in the logic circuit region; therefore, more functional circuit regions can be integrated in the logic circuit region, improving the chip's integration level. On the other hand, the peripheral capacitor regions and the storage capacitors can be formed in the same process, which helps reduce process steps.

[0046] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Figure 3 This is a schematic diagram of a dynamic random access memory in one embodiment of the present invention.

[0048] Please refer to Figure 3 A first wafer I is formed, which has a storage region and a plurality of peripheral capacitor regions 301 located outside the storage region. Each peripheral capacitor region 301 includes a plurality of peripheral capacitors (not shown in the figure). The storage region includes a plurality of storage repositories 302. Each storage repositories 302 includes a plurality of memory groups 3021. The plurality of memory groups 3021 are arranged in an array along a first direction X3 and a second direction Y3. Each memory group 3021 includes a plurality of memory cells (not shown in the figure). Each memory cell includes a storage capacitor (not shown in the figure).

[0049] Several peripheral capacitor regions 301 and memory regions (i.e., arrayed memory cells) are placed on a first wafer I. Subsequently, a second wafer with logic circuit regions is bonded to the first wafer I. On the one hand, the several peripheral capacitor regions 301 do not occupy the chip area of ​​the logic circuit region; therefore, more functional circuit regions can be integrated in the logic circuit region, improving the chip integration level. On the other hand, the several peripheral capacitor regions 301 and memory capacitors can be formed in the same process, which helps to reduce process steps.

[0050] In this embodiment, the plurality of storage cells are arranged in an array along the first direction X3 and the second direction Y3, and the structure of each storage capacitor is the same as the structure of each peripheral capacitor.

[0051] In this embodiment, the storage area includes eight storage repositories 302. In other embodiments, the number of storage repositories may be two, four, or other numbers, and the number of storage repositories can be adjusted according to actual needs.

[0052] In this embodiment, the memory group 3021 in a repository 302 is 8×8 in size, that is, a repository 302 contains 64 memory groups 3021. In other embodiments, the number of memory groups 3021 can be set according to actual storage needs, drive capabilities, etc.

[0053] The plurality of storage cells are arranged in an array along the first direction X3 and the second direction Y3, and each storage cell includes a storage capacitor.

[0054] In this embodiment, the structure of the plurality of peripheral capacitors is the same as that of the storage capacitor.

[0055] Each memory cell also includes a transistor, a bit line, and a word line, with the drain region of the transistor connected to the bit line and the storage capacitor electrically connected to the source region of the transistor.

[0056] In this embodiment, please refer to the circuit relationship between the plurality of peripheral capacitors. Figure 4 .

[0057] Figure 4 This is a circuit diagram of several peripheral capacitors in one embodiment of the present invention.

[0058] Please refer to Figure 4 The peripheral capacitors 801 in a peripheral capacitor region are divided into several capacitor groups 800. The peripheral capacitors 801 in each capacitor group 800 are connected in parallel, and the capacitor groups 800 are connected in series.

[0059] This can avoid the problem of all external capacitors failing due to the failure of one external capacitor or a certain external capacitor circuit in parallel connections; at the same time, the number of external capacitors connected in series or in parallel can be adjusted according to actual needs to obtain different overall circuit capacitance values.

[0060] In this embodiment, the method for forming the first wafer I is described in reference [reference needed]. Figures 5 to 9 .

[0061] Figures 5 to 9 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory according to an embodiment of the present invention.

[0062] Please refer to Figure 5 A substrate is provided, the substrate comprising a first region I and a second region II; a plurality of heavily doped regions 501 are formed in the second region II.

[0063] In this embodiment, the substrate has a first side and a second side facing each other.

[0064] It should be noted that, Figures 5 to 6 This is a top view of the first surface of the substrate.

[0065] The method for forming the plurality of heavily doped regions 501 includes: forming a first mask layer (not shown in the figure) on the surface of the first region I; using the first mask layer as a mask, implanting first doped ions into the second region II, and forming the heavily doped region 501 in the second region II.

[0066] The substrate is made of silicon. Implanting a large number of dopant ions into the silicon semiconductor material can improve the conductivity of silicon. The heavily doped region 501 is used to adjust the contact between the peripheral capacitor and the substrate from a metal-semiconductor contact to an ohmic contact, thereby reducing the contact resistance between the peripheral capacitor and the substrate.

[0067] Subsequently, a number of transistors are formed in the first region I to form an array of memory cells.

[0068] The second region II is used to form the plurality of peripheral capacitor regions.

[0069] The first region I has a well region 400, and the active region of the transistor is subsequently formed in the well region 400.

[0070] The method for forming the well region 400 includes: forming a second mask layer (not shown in the figure) on the surface of the second region II before forming the transistor; and implanting second doped ions into the first region using the second mask layer as a mask to form the well region (not shown in the figure).

[0071] A first isolation layer is provided between the active regions of adjacent transistors; a second isolation layer is provided between the plurality of heavily doped regions. For the methods of forming the active regions, the first isolation layer, and the second isolation layer, please refer to [reference needed]. Figure 6 and Figure 7 .

[0072] Please refer to Figure 6 A third mask layer 601 is formed on the surface of the substrate.

[0073] Please refer to Figure 7 Using the third mask layer 601 as a mask, the substrate is etched to form a first groove (not shown in the figure) between the plurality of active regions 402 and adjacent active regions 402 in the first region I, and a plurality of second grooves (not shown in the figure) are formed in the second region II; after forming the first groove and the second groove, the third mask layer 601 is removed; after removing the third mask layer 601, the first isolation layer 602 is formed in the first groove, and the second isolation layer 603 is formed in the second groove.

[0074] Specifically, the plurality of active regions 402 are formed within the trap region 400 in the first region I.

[0075] Please refer to Figure 8 A plurality of transistors 401 are formed in the first region I; after forming the plurality of transistors 401 and the plurality of heavily doped regions 501, a plurality of storage capacitors 407 and a plurality of peripheral capacitor regions are formed on the substrate surface, and a plurality of peripheral capacitors 502 in a peripheral capacitor region are electrically connected to a heavily doped region 501.

[0076] It should be noted that, Figures 8 to 9 This is a cross-sectional schematic diagram of the dynamic random access memory, showing only some of the memory cells and some of the peripheral capacitors.

[0077] In this embodiment, transistor 401 is a vertical channel transistor. In other embodiments, the transistor may not be limited to a vertical channel transistor.

[0078] The transistor 401 includes an active region 402, a gate dielectric layer 403 located on the sidewall of the active region 402, a gate 404 located on the surface of the gate dielectric layer 403, a source region 405 located in the active region 402 facing the first surface, and a drain region 406 located in the active region 402 facing the second surface b.

[0079] The storage capacitor 407 includes a first electrode layer 408, a second electrode layer 409, and a first dielectric layer 410 located between the first electrode layer 408 and the second electrode layer 409, wherein the second electrode layer 409 is located away from the first surface a relative to the first electrode layer 408.

[0080] The peripheral capacitor 502 includes a third electrode layer 503, a fourth electrode layer 504, and a second dielectric layer 505 located between the third electrode layer 503 and the fourth electrode layer 504. The fourth electrode layer 504 is located away from the first surface a relative to the three electrode layers 503.

[0081] The first dielectric layer 408 has a planar or U-shaped shape; the second dielectric layer 505 has a planar or U-shaped shape. In this embodiment, the first dielectric layer 409 is U-shaped; the second dielectric layer 505 is U-shaped. In other embodiments, the shape of the first dielectric layer is not limited to this; the shape of the second dielectric layer is not limited to this.

[0082] The aforementioned peripheral capacitor regions and storage capacitors can be formed in the same process, which helps to reduce process steps.

[0083] In this embodiment, after forming the plurality of transistors 401 and the plurality of heavily doped regions 501, and before forming the plurality of storage capacitors 407 and the plurality of peripheral capacitor regions, an etch stop layer 604 is formed on the substrate; after forming the etch stop layer 604, a first dielectric layer 605 is formed on the surface of the etch stop layer 604; after forming the first dielectric layer 605, the plurality of storage capacitors 407 and the plurality of peripheral capacitor regions are formed within the first dielectric layer 605.

[0084] In this embodiment, the storage capacitor 407 is located on the side of the transistor facing the first surface a, the bit line is located on the side of the transistor facing the second surface b, and the peripheral capacitor 502 and the storage capacitor 407 are located on the same side of the substrate.

[0085] In this embodiment, after forming the plurality of storage capacitors 407 and the plurality of peripheral capacitor regions, the bit line 411 is formed on the second surface b of the substrate.

[0086] Please continue to refer to this. Figure 8After forming the plurality of storage capacitors 407 and the peripheral capacitor region, a first metal layer 414 electrically connected to the second electrode layer 409 and a first electrical plug 415 electrically connected to the first metal layer 414 are also formed, the first electrical plug 415 being led out from the second surface b of the substrate; a second metal layer 412 electrically connected to the bit line 411 and a second electrical plug 413 electrically connected to the second metal layer 412 are also formed, the second electrical plug 413 being led out from the second surface b of the substrate; a third metal layer 505 electrically connected to the fourth electrode layer 504 and a third electrical plug 506 electrically connected to the third metal layer 505 are also formed, the third electrical plug 506 being led out from the second surface b of the substrate; a fourth metal layer 509 electrically connected to the heavily doped region 501 and a fourth electrical plug 510 electrically connected to the fourth metal layer 509 are also formed, the fourth electrical plug 510 being led out from the second surface b of the substrate.

[0087] Specifically, after the bit line 411 is formed, the second metal layer 412 is formed on the bit line 411; after the second metal layer 412 is formed, the second dielectric layer 606 is formed on the second surface b, and the second electrical plug 413 is formed in the second dielectric layer 606.

[0088] In this embodiment, a first conductive layer 416 is further provided between the first metal layer 414 and the second electrode layer 409; and a second conductive layer 507 is further provided between the second metal layer 505 and the fourth electrode layer 504.

[0089] Please refer to Figure 9 After the third electrical plug 506 and the fourth electrical plug 510 are formed, a number of electrical connecting lines 701 are also formed, which electrically connect the third metal layer 505 of one peripheral capacitor to the fourth metal layer 509 of another peripheral capacitor.

[0090] Specifically, the third electrode layer 504 of one peripheral capacitor 502 and the fourth electrode layer 503 of the other peripheral capacitor 502 are electrically connected to realize the series connection of the two peripheral capacitors 502.

[0091] Specifically, after the third electrical plug 506 and the fourth electrical plug 510 are formed, a third dielectric layer 700 is formed on the second surface of the substrate, and the electrical connection 701 is located within the third dielectric layer 700.

[0092] Please continue to refer to this. Figure 3A second wafer II is formed, which has a logic circuit region. The logic circuit region includes a plurality of first peripheral regions 303 and a second peripheral region 304. The plurality of first peripheral regions 303 are arranged in an array along a first direction X3 and a second direction Y3. The first wafer I and the second wafer II are bonded together, and one of the first peripheral regions 303 is electrically connected to one of the memory groups 302.

[0093] Each memory group 302 corresponds to a first peripheral area 303, and each first peripheral area 303 includes a decoder and driver area 3031 and a sensor amplifier area 3032. The decoder and driver area 3031 contains a decoder and a driver. The sensor amplifier area 3032 is used to house a sensor amplifier.

[0094] Accordingly, one embodiment of the present invention also provides a dynamic random access memory formed using the above method. Please refer to [link / reference needed]. Figure 3 , Figure 4 , Figure 8 and Figure 9 The system includes: a first wafer I, which has a storage region and a plurality of peripheral capacitor regions 301 outside the storage region. Each peripheral capacitor region 301 includes a plurality of peripheral capacitors. The storage region includes a plurality of storage repositories 302. Each storage repositories 302 includes a plurality of memory groups 3021. The plurality of memory groups 3021 are arranged in an array along a first direction X3 and a second direction Y3. Each memory group 3021 includes a plurality of memory cells. Each memory cell includes a storage capacitor. A second wafer II is bonded to the first wafer I. The second wafer II has a logic circuit region. The logic circuit region includes a plurality of first peripheral regions 303 and a second peripheral region 304. The plurality of first peripheral regions 303 are arranged in an array along a first direction X3 and a second direction Y3. Each first peripheral region 303 is electrically connected to and controls one of the memory groups 3021.

[0095] Several peripheral capacitor regions 301 and memory regions (i.e., arrayed memory cells) are placed on a first wafer I. Subsequently, a second wafer with logic circuit regions is bonded to the first wafer I. On the one hand, the several peripheral capacitor regions 301 do not occupy the chip area of ​​the logic circuit region; therefore, more functional circuit regions can be integrated in the logic circuit region, improving the chip integration level. On the other hand, the several peripheral capacitor regions 301 and memory capacitors can be formed in the same process, which helps to reduce process steps.

[0096] In this embodiment, the plurality of storage cells are arranged in an array along the first direction X3 and the second direction Y3, and the structure of each storage capacitor is the same as the structure of each peripheral capacitor.

[0097] Each memory cell also includes a transistor 401, a bit line 411, and a word line. The drain region 406 of the transistor 401 is connected to the bit line 411, and the memory capacitor 407 is electrically connected to the source region 405 of the transistor 401. The first wafer I has a plurality of heavily doped regions 501, and a plurality of peripheral capacitors 502 in a peripheral capacitor region are electrically connected to one of the heavily doped regions 501.

[0098] The storage capacitor 407 includes a first electrode layer 408, a second electrode layer 409, and a first dielectric layer 410 located between the first electrode layer 408 and the second electrode layer 409.

[0099] The peripheral capacitor includes a third electrode layer 503, a fourth electrode layer 504, and a second dielectric layer 505 located between the third electrode layer 503 and the fourth electrode layer 504.

[0100] The third electrode layer 503 of one peripheral capacitor 502 and the fourth electrode layer 504 of the other peripheral capacitor 502 are electrically connected to realize the series connection of the two peripheral capacitors.

[0101] Each memory group 302 corresponds to a first peripheral area 303, and each first peripheral area 303 includes a decoder and driver area 3031 and a sensor amplifier area 3032. The decoder and driver area 3031 contains a decoder and a driver. The sensor amplifier area 3032 is used to house a sensor amplifier.

[0102] In this embodiment, the peripheral capacitors in a peripheral capacitor region are divided into several capacitor groups 801. The peripheral capacitors 800 in each capacitor group 801 are connected in parallel, and the capacitor groups 801 are connected in series.

[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A dynamic random access memory, characterized in that, include: A first wafer has a storage region and a plurality of peripheral capacitor regions outside the storage region. Each peripheral capacitor region includes a plurality of peripheral capacitors. The storage region includes a plurality of storage repositories. Each storage repositories includes a plurality of memory groups. The plurality of memory groups are arranged in an array along a first direction and a second direction. Each memory group includes a plurality of memory cells. Each memory cell includes a storage capacitor. The plurality of peripheral capacitors in a peripheral capacitor region are divided into a plurality of capacitor groups. The peripheral capacitors in each capacitor group are connected in parallel, and the capacitor groups are connected in series. A second wafer bonded to the first wafer, the second wafer having a logic circuit region, the logic circuit region including a plurality of first peripheral regions and a second peripheral region, the plurality of first peripheral regions being arranged in an array along a first direction and a second direction, one of the first peripheral regions being electrically connected to and controlling one of the memory groups.

2. The dynamic random access memory as described in claim 1, characterized in that, The plurality of storage cells are arranged in an array along the first and second directions, and the structure of each storage capacitor is the same as the structure of each peripheral capacitor.

3. The dynamic random access memory as described in claim 2, characterized in that, Each memory cell also includes a transistor, a bit line, and a word line. The drain region of the transistor is connected to the bit line, and the memory capacitor is electrically connected to the source region of the transistor. The first wafer has several heavily doped regions, and several peripheral capacitors in a peripheral capacitor region are electrically connected to one of the heavily doped regions.

4. The dynamic random access memory as described in claim 2, characterized in that, The storage capacitor includes a first electrode layer, a second electrode layer, and a first dielectric layer located between the first electrode layer and the second electrode layer.

5. The dynamic random access memory as described in claim 1, characterized in that, The peripheral capacitor includes a third electrode layer, a fourth electrode layer, and a second dielectric layer located between the third electrode layer and the fourth electrode layer.

6. The dynamic random access memory as described in claim 5, characterized in that, The third electrode layer of one of the peripheral capacitors is electrically connected to the fourth electrode layer of the other peripheral capacitor, thereby realizing the series connection of the two peripheral capacitors.

7. The dynamic random access memory as described in claim 1, characterized in that, Each of the first peripheral regions includes a decoder and driver region and a sensor amplifier region.

8. A method for forming a dynamic random access memory, characterized in that, include: A first wafer is formed, the first wafer having a storage region and a plurality of peripheral capacitor regions located outside the storage region. A peripheral capacitor region includes a plurality of peripheral capacitors. The storage region includes a plurality of storage repositories. Each storage repositories includes a plurality of memory groups. The plurality of memory groups are arranged in an array along a first direction and a second direction. Each memory group includes a plurality of memory cells. Each memory cell includes a storage capacitor. The plurality of peripheral capacitors in a peripheral capacitor region are divided into a plurality of capacitor groups. The peripheral capacitors in each capacitor group are connected in parallel, and the capacitor groups are connected in series. A second wafer is formed, the second wafer having a logic circuit region, the logic circuit region including a plurality of first peripheral regions and a second peripheral region, the plurality of first peripheral regions being arranged in an array along a first direction and a second direction; The first wafer and the second wafer are bonded together, and a first peripheral region is electrically connected to a memory group.

9. The method for forming a dynamic random access memory as described in claim 8, characterized in that, The plurality of storage cells are arranged in an array along the first and second directions, and the structure of each storage capacitor is the same as the structure of each peripheral capacitor.

10. The method for forming a dynamic random access memory as described in claim 9, characterized in that, Each memory cell also includes a transistor, a bit line, and a word line, with the drain region of the transistor connected to the bit line and the storage capacitor electrically connected to the source region of the transistor.

11. The method for forming a dynamic random access memory as described in claim 10, characterized in that, The method for forming the first wafer includes: providing a substrate, the substrate including a first region and a second region; forming a plurality of transistors in the first region; forming a plurality of heavily doped regions in the second region; and after forming the plurality of transistors and the plurality of heavily doped regions, forming a plurality of storage capacitors and a plurality of peripheral capacitor regions on the surface of the substrate, wherein a plurality of peripheral capacitors in a peripheral capacitor region are electrically connected to a heavily doped region.

12. The method for forming a dynamic random access memory as described in claim 11, characterized in that, The method for forming the heavily doped region includes: forming a first mask layer on the surface of the first region; using the first mask layer as a mask, implanting a first dopant ion into the second region to form the heavily doped region in the second region.

13. The method for forming a dynamic random access memory as described in claim 11, characterized in that, The first region has a well region, and the active region of the transistor is located in the well region; the method of forming the well region includes: forming a second mask layer on the surface of the second region before forming the transistor; using the second mask layer as a mask, implanting a second dopant ion into the first region to form the well region.

14. The method for forming a dynamic random access memory as described in claim 13, characterized in that, The active regions of adjacent transistors are separated by a first isolation layer; the heavily doped regions are separated by a second isolation layer.

15. The method for forming a dynamic random access memory as described in claim 14, characterized in that, The method for forming the active region, the first isolation layer, and the second isolation layer includes: forming a third mask layer on the surface of the second region; using the third mask layer as a mask, etching the first region to form a first groove between the plurality of active regions and adjacent active regions; after forming the first groove, removing the third mask layer; and after removing the third mask layer, forming the first isolation layer in the first groove.

16. The method for forming a dynamic random access memory as described in claim 11, characterized in that, include: The substrate has a first side and a second side facing each other; the storage capacitor is located on the side of the transistor facing the first side, the bit line is located on the side of the transistor facing the second side, and the peripheral capacitor and the storage capacitor are located on the same side of the substrate.

17. The method for forming a dynamic random access memory as described in claim 16, characterized in that, The storage capacitor includes a first electrode layer, a second electrode layer, and a first dielectric layer located between the first electrode layer and the second electrode layer, wherein the second electrode layer is located away from the first surface relative to the first electrode layer; the peripheral capacitor includes a third electrode layer, a fourth electrode layer, and a second dielectric layer located between the third electrode layer and the fourth electrode layer, wherein the fourth electrode layer is located away from the first surface relative to the three electrode layers.

18. The method for forming a dynamic random access memory as described in claim 17, characterized in that, The first dielectric layer has a planar or U-shaped shape; the second dielectric layer has a planar or U-shaped shape.

19. The method for forming a dynamic random access memory as described in claim 17, characterized in that, After forming the plurality of storage capacitors and the peripheral capacitor region, the method further includes: forming a first metal layer electrically connected to the second electrode layer, and a first electrical plug electrically connected to the first metal layer, the first electrical plug being led out from the second surface of the substrate; forming a second metal layer electrically connected to the bit line, and a second electrical plug electrically connected to the second metal layer, the second electrical plug being led out from the second surface of the substrate; forming a third metal layer electrically connected to the fourth electrode layer, and a third electrical plug electrically connected to the third metal layer, the third electrical plug being led out from the second surface of the substrate; forming a fourth metal layer electrically connected to the heavily doped region, and a fourth electrical plug electrically connected to the fourth metal layer, the fourth electrical plug being led out from the second surface of the substrate.

20. The method for forming a dynamic random access memory as described in claim 19, characterized in that, After the third and fourth electrical plugs are formed, several electrical interconnects are also formed, which electrically connect the third metal layer of one peripheral capacitor to the fourth metal layer of another peripheral capacitor.

21. The method for forming a dynamic random access memory as described in claim 8, characterized in that, Each of the first peripheral regions includes a decoder and driver region and a sensor amplifier region.

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