Semiconductor structure and manufacturing method

Abstract

This invention discloses a semiconductor structure comprising an interconnect structure formed by a U-shaped portion and a horizontally extended portion, which can avoid the problems of linewidth shrinkage or line breakage in the interconnect structure and ensure the conductivity quality of the interconnect structure.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same. More specifically, this invention relates to a dynamic random access memory (DRAM) including a memory region and a peripheral region, and a method for manufacturing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of volatile memory. DRAM typically consists of a memory region comprised of an array of memory cells and a peripheral region comprised of control circuitry. The control circuitry in the peripheral region addresses each memory cell within the memory region via a complex number of column word lines and row bit lines, and is electrically connected to each memory cell to perform data reading, writing, or erasing. In advanced semiconductor manufacturing, by employing an architecture with buried word lines or buried bit lines, the chip size of DRAM devices can be significantly reduced. This architecture allows the active regions of the memory cells to be arranged at a denser pitch, achieving higher cell density.

[0003] In the DRAM manufacturing process, the semiconductor devices for memory cells and peripheral circuitry are formed simultaneously using the same manufacturing process. How to integrate the manufacturing process and ensure the manufacturing quality of the semiconductor devices for memory cells and peripheral circuitry is a topic of ongoing concern in this field. Summary of the Invention

[0004] One objective of this invention is to provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a peripheral region and a memory region, wherein the bends in the interconnect structure of the peripheral region are formed by connecting two horizontally extending portions using a U-shaped portion, which avoids the problems of linewidth contraction or line breakage that easily occur at bends in conventional interconnect structures.

[0005] A semiconductor structure according to an embodiment of the present invention includes a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. An interconnect structure includes at least two horizontally extending portions on the second dielectric layer, and a U-shaped portion passing through the second dielectric layer and a portion of the first dielectric layer and connecting adjacent ends of the two horizontally extending portions.

[0006] A method for manufacturing a semiconductor structure according to another embodiment of the present invention includes the following steps: First, a substrate is provided; then, a first dielectric layer and a second dielectric layer are formed on the substrate; next, at least one first opening is formed through the second dielectric layer and a portion of the first dielectric layer. Then, a conductive layer is formed on the second dielectric layer and fills the first opening; finally, a recessed process is performed on the conductive layer to form an interconnect structure. The interconnect structure includes at least two horizontally extending portions located on the second dielectric layer, and a U-shaped portion passing through the second dielectric layer and a portion of the first dielectric layer and connecting adjacent ends of the two horizontally extending portions. Attached Figure Description

[0007] Figures 1 to 11 This is a schematic diagram of the manufacturing steps of a semiconductor structure according to an embodiment of the present invention, wherein:

[0008] Figure 1 This is a planar schematic diagram of the semiconductor structure after the formation of the second dielectric layer. Figure 2 The left, middle, and right legends are respectively along Figure 1 Schematic diagram of cross sections of AA' tangent, BB' tangent and CC' tangent;

[0009] Figure 3 This is a planar schematic diagram of the semiconductor structure after the formation of the first and second openings. Figure 4 The left, middle, and right legends are respectively along Figure 3 Schematic diagram of cross sections of AA' tangent, BB' tangent and CC' tangent;

[0010] Figure 5 The left, middle, and right diagrams are schematic cross-sectional views of the semiconductor structure after the formation of the conductive layer, along the AA', BB', and CC' tangents, respectively.

[0011] Figure 6 This is a planar schematic diagram of a semiconductor structure after a mask layer has been formed on the conductive layer. Figure 7 The left, middle, and right legends are respectively along Figure 6 Schematic diagram of cross sections of AA' tangent, BB' tangent and CC' tangent;

[0012] Figure 8 This is a planar schematic diagram of the semiconductor structure after the recessed process. Figure 9 The left, middle, and right legends are respectively along Figure 6 Cross-sectional diagrams of the AA', BB', and CC' tangents; and

[0013] Figure 10 This is a planar schematic diagram of the semiconductor structure after the formation of the third dielectric layer. Figure 11The left, middle, and right legends are respectively along Figure 10 A cross-sectional diagram of the AA', BB', and CC' tangents.

[0014] Figure 12 The drawing is shown as Figure 11 Another embodiment of the semiconductor structure shown.

[0015] Figure 13 The drawing is shown as Figure 11 Another embodiment of the semiconductor structure shown.

[0016] The reference numerals in the attached figures are explained as follows:

[0017] 10 Substrates

[0018] 14. Isolation Structure

[0019] 16 Semiconductor Layers

[0020] 22 Semiconductor Layer

[0021] 24 Metal Layers

[0022] 26 Hard mask layers

[0023] 32. Spacer wall

[0024] 34 First dielectric layer

[0025] 36 Second dielectric layer

[0026] 38 Conductive Layer

[0027] 38a Liner

[0028] 40 mask layers

[0029] 42 Interconnection Structure

[0030] 42a U-shaped section

[0031] 42b Horizontal extension

[0032] 44 Storage Node Contact Structure

[0033] 44a Insertion part

[0034] 44b Contact pad portion

[0035] 54 Third dielectric layer

[0036] 56 air gap

[0037] AA' tangent

[0038] BB' tangent

[0039] CC' Tangent

[0040] BL bitline

[0041] E1 recessed process

[0042] OP1 First Opening

[0043] OP2 Second Opening

[0044] R1 Outer Area

[0045] R2 memory region

[0046] RE depression

[0047] S1 end Detailed Implementation

[0048] To enable those skilled in the art to further understand this invention, preferred embodiments are described below, along with accompanying drawings, to explain in detail the structure and desired effects of the invention. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments without departing from the spirit of this disclosure to achieve other embodiments.

[0049] Figures 1 to 11 This invention describes a method for manufacturing a semiconductor structure according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1 and Figure 2 First, a substrate 10 is provided, on which a peripheral region R1 and a memory region R2 are defined. The peripheral region R1 is a region for setting peripheral circuitry and may include, but is not limited to, semiconductor devices for controlling the operation and input / output of memory cells in the memory region R2, such as drivers, buffers, amplifiers, and decoders. The memory region R2 may contain a memory array composed of memory cells, such as a dynamic random access memory (DRAM) array. It should be specifically noted that... Figure 1 The shapes and layouts of the peripheral region R1 and memory region R2 shown are for illustrative purposes only and are not intended to limit the invention.

[0050] like Figure 2As shown, components of a semiconductor structure can be formed on the peripheral region R1 and memory region R2 of substrate 10 using the same manufacturing process. Examples include an isolation structure 14 disposed in substrate 10, multiple bit lines BL disposed on substrate 10, spacer walls 32 disposed on the sidewalls of the bit lines BL, a first dielectric layer 34 disposed on substrate 10 and filling the spaces between the bit lines BL, and a second dielectric layer 36 disposed on the first dielectric layer 34. Buried word lines (not shown) may also be provided in the memory region R2 of substrate 10, cutting through the active regions of memory cells to form buried gates of the memory cells. The isolation structure 14 is, for example, a shallow trench isolation (STI) structure, used to define the active regions of a semiconductor device (not shown) in the peripheral region R1 of substrate 10, and simultaneously define the active regions of memory cells (not shown) in the memory region R2 of substrate 10. The isolation structure 14 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or a combination of the above materials, but is not limited thereto. The bit line BL is disposed on the memory region R2 of the substrate 10 and partially overlaps with the active region. Figure 2As shown, the bit line BL may include a stacked structure, which, from bottom to top, may sequentially include a semiconductor layer 22, a metal layer 24, and a hard mask layer 26. The material of the semiconductor layer 22 may include single-crystal silicon, polysilicon, amorphous silicon, or other silicon-containing or silicon-free semiconductor materials. The material of the metal layer 24 may include aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium-aluminum alloy (TiAl), or other suitable low-resistivity metal materials. The hard mask layer 26 may include a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or other suitable dielectric materials. In some embodiments, an interface layer (not shown) may be included between the semiconductor layer 22 and the metal layer 24, for example, a single layer or stack composed of titanium (Ti), tungsten silicide (WSi), tungsten nitride (WN), other suitable metal silicides, and / or metal nitrides. The material of the spacer wall 32 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or other suitable dielectric materials, and may have a single-layer or multi-layer structure. The spacer wall 32 can protect the bit line BL and facilitate the connection between the bit line BL and the memory node contact 44 (see reference) in subsequent manufacturing processes. Figure 9 Electrical isolation between the substrate 10 and the memory region R2. A first dielectric layer 34 is disposed entirely on the peripheral region R1 and the memory region R2 of the substrate 10 and fills the gap between the bit lines BL. The top surface of the first dielectric layer 34 can be planarized to be flush with the top surface of the bit lines BL (the top surface of the hard mask portion 26). A second dielectric layer 36 completely covers the first dielectric layer 34 for subsequent recess processes E1 (see reference). Figure 9 The first dielectric layer 34 and the second dielectric layer 36 serve as an etching buffer layer to protect the underlying structure (e.g., bit line BL). The materials of the first dielectric layer 34 and the second dielectric layer 36 may respectively include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or other suitable dielectric materials. According to one embodiment of the present invention, the first dielectric layer 34 may include silicon oxide, and the second dielectric layer 36 may include silicon nitride, but is not limited thereto. The methods for manufacturing the isolation structure 14, the bit line BL, the spacer 32, the first dielectric layer 34, and the second dielectric layer 36 are well known in the art and will not be described in detail herein.

[0051] Please refer to Figure 3 and Figure 4 Then, one or more patterning processes (e.g., lithography and etching processes) can be performed to form the first opening OP1 and the second opening OP2 in the peripheral region R1 and the memory region R2, respectively. For example... Figure 3 and Figure 4As shown, the peripheral region R1 may include multiple first openings OP1, which pass through the second dielectric layer 36 and extend into the first dielectric layer 34, but do not penetrate the first dielectric layer 34. The positions of the first openings OP1 are determined according to the interconnect structure 42 (reference). Figure 8 and Figure 9 The first opening OP1 can be designed to be located anywhere on the interconnect structure 42, such as at bends in the interconnect structure 42, but is not limited thereto. From a plan view, the first opening OP1 can be irregularly arranged and can have different sizes. The second opening OP2 is located between bit lines BL, passing through the second dielectric layer 36 and the first dielectric layer 34 of the memory region R2 and exposing a portion of the surface of the substrate 10. The location of the second opening OP2 is determined based on the active region of the memory cell (not shown) and the memory node contact 44 (see reference 44). Figure 9 The location of the second opening OP2 is designed accordingly. From the plan view, the second opening OP2 can be arranged in an array and has approximately the same size.

[0052] Please refer to Figure 5Next, an epitaxial growth process can be performed to form a semiconductor layer 16 at the bottom of the second opening OP2. Then, a deposition process is performed to form a liner 38a along the surface of the second dielectric layer 36, the sidewalls of the first opening OP1, and the bottom surface of the second opening OP2. A conductive layer 38 is then formed on the liner 38a, filling the first opening OP1 and the second opening OP2. Suitable deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The semiconductor layer 16 is in direct contact with the substrate 10, and the material may include, but is not limited to, single-crystal silicon, polysilicon, or silicon-phosphorus (SiP). In some embodiments, the substrate 10 exposed from the second opening OP2 is also partially etched away during etching of the second opening OP2, increasing the depth of the second opening OP2 and thus increasing the contact area between the semiconductor layer 16 and the substrate 10. The liner 38a and the conductive layer 38 may each comprise a metal, a metal compound, or an alloy. For example, the substrate 38a may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium-tungsten (Ti / W), or combinations thereof, but is not limited thereto; the conductive layer 38 may include aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum (TiAl) alloy, or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, the substrate 38a may include titanium nitride (TiN), and the conductive layer 38 may include tungsten (W). In some embodiments, a metal silicide layer (not shown) may also be included between the substrate 38a and the semiconductor layer 16. The material may include titanium silicide (TiSix), tungsten silicide (WSix), tantalum silicide (TaSix), molybdenum silicide (MoSix), cobalt silicide (CoSix), or nickel silicide (NiSix), or combinations thereof, but is not limited thereto. A planarization process (e.g., etch-back and / or chemical mechanical polishing) can be performed on the conductive layer 38 to remove excess conductive layer 38 until the conductive layer 38 of the peripheral region R1 and the memory region R2 has a flat surface and a predetermined thickness.

[0053] Please refer to Figure 6 and Figure 7Next, a mask material layer (e.g., a photoresist layer or a dielectric material layer) can be formed comprehensively on the conductive layer 38 of the peripheral region R1 and the memory region R2. Then, the excess portion of the mask material layer is removed by exposure development or etching to form a patterned mask layer 40 on the conductive layer 38. According to an embodiment of the present invention, as Figure 6 As shown, the mask layer 40 of the peripheral region R1 may include multiple wiring patterns, wherein, according to the interconnect structure 42 (reference... Figure 8 and Figure 9 The design allows for irregularly arranged trace patterns with varying sizes. The first opening OP1 is located between the ends of two adjacent trace patterns, partially overlapping the ends of the trace patterns in the vertical direction. According to a preferred embodiment of the invention, as... Figure 6 As shown, the wiring patterns of the mask layer 40 in the peripheral region R1 are all straight-line patterns, without any bends. The mask layer 40 in the memory region R2 may include multiple island-shaped patterns, which are respectively arranged in an array corresponding to the second opening OP2. According to an embodiment of the present invention, each island-shaped pattern and the corresponding second opening OP2 are offset and partially overlap in the vertical direction, and have approximately the same size.

[0054] Please refer to Figure 8 and Figure 9 Next, a recess process E1 (e.g., dry etching) is performed on the conductive layer 38 to etch away the conductive layer 38, the substrate 38a, and the second dielectric layer 36 exposed from the mask layer 40, thereby forming a recess RE that passes through the conductive layer 38 and the substrate 38a and extends into a portion of the second dielectric layer 36. This patternes the conductive layer 38 in the peripheral region R1 into the interconnect structure 42, and simultaneously patterns the conductive layer 38 in the memory region R2 into the memory node contact structure 44. It is worth noting that most of the conductive layer 38 filling the first opening OP1 and the second opening OP2 will remain in the first opening OP1 and the second opening OP2 after the recess process E1, becoming part of the interconnect structure 42 and the memory node contact structure 44 (i.e., the U-shaped portion 42a and the plug portion 44a), respectively.

[0055] In detail, such as Figure 9 Intermediate legend (along) Figure 8The image shows a cross-sectional view of the BB' tangent (the BB' tangent is the tangent along the trace of the interconnect structure 42). The interconnect structure 42 includes an integrally formed U-shaped portion 42a and a horizontally extending portion 42b. The horizontally extending portion 42b is located directly above the second dielectric layer 36 and is formed by transferring the trace pattern of the mask layer 40 of the peripheral region R1 to the conductive layer 38. It is the main part of the trace of the interconnect structure 42. According to an embodiment of the present invention, the horizontally extending portions 42b are all straight and do not include bends. The U-shaped portion 42a connects the adjacent ends S1 of the two horizontally extending portions 42b and passes through the second dielectric layer 36 and a portion of the first dielectric layer 34. The U-shaped portion 42a is formed by the conductive layer 38 filling the first opening OP1, and its location is determined by the location of the first opening OP1. It can be located at any part of the trace of the interconnect structure 42. For example, Figure 8 As shown, the U-shaped portion 42a can be located at the bend of the interconnect structure 42 trace, serving as a connector between two staggered horizontal extension portions 42b. In this case, the end S1 of the horizontal extension portion 42b connected to one end of the U-shaped portion 42a is not located on the length extension line of the horizontal extension portion 42b connected to the other end of the U-shaped portion 42a. That is, the line connecting the ends S1 of adjacent horizontal extension portions 42b is not parallel to the length extension line of the horizontal extension portion 42b. Figure 9 Legend on the right (along) Figure 8 As shown in the cross-sectional view along the CC' tangent, the storage node contact structure 44 may include an integrally formed plug portion 44a and a contact pad portion 44b located on the plug portion 44a. The plug portion 44a is formed by a conductive layer 38 filled in the second opening OP2, and the contact pad portion 44b is formed by transferring the island pattern of the mask layer 40 to the conductive layer 38. According to an embodiment of the present invention, the plug portion 44a and the contact pad portion 44b partially overlap in the vertical direction and include a misalignment.

[0056] Please refer to Figure 10 and Figure 11Next, a deposition process (e.g., chemical deposition, physical vapor deposition, or atomic layer deposition) can be performed to form a third dielectric layer 54 on the second dielectric layer 36, filling the recesses RE between interconnect structures 42 and between memory node contact structures 44. Then, a planarization process (e.g., etch-back and / or chemical mechanical polishing) is performed to remove excess third dielectric layer 54 beyond the recesses RE until the top surfaces of the interconnect structures 42 and memory node contact structures 44 are exposed. The material of the third dielectric layer 54 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations thereof, but is not limited to these. According to one embodiment of the present invention, the third dielectric layer 54 may include silicon nitride (SiN). From a plan view, as... Figure 10 As shown, after the planarization process, only the horizontal extension portion 42b of the interconnect structure 42 is exposed from the surface of the third dielectric layer 54, and only the contact pad portion 44b of the storage node contact structure 44 is exposed from the surface of the third dielectric layer 54. The third dielectric layer 54 completely covers the top surface of the U-shaped portion 42a and surrounds the adjacent end S1 of the horizontal extension portion 42b connected to the U-shaped portion 42a. The third dielectric layer 54 can directly contact the sidewall of the horizontal extension portion 42b and the top surface of the U-shaped portion 42a, such as... Figure 11 The legends on the left and in the middle are shown.

[0057] Please refer to Figure 12 The drawing is shown as Figure 11 Another embodiment of the semiconductor structure shown is presented. (Performance...) Figure 9 During the recess process E1, it is possible to etch the recess process E1 further down, giving the recess RE a deeper depth. For example, the recess RE in the peripheral region R1 can pass through the conductive layer 38, the substrate 38a, the second dielectric layer 36, and extend into the first dielectric layer 34; the recess RE in the memory region R2 can pass through the conductive layer 38, the substrate 38a, the second dielectric layer 36, and extend into the hard mask layer 26. Therefore, as... Figure 12 As shown, the bottom surface of the third dielectric layer 54, which fills the recesses RE in the peripheral region R1 and the memory region R2, is lower than the bottom surface of the second dielectric layer 36.

[0058] Please refer to Figure 13 The drawing is shown as Figure 11 Another embodiment of the semiconductor structure shown. When the depth of the recess RE of the U-shaped portion 42a is deeper or the aspect ratio is larger, the third dielectric layer 54 may not completely fill the recess RE of the U-shaped portion 42a, but instead surround an air gap 56 within the recess RE. In other embodiments, the air gap 56 may be surrounded by both the U-shaped portion 42a and the third dielectric layer 54.

[0059] In conventional techniques for fabricating interconnect structures, the wiring patterns (including straight and bent patterns) are typically defined in a mask layer, followed by etching or recessed processes to transfer the mask pattern to a conductive layer. However, as linewidths and spacing gradually decrease, it becomes increasingly difficult to define ideal wiring patterns in the mask layer. For example, pattern anomalies often occur at the bends of the wiring, leading to defects such as linewidth contraction or broken lines in the interconnect structure formed after transfer to the conductive layer. This invention utilizes a U-shaped portion 42a as a connector between the horizontally extending portions 42b to achieve the bends in the interconnect structure 42. This eliminates the need to form any bent wiring patterns in the mask layer 40, avoiding the linewidth contraction or broken line problems encountered in conventional techniques and ensuring the conductivity quality of the interconnect structure 42. In addition, in some embodiments of the present invention, the first opening OP1 may be made to penetrate the first dielectric layer 34 and expose the active region of the substrate 10. Therefore, the U-shaped portion 42a can directly contact and be electrically connected to the active region of the substrate 10 in the peripheral region R1, so that the U-shaped portion 42a can not only serve as a connector between the horizontal extension portions 42b, but also be used to realize the electrical connection between the horizontal extension portions 42b and the active region of the substrate 10.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A substrate; A first dielectric layer is located on the substrate; A second dielectric layer is located on the first dielectric layer; as well as An interconnection structure, including: At least two horizontally extending portions are located on the second dielectric layer; and A U-shaped portion passes through the second dielectric layer and a portion of the first dielectric layer and connects between the adjacent ends of the two horizontally extending portions; The two horizontal extension portions and the U-shaped portion are integrally formed. From the plan view, the line connecting the adjacent ends of the two horizontal extension portions is not parallel to the extension line of either of the two horizontal extension portions in the length direction.

2. The semiconductor structure as described in claim 1, characterized in that, It also includes a liner disposed between the interconnect structure and the first dielectric layer and the second dielectric layer.

3. The semiconductor structure as described in claim 1, characterized in that, It also includes a third dielectric layer disposed on the second dielectric layer and filling the depression of the U-shaped portion.

4. The semiconductor structure as described in claim 3, characterized in that, The top surface of the third dielectric layer is flush with the top surfaces of the two horizontally extended portions.

5. The semiconductor structure as described in claim 3, characterized in that, The third medium layer surrounds an air gap in the recess of the U-shaped portion.

6. The semiconductor structure as described in claim 3, characterized in that, The bottom surface of the third dielectric layer is lower than the bottom surface of the two horizontally extending portions.

7. The semiconductor structure as described in claim 3, characterized in that, The third dielectric layer is in direct contact with the sidewalls of the two horizontally extending portions and the top surface of the U-shaped portion.

8. The semiconductor structure as described in claim 3, characterized in that, From the plan view, the adjacent ends of the two horizontally extending portions are surrounded by the third dielectric layer.

9. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a substrate; A first dielectric layer is formed on the substrate; A second dielectric layer is formed on the first dielectric layer; Forming at least one first opening through the second dielectric layer and a portion of the first dielectric layer; A conductive layer is formed on the second dielectric layer and filled into the first opening; as well as A recessed process is performed on the conductive layer to form an interconnect structure, wherein the interconnect structure includes: at least two horizontally extending portions located on the second dielectric layer; and A U-shaped portion passes through the second dielectric layer and a portion of the first dielectric layer and connects between the adjacent ends of the two horizontally extending portions; In the plan view, the line connecting the adjacent ends of the two horizontal extensions is not parallel to the extension line along the length of either of the two horizontal extensions.

10. The method for manufacturing a semiconductor structure as described in claim 9, characterized in that, The two horizontally extending portions are integrally formed with the U-shaped portion.

11. The method for manufacturing a semiconductor structure as described in claim 9, characterized in that, Also includes: A liner is formed along the surface of the second dielectric layer and the sidewalls and bottom surface of the first opening; as well as The conductive layer is formed on the liner.

12. The method for manufacturing a semiconductor structure as described in claim 9, characterized in that, Also includes: A third dielectric layer is formed on the second dielectric layer: and Remove part of the third dielectric layer until the top surfaces of the two horizontally extending portions are exposed.

13. The method for manufacturing a semiconductor structure as described in claim 12, characterized in that, The bottom surface of the third dielectric layer is lower than the bottom surface of the two horizontally extending portions.

14. The method for manufacturing a semiconductor structure as described in claim 12, characterized in that, The third dielectric layer is in direct contact with the sidewalls of the two horizontally extending portions and the top surface of the U-shaped portion.

15. The method for manufacturing a semiconductor structure as described in claim 12, characterized in that, The third medium layer surrounds an air gap in the recess of the U-shaped portion.

16. The method for manufacturing a semiconductor structure as described in claim 12, characterized in that, From the plan view, the adjacent ends of the two horizontally extending portions are surrounded by the third dielectric layer.

17. The method for manufacturing a semiconductor structure as described in claim 9, characterized in that, Also includes: Yu Multiple bit lines are formed on the substrate; The first dielectric layer is formed to fill the gaps between the bit lines; The second dielectric layer is formed on the first dielectric layer and the plurality of bit lines; Multiple second openings are formed, located between the multiple bit lines and penetrating the second dielectric layer and the first dielectric layer; The conductive layer is formed on the plurality of bit lines and fills the plurality of second openings; as well as The conductive layer is subjected to the recess process to form multiple memory node contact structures, wherein each memory node contact structure includes: A plug portion is located in the second opening; as well as A contact pad portion is located above the plug portion, and the top surfaces of the two horizontally extending portions are flush with the top surface of the contact pad portion.

Images