Integrated circuit memory device and variable resistance memory device

Abstract

An integrated circuit memory device and a variable resistance memory device are provided. The integrated circuit memory device includes a plurality of row select transistors and dummy row select transistors on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells electrically connected to corresponding word lines of the plurality of word lines are provided. A plurality of dummy memory cells electrically connected to corresponding dummy word lines of the plurality of dummy word lines are provided. A first wiring structure electrically connecting a first word line of the plurality of word lines to a first row select transistor of the plurality of row select transistors is provided, and a second wiring structure electrically connecting the plurality of dummy word lines together and electrically connecting the plurality of dummy word lines to the dummy row select transistors is provided.

Description

Technical Field

[0001] The example implementation relates to integrated circuit devices, and more specifically, to integrated circuit memory devices. Background Technology

[0002] To achieve high integration, variable resistive memory devices can utilize a cell-on-periphery (COP) structure. Using this structure, a variable resistive memory device can include word lines, bit lines, and memory cells, with each memory cell potentially adjacent to the intersection of one of the word lines and one of the bit lines. The variable resistive memory device can also include dummy word lines, dummy bit lines, and dummy memory cells. Each dummy memory cell can be connected to a dummy word line and / or a dummy bit line. The word lines and bit lines can be electrically connected to transistors formed within the substrate. Furthermore, the dummy word lines and dummy bit lines can also be electrically connected to transistors formed within the substrate. Summary of the Invention

[0003] The example implementation provides a highly integrated variable resistance storage device.

[0004] According to these exemplary embodiments, a variable resistive memory device is provided, which may include: a row select transistor on a substrate; a dummy row select transistor on the substrate; word lines and dummy word lines disposed on the row select transistor and the dummy row select transistor; bit lines disposed on the word lines and the dummy word lines; a memory cell structure; a dummy memory cell structure; a first wiring structure connecting one of the word lines and one of the row select transistors to each other; and a second wiring structure connecting the dummy word lines and the dummy row select transistors. The word lines and dummy word lines may extend in a first direction parallel to the surface of the substrate. The bit lines may extend in a second direction perpendicular to the first direction. Each memory cell structure may be connected to one of the word lines and one of the bit lines. Each dummy memory cell structure may be connected to one of the dummy word lines and one of the bit lines. The ends of the dummy word lines may be merged together by the second wiring structure.

[0005] According to another example embodiment, a variable resistive memory device is provided, which may include: a memory cell disposed at the intersection of a word line and a bit line; a dummy memory cell connected to a dummy word line; a row select transistor for controlling the word line; a dummy row select transistor for controlling the dummy word line; a first wiring connecting the word line and the row select transistor; and a second wiring connecting the dummy word line and the dummy row select transistor. The number of row select transistors may be equal to the number of word lines, but the number of dummy row select transistors may be less than the number of dummy word lines. The ends of the second dummy word line may also be merged together, and the second dummy row select transistor may be electrically connected to the merged second dummy word line.

[0006] According to another embodiment, a variable resistive memory device is provided, which may include: a memory cell disposed at the intersection of a word line and a bit line; a dummy memory cell connected to a dummy word line; a row select transistor for controlling the word line; and a dummy row select transistor for controlling the dummy word line. Each row select transistor can be connected to a corresponding word line. Moreover, the ends of the dummy word lines can be merged together. The dummy row select transistor can be electrically connected to the merged dummy word line.

[0007] According to another embodiment, an integrated circuit memory device may include a plurality of row select transistors and dummy row select transistors on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells electrically connected to corresponding word lines among the plurality of word lines are also provided. Furthermore, a plurality of dummy memory cells electrically connected to corresponding dummy word lines among the plurality of dummy word lines are provided. A first wiring structure is provided that electrically connects a first word line among the plurality of word lines to a first row select transistor among the plurality of row select transistors. A second wiring structure is provided that electrically connects the plurality of dummy word lines together and electrically connects the plurality of dummy word lines to the dummy row select transistors. A plurality of bit lines may also be provided, perpendicularly spaced from the plurality of word lines and the plurality of dummy word lines and electrically connected to corresponding memory cells among the plurality of memory cells. Moreover, a plurality of dummy bit lines may be provided, electrically connected to corresponding dummy memory cells among the plurality of dummy memory cells and electrically connected together.

[0008] In another embodiment, the variable resistance memory device may include select transistors electrically connected to multiple dummy word lines. That is, a select transistor may not be required for each dummy word line. Therefore, the total number of select transistors can be reduced, and the chip size of the variable resistance memory device can also be reduced. Attached Figure Description

[0009] The exemplary implementation will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 13 Examples of implementations are embodied as described herein and are non-limiting.

[0010] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment;

[0011] Figure 2 This is a schematic plan view illustrating an array of memory cells in a variable resistive storage device according to an exemplary embodiment;

[0012] Figure 3 This is a cross-sectional view showing a portion of the memory cell array and peripheral circuitry in a variable resistive storage device according to an example embodiment;

[0013] Figure 4This is a circuit diagram illustrating an example of a memory cell array in a variable resistive storage device according to an exemplary embodiment;

[0014] Figure 5 This is a circuit diagram of a portion of a variable resistance storage device according to an example embodiment;

[0015] Figure 6 This is a circuit diagram of a portion of a variable resistance storage device according to an example embodiment;

[0016] Figures 7 to 11 This is a layout diagram showing a portion of a variable resistance storage device; and

[0017] Figure 12 and Figure 13 This is a cross-sectional view showing a variable resistive storage device including an array of memory cells according to an example embodiment. Detailed Implementation

[0018] In the following text, a direction parallel to the upper surface of the substrate is referred to as the first direction, and a direction parallel to the upper surface of the substrate and perpendicular to the first direction is referred to as the second direction. A direction perpendicular to the upper surface of the substrate is referred to as the perpendicular direction.

[0019] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present invention. Referring now to... Figure 1 The storage device 1200 may include a storage cell array 1210, a write / read circuit 1400, and a control circuit 1300. The storage device 1200 may also include a row decoder 1220, a column decoder 1230, a voltage generator 1240, and a reference signal generator 1250. Furthermore, the write / read circuit 1400 may include a write driver (WD) 1410, a read circuit 1420 (e.g., a sense amplifier (SA) circuit), a write buffer (WB) 1430, a page buffer (PB) 1440, and a verification circuit 1450.

[0020] The memory cells within the memory cell array 1210 can be connected to word lines WL and bit lines BL. When various voltage or current signals are supplied through the bit lines BL and word lines WL, data can be written to or read from the selected memory cells; it can also prevent data from being written to or read from unselected memory cells.

[0021] The address ADDR indicating the accessed memory cell can be received by the control circuitry 1300 according to the command CMD. The address ADDR may include a row address R_ADDR for selecting word lines WL in the memory cell array 1210 and a column address C_ADDR for selecting bit lines BL in the memory cell array 1210. The row decoder 1220 can perform a word line selection operation in response to the row address R_ADDR, and the column decoder 1230 can perform a bit line selection operation in response to the column address C_ADDR.

[0022] The write / read circuit 1400 can be connected to the bit line BL. Therefore, the write / read circuit 1400 can write data to or read data from the memory cell array. The write / read circuit 1400 can be connected to the row decoder 1220 and the column decoder 1230.

[0023] For example, during a write operation, a set voltage (VST) or reset voltage (VRST) generated at voltage generator 1240 can be supplied to the selected memory cell, and inhibit voltages Vinhx and Vinhy can be supplied to unselected word lines and unselected bit lines. During a read operation, a read voltage VRD generated at voltage generator 1240 can be supplied to the selected memory cell. The write / read circuit 1400 can supply write voltage or write current to the memory cell array 1210 according to the data via column decoder 1230. The write / read circuit 1400 may include a verification section for distinguishing data during a read operation. The verification section may be connected to a node (e.g., a sensing node) of bit line BL and can compare the sensed voltage or sensed current at the sensing node so that data in the selected memory cell can be read. A reference voltage VREF and / or a reference current IREF generated at reference signal generator 1250 can be supplied to the write / read circuit 1400, so the reference voltage VREF and / or the reference current IREF can be used to distinguish data during a read operation.

[0024] The write / read circuit 1400 can supply a pass / fail signal P / F to the control circuit 1300. The pass / fail signal P / F can indicate whether a write or read operation was successful. The control circuit 1300 can refer to the pass / fail signal P / F to control write and read operations in the memory cell array 1210.

[0025] The control circuit 1300 can generate multiple control signals CTL1 to CTL5 based on the command CMD, address ADDR, control signal CTRL, and pass / fail signal P / F. The first control signal CTL1 can be supplied to the voltage generator 1240, the second control signal CTL2 can be supplied to the reference signal generator 1250, and the third control signal CTL3 can be supplied to the write / read circuit 1400. The fourth control signal CTL4 can be supplied to the row decoder 1220 (as the row address R_ADDR), and the fifth control signal CTL5 can be supplied to the column decoder 1230 (as the column address C_ADDR).

[0026] Figure 2 This is a schematic plan view illustrating an array of memory cells in a variable resistive storage device according to an example embodiment. Figure 3 This is a cross-sectional view showing a portion of the memory cell array and peripheral circuitry in a variable resistive storage device according to an example embodiment. Figure 4 This is a circuit diagram illustrating an example of a memory cell array in a variable resistive memory device according to an exemplary embodiment.

[0027] A storage cell array can include multiple cell blocks. Figure 4 A cell block is shown. A variable resistive storage device may include a storage cell array 1210 (see reference). Figure 1 ) and peripheral circuitry. Peripheral circuitry may include, for example, reference... Figure 1 The description includes the write / read circuit 1400, control circuit 1300, row decoder 1220, column decoder 1230, voltage generator 1240, and reference signal generator 1250.

[0028] Reference Figures 2 to 4 The memory cell array may include multiple word lines (WL) 200, multiple dummy word lines (DWL) 202, multiple bit lines (BL) 230, multiple dummy bit lines (DBL), multiple memory cell structures 220, and multiple dummy memory cell structures 222. Furthermore, memory cell structures 220 connected to the same word line (WL) 200 may be defined as page cells.

[0029] The variable resistance storage device can be formed on the substrate 100, such as Figure 3 As shown. Substrate 100 may include semiconductor materials such as silicon, germanium, or silicon-germanium, or III-V semiconductor compounds such as GaP, GaAs, or GaSb. In some example embodiments, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0030] The variable resistance memory device may have a cell-on-periphery (COP) structure, which includes peripheral circuitry formed on the substrate 100 and memory cells stacked on the peripheral circuitry.

[0031] The substrate 100 can be divided into active regions and isolation regions. The isolation regions can be areas in which isolation patterns 102 comprising insulating material are formed to fill trenches (e.g., shallow trenches) in the substrate 100. In some embodiments, the active and isolation regions can be formed using a shallow trench isolation (STI) process.

[0032] A transistor 110 for configuring peripheral circuitry and first lower wirings 130a, 130b, 130c, 130d, and 130e for electrically connecting the transistor 110 can be formed on a substrate 100. The first lower wirings 130a, 130b, 130c, 130d, and 130e may include conductive patterns 130b and 130d and contact plugs 130a, 130c, and 130e. For example... Figure 3 As shown, the first lower wirings 130a, 130b, 130c, 130d and 130e can have a multi-layer structure.

[0033] The lower insulating layers 140a, 140b, and 140c can be formed to cover the peripheral circuitry. The upper surface of each of the lower insulating layers 140a, 140b, and 140c can be substantially flat (e.g., planarized). Furthermore, a memory cell array can be formed on the uppermost lower insulating layer 140c. For example, word lines 200 (hereinafter also referred to as first word lines 200) and dummy word lines 202 (hereinafter also referred to as first dummy word lines 202) can be formed on the uppermost lower insulating layer 140c. The word lines 200 can extend in a first direction D1 and can be spaced apart from each other in a second direction D2.

[0034] The memory cell structure and the dummy memory cell structure constitute a cell block. In an example embodiment, the dummy word lines 202 may be disposed at the edge portion of the cell block in the second direction D2. The dummy word lines 202 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. Figure 2 and Figure 4 As shown, the dummy word line DWL can be adjacent to the word line WL located at the edge portion of the cell block in the second direction D2.

[0035] Bit line 230 and dummy bit line DBL can be formed on word line 200 and on dummy word line 202. Bit line 230 and dummy bit line DBL can be spaced apart from word line 200 and dummy word line 202 in the vertical direction. Bit line 230 can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0036] In an example implementation, a dummy bit line DBL may be disposed at the edge portion of the cell block in the first direction D1. The dummy bit line DBL may extend in the second direction D2, and the dummy bit lines DBL may be spaced apart from each other in the first direction D1. The dummy bit line DBL may be adjacent to a bit line BL disposed at the edge portion of the cell block in the first direction D1.

[0037] When word lines and bit lines with fine widths and spacing are formed using a patterning process, word lines and bit lines located at the edge portions may not be patterned to have the target linewidth and target spacing due to the etching load effect. Therefore, as mentioned above, multiple word lines and bit lines located at the edge portions of a cell block can be used as dummy word lines and dummy bit lines that do not actually perform any operations. Figure 2 The diagram shows only four (4) dummy word lines (DWL) and four (4) dummy bit lines (DBL), but the number of dummy word lines and dummy bit lines is not limited to this. Each memory cell structure 220 (hereinafter also referred to as the first memory cell structure 220) can be located at the intersection of one of the word lines 200 and one of the bit lines 230; and each memory cell structure 220 can be electrically connected to one of the word lines 200 and one of the bit lines 230.

[0038] The memory cell structure 220 may include at least a selector 212 and a variable resistor 216, with the variable resistor 216 operating as a memory storage unit. In an example embodiment, the memory cell structure 220 may include a stack of a lower electrode 210, a selector 212, an intermediate electrode 214, a variable resistor 216, and an upper electrode 218. The memory cell structure 220 can be used as individual memory cells.

[0039] The variable resistor 216 may be referred to as a variable resistive device or variable resistive material, and the selection device 212 may be referred to as a switching device, which is used to "access" the variable resistive device. In the example embodiment, the lower electrode 210 may contact the upper surface of one of the word lines 200, and the upper electrode 218 may contact the lower surface of one of the bit lines 230. The variable resistor 216 may be disposed between one of the bit lines 230 and the selection device 212, and the variable resistor 216 may be electrically connected to one of the bit lines 230 and the selection device 212. The selection device 212 may be disposed between one of the word lines 200 and the variable resistor 216, and the selection device 212 may be electrically connected to the variable resistor 216 and the corresponding word line 200.

[0040] Each dummy memory cell structure 222 (hereinafter also referred to as a first dummy memory cell structure 222) can be connected to a dummy word line 202 and / or a dummy bit line DBL. Therefore, a corresponding dummy memory cell structure 222 can be located at the intersection of one of the dummy word lines 202 and one of the bit lines 230. Furthermore, some of the dummy memory cell structures 222 can be located at the intersection of one of the word lines 200 and one of the dummy bit lines DBL. Furthermore, some of the dummy memory cell structures 222 can be located at the intersection of one of the dummy word lines 202 and one of the dummy bit lines DBL. Therefore, a corresponding dummy memory cell structure in the dummy memory cell structure 222 can be connected to one of the dummy word lines 202 and / or one of the dummy bit lines DBL. Those skilled in the art will understand that the dummy memory cell structure 222 can be used as a dummy memory cell in which no data is stored. Nevertheless, the virtual storage cell structure 222 offers other advantages, as described herein.

[0041] The dummy memory cell structure 222 may have a stacked structure substantially the same as that of the memory cell structure 220. For example, the dummy memory cell structure 222 may include a vertical stack of a lower electrode 210, a select device 212, an intermediate electrode 214, a variable resistor 216, and an upper electrode 218. The lower electrode 210 may include, for example, metal nitrides (such as titanium nitride (TiNx), tungsten nitride (WNx), and tantalum nitride (TaNx)) or metal silicon nitrides (such as titanium silicon nitride (TiSiNx)). The select device 212 may include a bidirectional threshold switch (OTS) material that switches on and off based on the difference in resistances according to the applied voltage while remaining amorphous. In an example embodiment, the OTS material may include, for example, germanium (Ge), silicon (Si), arsenic (As), and / or tellurium (Te). Furthermore, the OTS material may also include, for example, selenium (Se), sulfur (S), carbon (C), nitrogen (N), indium (In), boron (B), or similar materials. Therefore, in some embodiments, the OTS material may include, for example: AsTeGeSiIn, GeTe, SnTe, GeSe, SnSe, AsTeGeSiSbS, AsTeGeSiInP, AsTeGeSi, As2Te3Ge, As2Se3Ge, As... 25 (Te 90 Ge 10 ) 75 Te 40 As 35 Si 18 Ge 6.75 In 0.25 Te 28 As 34.5 Ge15.5 S 22 Te 39 As 36 Si 17 Ge7P, As 10 Te 21 S2Ge 15 Se 50 Sb2, Si5Te 34 As 28 Ge 11 S 21 Se1, AsTeGeSiSeNS, AsTeGeSiP, AsSe, AsGeSe, AsTeGeSe, ZnTe, GeTePb, GeSeTe, AlAsTe, SeAsGeC, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, GeAsBiSe, Ge x Se 1-x .

[0042] The variable resistor 216 may include a material whose resistance changes according to a phase transition in its material structure. In an example embodiment, the variable resistor 216 may include a chalcogenide-based material in which germanium (Ge), antimony (Sb), and / or tellurium (Te) are combined in a predetermined ratio. In an example embodiment, the variable resistor 216 may include a superlattice in which germanium-tellurium (GeTe) and antimony-tellurium (SbTe) are repeatedly stacked. In an example embodiment, the variable resistor 216 may include an IST containing indium antimony-tellurium or a BST containing bismuth antimony-tellurium. The variable resistor 216 may also include, for example, carbon (C), nitrogen (N), boron (B), and oxygen (O).

[0043] In an example implementation, the variable resistor 216 may comprise a perovskite-based material or a transition metal oxide. Perovskite-based materials may include, for example, STO (SrTiO3), BTO (BaTiO3), or PCMO (PrTiO3). 1-X Ca X MnO3). Transition metal oxides may include, for example, titanium oxide (TiOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), and hafnium oxide (HfOx). According to some embodiments, these materials may be used alone or in combination of two or more.

[0044] The intermediate electrode 214 and the upper electrode 218 may include metal nitrides, such as titanium nitride (TiNx), tungsten nitride (WNx), and tantalum nitride (TaNx); however, in other embodiments, the intermediate electrode 214 may be omitted.

[0045] The first insulating layer 224 and the second insulating layer 226 can fill the space between word line 200 and dummy word line 202, as well as the space between memory cell structure 220 and dummy memory cell structure 222. Contact plugs 130f and 130g can pass through the first insulating layer 224, the second insulating layer 226, and the lower insulating layers 140b and 140c. Furthermore, contact plugs 130f and 130g can be electrically connected to the bit line 230 and peripheral circuitry on the substrate 100. Word line 200 can be connected to transistor 110 via first lower wirings 130a, 130b, 130c, 130d, and 130e, as shown. In contrast, dummy word line 202 can be merged into a single line via first lower wirings 130a, 130b, 130c, 130d, and 130e. In the example implementation, at least two dummy word lines 202 can be merged into one through first bottom wirings 130a, 130b, 130c, 130d, and 130e, meaning that at least some of the dummy word lines can be electrically connected to each other. Furthermore, the merged dummy word lines can be connected to one of the transistors 110.

[0046] Figure 5 This is a circuit diagram of a portion of a variable resistance storage device according to an example embodiment. Specifically, Figure 5 This shows a portion of the line decoder connected to the word line and the dummy word line. Figure 5 For ease of description, only eight (8) character lines and four (4) dummy character lines are shown. (See reference...) Figure 5 The memory cell MC can be connected to word lines WL1 to WL8 and bit lines BL1 to BLn. The dummy memory cell DMC can be connected to dummy word lines DWL1 to DWL4 and to bit lines BL1 to BLn. Figure 5 In order to reduce the complexity of the attached diagram, the dummy bit lines have been omitted.

[0047] The memory cell MC and the dummy memory cell DMC can have the same stacking structure as the memory cell structure 220 and the dummy memory cell structure 222 described above. The row decoder may include a pre-decoder (not shown), row selection transistors LX1 and LX2, global row selection transistors GX1 to GX4 (GX1, GX2, GX3 and GX4), and a first transistor GXq1. The first transistor GXq1 may be electrically connected to the data sensing node SDL and the negative voltage VNEG.

[0048] In the following text, each transistor may include a gate structure 106 (see reference). Figure 3 ), first impurity region 104a (refer to) Figure 3 ) and second impurity region 104b (reference) Figure 3The first impurity region 104a and the second impurity region 104b can be used as source / drain regions. In the example embodiment, row selection transistors LX1 and LX2, global row selection transistors GX1 to GX4, and the first transistor GXq1 can be NMOS transistors.

[0049] Word lines WL1 to WL8 can be connected to the first sludge regions of row select transistors LX1 and LX2, respectively. That is, one of word lines WL1 to WL8 can be connected to the first sludge region of one of row select transistors LX1 and LX2. Therefore, the number of row select transistors LX1 and LX2 can be equal to the number of word lines WL1 to WL8.

[0050] In an example implementation, word lines WL1 to WL8 may include a first word line group WL1, WL2, WL3, and WL4, and a second word line group WL5, WL6, WL7, and WL8. Gates included in the first row select transistor LX1 connected to the first word line groups WL1, WL2, WL3, and WL4 may be electrically connected to each other, and these gates may serve as the common gate of the first row select transistor LX1. Gates included in the second row select transistor LX2 connected to the second word line groups WL5, WL6, WL7, and WL8 may be electrically connected to each other, and these gates may serve as the common gate of the second row select transistor LX2. For convenience, the number of word lines included in a word line group is described as 4, but it is not limited to this. The number of word lines included in a word line group may be more or less.

[0051] The second impurity regions of row select transistors LX1 and LX2 can be connected to global row select transistors GX1 through GX4, respectively. In the example embodiment, the second impurity regions of row select transistors LX1 and LX2, which are connected to word lines selected sequentially in each word line group, can be connected to one of the global row select transistors GX1 through GX4. That is, the second impurity region of each of row select transistors LX1 and LX2 can be shared with the first impurity region of one of the global row select transistors GX1 through GX4.

[0052] The second impurity regions of global row selection transistors GX1 to GX4 can be electrically connected to each other, and the second impurity regions can be merged together. A second impurity region can be connected to a first transistor GXq1.

[0053] For example, the case where the first word line WL1 is selected can be described. The first transistor GXq1 can be turned on. Among the global row select transistors GX1 to GX4, global row select transistor GX1 can be turned on, and the other global row select transistors GX2 to GX4 can be turned off. Furthermore, the first row select transistor LX1 can be turned on, and the second row select transistor LX2 can be turned off. Therefore, the write driver 1410 can be connected to the first word line WL1. The write driver 1410 can be connected between the first transistor GXq1 and the negative voltage VNEG. Therefore, the first word line WL1 can be connected to the negative voltage VNEG.

[0054] The ends of dummy word lines DWL1 to DWL4 in the first direction can be merged into a single merged word line. The merged dummy word lines DWL1 to DWL4 can be connected to the first impurity region of a dummy row select transistor LXD. That is, multiple dummy memory cells DMCs electrically connected to dummy word lines DWL1 to DWL4 can be electrically connected to the first impurity region of the dummy row select transistor LXD. Therefore, depending on the switching of the dummy row select transistor LXD, voltage can be applied to (or not applied to) dummy word lines DWL1 to DWL4. Furthermore, the same voltage can be applied to all dummy word lines DWL1 to DWL4.

[0055] As described above, the ends of the dummy word lines DWL1 to DWL4 do not necessarily need to be connected to multiple dummy row select transistors; therefore, the number of dummy row select transistors LXD does not necessarily equal the number of dummy word lines DWL1 to DWL4. For example, the number of dummy row select transistors LXD can be less than the number of dummy word lines DWL1 to DWL4.

[0056] Specifically, the ends of multiple dummy word lines DWL1 to DWL4 can be merged into a single "merged" dummy word line. The merged dummy word lines DWL1 to DWL4 can be connected to a dummy row select transistor LXD. Therefore, the number of circuits (e.g., transistors) connected to the dummy word lines DWL1 to DWL4 can be advantageously reduced. Furthermore, the horizontal area of ​​the substrate used to form the transistors can be reduced, thus reducing the chip size of the variable resistance memory device.

[0057] Figure 6 This is a circuit diagram of a portion of a variable resistance storage device according to an example embodiment. Specifically, Figure 6 A portion of the column decoder connected to the bit lines and the dummy bit lines are shown. Figure 6 For ease of description, only eight bit lines and four dummy bit lines are shown in the diagram. (See reference...) Figure 6The memory cell MC can be connected to the corresponding word lines WL1-WLn and the corresponding bit lines BL1-BL8. Furthermore, the dummy memory cell DMC can be connected to the word lines WL1-WLn and the dummy bit lines DBL1-DBL4 (DBL1, DBL2, DBL3, and DBL4). Figure 6 In order to reduce the complexity of the attached diagram, the dummy word lines have been omitted.

[0058] The column decoder may include a pre-decoder (not shown), column selection transistors LY1 and LY2, global column selection transistors GY1 to GY4 (GY1, GY2, GY3, and GY4), and a second transistor GYq1. The second transistor GYq1 may be connected to the power supply voltage VPP.

[0059] In the example implementation, the column selection transistors LY1 and LY2, the global column selection transistors GY1 to GY4, and the second transistor GYq1 can be PMOS transistors.

[0060] Bit lines BL1 to BL8 can be connected to the first impurity regions of column select transistors LY1 and LY2, respectively. That is, one of the bit lines BL1 to BL8 can be connected to the first impurity region of one of the column select transistors LY1 and LY2. Therefore, the number of column select transistors LY1 and LY2 can be equal to the number of bit lines BL1 to BL8.

[0061] In an example implementation, bit lines BL1 to BL8 may include first bit line groups BL1, BL2, BL3, and BL4, and second bit line groups BL5, BL6, BL7, and BL8. The gates of the first column select transistor LY1 connected to the first bit line groups BL1, BL2, BL3, and BL4 may be electrically connected to each other, and these gates may serve as the common gate of the first column select transistor LY1. The gates of the second column select transistor LY2 connected to the second bit line groups BL5, BL6, BL7, and BL8 may be electrically connected to each other, and these gates may serve as the common gate of the second column select transistor LY2.

[0062] The second impurity regions of column select transistors LY1 and LY2 can be connected to global column select transistors GY1 through GY4, respectively. In the example embodiment, the second impurity regions of column select transistors LY1 and LY2, which are connected to bit lines selected sequentially in each bit line group, can be connected to one of the global column select transistors GY1 through GY4. That is, the second impurity region of each of column select transistors LY1 and LY2 can be shared with the first impurity region of one of the global column select transistors GY1 through GY4.

[0063] The second impurity regions of global column selection transistors GY1 to GY4 can be electrically connected to each other, and the second impurity regions can be merged. A second impurity region can be connected to a second transistor GYq1.

[0064] For example, the case of selecting the first bit line BL1 can be described. Among the global column select transistors GY1 to GY4, global column select transistor GY1 is turned on, and the other global column select transistors GY2 to GY4 are turned off. Furthermore, the first column select transistor LY1 is turned on, and the second column select transistor LY2 is turned off. Therefore, bit line BL1 can be connected to the power supply voltage VPP.

[0065] The ends of dummy bit lines DBL1 to DBL4 in the second direction can be merged into a single merged dummy bit line. The merged dummy bit lines DBL1 to DBL4 can be connected to the first impurity region of a dummy column select transistor LYD. That is, multiple dummy memory cells DMCs electrically connected to dummy bit lines DBL1 to DBL4 can be electrically connected to the first impurity region of the dummy column select transistor LYD. Therefore, depending on the switching of the dummy column select transistor LYD, a voltage can be applied to or not applied to dummy bit lines DBL1 to DBL4. Furthermore, the same voltage can be applied to all dummy bit lines DBL1 to DBL4.

[0066] As described above, the ends of the dummy bit lines DBL1 to DBL4 do not need to be connected to multiple dummy column select transistors respectively. Therefore, the number of column select transistors LYD may not be equal to the number of dummy bit lines DBL1 to DBL4. The number of dummy column select transistors LYD may be less than the number of dummy bit lines DBL1 to DBL4.

[0067] Specifically, the ends of dummy bit lines DBL1 to DBL4 can be merged into a single merged dummy bit line. The merged dummy bit lines DBL1 to DBL4 can be connected to a dummy column select transistor LYD. Therefore, it is advantageous to reduce the number of circuits (e.g., transistors) connected to dummy bit lines DBL1 to DBL4; and it is also possible to reduce the horizontal area of ​​the substrate used to form the transistor.

[0068] As described above, dummy memory cells can be configured to connect to dummy word lines and / or dummy bit lines. This reduces the number of transistors connected to the dummy memory cells. Consequently, the chip size of variable resistive memory devices can be reduced.

[0069] The effect of reducing the chip size of variable resistance memory devices can be described below with reference to the layout diagram. Figures 7 to 11 This is a layout diagram showing a portion of a variable resistance storage device. Figures 7 to 11 The dummy word line, dummy row select transistor, word line, and row select transistor are shown. Figures 7 to 11 The wiring and interconnections shown can be used as a reference. Figure 3 This is part of the first lower wiring diagram.

[0070] exist Figures 7 to 11 For ease of description, only four (4) word lines and four (4) dummy word lines are shown; however, the number of word lines and dummy word lines is not limited to this. Even if more word lines and dummy word lines are provided, the row select transistor and the dummy row select transistor can be configured in the same way.

[0071] Figure 7 The arrangement of transistors formed on a substrate and contact plugs connected to the transistors is shown. (Refer to...) Figure 7 The substrate 100 can be divided into active regions 100a and 100b and an isolation region. In an example embodiment, the active regions 100a and 100b can have an isolated shape, and the active regions 100a and 100b can be arranged such that the second direction D2 is the length direction. Multiple active regions 100a and 100b can be spaced apart from each other in the first direction D1, and the active regions 100a and 100b can be arranged in the first direction D1. The number of active regions 100a and 100b arranged in the first direction D1 can be one more than the number of word lines. Figure 7 As shown, when four (4) word lines are formed, five active regions 100a and 100b can be set on the first direction D1.

[0072] Word lines and dummy word lines can be configured to be spaced apart from the upper surface of substrate 100. The portion of substrate 100 facing the word lines is called word line region II, and the portion of substrate 100 facing the dummy word lines is called dummy word line region I.

[0073] The active region electrically connected to the word line is called the first active region 100a, and the active region electrically connected to the dummy word line is called the second active region 100b. For example, only one second active region 100b can be set.

[0074] The first active region 100a and the second active region 100b may be located at least within the word line region II and the dummy word line region I of the substrate 100. That is, the first active region 100a and the second active region 100b may be disposed on the substrate 100 facing the region used to form the memory cell. However, the first active region 100a and the second active region 100b may not be located outside the word line region I and the dummy word line region II of the substrate 100. One end of each of the first active region 100a and the second active region 100b in the second direction D2 may be configured to at least not detach from (e.g., not protrude beyond) one end of the dummy word line region I in the second direction D2.

[0075] like Figure 7As shown, the first active region 100a and the second active region 100b can be mainly disposed in the word line region II of the substrate 100. In an example embodiment, the first active region 100a and the second active region 100b can be disposed in the word line region II and the portion of the dummy word line region I adjacent to the boundary between the word line region II and the dummy word line region I. In some example embodiments, the first active region 100a and the second active region 100b can be disposed only in the word line region II of the substrate, and may not be disposed in the dummy word line region I.

[0076] The first gate structure 300a may be configured to span multiple first active regions 100a, and the first gate structure 300a may extend in the first direction D1. The second gate structure 300b may be configured to span a second active region 100b. The first gate structure 300a and the second gate structure 300b may be spaced apart from each other in the first direction D1.

[0077] The first gate structure 300a may have a structure in which a gate insulating layer, a first gate electrode, and a mask pattern are stacked. The second gate structure 300b may have a structure in which a gate insulating layer, a second gate electrode, and a mask pattern are stacked.

[0078] The first and second impurity regions can be formed on both sides of the first gate structure 300a in the first active region 100a. Therefore, a MOS transistor (e.g., an NMOS transistor) can be formed at each of the first active regions 100a. Figure 7 As shown, four MOS transistors can be formed, and a first gate electrode can be used as the common gate electrode for these four MOS transistors. For example, the MOS transistor formed on the first active region 100a can correspond to... Figure 5 The row selection transistor LX1 is shown. That is, the first active region 100a can be the region used to form the row selection transistor.

[0079] The first and second impurity regions can be formed on both sides of the second gate structure 300b in the second active region 100b. Therefore, a MOS transistor can be formed in the second active region 100b. The MOS transistor formed on the second active region 100b can correspond to... Figure 5 The dummy row select transistor LXD is shown. That is, the second active region 100b can be the region used to form the dummy row select transistor. A first lower insulating interlayer (not shown) can be formed on the substrate 100 to cover the first gate structure 300a and the second gate structure 300b.

[0080] The first contact plug 310a and the second contact plug 310b can pass through the first lower insulating layer and the mask pattern. The first contact plug 310a can contact the first gate electrode, and the second contact plug 310b can contact the second gate electrode. The third contact plug 320a and the fourth contact plug 320b can pass through the first lower insulating layer. The third contact plug 320a can contact the first impurity region of the first active region 100a, and the fourth contact plug 320b can contact the second impurity region of the first active region 100a. The fifth contact plug 330a and the sixth contact plug 330b can pass through the first lower insulating layer. The fifth contact plug 330a can contact the first impurity region of the second active region 100b, and the sixth contact plug 330b can contact the second impurity region of the second active region 100b. Preferably, the upper surfaces of the first to sixth contact plugs 310a, 310b, 320a, 320b, 330a, and 330b can be substantially coplanar with each other.

[0081] Reference Figure 8 A first routing line 340a may be formed on a first contact plug 310a, and the first routing line 340a may be electrically connected to the first contact plug 310a. The first routing line 340a may include a first portion connected to the first contact plug 310a arranged in a first direction D1 and a second portion extending from one end of the first portion in a second direction D2. A second wiring 340b may be formed on the second contact plug 310b. A first pad pattern 350a may be formed on a third contact plug 320a. A second pad pattern 350b may be formed on a fifth contact plug 330a. A third wiring 360a may be formed on a fourth contact plug 320b, and a fourth wiring 360b may be formed on a sixth contact plug 330b. The upper surfaces of the first routing line 340a, the second to fourth wirings 340b, 360a and 360b, and the first and second pad patterns 350a and 350b may be substantially coplanar with each other.

[0082] Reference Figure 9 A third pad pattern 370a may be formed on a first pad pattern 350a. The third pad pattern 370a may be electrically connected to the first pad pattern 350a. Each third pad pattern 370a may be connected to the bottom of one of the word lines thereon. Therefore, each third pad pattern 370a may extend in the second direction D2 to the lower part of one of the word lines for electrical connection. The bottom of the first end of the third pad pattern 370a in the second direction D2 may make contact with the first pad pattern 350a. In each third pad pattern 370a, the upper surface of the second end in the second direction D2, opposite to the first end, may be positioned facing said one of the word lines.

[0083] In an example implementation, multiple third pad patterns 370a may have different shapes (e.g., different lengths). The third pad patterns 370a may be spaced apart from each other in a first direction D1. A fourth pad pattern 380 may be formed on a second pad pattern 350b. The fourth pad pattern 380 may be electrically connected to the second pad pattern 350b. The fourth pad pattern 380 may be connected to the bottom of a dummy word line thereon. The fourth pad pattern 380 may extend to the lower part of the dummy word line for electrical connection. The fourth pad pattern 380 may include a first portion 380a, a second portion 380b, and a branch line 380c. In the fourth pad pattern 380, the first portion 380a may directly contact the second pad pattern 350b and may extend in a second direction D2. The second portion 380b may extend from one end of the first portion 380a in the first direction D1. The branch line 380c may extend in the second direction D2. Each branch line 380c can extend from the second portion 380b to the lower part of one of the dummy word lines. In an example embodiment, the branch line 380c can be disposed on the dummy word line area I. The first portion 380a, the second portion 380b, and the branch line 380c can be connected to each other. In some embodiments of the invention, the upper surfaces of the third pad pattern 370a and the fourth pad pattern 380 can be substantially coplanar with each other.

[0084] Reference Figure 10 A seventh contact plug 390a for contacting word lines can be formed on the third pad pattern 370a. An eighth contact plug 390b for contacting dummy word lines can be formed on the fourth pad pattern 380. The seventh contact plug 390a can be configured to face the area for forming the word lines. In an example embodiment, the seventh contact plug 390a can be disposed on the upper edge of the third pad pattern 370a. The eighth contact plug 390b can be configured to face the area for forming the dummy word lines. In an example embodiment, the eighth contact plug 390b can be disposed on the upper edge of the branch line 380c in the fourth pad pattern 380. However, the contact plugs connected to the dummy word lines may not be disposed on the first portion 380a of the fourth pad pattern 380.

[0085] Reference Figure 11 The word lines 200 extending in the first direction D1 can be formed on the seventh contact plug 390a. The dummy word lines 202 extending in the first direction D1 can be formed on the eighth contact plug 390b. For ease of description, in Figure 11The diagram shows contact plugs 390a and 390b located below word line 200 and dummy word line 202. Specifically, the upper surface of the eighth contact plug 390b can contact the bottom of the dummy word line 202. A fourth pad pattern 380 can connect the eighth contact plugs 390b to each other and can extend above the first impurity region of the second active region 100b. A second pad pattern 350b can contact the bottom of the fourth pad pattern 380, and a fifth contact plug 330a can be connected to the second pad pattern 350b and the first impurity region of the second active region 100b. Therefore, multiple dummy word lines 202 can be electrically connected to the first impurity region of the second active region 100b through a second wiring structure including the eighth contact plug 390b, the fourth pad pattern 380, the second pad pattern 350b, and the fifth contact plug 330a. Therefore, the dummy word line 202 can be electrically merged into one through the eighth contact plug 390b and the fourth pad pattern 380, and the dummy word lines 202 can be electrically connected to each other. The merged dummy word line 202 can be electrically connected to a select transistor (e.g., a dummy row select transistor).

[0086] Word lines 200 can be electrically connected to the first impurity region of the first active region 100a via a first wiring structure including a seventh contact plug 390a, a third pad pattern 370a, a first pad pattern 350a, and a third contact plug 320a. Therefore, one of the word lines 200 and one of the selection transistors (e.g., a row selection transistor) can be electrically connected to each other via the first wiring structure. Thus, the number of word lines 200 can be equal to the number of row selection transistors.

[0087] Although not shown, the memory cell structure and the dummy memory cell structure can be formed on word line 200 and dummy word line 202, as shown in reference. Figures 2 to 4 Furthermore, bit lines and dummy bit lines can be formed on the memory cell structure and the dummy memory cell structure. Based on the above, refer to... Figures 7 to 11 This describes the layout of the dummy word line 202 and a dummy row select transistor connected to the dummy word line 202.

[0088] Similarly, dummy bit lines can be routed (such as...) Figure 3 The first bottom wiring in the circuit is merged with each other, and the merged dummy bit lines can be connected to a dummy column select transistor. In this case, in a variable resistive memory device, the circuit including bit lines and dummy bit lines can be configured as follows: Figure 6 The circuit diagram shown. Dummy bit lines and dummy column select transistors can have the same characteristics as... Figures 7 to 11 The layout of the dummy word line 202 and the dummy row select transistor shown is similar. Furthermore, the wiring connected to the dummy bit line can have the same layout as that connected to... Figures 7 to 11The routing of the dummy word line 202 shown (e.g., the second routing structure) has a similar layout. However, the dummy bit lines and bit lines can extend in the second direction D2.

[0089] The following is a brief description of a method for operating a variable-resistance memory device according to an example embodiment. Row decoders and column decoders can operate in response to row and column addresses. Therefore, one of a plurality of memory cells can be selected as the selected memory cell. During a data write operation, voltages for writing data to the selected memory cell can be supplied to the selected word line and the selected bit line, respectively. Therefore, the variable resistor of the selected memory cell can have a high-resistance state or a low-resistance state. Furthermore, inhibit voltages Vinhx and Vinhy can be supplied to the unselected word line and the unselected bit line, respectively.

[0090] A first dummy voltage can be supplied to the dummy word line. This first dummy voltage can be supplied to prevent leakage current through the dummy memory cell during data writing to the selected memory cell. The dummy row select transistor can be turned on, and the same first dummy voltage can be supplied to the dummy word line connected to the dummy row select transistor.

[0091] During a data read operation, the voltage used to read data from the selected memory cell can be supplied to the selected word line and the selected bit line, respectively. Current may or may not flow through the selected memory cell, depending on the data being written to it. Therefore, data written to the selected memory cell can be read. Furthermore, inhibit voltages Vinhx and Vinhy can be supplied to the unselected word line and the unselected bit line, respectively.

[0092] A second dummy voltage can be supplied to the dummy word line. This second dummy voltage can prevent leakage current through the dummy memory cell during data reading from the selected memory cell. The dummy row select transistor can be turned on, and the same second dummy voltage can be supplied to the dummy word line connected to the dummy row select transistor.

[0093] In variable resistance storage devices, the memory cell array can have a three-dimensional stacked structure. For example, Figure 12 and Figure 13 This is a cross-sectional view showing a variable resistance storage device including a stacked array of memory cells according to an example embodiment.

[0094] Figure 12 This is a cross-sectional view cut along the first direction D1 in a variable resistor storage device. Figure 13 This is a cross-sectional view of a variable resistor storage device cut in the second direction D2. Figure 12 This is a cross-sectional view taken along the dummy character line. (Refer to...) Figure 12 and Figure 13A transistor 110 for configuring peripheral circuitry can be formed on a substrate 100. First lower wirings 130a, 130b, 130c, 130d, and 130e can be formed to be electrically connected to the transistor 110.

[0095] The lower insulating layers 140a, 140b, and 140c can be formed to cover the peripheral circuitry. The memory cell array can be vertically stacked on the upper surface of the uppermost lower insulating layer 140c. A first word line 200 and a first dummy word line 202 can be formed on the uppermost lower insulating layer 140c. The first word line 200 can extend in a first direction D1, and the first word lines 200 can be spaced apart from each other in a second direction D2.

[0096] Bit lines 230 and dummy bit lines (not shown) may be formed on the first word line 200 and the first dummy word line 202. Bit lines 230 and dummy bit lines may be spaced apart from the first word line 200 and the first dummy word line 202 in a vertical direction. Bit lines 230 may extend in a second direction D2 and may be spaced apart from each other in a first direction D1. Each first memory cell structure 220 may be located at the intersection of one of the first word lines 200 and one of the bit lines 230. The first dummy memory cell structure 222 may be connected to the first dummy word line 202 and / or the dummy bit line.

[0097] The first character line 200 and the first dummy character line 202 can be referenced. Figures 2 to 4 The described word lines and dummy word lines are essentially the same. Bit line 230 and dummy bit lines can be compared with references. Figures 2 to 4 The described bit lines and dummy bit lines are essentially the same. Furthermore, the first memory cell structure 220 and the first dummy memory cell structure 222 can be compared with reference to... Figures 2 to 4 The described storage unit structure is basically the same as the virtual storage unit structure.

[0098] In the example implementation, the layout of the first lower wiring connected to the first dummy word line 202 can be the same as that of the referenced one. Figures 7 to 11 The layout of the wiring connected to the dummy word line is basically the same as described.

[0099] The second memory cell structure 420 and the second dummy memory cell structure 422 can be formed on the bit line 230. Furthermore, the second dummy memory cell structure 422 can be formed on a dummy bit line. The second word line 430 and the second dummy word line 432 can be formed on the second memory cell structure 420 and the second dummy memory cell structure 422.

[0100] The second character line 430 and the second dummy character line 432 may extend in the first direction D1, and the second character line 430 and the second dummy character line 432 may be spaced apart from each other in the second direction D2. The second character line 430 may be configured to face the first character line 200. The second dummy character line 432 may be configured to face the first dummy character line 202.

[0101] Each second memory cell structure 420 may be located at the intersection of one of the second word lines 430 and one of the bit lines 230. The second dummy memory cell structure 422 may be connected to the second dummy word line 432 and / or the dummy bit line.

[0102] In the example implementation, the second storage cell structure 420 and the second virtual storage cell structure 422 may have the same characteristics as the referenced structure. Figures 2 to 4 The stacked structure described is the same as the stacked structure of the memory cell structure and the dummy memory cell structure. For example, each of the second memory cell structure 420 and the second dummy memory cell structure 422 may include a stacked second lower electrode 410, a second selection device 412, a second intermediate electrode 414, a second variable resistor 416, and a second upper electrode 418.

[0103] In some example implementations, the second memory cell structure 420 and the second dummy memory cell structure 422, as well as the first memory cell structure 220 and the first dummy memory cell structure 222, may be symmetrical about bit line 230. Furthermore, as described above, the memory cell structures are stacked vertically, and bit line 230 may be shared by both the first memory cell structure 220 and the second memory cell structure 420.

[0104] The first insulating layer 224 and the second insulating layer 226 can be formed to fill the space between the first word line 200 and the first dummy word line 202, as well as the space between the first memory cell structure 220 and the first dummy memory cell structure 222. The third insulating layer 240 and the fourth insulating layer 424 can be formed to fill the space between the bit line 230 and the dummy bit line, as well as the space between the second memory cell structure 420 and the second dummy memory cell structure 422. The fifth insulating layer 426 can be formed to fill the space between the second word line 430 and the second dummy word line 432. Although not shown, upper metal wiring can be further formed on the second word line 430, the second dummy word line 432, and the fifth insulating layer 426.

[0105] In addition, such as Figure 13 As shown, the contact plug 450a can pass through the first insulating layer 224 and the second insulating layer 226, and the contact plug 450a can be electrically connected to the bit line 230 and the dummy bit line, as well as the peripheral circuitry on the substrate 100. Furthermore, Figure 12The vertically stacked contact plugs 450a and 450b shown can pass through the first to fourth insulating interlayers 224, 226, 240 and 424, and the contact plugs 450a and 450b can be electrically connected to the second word line 430 and the second dummy word line 432 and the peripheral circuitry on the substrate 100.

[0106] The second word line 430 can be electrically connected to a transistor (e.g., a second row select transistor) on the substrate 100 via contact plugs 450a and 450b and first lower wirings 130a, 130b, 130c, 130d, and 130e. The second dummy word line 432 can contact contact plugs 450a and 450b. Contact plugs 450a and 450b can be connected to each other via the first lower wirings 130a, 130b, 130c, 130d, and 130e. Therefore, the second dummy word line 432 can be electrically connected to a transistor (e.g., a second dummy row select transistor).

[0107] In the example implementation, the first lower wiring connected to the second dummy word line 432 may have the same characteristics as the referenced one. Figures 7 to 11 The layout of the wiring connected to the dummy word lines is substantially the same as described above. As mentioned above, the ends of the second dummy word lines 432 may not be individually connected to the second dummy row select transistors, therefore the number of second dummy row select transistors may not be equal to the number of second dummy word lines 432. The number of second dummy row select transistors may be less than the number of second dummy word lines 432. Therefore, the number of circuits (e.g., transistors) electrically connected to the second dummy word lines can be reduced. The horizontal area of ​​the substrate used to form the transistors can be reduced, thus reducing the chip size of the variable resistance memory device.

[0108] exist Figure 12 and Figure 13 The present invention has already described a memory cell structure that is vertically stacked in two layers. However, according to another embodiment of the invention, the memory cell structure can be stacked in the same manner to form three or more layers. Furthermore, even if the memory cell structure is stacked in multiple layers, dummy word lines at the same level can be merged into one by wiring below the dummy word line, and dummy word lines at the same level can be connected to a transistor.

[0109] The implementation can be used in variable resistive storage devices and systems including them. Specifically, the implementation can be used in electronic devices such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), computers, laptops, cellular phones, smartphones, MP3 players, personal digital assistants (PDAs), portable multimedia players (PMPs), digital TVs, digital cameras, portable game consoles, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, or similar devices.

[0110] The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means plus function clause is intended to cover structures described herein as performing said function, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting to the specific exemplary embodiments disclosed, and it will be understood that modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

[0111] This application claims priority to Korean Patent Application No. 10-2020-0137306, filed on October 22, 2020, the disclosure of which is incorporated herein by reference.

Claims

1. An integrated circuit storage device, comprising: Multiple rows of selected transistors on a substrate; Dummy row selection transistors on the substrate; Multiple word lines and multiple dummy word lines on the substrate; Multiple storage units are electrically connected to the corresponding word lines among the multiple word lines; Multiple dummy memory cells are electrically connected to corresponding dummy word lines among the multiple dummy word lines; The first wiring structure electrically connects the first word line among the plurality of word lines to the first row selection transistor among the plurality of row selection transistors; as well as The second wiring structure electrically connects the plurality of dummy word lines together and electrically connects the plurality of dummy word lines to the dummy row select transistor.

2. The integrated circuit memory device according to claim 1 further includes a plurality of bit lines, the plurality of bit lines being perpendicularly spaced from the plurality of word lines and the plurality of dummy word lines, and electrically connected to corresponding memory cells and corresponding dummy memory cells among the plurality of memory cells and the plurality of dummy memory cells.

3. The integrated circuit memory device of claim 2, wherein the substrate includes a first active region in which the plurality of row select transistors are formed and a second active region in which the dummy row select transistors are formed; The word lines and the dummy word lines extend longitudinally across the substrate in a first direction, and the bit lines extend longitudinally across the substrate in a second direction, the second direction being perpendicular to the first direction; The first active region and the second active region are spaced apart from each other in the first direction; and The first active region and the second active region are arranged such that their length direction is the same as the second direction.

4. The integrated circuit memory device according to claim 1, further comprising: Multiple bit lines are perpendicularly spaced from the multiple word lines and the multiple dummy word lines, and are electrically connected to the corresponding memory cells among the multiple memory cells; as well as Multiple dummy bit lines are electrically connected to the corresponding dummy memory cells among the multiple dummy memory cells, and are electrically connected together.

5. The integrated circuit memory device of claim 4, further comprising a dummy column select transistor having source / drain regions electrically connected to the plurality of dummy bit lines.

6. The integrated circuit memory device of claim 1, wherein the substrate includes a first active region in which the plurality of row select transistors are formed and a second active region in which the dummy row select transistors are formed; and The second wiring structure includes: (i) a first contact plug electrically connected to the source / drain region of the dummy row select transistor, (ii) a pad pattern electrically connected to the first contact plug, and (iii) a plurality of second contact plugs extending between the pad pattern and a corresponding dummy word line among the plurality of dummy word lines and electrically connecting the pad pattern to the corresponding dummy word line among the plurality of dummy word lines.

7. A variable resistance storage device, comprising: Row selection transistors on a substrate; Dummy row selection transistors on the substrate; Word lines and dummy word lines are disposed above the row select transistor and the dummy row select transistor, and the word lines and dummy word lines extend in a first direction parallel to the surface of the substrate; Bit lines above the word lines and the dummy word lines, the bit lines being spaced apart from the word lines and the dummy word lines in a vertical direction perpendicular to the surface of the substrate, and extending in a second direction perpendicular to the first direction; A memory cell structure, each of the memory cell structures being connected to one of the word lines and one of the bit lines; A virtual memory cell structure, each of the virtual memory cell structures being connected to one of the virtual word lines and one of the bit lines; A first wiring structure connects one of the word lines and one of the row select transistors to each other; and The second wiring structure connects the dummy word line and the dummy row select transistor. The ends of the dummy word lines are merged into one through the second wiring structure.

8. The variable resistance memory device of claim 7, wherein the substrate includes a first active region for forming the row select transistor and a second active region for forming the dummy row select transistor.

9. The variable resistor storage device of claim 8, wherein the first active region and the second active region are spaced apart in the first direction, and the first active region and the second active region are arranged such that the second direction is a length direction.

10. The variable resistance memory device of claim 8, wherein the first active region and the second active region are located in the regions of the substrate for forming the dummy word line and the word line.

11. The variable resistance memory device of claim 8, wherein the row selection transistor comprises: A common first gate structure extends in the first direction to span the first active region; as well as The first impurity region and the second impurity region are located on both sides of the common first gate structure in the first active region.

12. The variable resistance memory device of claim 8, wherein the dummy row select transistor comprises: A second gate structure extends in the first direction to span the second active region; as well as The first impurity region and the second impurity region are located on both sides of the second gate structure in the second active region.

13. The variable resistance storage device of claim 8, wherein the second wiring structure comprises: The second contact plug contacts the bottom of the dummy character line; A pad pattern extends over the second active area, the pad pattern connecting to the bottom of the second contact plug; as well as The first contact plug connects the bottom of the pad pattern and the second active area to each other.

14. The variable resistor storage device of claim 13, wherein the pad pattern comprises: The first portion of the first contact plug is contacted, and the first portion extends in the second direction; The second part extends from one end of the first part in the first direction; as well as Branch lines extend from the second part to the second contact plug, respectively.

15. The variable resistance memory device of claim 7, wherein the number of dummy row select transistors is less than the number of dummy word lines.

16. The variable resistance storage device according to claim 7, wherein the storage cell structure and the dummy storage cell structure constitute a cell block, and the dummy word line is disposed at the edge portion of the cell block in the second direction.

17. The variable resistance storage device according to claim 7, further comprising: A second word line and a second dummy word line above the bit line, the second word line and the second dummy word line being spaced apart from the bit line in the vertical direction and extending in the first direction; A second memory cell structure, each of the second memory cell structures being connected to one of the second word lines and one of the bit lines; The second dummy memory cell structure, each of the second dummy memory cell structures is connected to one of the second dummy word lines and one of the bit lines; The second row selects transistors, which are electrically connected to the second word line respectively; as well as The second dummy row selects the transistor; The ends of the second dummy word line are merged into one, and the second dummy row select transistor is electrically connected to the merged second dummy word line.

18. The variable resistance memory device of claim 17, further comprising a third wiring connected to the end of the second dummy word line and the second dummy row select transistor.

19. A variable resistance storage device, comprising: The storage unit is located at the intersection of the word line and the bit line; Virtual memory cells connected to virtual word lines; Row selection transistors used to control the word lines, the number of which is equal to the number of word lines; The virtual row select transistors used to control the virtual word lines are less than the number of virtual word lines. A first wiring connecting the word line and the row select transistor; as well as The second wiring connects the dummy word line and the dummy row select transistor. The ends of the dummy word lines are merged into one, and the dummy row select transistor is electrically connected to the merged dummy word line.

20. The variable resistance storage device of claim 19, wherein the second wiring comprises: The second contact plug contacts the bottom of the dummy character line; A pad pattern extends over a stub region of the dummy row select transistor, the pad pattern connecting to the bottom of the second contact plug; as well as The first contact plug connects the bottom of the pad pattern and the impurity area to each other.

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