Semiconductor transistor on a multilayer substrate

Abstract

The invention relates to a semiconductor transistor on a multilayer substrate. A semiconductor device is provided that includes a multilayer substrate, a first doped region, a second doped region, and a gate structure. The multilayer substrate has a device layer over an isolation layer, and the device layer includes a first region having a first substrate thickness and a second region having a second substrate thickness that is less than the first substrate thickness. The first doped region is in the first region and the second doped region is in the second region. The gate structure is between the first doped region and the second doped region.

Description

TECHNICAL FIELD

[0001] The disclosed subject matter relates generally to semiconductor devices, and more particularly to semiconductor transistors on a multilayer substrate and methods of forming the same. BACKGROUND

[0002] In modern society, the widespread use of electricity has enabled various applications of semiconductor devices in electronic circuits. In particular, transistors are a common type of semiconductor active device that are often used as amplifiers and switches. Transistors can be used in different applications, such as low or high frequency applications, and low, medium, or high power applications.

[0003] The presence of parasitic components, such as parasitic inductance, capacitance, conductance, and resistance, can combine to attenuate and degrade the device performance of these transistors. It is critical for certain applications to ensure that the parasitic components are kept at a low level or at least at an acceptable level.

[0004] One of the possible solutions to reduce parasitic components is to fabricate transistors on a silicon-on-insulator substrate. Silicon-on-insulator substrates are capable of reducing parasitic interactions between the transistors and a bulk semiconductor substrate, thereby enabling improved device performance compared to transistors formed on a bulk semiconductor substrate.

[0005] As the semiconductor industry continues to develop, there is a need to provide further device performance improvements for semiconductor transistors and methods of forming the same. SUMMARY

[0006] To achieve the above and other aspects of the present disclosure, a semiconductor transistor on a multilayer substrate and a method of forming the same are provided.

[0007] According to an aspect of the present disclosure, a semiconductor device includes a multilayer substrate, a first doped region, a second doped region, and a gate structure. The multilayer substrate has a device layer over an isolation layer, and the device layer includes a first region having a first substrate thickness and a second region having a second substrate thickness less than the first substrate thickness. The first doped region is in the first region, and the second doped region is in the second region. The gate structure is between the first doped region and the second doped region.

[0008] According to another aspect of the present disclosure, a semiconductor device includes a multilayer substrate, a gate structure, a first doped region, and a second doped region. The multilayer substrate has a device layer over an isolation layer, and the gate structure is over the device layer. The first doped region and the second doped region are in the device layer, adjacent to and on opposite sides of the gate structure. A bottom surface of the first doped region is higher than a bottom surface of the second doped region.

[0009] According to yet another aspect of the present disclosure, a method of forming a semiconductor device is provided, including: providing a multi-layered substrate having a device layer over an isolation layer; and forming a gate structure over a first region of the device layer having a first substrate thickness. A second region of the device layer having a second substrate thickness is formed adjacent to the gate structure, such that the second substrate thickness is less than the first substrate thickness. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments of the present disclosure will be better understood with a reference to the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 2A to 7C is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, illustrating a method of integrating three different types of active devices on the same semiconductor device.

[0013] Figure 8 is a cross-sectional view of a semiconductor device having three different types of active devices according to an embodiment of the present disclosure.

[0014] For the sake of simplicity and clarity, the drawings illustrate the general manner of construction, and specific descriptions and details of well-known features and techniques can be omitted to avoid unnecessarily obscuring the discussion of the embodiments of the described devices.

[0015] In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings can be exaggerated relative to other elements to help improve the understanding of the embodiments of the devices. Like reference numerals designate like elements throughout the drawings, and similar reference numerals can but do not necessarily designate similar elements. DETAILED DESCRIPTION

[0016] The present disclosure relates to semiconductor transistors on multi-layered substrates and methods of forming the same.

[0017] Generally, multi-layered substrates can be used in place of bulk semiconductor substrates to improve device performance of active devices formed thereon. Multi-layered substrates can include an insulator layer disposed between a thin semiconductor device layer and a bulk substrate. Known multi-layered substrates can include a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-on-sapphire substrate.

[0018] Electrical interactions between the active devices and the bulk substrate can result in detrimental parasitic effects. By providing electrical isolation from the bulk substrate, the insulator layer of the multi-layered substrate advantageously reduces these electrical interactions, particularly parasitic capacitances.

[0019] Various embodiments of the present disclosure are now described in detail. It should be noted that like and corresponding elements are denoted by the same reference numbers. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or to be limited to the present disclosure. Certain structural elements can be conventionally manufactured, for example, using known processes and techniques, and various aspects of the present disclosure can be implemented using the processes and methods specifically disclosed.

[0020] Figure 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 can be part of a semiconductor integrated circuit (IC) device. The semiconductor device 100 can be located in a device region that includes multiple transistors. In this embodiment of the present disclosure, the semiconductor device 100 can include a pair of extended-drain metal-oxide semiconductor field-effect (EDMOS) transistors.

[0021] The semiconductor device 100 can be formed on a multilayer substrate 102. The multilayer substrate 102 can include an insulator layer 104 and a semiconductor device layer 106 formed over the insulator layer 104. The insulator layer 104 can include an electrically insulating material, such as but not limited to silicon dioxide or sapphire. Other electrically insulating materials known in the art can be contemplated as suitable for use in all embodiments of the present disclosure. The device layer 106 can serve as a pathway for electrical current and can include a semiconductor material, such as but not limited to silicon or germanium. Other semiconductor materials known in the art can be contemplated as suitable for use in all embodiments of the present disclosure.

[0022] A cavity 108 can be formed in the device layer 106, thereby forming different regions in the device layer; a first region not located under the cavity and a second region located under the cavity 108. The cavity 108 does not extend through the device layer 106. The first region has a first upper surface and a first substrate thickness SI, and the second region has a second upper surface and a second substrate thickness S2. The first substrate thickness SI is greater than the second substrate thickness S2, such that the first upper surface of the first region is located above the second upper surface of the second region. The cavity 108 can have a cavity depth C from the first upper surface of the first region of the device layer 106.

[0023] A gate structure 110 can be formed over the first region of the device layer 106, and each gate structure 110 can include multiple elements, such as but not limited to a gate electrode disposed over a gate dielectric layer; these elements are not shown so as not to obscure the present disclosure. A gate spacer 112 can be formed on the sidewalls of the gate structure 110. The gate spacer 112 can include a dielectric material, such as but not limited to silicon oxide, silicon nitride, or the like. The gate spacer 112 can be used to isolate the gate structure 110 from adjacent conductive features. As shown, the cavity 108 can be disposed between pairs of the gate structure 110. Figure 1 ​

[0024] A plurality of doped regions 114, 116 can be formed on opposite sides of the gate structure 110 in the device layer 106. Specifically, a source region 114 can be formed in a first region of the device layer, and a drain region 116 can be formed in a second region of the device layer 106. Although the source and drain regions 114, 116 are illustrated as having the same form, it should be understood that the form of the source and drain regions can vary depending on the technology node and design requirements of the semiconductor device 100. The drain region 116 can be a shared drain region between pairs of the gate structures 110, as Figure 1 illustrated.

[0025] In embodiments of the present disclosure, the source region 114 can be formed in a first region of the device layer 106, and the drain region 116 can be formed in a second region of the device layer 106. A lower surface of the drain region 116 can be located below a lower surface of the source region 114. For exemplary embodiments of EDMOS transistors, the drain region 116 is formed farther from the gate structure 110 than the source region 114 is from the gate structure 110.

[0026] The semiconductor device 100 can also include a plurality of doped wells 118, 120 located in the device layer 106. The plurality of doped wells 118, 120 can include a first doped well 118 and a second doped well 120. The first doped well 118 can function as a drift well, and the second doped well 120 can function as a body well of the semiconductor device 100. For example, the dopant concentration and / or the dopant depth of the doped wells 118, 120 in the device layer 106 can vary depending on the technology node and design requirements of the semiconductor device 100.

[0027] An insulating layer 122 can be formed to partially overlap an upper surface of the gate structure 110 and extend toward the drain region 116. The insulating layer 122 can be conformally deposited, which can not cover the drain region 116. The insulating layer 122 can be a single layer of dielectric material or a multi-layer of dielectric material. For example, the single layer of insulating layer 122 can include silicon oxide. In another example, the multi-layer of insulating layer 122 can include a first layer of silicon oxide, a layer of silicon nitride disposed on the first layer of silicon oxide, and a second layer of silicon oxide disposed on the layer of silicon nitride. In embodiments of the present disclosure, the insulating layer 122 can function as a silicide alignment box (SAB) layer.

[0028] A plurality of contacts 124, 126 can be formed in a dielectric layer 128 covering the device layer 106. The plurality of contacts 124, 126 can include a source contact 124 formed on the source region 114 in a first region of the device layer 106, and a drain contact 126 formed on the drain region 116 in a second region of the device layer 106. The source contact 124 can have a height that is less than the drain contact 126.

[0029] The plurality of contacts 124, 126 can be used to provide electrical connections between the source and drain regions 114, 116 of the semiconductor device 100 and other regions of a semiconductor IC device, such as a logic device or a memory device, through a plurality of interconnect structures 130. The plurality of interconnect structures 130 can include via structures, line structures, or a combination of via structures and line structures.

[0030] The semiconductor device 100 can further include a dielectric liner 132 formed over the device layer 106, covering the source and drain regions 114, 116 and the gate structure 110. The dielectric liner 132 can be an etch stop layer used to provide a relatively high etch selectivity layer, allowing for precise formation of features, such as the plurality of contacts 124, 126, advantageously minimizing any potential damage to the device layer 106 during the fabrication process. In embodiments of the present disclosure, the dielectric liner 132 can include silicon oxide, silicon nitride, or the like.

[0031] An exemplary capacitor has been conceived; an insulating dielectric layer 128 is inserted between the conductive device layer 106 and the interconnect structure 130. The result of having such a capacitor is that a parasitic capacitance is formed between the interconnect structure 130 and the device layer 106 around the drain region 116 of the semiconductor device 100. This parasitic capacitance causes a resistance-capacitance (RC) delay and thus reduces the switching speed of the semiconductor device 100.

[0032] The cavity 108 advantageously reduces the parasitic capacitance around the drain region 116 by increasing the separation distance between the device layer 106 and the interconnect structure 130, thereby improving device performance. The dielectric layer 128 can have a first dielectric thickness Dl over the first region of the device layer 106 and a second dielectric thickness D2 over the second region; the first dielectric thickness Dl is less than the second dielectric thickness D2.

[0033] Since the parasitic capacitance around the drain region 116 greatly affects the switching speed of the semiconductor device 100, it is advantageous to improve the parasitic capacitance around the drain region 116. For example, a large parasitic capacitance causes a delay in the rise of the drain current after the gate structure turns on. In another example, a large parasitic capacitance causes a delay in the fall of the drain current after the gate structure turns on. Thus, by reducing the parasitic capacitance around the drain region 116, the corresponding gate-drain capacitance can be correspondingly reduced, thereby enabling a faster switching speed and improved device performance.

[0034] Figures 2A to 7C is a cross-sectional view of a semiconductor device 200 according to embodiments of the present disclosure, illustrating various stages of forming the semiconductor device 200. Figures 2A to 7CExemplary methods for integrating three different types of active devices on the same semiconductor device 200 are provided.

[0035] In particular, FIGS. 2-7 with suffix“A” are cross-sectional views of a first region 232 of the semiconductor device 200 defined to form a first active device 238, FIGS. with suffix“B” are cross-sectional views of a second region 234 of the semiconductor device 200 defined to form a second active device 240, and FIGS. with suffix“C” are cross-sectional views of a third region 236 of the semiconductor device 200 defined to form a third active device 242. In this embodiment of the disclosure, the first active device 238 can be an asymmetric complementary metal-oxide semiconductor (CMOS) transistor, the second active device 240 can be an extended-drain metal-oxide semiconductor (EDMOS) transistor, and the third active device 242 can be a lateral diffusion metal-oxide semiconductor (LDMOS) transistor.

[0036] The semiconductor device 200 can be part of a semiconductor IC device and can include a multilayer substrate 102. The multilayer substrate 102 can include an insulator layer 104 and a semiconductor device layer 106 formed over the insulator layer 104. The device layer 106 can have a first substrate thickness SI.

[0037] Figures 2A to 2C A semiconductor device 200 after formation of a plurality of isolation features 244, 246 is illustrated. The plurality of isolation features 244, 246 can be disposed in the multilayer substrate 102 and can include a dielectric material adapted to at least electrically isolate adjacent conductive features from one another. The dielectric material can include, but is not limited to, silicon dioxide. Other dielectric materials known in the art can also be used. The plurality of isolation features 244, 246 can include an inter-device isolation region 244 and an intra-device isolation region 246.

[0038] The inter-device isolation region 244 can be disposed to electrically isolate or separate different regions 232, 234, 236 of the semiconductor device 200, as shown. The inter-device isolation region 244 can extend through the device layer 106. The inter-device isolation region 244 can include a dielectric material adapted to at least electrically isolate different regions of the semiconductor device 200 from one another. The inter-device isolation region 244 can include a deep trench isolation (DTI) region, among others. Figures 2A to 2C The intra-device isolation region 246 can be disposed for electrical performance considerations. For example, as shown, the intra-device isolation region 246 can be disposed in the third region 236 of the semiconductor device 200 for the third active device 242 designed for high voltage applications. The intra-device isolation region 246 can include a shallow trench isolation (STI) region, among others.

[0039] Figure 2C

[0040] ​​Figures 3A to 3C Figure 3A succession Figure 2A , Figure 3B succession Figure 2B , Figure 3C succession Figure 2C FIG. 10 illustrates the semiconductor device 200 after formation of the conductive well 248 according to embodiments of the present disclosure. The conductive well 248 can be disposed according to design requirements of the active device. For example, the conductive well 248 can be disposed for the first active device 238 in the first region 232 of the semiconductor device 200, as shown in FIG. 10. The conductive well 248 can be formed by introducing dopants into the device layer 106. The dopant concentration and / or dopant depth can vary according to the technology node and design requirements of the first active device 238. In embodiments of the present disclosure, the conductive well 248 can serve as a logic well for the first active device 238. Figure 3A

[0041] Figures 4A to 4C Figure 4A succession Figure 3A , Figure 4B succession Figure 3B , Figure 4C succession Figure 3C FIG. 11 illustrates the semiconductor device 200 after formation of the gate structures 110 and the doped wells 120 according to embodiments of the present disclosure. The gate structures 110 can be formed over the upper surface of the device layer 106, and each gate structure 110 can include a plurality of elements, such as but not limited to a gate electrode disposed over a gate dielectric layer, which are not shown to avoid obscuring the present disclosure.

[0042] The doped wells 120 can be disposed according to design requirements of the active device, for example, the doped wells 120 can be disposed for the second and third active devices 240, 242 in the second and third regions 234, 236 of the semiconductor device 200, as shown in FIGS. 11 and 12, respectively. The doped wells 120 can be formed by introducing dopants into the device layer 106. The dopants in the plurality of doped wells 120 can or can not include the same type of dopants as the conductive well 248 in the first region 232 of the semiconductor device 200. The dopant concentration and / or dopant depth can vary according to the technology node and design requirements of the second and third active devices, respectively. In embodiments of the present disclosure, the doped wells 120 can serve as body wells for the second and third active devices 240, 242. Figure 4B Figure 4C

[0043] Figures 5A to 5C Figure 5A succession Figure 4A , Figure 5B succession Figure 4B , Figure 5C succession Figure 4C ​​​​​​embodiments of the present disclosure. The cavity 108 can be disposed over the drain of the active devices to be subsequently formed. The cavity 108 can have a cavity depth C from the upper surface of the device layer 106. It should be appreciated that Figures 5A to 5C The cavities 108 in the device layer 106 can not necessarily have the same cavity depth C or width. The depth C and width of the cavities can vary depending on the design requirements of the active devices.

[0044] The formation of the cavities 108 has resulted in different thicknesses of the device layer 106. Specifically, the portions of the device layer 106 that are located below the cavities 108 have a second substrate thickness S2, while the other portions of the device layer 106 that are not located below the cavities retain the first substrate thickness S1; the second substrate thickness S2 is less than the first substrate thickness S1.

[0045] In embodiments of the present disclosure, the cavities 108 can be formed by the exemplary patterning techniques described herein. A patterning layer (not shown) can be deposited over the multilayer substrate 102 and the gate structure 110. The patterning layer can include a material that can be patterned, such as but not limited to a photoresist layer, a hard mask layer, or a combination thereof. Openings (not shown) can be formed in the patterning layer using a patterning process, exposing portions of the upper surface of the device layer 106.

[0046] The openings in the patterning layer can extend into the device layer 106 of the multilayer substrate 102 to form the cavities 108 using a material removal process. Suitable material removal processes can include an anisotropic dry etching process, such as a reactive ion etching (RIE) process. After the cavities 108 are formed, the patterning layer can be removed by another material removal process.

[0047] The doped wells 118 can be provided according to the design requirements of the active devices. For example, the doped wells 118 can be formed in the device layer 106 for the second and third active devices 240, 242, as shown in Figure 5B and Figure 5C In embodiments of the present disclosure, the doped wells 118 can function as drift wells for the second and third active devices 240, 242, and can be formed by introducing dopants into the device layer 106 at the second and third regions 234, 236 of the semiconductor device 200.

[0048] Figures 6A to 6C ( Figure 6A Continuing Figure 5A , Figure 6B Continuing Figure 5B , Figure 6C Continuing Figure 5C) illustrates a semiconductor device 200 after formation of gate spacers 112, source regions 114, drain regions 116, and insulating layers 122 according to embodiments of the present disclosure. Gate spacers 112 can be fabricated on sidewalls of gate structures 110. Gate spacers 112 can be used to isolate gate structures 110 from adjacent conductive features.

[0049] Source and drain regions 114, 116 can be formed by introducing dopants into device layer 106. Drain regions 116 can be disposed in device layer 106 adjacent to respective gate structures 110 and beneath a plurality of cavities 108. Source regions 114 can be disposed in device layer 106 opposite the drain regions 116 from gate structures 110.

[0050] Gate spacers 112 and insulating layers 122 can be formed by various deposition and patterning processes. Gate spacers 112 can be deposited on sidewalls of gate structures 110. A conformal deposition process can be preferably employed to form gate spacers 112. The conformal deposition process can include, but is not limited to, an ALD process or a highly conformal CVD process to deposit a spacer material. The spacer material can be patterned to form gate spacers 112.

[0051] Similar to the fabrication process of gate spacers 112, a conformal deposition process can be preferably employed to form insulating layers 122. An insulating material can be deposited and patterned to form insulating layers 122 that partially overlap the upper surfaces of gate structures 110 and extend toward drain regions 116. As shown in Figure 6B and Figure 6C According to design requirements of second and third active devices 240, 242, insulating layers 122 can be formed in second and third regions 234, 236 of semiconductor device 200 and do not cover drain regions 116, as shown. In embodiments of the present disclosure, insulating layers 122 can be used as silicide alignment block (SAB) layers.

[0052] Figures 7A to 7C ( Figure 7A Continuing Figure 6A , Figure 7B Continuing Figure 6B , Figure 7C Continuing Figure 6C ) illustrates a semiconductor device 200 after formation of dielectric liners 132 according to embodiments of the present disclosure. Dielectric liners 132 can be deposited over device layer 106 covering source and drain regions 114, 116 and gate structures 110. Dielectric liners 132 can be etch stop layers used to provide a relatively high etch selectivity layer to allow features, such as a plurality of contacts 124, 126, to be formed over multilayer substrate 102 with precision, thereby minimizing any potential damage to device layer 106. In embodiments of the present disclosure, dielectric liners 132 can be silicon oxide, silicon nitride, or the like.

[0053] A dielectric layer 128 can be formed over the dielectric liner 132. The dielectric layer 128 overlying the dielectric liner 132 can have different thicknesses. Specifically, the dielectric layer 128 over the portion of the device layer 106 having the first substrate SI can have a first dielectric thickness Dl, and the dielectric layer 128 over the portion of the device layer 106 having the second substrate S2 can have a second dielectric thickness D2; the first dielectric thickness Dl is less than the second dielectric thickness D2.

[0054] Further processing steps can be performed on the semiconductor device 200 to form various features known in the art, such as contacts 124, 126 and interconnect structures 130. The contacts 124, 126 can be formed to establish electrical connections between the source and drain regions 114, 116 of the semiconductor device 200 and the back end of line (BEOL) region. The portion of the dielectric layer 128 having the greater dielectric thickness D2 advantageously reduces parasitic capacitance between the device layer 106 and the interconnect structures 130, thereby improving the switching speed and device performance of the semiconductor device 200.

[0055] Figure 8 is a cross-sectional view of a semiconductor device 300 having three different types of active devices integrated together, in accordance with an embodiment of the present disclosure. The semiconductor device 300 can be part of a semiconductor integrated circuit (IC) device. The semiconductor device 300 can be located in a device region that includes a plurality of transistors.

[0056] The semiconductor device 300 can be fabricated using the methods described in Figures 2A to 7C The semiconductor device 300 can have a first region 232 defined to form a first active device 238, a second region 234 defined to form a second active device 240, and a third region 236 defined to form a third active device 242. The first, second, and third regions 232, 234, 236 can be electrically isolated or separated from each other using a device isolation region 244. In embodiments of the present disclosure, the device isolation region 244 can include a deep trench isolation (DTI) region, or the like.

[0057] In this embodiment of the present disclosure, the first active device 238 can be an asymmetric complementary metal-oxide semiconductor (CMOS) transistor, the second active device 240 can be an extended-drain metal-oxide semiconductor (EDMOS) transistor, and the third active device 242 can be a lateral diffusion metal-oxide semiconductor (LDMOS) transistor.

[0058] Those skilled in the art will appreciate that embodiments having integrated CMOS transistors, integrated EDMOS transistors, and integrated LDMOS transistors are merely exemplary examples and are not intended to limit the scope of the present disclosure. Rather, the above detailed description will provide a convenient guide for implementing embodiments having other types of transistors without departing from the spirit and scope of the present disclosure.

[0059] As presented in the above disclosure, semiconductor transistors on a multilayer substrate and methods of forming the same are provided. The multilayer substrate can have a device layer over an insulator layer. By forming a cavity in the device layer, the transistors can achieve a significant reduction in parasitic capacitance around their respective drain regions. Regions of the device layer that are below the cavity are thinner than those that are not below the cavity.

[0060] A dielectric layer formed over the device layer can have a thickness that is greater than the thinner regions of the device layer. The wider separation distance between the device layer and the overlying interconnect structure advantageously reduces the parasitic capacitance of the transistors, thereby improving transistor device performance.

[0061] Table 1 below illustrates a set of exemplary simulation data based on transistors formed on a multilayer substrate having a varying dielectric thickness D2, showing potential parasitic capacitance reduction as the varying dielectric layer thickness D2 / varying cavity depth C.

[0062]

[0063] Further, by using the methods disclosed herein, designers increase design flexibility and can selectively integrate different types of transistors on the same semiconductor device. Exemplary embodiments of asymmetric CMOS transistors, EDMOS transistors, and LDMOS transistors have been presented above. Thus, semiconductor devices can be customized to achieve improved device performance and to take advantage of different strengths of transistors of these different technologies.

[0064] The terms "top," "bottom," "over," "under," and like terms in the description and in the claims, if any, are used for descriptive purposes and are not necessarily meant to be descriptive of permanent or absolute positions. It is understood that the terms used in this manner are interchangeable as appropriate to enable embodiments of the devices described herein to operate in orientations other than those exemplified or otherwise described herein.

[0065] Further, the formation of a first feature over or on a second feature in the following description can include embodiments in which the first and second features are formed to be in direct contact, and can also include embodiments in which additional features can be formed to be interposed between the first and second features such that the first and second features can not be in direct contact.

[0066] Similarly, if the methods described herein include a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps can be performed, and certain of the specified steps can be omitted, and / or other specified steps can be added, to the methods.

[0067] In addition, unless otherwise indicated, all numbers expressing quantities of materials, ratios, and numerical properties of the specification and claims are to be understood as being modified in all instances by the term "about." Also, as used in the specification and claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise.

[0068] While several exemplary embodiments have been given above in the detailed description of the device, it should be understood that there can be numerous variations. It should be further understood that the embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the device in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes can be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: a multilayer substrate having a device layer over an isolation layer, the device layer including a first region having a first substrate thickness and a second region having a second substrate thickness less than the first substrate thickness; a first doped region in the first region; a second doped region in the second region; and a gate structure between the first doped region and the second doped region, wherein a top surface of the gate structure is planar, and wherein the gate structure is over the first region of the device layer and spaced apart from the second region of the device layer.

2. The semiconductor device of claim 1, further comprising a dielectric layer over the device layer, the dielectric layer having a first dielectric thickness over the first region of the device layer and a second dielectric thickness over the second region, wherein the first dielectric thickness is less than the second dielectric thickness.

3. The semiconductor device of claim 1, further comprising a first contact over the first doped region and a second contact over the second doped region, the first contact having a height less than a height of the second contact.

4. The semiconductor device of claim 1, wherein the gate structure is over the first region of the device layer.

5. The semiconductor device of claim 1, wherein the second doped region is a drain region of the semiconductor device.

6. The semiconductor device of claim 1, wherein the second doped region is positioned farther from the gate structure than the first doped region.

7. The semiconductor device of claim 6, wherein the semiconductor device is an extended drain metal oxide semiconductor transistor.

8. The semiconductor device of claim 1, further comprising an insulating layer partially overlapping an upper surface of the gate structure and extending toward the second region of the device layer.

9. A semiconductor device, comprising: a multilayer substrate having a device layer over an isolation layer, the device layer including a first region having a first substrate thickness and a second region having a second substrate thickness less than the first substrate thickness; a gate structure over the device layer, wherein a top surface of the gate structure is planar, and wherein the gate structure is over the first region of the device layer and spaced apart from the second region of the device layer; and a first doped region and a second doped region in the device layer, the first doped region and the second doped region adjacent to and on opposite sides of the gate structure, wherein a bottom surface of the first doped region is above a bottom surface of the second doped region.

10. The semiconductor device of claim 9, wherein the first doped region is in the first region of the device layer, the second doped region is in the second region of the device layer, and an upper surface of the first region is above an upper surface of the second region. ​ 11. The semiconductor device of claim 9, further comprising a first contact over the first doped region and a second contact over the second doped region, wherein a bottom surface of the first contact is above a bottom surface of the second contact.

12. The semiconductor device of claim 9, wherein the first doped region is in a thicker device layer than the second doped region.

13. A method of forming a semiconductor device, comprising: providing a multi-layered substrate having a device layer over an isolation layer; forming a gate structure over a first region of the device layer having a first substrate thickness; and forming a second region of the device layer having a second substrate thickness adjacent to the gate structure, the second substrate thickness being less than the first substrate thickness, wherein a top surface of the gate structure is planar, and wherein the gate structure is over the first region of the device layer and spaced apart from the second region of the device layer.

14. The method of claim 13, wherein forming the second region of the device layer comprises forming a cavity in the second region of the device layer.

15. The method of claim 14, wherein the cavity is formed using a patterning technique.

16. The method of claim 13, further comprising: forming a first doped region in the first region of the device layer adjacent to the gate structure; and forming a second doped region in the second region of the device layer, wherein a bottom surface of the first doped region is above a bottom surface of the second doped region.

17. The method of claim 14, further comprising: forming an insulating layer partially overlapping an upper surface of the gate structure and over sidewalls and a bottom surface of the cavity in the second region of the device layer.

18. The method of claim 13, further comprising: depositing a dielectric layer over the first and second regions of the device layer, wherein the dielectric layer has a first dielectric thickness over the first region and a second dielectric thickness over the second region, the first dielectric thickness being greater than the second dielectric thickness.

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