Reverse conducting semiconductor device and method for manufacturing reverse conducting semiconductor device

Abstract

The invention relates to a reverse conducting semiconductor device and a method for manufacturing the reverse conducting semiconductor device. A reverse conducting semiconductor device is provided which avoids a substantial increase in manufacturing cost and has high latch-up tolerance and low recovery loss. A semiconductor substrate (50) has a first main surface (F1) and a second main surface (F2). A base contact layer (14) is arranged between a base layer (15) and the first main surface (F1) and constitutes a part of the first main surface (F1). An anode contact region (24) is arranged between an anode layer (25) and the first main surface (F1) and constitutes a part of the first main surface (F1), and the anode contact region has a second conductive type impurity concentration peak value higher than that of the anode layer (25). The anode contact region (24) includes a first anode contact layer (24b), and the first anode contact layer has a lower net concentration than the base contact layer (14) and a higher first conductive type impurity concentration than the base contact layer (14).

Description

Technical Field

[0001] The present invention relates to a reverse conducting semiconductor device and a method for manufacturing the reverse conducting semiconductor device. Background Art

[0002] For power modules that perform variable speed control of three-phase motors in general inverters, AC servos, etc., from the perspective of energy saving, insulated gate bipolar transistors (IGBTs) and freewheeling diodes are used. In this case, compared with using both a semiconductor device as an IGBT and a semiconductor device as a freewheeling diode (a diode for reverse conduction), by using a reverse conducting semiconductor device having an IGBT region and a diode region, i.e., a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT), the area occupied by the IGBT and the diode in the power module can be reduced. Therefore, the power module can be miniaturized.

[0003] For example, according to International Publication No. 2014 / 097454 (Patent Document 1), a semiconductor device in which an IGBT region and a diode region are formed on the same semiconductor substrate is disclosed. The IGBT region has a collector layer, an IGBT drift layer, a gate electrode, an emitter layer, a main body layer, and a main body contact layer with a high impurity concentration. The diode region has a trench electrode, a diode drift layer, a cathode layer, an anode layer, and an anode contact layer with a high impurity concentration. The diode region is divided into unit diode regions by a gate electrode or a trench electrode. In the unit diode region adjacent to the IGBT region, when the surface of the semiconductor substrate is viewed from above, the anode layer and the anode contact layer are mixedly arranged, and the anode contact layer is arranged at least in the portion opposite to the emitter layer across the gate electrode. In the semiconductor device, in the unit diode region adjacent to the IGBT region, the anode contact layer is not formed on the entire surface, but is formed locally. By setting such a structure, the amount of holes injected from the anode contact layer to the diode drift layer during diode operation is reduced. As a result, the recovery loss at the diode region can be reduced.

[0004] Patent Document 1: International Publication No. 2014 / 097454

[0005] From the perspective of manufacturing efficiency of semiconductor devices, it is preferred to centrally form the anode contact layer and the main contact layer through a common ion implantation process. In this case, the impurity concentrations of the anode contact layer and the main contact layer are substantially the same. If the impurity concentration is increased, the amount of holes injected from the anode contact layer to the diode drift layer increases, and thus the recovery loss in the diode region increases. On the contrary, if the impurity concentration is further reduced, the latch-up tolerance in the IGBT region is likely to be insufficient. In order to improve this trade-off relationship, it is preferred to make the impurity concentration of the anode contact layer lower than the impurity concentration of the main contact layer. On the other hand, in order to set such a concentration difference, it is usually necessary to greatly complicate the impurity addition process, resulting in a significant increase in manufacturing costs. Summary of the invention

[0006] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a reverse conducting semiconductor device having high latch-up resistance and low recovery loss while avoiding a significant increase in manufacturing cost.

[0007] The reverse conducting semiconductor device of the present invention has an insulated gate bipolar transistor region and a diode region, and the reverse conducting semiconductor device has a semiconductor substrate, an insulating gate structure, a collector electrode, and an emitter electrode. The semiconductor substrate is included in the insulated gate bipolar transistor region and the diode region, and the semiconductor substrate has a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate includes a drift layer of the first conductivity type, a base layer of the second conductivity type different from the first conductivity type, an emitter layer of the first conductivity type, a base contact layer of the second conductivity type, a collector layer of the second conductivity type, an anode layer of the second conductivity type, an anode contact region of the second conductivity type, and a cathode layer of the first conductivity type. The drift layer spans the insulated gate bipolar transistor region and the diode region. The base layer is arranged between the drift layer and the first main surface in the insulated gate bipolar transistor region. The emitter layer is arranged between the base layer and the first main surface in the insulated gate bipolar transistor region. The base contact layer is arranged between the base layer and the first main surface in the insulated gate bipolar transistor region, and constitutes a part of the first main surface. The collector layer is arranged between the drift layer and the second main surface in the insulated gate bipolar transistor region. The anode layer is arranged between the drift layer and the first main surface in the diode region. The anode contact region is arranged between the anode layer and the first main surface in the diode region, and constitutes a part of the first main surface, and the anode contact region has a second conductive type impurity concentration peak value higher than that of the anode layer. The cathode layer is arranged between the drift layer and the second main surface in the diode region. The insulated gate structure is used to form a channel for controlling an electrical path between the emitter layer and the drift layer through the base layer. The collector electrode is electrically connected to the collector layer and the cathode layer. The emitter electrode is in contact with the base contact layer and the anode contact region. The anode contact region includes a first anode contact layer, and the first anode contact layer has a lower net concentration than the base contact layer and a higher first conductive type impurity concentration than the base contact layer.

[0008] The method for manufacturing the reverse conducting semiconductor device for manufacturing the reverse conducting semiconductor device comprises the following steps: adding the first conductive type impurity to the emitter layer by ion implantation onto the first main surface of the semiconductor substrate; and adding the first conductive type impurity to the first anode contact layer by ion implantation onto the first main surface of the semiconductor substrate. The step of adding the first conductive type impurity to the emitter layer and the step of adding the first conductive type impurity to the first anode contact layer are simultaneously performed as a common step of adding the first conductive type impurity.

[0009] Effects of the Invention

[0010] According to the reverse conducting semiconductor device according to the present invention, a high latch-up tolerance and a low recovery loss can be achieved while avoiding a significant increase in manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view schematically showing the structure of the reverse conducting semiconductor device in the first embodiment.

[0012] Figure 2 It roughly indicates Figure 1 A partial top view of the structure of a reverse conducting semiconductor device observed along the first main surface of the semiconductor substrate in region II.

[0013] Figure 3 is along Figure 2 A partial cross-sectional view along line III-III.

[0014] Figure 4 is along Figure 2 A partial cross-sectional view along line IV-IV.

[0015] Figure 5 is along Figure 2 A partial cross-sectional view along line VV.

[0016] Figure 6 is along Figure 1 A partial cross-sectional view along line VI-VI.

[0017] Figure 7 is along Figure 1 A partial cross-sectional view along line VII-VII.

[0018] Figure 8 It roughly indicates Figure 1 Flowchart of a method for manufacturing a reverse conducting semiconductor device.

[0019] Fig. 9 is with Figure 2 The cross-sections common to the lines III-III, IV-IV, and VV in FIG. Figure 8 A partial cross-sectional view of a process in a manufacturing method.

[0020] Fig.10 is with Figure 2 The cross-sections common to the lines III-III, IV-IV, and VV in FIG. Figure 8 A partial cross-sectional view of a process in a manufacturing method.

[0021] Fig.11 is with Figure 2 The cross section of line III-III in FIG. Figure 8 A partial cross-sectional view of a process in a manufacturing method.

[0022] Fig.12 is with Figure 2 The cross section common to the line IV-IV and the line VV in FIG. Fig.11 A partial cross-sectional view of the process.

[0023] Fig.13 is with Figure 2 The cross section of line III-III in FIG. Figure 8 A partial cross-sectional view of a process in a manufacturing method.

[0024] Fig.14 is with Figure 2 The cross section of line IV-IV in FIG. 1 is schematically shown correspondingly. Fig.13 A partial cross-sectional view of the process.

[0025] Fig.15 is with Figure 2 The cross section of line VV in FIG. 1 is schematically shown correspondingly. Fig.13 A partial cross-sectional view of the process.

[0026] Fig.16 Yes means Figure 1 A top view of a modified example of .

[0027] Fig.17 So with Figure 2 The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the second embodiment, as viewed along the first main surface of the semiconductor substrate.

[0028] Fig.18 So with Figure 2 The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the third embodiment, as viewed along the first main surface of the semiconductor substrate.

[0029] Fig.19 So with Figure 2 The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the fourth embodiment, as viewed along the first main surface of the semiconductor substrate.

[0030] Fig. 20 So with Figure 2 The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the fifth embodiment, as viewed along the first main surface of the semiconductor substrate.

[0031] Fig.21 So with Figure 2 The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the sixth embodiment, as viewed along the first main surface of the semiconductor substrate.

[0032] Fig. 22 So with Figure 2The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the seventh embodiment, as viewed along the first main surface of the semiconductor substrate.

[0033] Fig.23 So with Figure 2 The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the eighth embodiment, as viewed along the first main surface of the semiconductor substrate.

[0034] Fig.24 So with Figure 2 The same viewing angle schematically shows a partial plan view of the structure of the reverse conducting semiconductor device according to the ninth embodiment, as viewed along the first main surface of the semiconductor substrate.

[0035] Fig.25 is Figure 3 A graph showing an example of concentration distribution of the semiconductor substrate included in the reverse conducting semiconductor device according to the tenth embodiment within the depth range of the single-dot chain line DD.

[0036] Fig.26 This is a graph showing an example of measurement results of the relationship between the net peak concentration and the controllable Vcc of the anode layer of the reverse conducting semiconductor device according to the tenth embodiment.

[0037] Fig. 27 This is a graph showing an example of measurement results of the relationship between the net peak concentration of the first anode contact layer of the reverse conducting semiconductor device according to the tenth embodiment and the on-voltage of the diode.

[0038] Fig.28 is Figure 2 A graph showing an example of concentration distribution of the semiconductor substrate included in the reverse conducting semiconductor device according to the eleventh embodiment, within the depth range of the single-dot chain line.

[0039] Fig.29 is Figure 2 A graph showing an example of concentration distribution of the semiconductor substrate of the reverse conducting semiconductor device according to the twelfth embodiment within the depth range of the single-dot chain line.

[0040] Fig.30 is Figure 2 A graph showing an example of concentration distribution of the semiconductor substrate of the reverse conducting semiconductor device according to the thirteenth embodiment, within the depth range of the single-dot chain line. DETAILED DESCRIPTION

[0041] The following is an explanation of the embodiments based on the accompanying drawings. In addition, in the following drawings, the same reference numerals are used for the same or equivalent parts, and their descriptions are not repeated. In some drawings, XYZ orthogonal coordinate axes are shown for convenience of viewing the drawings. In the drawings, regarding the impurity concentration, n - Indicates the net concentration ratio n + Low, n ++ Indicates the net concentration ratio n + High, p + Indicates that the net concentration is higher than p, p ++ Indicates the net concentration ratio p + high.

[0042] In the following embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type, in other words, the case where the first conductivity type impurity is a donor and the second conductivity type impurity is an acceptor is described. Such selection of conductivity type is a typical selection for obtaining good characteristics of IGBT. However, as a modified example, the first conductivity type may be p-type and the second conductivity type may be n-type. In this modified example, it should be understood that the donor and the acceptor in this specification are exchanged with each other.

[0043] In this specification, net concentration refers to the absolute value of the difference between donor concentration and acceptor concentration, and net peak concentration refers to the peak value of the net concentration in the region mentioned. In addition, the numerical value of the concentration is expressed by the number of atoms per unit volume.

[0044] <Implementation Method 1>

[0045] (Overview of the structure)

[0046] Figure 1 1 is a top view schematically showing the structure of the RC-IGBT 100 (reverse conducting semiconductor device) according to the first embodiment. As a planar layout (XY plane layout), the RC-IGBT 100 includes an IGBT region 10, a diode region 20, a terminal region 30, and a pad region 40. Figure 1 In order to facilitate the observation of the drawings, the diode region 20 is marked with a dot pattern. The IGBT region 10 and the diode region 20 are collectively referred to as a unit region. A pad region 40 is arranged adjacent to the unit region. A control pad 41 for controlling the RC-IGBT 100 is provided in the pad region 40. A terminal region 30 for maintaining the withstand voltage of the RC-IGBT 100 is arranged around the region including the unit region and the pad region 40.

[0047] Figure 2 It roughly indicates Figure 1FIG. 1 is a partial plan view of the structure of the RC-IGBT 100 viewed along the first main surface of the semiconductor substrate 50 in the region II. Figure 3 to Figure 5 Along Figure 2 The partial cross-sectional view of the line III-III, line IV-IV and line VV. Figure 2 In order to facilitate observation of the drawings, the structure above the first main surface is not shown in the figure.

[0048] The RC-IGBT 100 includes a semiconductor substrate 50, an active trench gate 11 (insulated gate structure), a collector electrode 7, and an emitter electrode 5. The semiconductor substrate 50 is included in the IGBT region 10 and the diode region 20, and has an upper surface F1 (first main surface) and a lower surface F2 (second main surface opposite to the first main surface). The upper surface F1 and the lower surface F2 each span the IGBT region 10 and the diode region 20. In other words, the upper surface F1 and the lower surface F2 each extend continuously between the IGBT region 10 and the diode region 20. It is preferred that the upper surface F1 is not n-type in the diode region 20.

[0049] The semiconductor substrate 50 includes an n-type - drift layer 1, p-type base layer 15, n-type emitter layer 13, p-type ++ Base contact layer 14, p-type collector layer 16, p-type anode layer 25, p-type anode contact region 24, and n-type cathode layer 26. - The drift layer 1 spans across the IGBT region 10 and the diode region 20. In other words, n - The drift layer 1 extends continuously between the IGBT region 10 and the diode region 20 .

[0050] The p-type base layer 15 is disposed on the n-type base layer 15 in the IGBT region 10. - The n-type emitter layer 13 is disposed between the p-type base layer 15 and the upper surface F1 in the IGBT region 10. ++ The base contact layer 14 is disposed between the p-type base layer 15 and the upper surface F1 in the IGBT region 10, and constitutes a portion of the upper surface F1. The p-type collector layer 16 is disposed between the p-type base layer 15 and the upper surface F1 in the IGBT region 10. - between the drift layer 1 and the lower surface F2.

[0051] The p-type anode layer 25 is disposed on the n-type anode layer of the diode region 20 . - The net peak concentration of the p-type anode layer 25 is preferably greater than or equal to 1×10 16 / cm 3 In this embodiment, if Figure 5As shown in FIG. 1 , the p-type anode layer 25 constitutes a portion of the upper surface F1. The cathode layer 26 is disposed on the n-type anode layer 25 in the diode region 20. - The anode contact region 24 is disposed between the p-type anode layer 25 and the upper surface F1 in the diode region 20 and constitutes a part of the upper surface F1 . The anode contact region 24 has a higher acceptor concentration peak than the p-type anode layer 25 .

[0052] The p-type anode contact region 24 includes p + Anode contact layer 24b (first anode contact layer), p ++ Anode contact layer 24a (second anode contact layer). + The anode contact layer 24b and p ++ Compared with the base contact layer 14, it has a lower net concentration and a higher donor concentration. + The anode contact layer 24b and p ++ Compared with the anode contact layer 24a, it has a lower net concentration. + The anode contact layer 24b and p ++ Compared with the anode contact layer 24a, it has a higher donor concentration. + The net peak concentration of the anode contact layer 24b is greater than or equal to 1×10 18 / cm 3 .

[0053] The active trench gate 11 is used to form a gate electrode for the n-type emitter layer 13 and the n-type emitter layer 13 through the p-type base layer 13. - The channel controls the electrical path between the drift layers 1. The potential of the active trench gate 11 is controlled by applying a potential to the gate pad 41c.

[0054] The collector electrode 7 is electrically connected to the p-type collector layer 16 and the cathode layer 26. The collector electrode 7 extends across the IGBT region 10 and the diode region 20. In other words, the collector electrode 7 extends continuously between the IGBT region 10 and the diode region 20. ++ The base contact layer 14 is in contact with the anode contact region 24. The emitter electrode 5 straddles the IGBT region 10 and the diode region 20. In other words, the emitter electrode 5 continuously extends between the IGBT region 10 and the diode region 20.

[0055] (Overview of Manufacturing Method)

[0056] In the method for manufacturing the RC-IGBT 100 of the present embodiment, the steps of adding a donor to the n-type emitter layer 13 and the steps of adding a donor to the n-type emitter layer 13 are performed. + The donor addition step of the anode contact layer 24b is regarded as a common donor addition step (refer to the following). Fig.11 and Fig.12In addition, p ++ The process of adding acceptors to the base contact layer 14 and performing p + The process of adding the acceptor to the anode contact layer 24b is regarded as a common acceptor adding process (refer to the following). Figure 13 to Figure 15 The amount of donor ions (first conductivity type impurity ions) implanted per unit area in the common donor addition step is lower than the amount of acceptor ions (second conductivity type impurity ions) implanted per unit area in the common acceptor addition step. By the above donor addition step, the n-type emitter layer 13 is formed while the p-type emitter layer 13 is formed. + The net concentration ratio p of the anode contact layer 24b is ++ The base contact layer 14 has a low net concentration of counter-doping.

[0057] (Details of the structure)

[0058] Hereinafter, the details of the first embodiment will be described, although some parts overlap with the above-mentioned general description.

[0059] Reference Figure 1 The IGBT region 10 and the diode region 20 each extend from one end side to the other end side of the RC-IGBT 100, and the IGBT region 10 and the diode region 20 are alternately arranged in a strip shape in a direction perpendicular to the extending direction. Figure 1 , showing three IGBT regions 10 and two diode regions, all diode regions 20 are sandwiched by the IGBT region 10. In addition, the number of IGBT regions 10 and diode regions 20 is not limited to this, and is arbitrary. Figure 1 In this case, all the IGBT regions 10 are sandwiched by the diode regions 20. Alternatively, the number of IGBT regions 10 and the number of diode regions 20 may be the same, and they may be alternately arranged.

[0060] exist Figure 1In the figure, a pad area 40 is provided adjacent to the IGBT area 10 on the lower side of the paper. The control pad 41 may be, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sensing diode pads 41d and 41e. The current sensing pad 41a is used to detect the current flowing through the cell area of ​​the RC-IGBT 100. To this end, the current sensing pad 41a is electrically connected to a part of the IGBT cell or the diode cell in the cell area in such a manner that a current of a few to tens of thousands of the current flowing through the entire cell area of ​​the RC-IGBT 100 flows. A gate drive voltage for on-off control of the RC-IGBT 100 is applied to the gate pad 41c. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b may be electrically connected to the p-type base layer via the p-type contact layer. The temperature sensing diode pads 41d and 41e are electrically connected to the anode and cathode of the temperature sensing diode provided in the RC-IGBT 100. The temperature of the RC-IGBT 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0061] As a withstand voltage maintenance structure possessed by the terminal region 30, for example, an FLR (Field Limmiting Ring) or a VLD (Variation of Lateral Doping) is provided in a manner that surrounds the cell region on the upper surface F1 side of the RC-IGBT 100. The FLR is composed of a ring-shaped p-type terminal well layer, and the VLD is composed of a p-type well layer having a concentration gradient. The number of p-type terminal well layers at the FLR and the concentration distribution at the VLD can be appropriately selected according to the withstand voltage design of the RC-IGBT 100. In addition, the withstand voltage level of the RC-IGBT is not particularly limited. In addition, a p-type terminal well layer can be provided over substantially the entire area of ​​the pad region 40, or at least any one of an IGBT cell and a diode cell can be provided in the pad region 40.

[0062] Reference Figure 2 In the IGBT region 10, an active trench gate 11 composed of an active gate electrode 11a and a gate insulating film 11b, a dummy trench gate 12 composed of a dummy gate electrode 12a and a dummy trench insulating film 12b, an n-type emitter layer 13, and a p ++The base contact layer 14. In addition, the dummy trench gate 12 may be omitted. The active gate electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c, and a gate potential is applied thereto. The dummy gate electrode 12a of the dummy trench gate 12 is electrically connected to the emitter electrode 5 through a wiring (not shown), and an emitter potential is applied thereto. The dummy gate electrode 12a is connected to the n-type electrode 5 via the dummy trench insulating film 12b. - The n-type drift layer 1 is opposite to the n-type drift layer 1. The sidewall of the dummy trench gate 12 is not formed with an n-type emitter layer 13 but with a p-type emitter layer 13. ++ Base contact layer 14 .

[0063] In the diode region 20, a diode trench gate 21 composed of a diode trench electrode 21a and a diode trench insulating film 21b, a p-type anode layer 25, and a p-type gate electrode 21a are arranged. ++ Anode contact layer 24a, p + Anode contact layer 24b. In the first embodiment, p ++ The anode contact layer 24a is configured in a strip shape and is orthogonal to the diode trench gate 21. ++ The anode contact layer 24a is separated from the p-type anode layer 25. + The anode contact layer 24b is configured in a strip shape. Figure 2 In FIG. 1 , a structure having one active trench gate 11 and three dummy trench gates 12 arranged next to the active trench gate 11 is shown. Figure 2 Although not shown in the figure, the structure is repeated in the Y direction. In addition, in each of the above structures, the number of active trench gates 11 is any number greater than or equal to 1, and the number of dummy trench gates 12 is any number greater than or equal to 0. Therefore, the dummy trench gates 12 may also be omitted.

[0064] Reference Figure 3 (along Figure 2 The IGBT region 10 has an n-type carrier storage layer 2 arranged on the n-type carrier storage layer 2. - between the drift layer 1 and the upper surface F1; a p-type base layer 15 disposed between the carrier storage layer 2 and the upper surface F1; and an n-type emitter layer 13 and a p ++ Base contact layers 14 are each disposed between p-type base layer 15 and upper surface F1 .

[0065] The n-type carrier storage layer 2 is provided on the n - The upper surface of the drift layer 1 (the surface facing the upper surface F1) has a larger - The drift layer 1 has a high donor concentration. The n-type carrier storage layer 2 can reduce the conduction loss when a current flows through the IGBT region 10. In addition, the n-type carrier storage layer 2 and the n -The drift layer 1 is an n-type region that is in contact with each other, so the two can also be regarded as drift layers. - Drift layer 1.

[0066] The p-type base layer 15 is arranged on the n-type carrier storage layer 2 (n-type base layer 15 is arranged on the n-type carrier storage layer 2 when the n-type carrier storage layer 2 is omitted). - The p-type base layer 15 is in contact with the gate insulating film 11 b of the active trench gate 11 .

[0067] The n-type emitter layer 13 and the p ++ Each base contact layer 14 is disposed on the p-type base layer 15 and partially constitutes the upper surface F1. The n-type emitter layer 13 is in contact with the gate insulating film 11b of the active trench gate 11. ++ The base contact layer 14 has a higher acceptor concentration than that of the p-type base layer 15 .

[0068] In the present embodiment, the emitter electrode 5 has an electrode layer 5a and a barrier metal layer 5b between the electrode layer 5a and the upper surface F1 of the semiconductor substrate 50. The material of the barrier metal layer 5b is preferably selected in a manner to obtain a good ohmic contact with the semiconductor substrate 50, and can be, for example, a conductor containing titanium (Ti), for example, titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). The electrode layer 5a is, for example, an aluminum alloy layer such as an aluminum silicon alloy (Al-Si alloy) layer. At least one plated film formed by chemical plating or electrolytic plating can also be formed on the aluminum alloy layer. The plated film is composed of, for example, nickel (Ni). In the case where there is a tiny area such as between adjacent interlayer insulating films 4 that cannot be well buried by the electrode layer 5a, in order to well bury the area, a part composed of the above-mentioned material can be formed after a part composed of a material with good burying properties, i.e., tungsten, is formed.

[0069] In addition, the IGBT region 10 has a structure that penetrates the n-type emitter layer 13, the p-type base layer 15, and the carrier storage layer 2 from the upper surface F1 to each of the n-type emitter layer 13, the p-type base layer 15, and the carrier storage layer 2. -An active trench gate 11 and a dummy trench gate 12 of a drift layer 1. The active trench gate 11 and the dummy trench gate 12 are arranged in a trench formed in a semiconductor substrate 50. Specifically, the active trench gate 11 has a gate insulating film 11b formed on the inner wall of the trench and an active gate electrode 11a formed in the trench via the gate insulating film 11b. If a gate drive voltage is applied to the active gate electrode 11a, a channel is formed in a p-type base layer 15 in contact with the gate insulating film 11b. The dummy trench gate 12 has a dummy trench insulating film 12b formed on the inner wall of the trench and a dummy gate electrode 12a formed in the trench via the dummy trench insulating film 12b. An interlayer insulating film 4 is arranged on the active trench gate 11. The interlayer insulating film 4 is insulated from each other by being arranged between the active trench gate 11 and the barrier metal layer 5b of the emitter electrode 5. The interlayer insulating film 4 over the dummy trench gate 12 may be omitted, in which case the dummy gate electrode 12 a and the emitter electrode 5 are in contact with each other.

[0070] The IGBT region 10 has a - The n-type buffer layer 3 is disposed between the drift layer 1 and the lower surface F2. The n-type buffer layer 3 has a - The drift layer 1 has a high donor concentration. The n-type buffer layer 3 is provided to suppress the penetration of the depletion layer extending from the p-type base layer 15 toward the lower surface F2 when the RC-IGBT 100 is in the off state. In addition, the buffer layer 3 may be omitted. In addition, since the n-type buffer layer 3 and the n-type - The drift layer 1 is an n-type region that is in contact with each other, and therefore both of them can also be regarded as a drift layer.

[0071] In addition, the IGBT region 10 has an n-type buffer layer 3 (n-type buffer layer 3 is omitted). - There is a p-type collector layer 16 between the drift layer 1) and the lower surface F2. The p-type collector layer 16 partially constitutes the lower surface F2 and is ohmically connected to the collector electrode 7 by contacting the collector electrode 7. The collector electrode 7 can be composed of at least any one of Al, AlSi, Ni, Ti and Au. Similar to the emitter electrode 5, it can also be composed of an aluminum alloy or a laminate of an aluminum alloy and a plated film. The structure of the collector electrode 7 can also be different from that of the emitter electrode 5.

[0072] The n-type emitter layer 13 is provided in contact with the gate insulating film 11b on both sides in the Y direction (the width direction of the active trench gate 11). Figure 2 In the X direction (the extension direction of the active trench gate 11), ++ The base contact layers 14 are arranged alternately. A p-type base contact layer 14 is also provided between two adjacent dummy trench gates 12. ++ Base contact layer 14 .

[0073] The active gate electrode 11a may be made of polysilicon to which phosphorus or the like is added, or a metal. The electrode layer 5a of the emitter electrode 5 may be made of at least one of Al and AlSi. The barrier metal layer 5b of the emitter electrode 5 may also be made of Ti, TiN, TiSi, or CoSi, and may include a plug made of W or the like.

[0074] Alternatively, the barrier metal layer 5b may be omitted and the electrode layer 5a may be in contact with the semiconductor substrate 50 instead of the barrier metal layer 5b. Alternatively, the barrier metal layer 5b may be provided only on the n-type portion of the upper surface F1, for example, on the n-type emitter layer 13.

[0075] Reference Figure 3 (along Figure 2 The diode region 20 has a p-type anode layer 25 disposed on the n-type anode layer 25. - between the drift layer 1 and the upper surface F1; and p + The anode contact layer 24b is disposed between the p-type anode layer 25 and the upper surface F1. + The anode contact layer 24b penetrates and reaches n - The diode trench gate 21 of the drift layer 1. The diode trench gate 21 is arranged in a trench formed in the semiconductor substrate 50. Specifically, the diode trench gate 21 has a diode trench insulating film 21b formed on the inner wall of the trench, and a diode trench electrode 21a formed in the trench through the diode trench insulating film 21b. By directly configuring the emitter electrode 5 on the diode trench gate 21, an emitter potential is applied to the diode trench electrode 21a. As a modified example, an interlayer insulating film 4 can be provided on the diode trench gate 21. In this case, the diode trench electrode 21a of the diode trench gate 21 is electrically connected to the emitter electrode 5 through a wiring not shown. The diode trench electrode 21a is connected to the n-type semiconductor substrate 5 through the diode trench insulating film 21b. - type drift layer 1 is opposite.

[0076] In addition, the diode region 20 has a - An n-type buffer layer 3 between the drift layer 1 and the lower surface F2, and an n-type cathode layer 26 disposed between the n-type buffer layer 3 and the lower surface F2. The n-type cathode layer 26 partially constitutes the lower surface F2 and is in contact with the collector electrode 7. In addition, the p-type anode layer 25 may also be constituted by the same structure as the stacked structure of the p-type base layer 15 and the carrier storage layer 2 of the IGBT region 10. In addition, as described above, the barrier metal layer 5b may be omitted, and the electrode layer 5a may be in contact with the semiconductor substrate 50 instead of the barrier metal layer 5b.

[0077] p + The donor concentration of the anode contact layer 24b is greater than or equal to n - Donor concentration in drift layer 1. + The acceptor concentration of the anode contact layer 24b is greater than or equal to p + The donor concentration of the anode contact layer 24b. + The peak value of the acceptor concentration of the anode contact layer 24b is higher than the peak value of the acceptor concentration of the p-type anode layer 25. + The net doping concentration of the anode contact layer 24 b is higher than the net doping concentration of the p-type anode layer 25 .

[0078] Reference Figure 4 (along Figure 2 The section of line IV-IV in Figure 3 Differently, in this cross section, a p ++ The anode contact layer 24a is not provided with p + Anode contact layer 24b. ++ The net doping concentration of the anode contact layer 24a is greater than p + The net doping concentration of the anode contact layer 24b is high.

[0079] Reference Figure 5 (along Figure 2 The cross section of line VV in Figure 3 and Figure 4 Differently, in this cross section, no p is configured in the diode region 20. ++ Anode contact layer 24a and p + The anode contact layer 24 b and therefore the p-type anode layer 25 are in contact with the barrier metal layer 5 b of the emitter electrode 5 .

[0080] Reference Figure 2 In the embodiment 1, the anode contact region 24 and the p-type anode layer 25 are alternately arranged in the X direction (the extending direction of the diode trench gate 21) between two adjacent diode trench gates 21. + Anode contact layers 24b are provided between ++ Anode contact layer 24a.

[0081] In the present embodiment, the IGBT region 10 and the diode region 20 are in contact with each other, but there may be another region between them. In either case, the IGBT region 10 and the diode region 20 share one semiconductor substrate 50. In the former case, the end of the p-type collector layer 16 may be located at the boundary between the IGBT region 10 and the diode region 20, or may extend into the diode region 20 by a distance U1 ( Figure 3 to Figure 5). In the case of U1>0, since the distance between the n-type cathode layer 26 and the active trench gate 11 can be increased, even when the gate drive voltage is applied to the active gate electrode 11a when the freewheeling diode of the RC-IGBT 100 is in operation, the current from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n-type cathode layer 26 can be suppressed. For this reason, the distance U1 is preferably, for example, about 100 μm. However, depending on the purpose of the RC-IGBT, the distance U1 is sometimes preferably greater than or equal to 0 and less than 100 μm. In addition, as a modification, by injecting an acceptor into the lower surface F2, Figure 3 to Figure 5 A part of the region where the n-type cathode layer 26 is arranged may be made into a p-type region.

[0082] n - The donor of the drift layer 1 can be arsenic or phosphorus, n - The donor concentration of the drift layer 1 is, for example, greater than or equal to 1×10 12 / cm 3 and less than or equal to 1×10 15 / cm 3 The donor of the n-type emitter layer 13 may be arsenic or phosphorus. The donor concentration of the n-type emitter layer 13 is, for example, greater than or equal to 1×10 17 / cm 3 and less than or equal to 1×10 20 / cm 3 The donor of the n-type carrier accumulation layer 2 may be arsenic or phosphorus. The donor concentration of the n-type carrier accumulation layer 2 may be greater than or equal to 1×10 13 / cm 3 and less than or equal to 1×10 17 / cm 3 The donors of the n-type buffer layer 3 may be phosphorus (P) and protons (H + ), the donor concentration of the n-type buffer layer 3 is, for example, greater than or equal to 1×10 12 / cm 3 and less than or equal to 1×10 18 / cm 3 The donor of the n-type cathode layer 26 may be arsenic or phosphorus. The donor concentration of the n-type cathode layer 26 may be greater than or equal to 1×10 16 / cm 3 and less than or equal to 1×10 21 / cm 3 .

[0083] The acceptor of the p-type anode contact region 24 may be boron or aluminum. The acceptor concentration of the p-type anode contact region 24 is, for example, greater than or equal to 1×10 15 / cm 3 and less than or equal to 1×1020 / cm 3 . p ++ The acceptor of the base contact layer 14 can be boron or aluminum. ++ The acceptor concentration of the base contact layer 14 is, for example, greater than or equal to 1×10 15 / cm 3 and less than or equal to 1×10 20 / cm 3 The donor of the p-type base layer 15 may be boron or aluminum. The donor concentration of the p-type base layer 15 is, for example, greater than or equal to 1×10 12 / cm 3 and less than or equal to 1×10 19 / cm 3 The acceptor of the p-type collector layer 16 may be boron or aluminum. The acceptor concentration of the p-type collector layer 16 is, for example, greater than or equal to 1×10 16 / cm 3 and less than or equal to 1×10 20 / cm 3 The acceptor of the p-type anode layer 25 may be boron or aluminum. The acceptor concentration of the p-type anode layer 25 is, for example, greater than or equal to 1×10 12 / cm 3 and less than or equal to 1×10 19 / cm 3 .

[0084] Next, the structure of the terminal region 30 will be described below. Figure 6 and Figure 7 Along Figure 1 Partial cross-sectional view along line VI-VI and line VII-VII.

[0085] As described above, each of the upper surface F1 and the lower surface F2 not only crosses the IGBT region 10 and the diode region 20, but also crosses the terminal region 30. In other words, they extend continuously between the IGBT region 10, the diode region 20, and the terminal region 30. - As described above, the drift layer 1 not only extends over the IGBT region 10 and the diode region 20, but also extends over the termination region 30. In other words, n - The drift layer 1 extends continuously between the IGBT region 10 , the diode region 20 , and the termination region 30 .

[0086] In the terminal area 30, at n - The surface of the drift layer 1 facing the upper surface F1 is provided with n + The p-type channel stop layer 32 and a plurality of p-type terminal well layers 31. The acceptor of the p-type terminal well layer 31 may be boron or aluminum. The acceptor concentration of the p-type terminal well layer 31 is, for example, greater than or equal to 1×10 14 / cm 3and less than or equal to 1×10 19 / cm 3 The p-type end well layer 31 surrounds the cell region including the IGBT region 10 and the diode region 20. The p-type end well layer 31 is provided in a plurality of ring-shaped patterns, and the number of the ring-shaped patterns is appropriately selected according to the withstand voltage design of the RC-IGBT 100. + The p-type channel stopper layer 32 surrounds the p-type end well layer 31 .

[0087] In n - A p-type terminal collector layer 16a is provided between the drift layer 1 and the lower surface F2 of the semiconductor substrate 50. The p-type terminal collector layer 16a is continuously formed as a whole with the p-type collector layer 16 provided in the cell region. Therefore, the p-type terminal collector layer 16a and the p-type collector layer 16 are collectively referred to as a collector layer. The p-type terminal collector layer 16a may extend into the diode region 20 by a distance U2. Figure 1 When the diode region 20 and the termination region 30 are adjacent to each other as shown, the distance between the n-type cathode layer 26 and the p-type termination well layer 31 of the diode region 20 increases by satisfying U2>0. This can prevent the p-type termination well layer 31 from operating as the anode of the diode. The distance U2 is, for example, about 100 μm.

[0088] The collector electrode 7 not only straddles the IGBT region 10 and the diode region 20 as described above, but also straddles the termination region 30. In other words, the collector electrode 7 extends continuously between the IGBT region 10, the diode region 20, and the termination region 30.

[0089] The emitter electrode 5 not only spans the IGBT region 10 and the diode region 20 as described above, but also spans a portion of the termination region 30. In other words, the emitter electrode 5 extends continuously between the IGBT region 10, the diode region 20, and a portion of the termination region 30. On the upper surface F1 of the semiconductor substrate 50, the termination region 30 has a termination electrode 6 separated from the emitter electrode 5. Similar to the emitter electrode 5 having the electrode layer 5a and the barrier metal layer 5b, the termination electrode 6 may have the electrode layer 6a and the barrier metal layer 6b. The termination electrode 6, the p-type termination well layer 31, and the n-type termination well layer 32 may be connected to the p-type termination well layer 33. + The channel stopper layers 32 are electrically connected to each other through contact holes formed in the interlayer insulating film 4 on the upper surface F1. The emitter electrode 5 and the terminal electrode 6 are electrically connected through the semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating Silicon Nitride).

[0090] The terminal region 30 is provided with a terminal protection film 34 that covers the emitter electrode 5, the terminal electrode 6, and the semi-insulating film 33. The terminal protection film 34 is made of, for example, polyimide.

[0091] (Details of the manufacturing method)

[0092] Figure 8 1 is a flow chart schematically showing a method for manufacturing the RC-IGBT 100 . Figures 9 to 15 It roughly indicates Figure 8 A partial cross-sectional view of a process in the manufacturing method of. In addition, Fig. 9 The cross section and Figure 2 The cross section shared by line III-III, line IV-IV and line VV in FIG. Fig.10 The cross section is also Figure 2 The cross section shared by line III-III, line IV-IV and line VV in FIG. Fig.11 and Fig.12 Showing the same process, Fig.11 The cross section and Figure 2 The cross section of line III-III in corresponds to, in addition, Fig.12 The cross section and Figure 2 The cross section shared by the line IV-IV and the line VV in FIG. Figure 13 to Figure 15 Showing the same process, Figure 11 to Figure 15 Their respective cross sections and Figure 2 The cross-sections correspond to the lines III-III, IV-IV and VV.

[0093] Reference Fig. 9 In step ST10 ( Figure 8 ), a semiconductor substrate 50 is prepared. The prepared semiconductor substrate 50 is, for example, a wafer made by the FZ (Floating Zone) method, i.e., an FZ wafer, a wafer made by the MCZ (Magnetic applied Zochralki) method, i.e., an MCZ wafer, or an epitaxial wafer. The prepared semiconductor substrate 50 is included in the completed RC-IGBT 100 and directly becomes n - The drift layer 1 is of n-type as a whole. The donor concentration is appropriately selected according to the withstand voltage of the RC-IGBT 100. For example, when the withstand voltage is 1200V, the donor concentration is adjusted so that n -The resistivity of the drift layer 1 is about 40 to 120 Ω·cm. By performing ion implantation on the semiconductor substrate 50 prepared in this way and then performing heat treatment, the desired layer (region) is formed in the semiconductor substrate 50. During the heat treatment, the implanted ions are diffused and activated. The description of the heat treatment is omitted below, but the heat treatment can be carried out at an appropriate timing. The order of the ion implantation process can be swapped. In addition, other processes can also be swapped within the range that does not cause hindrance.

[0094] In step ST20, the end area 30 ( Figure 6 and Figure 7 ) is formed by a known manufacturing method. For example, in order to form an FLR having a p-type terminal well layer 51 as a withstand voltage retention structure of the terminal region 30, acceptor ions are added by ion implantation. In addition, as for part or all of the ion implantation for forming the terminal region 30, it is also possible to perform ion implantation simultaneously when performing ion implantation on the IGBT region 10 and the diode region 20 as described below.

[0095] In steps ST30 and ST40 ( Figure 8 ), a p-type base layer 15 and a p-type anode layer 25 are formed by injecting acceptors such as boron (B) from the upper surface F1 side of the semiconductor substrate 50. Since the donors and acceptors are added by ion implantation after masking is performed on the upper surface F1 of the semiconductor substrate 50, they are selectively formed on the upper surface F1 of the semiconductor substrate 50. In addition, masking refers to a process of applying a resist on the semiconductor substrate 50 and using photolithography to form an opening in a specified area of ​​the resist, thereby forming a mask. By using this mask, ion implantation or etching and other processes can be performed on a specific area of ​​the semiconductor substrate 50. The p-type anode layer 25 and the p-type base layer 15 are formed by ion implantation of acceptors simultaneously or individually. In the case of forming them separately, their respective structures can be adjusted independently. By ion implantation of acceptors for forming the p-type anode layer 25, a p-type end well layer 51 ( Figure 6 and Figure 7 ). When they are formed separately, their structures can be adjusted independently. Alternatively, the p-type terminal well layer 51, the p-type base layer 15, and the p-type anode layer 25 may be formed simultaneously.

[0096] In step ST50 ( Figure 8 ), by injecting donors such as phosphorus (P) from the upper surface F1 side of the semiconductor substrate 50, an n-type carrier storage layer 2 is formed.

[0097] Reference Fig.10 In step ST60 ( Figure 8), an active trench gate 11, a dummy trench gate 12, and a diode trench gate 21 are formed. Specifically, first, trenches for these are formed by etching. For example, an oxide film (e.g., SiO2) having an opening can be used for etching. 2 In addition, Fig.10 The spacing of the grooves is uniform, but the spacing of the grooves can also be uneven. Next, the inner wall of the above-mentioned groove is oxidized by heating the semiconductor substrate 50 in an atmosphere containing oxygen. Thus, the gate insulating film 11b, the dummy trench insulating film 12b and the diode trench insulating film 21b are formed at the same time. In the subsequent process, the portion of the surface of the semiconductor substrate 50 that is unnecessarily oxidized by the oxidation is removed. Next, in the groove, doped polysilicon is deposited by CVD (chemical vapor deposition) or the like, thereby forming an active gate electrode 11a, a dummy gate electrode 12a and a diode trench electrode 21a.

[0098] Reference Fig.11 (and Figure 2 The cross section of line III-line III corresponds to Fig.12 (and Figure 2 In step ST70 ( Figure 8 ), an n-type emitter layer 13 and a p + The implantation mask 61 for the anode contact layer 24b (first anode contact layer) has a shape that allows the n-type emitter layer 13 and the p-type emitter layer 14 to be formed. + Anode contact layer 24b (see Figure 3 ) area. In step ST80 ( Figure 8 ) in the step of adding a donor to the n-type emitter layer 13 by ion implantation onto the upper surface F1 of the semiconductor substrate 50 using the implantation mask 61 and the step of adding a donor to the p-type emitter layer 13. + Anode contact layer 24b (see Figure 3 ) are performed simultaneously as a common donor adding step. Fig.11 In, it becomes p + Anode contact layer 24b (see Figure 3 ) is a temporary region 24bD that is n-type instead of p-type. The temporary region 24bD is n-type by adding donors in the same manner as the n-type emitter layer 13. Thereafter, the implantation mask 61 is removed.

[0099] Reference Fig.13 (and Figure 2 The cross section of line III-line III corresponds to the cross section of line III), Fig.14 (and Figure 2The cross-sections of line IV-line IV and line V-line V correspond to the cross-sections of line IV-line IV and line V-line V), Fig.15 (and Figure 2 In step ST90 ( Figure 8 ), forming p ++ Base contact layer 14, p + Anode contact layer 24b (first anode contact layer), p ++ The implantation mask 62 for the anode contact layer 24a (second anode contact layer) is provided. The implantation mask 62 has a ++ Base contact layer 14, p + Anode contact layer 24b and p ++ The anode contact layer 24a is exposed in the opening. Figure 8 ) is performed by ion implantation onto the upper surface F1 of the semiconductor substrate 50 using the implantation mask 62. ++ The acceptor addition step of the base contact layer 14 is performed + Anode contact layer 24b ( Figure 3 ) of the acceptor addition process, and p ++ The acceptor addition step of the anode contact layer 24a is performed as a common acceptor addition step. + Anode contact layer 24b ( Figure 3 ) is added to the acceptor, and the temporary region 24bD ( Fig.11 ) becomes p-type + Anode contact layer 24b. In order to be able to reverse the conductivity type in this way, a common donor adding step ( Figure 13 to Figure 15 ) is higher than the amount of donor ions implanted per unit area in the common acceptor addition step ( Fig.11 and Fig.12 ) has a low implantation amount of acceptor ions per unit area. Thereafter, the implantation mask 62 is removed.

[0100] In addition, as described above, the order of the ion implantation steps can be reversed. Figure 13 to Figure 15 ) and acceptor addition process ( Fig.11 and Fig.12 In this case, at the time point between the two addition steps, the + The region of the anode contact layer 24b replaces the temporary region 24bD ( Fig.11 ), forming a ++ The base contact layer 14 similarly has a p-type region with a high net concentration.

[0101] In step ST110 ( Figure 8 ), for example, formed by SiO 2The interlayer insulating film 4 (see Figure 3 to Figure 5 ). Furthermore, a contact hole is formed in the interlayer insulating film 4. The contact hole is formed between the n-type emitter layer 13 and the p-type emitter layer 14. ++ Base contact layer 14, p + Anode contact layer 24b, p ++ On each of the anode contact layer 24a, the dummy gate electrode 12a and the diode trench electrode 21a.

[0102] In step ST120 ( Figure 8 ) as the emitter electrode 5 (refer to Figure 3 to Figure 5 ) to form a barrier metal layer 5b and an electrode layer 5a. The barrier metal layer 5b is formed by forming a titanium nitride film by PVD (Physical Vapor Deposition) or CVD. As the electrode layer 5a, for example, an aluminum alloy layer such as an aluminum silicon alloy (Al-Si alloy) layer is formed by PVD such as sputtering or evaporation. At least one plated film formed by chemical plating or electrolytic plating may also be formed on the aluminum alloy layer. The plated film is composed of, for example, nickel (Ni) or its alloy. By forming at least a portion of the electrode layer 5a by a plating method, the thickness of the electrode layer 5a can be easily ensured. By thickening the electrode layer 5a, the heat capacity becomes larger, thereby improving the heat resistance of the electrode layer 5a.

[0103] In step ST130 ( Figure 8 ), a back surface structure is formed. The back surface structure is formed, for example, as follows.

[0104] First, the thickness of the semiconductor substrate 50 is reduced to a predetermined design thickness by polishing the lower surface F2 of the semiconductor substrate 50. The design thickness is, for example, 80 μm to 200 μm.

[0105] Next, the n-type buffer layer 3 is formed by implanting donors into the lower surface F2 of the semiconductor substrate 50. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the terminal region 30. Alternatively, the n-type buffer layer 3 may be formed only in the IGBT region 10 or the diode region 20. The implantation of donors may be performed, for example, by implanting phosphorus (P) ions and protons (H +) is performed by at least any one of the implantations of phosphorus and protons. Protons can be implanted from the lower surface F2 of the semiconductor substrate 50 to a deep position at a relatively low acceleration energy. In addition, by changing the acceleration energy, the implantation depth of the protons can be changed relatively easily. Therefore, if multiple ion implantations are performed while changing the acceleration energy when the n-type buffer layer 3 is formed by protons, it is easy to fully ensure the size of the n-type buffer layer 3 in the thickness direction (Z direction) of the semiconductor substrate 50 compared to the case of formation by phosphorus. On the other hand, phosphorus has a high activation rate as a donor compared to protons. Therefore, by forming the n-type buffer layer 3 with phosphorus, even with a thin semiconductor substrate 50, the effect of more reliably suppressing the penetration of the depletion layer can be obtained. In order to further enhance this effect, it is preferred to form the n-type buffer layer 3 by implanting both protons and phosphorus, in which case the protons are implanted from the lower surface F2 to a deeper position than the phosphorus.

[0106] In addition, the p-type collector layer 16 is formed by injecting an acceptor into the lower surface F2 of the semiconductor substrate 50. The acceptor injection is performed by, for example, injecting boron (B). When the p-type collector layer 16 is formed, a p-type terminal collector layer 16a may also be formed in the terminal region 30 at the same time (see Figure 6 and Figure 7 ).

[0107] Next, an n-type cathode layer 26 is formed in the diode region 20 by, for example, implanting phosphorus (P) (see Figure 3 to Figure 5 ). The amount of donors injected to form the n-type cathode layer 26 is greater than the amount of acceptors injected to form the p-type collector layer 16. Figure 3 to Figure 5 , the depths of the p-type collector layer 16 and the n-type cathode layer 26 from the lower surface F2 are shown to be the same, but the depth of the n-type cathode layer 26 is preferably greater than or equal to the depth of the p-type collector layer 16. Since acceptors are also injected into the region where the n-type cathode layer 26 is formed, donors that are larger than the amount that cancels the acceptors are injected.

[0108] The ions injected into the lower surface F2 side of the semiconductor substrate 50 can be activated by laser annealing in which a laser is irradiated to the lower surface F2. By laser annealing, not only the p-type collector layer 16 but also the n-type buffer layer 3 located at a relatively shallow distance from the lower surface F2 can be activated at the same time. When protons are used for the n-type buffer layer 3, the heat treatment temperature suitable for its activation is relatively low, which is about 380°C to 450°C. Therefore, it is necessary to be careful not to make the area where the protons are injected reach a temperature higher than about 380°C to 450°C. Since laser annealing can make the area near the lower surface F2 of the semiconductor substrate 50 a high temperature, even after protons are injected into the n-type buffer layer 3 away from the lower surface F2, by appropriately adjusting the laser irradiation conditions, the area near the lower surface F2 can be heated to a high temperature without exceeding the above-mentioned temperature range.

[0109] Next, the collector electrode 7 ( Figure 3 to Figure 5 ). The collector electrode 7 is formed across the IGBT region 10, the diode region 20 and the terminal region 30 of the lower surface F2. The collector electrode 7 can also be formed on the entire surface of the lower surface F2. As the collector electrode 7, for example, an aluminum alloy layer such as an aluminum silicon alloy (Al-Si alloy) layer or a titanium (Ti) layer is formed by PVD such as sputtering or evaporation. For example, a stacked structure can also be provided by these layers, a nickel (Ni) layer or a gold (Au) layer. In addition, at least one plated film formed by chemical plating or electrolytic plating can also be formed on the metal film formed by PVD.

[0110] In addition, step ST130 may be performed at a timing between the formation of the aluminum alloy layer and the formation of at least one plating film in the above description related to step ST120 .

[0111] In this way, the RC-IGBT 100 is manufactured. In mass production, when the wafer-level process is completed, a plurality of RC-IGBTs 100 arranged in a matrix are formed on one wafer. These are cut into individual RC-IGBTs 100 by laser dicing or blade dicing.

[0112] (Effect)

[0113] According to the first embodiment, first, the p of the diode region 20 + The anode contact layer 24b and the p-type IGBT region 10 ++ The net concentration of the base contact layer 14 is lower than that of the base contact layer 14. This net concentration difference can achieve high latch-up resistance of the IGBT region 10 and low recovery loss of the diode region 20. + The anode contact layer 24b and p ++The base contact layer 14 has a higher donor concentration than the base contact layer 14. By utilizing this high donor concentration, the process of adjusting the acceptor concentration can be simplified to avoid a significant increase in manufacturing cost when the above-mentioned net concentration difference is obtained. As a result, a significant increase in manufacturing cost can be avoided, and high latch-up tolerance and low recovery loss can be achieved.

[0114] Specifically, the donor addition process of the n-type emitter layer 13 and the p-type emitter layer 14 are performed. + The donor addition step of the anode contact layer 24b is referred to as a common donor addition step ( Fig.11 and Fig.12 ) and simultaneously. Thus, the process of adding a donor to the n-type emitter layer 13 and the process of adding a donor to the p-type emitter layer 13 are performed simultaneously. + Compared with the case where the step of adding the donor to the anode contact layer 24b is performed separately, the manufacturing method is simplified, and thus the manufacturing cost can be reduced.

[0115] In addition, p ++ The process of adding acceptors to the base contact layer 14 and performing p + The acceptor addition step of the anode contact layer 24b is referred to as a common acceptor addition step ( Figure 13 to Figure 15 ) and proceed simultaneously. ++ The process of adding acceptors to the base contact layer 14 and performing p + Compared with the case where the acceptor addition step of the anode contact layer 24b is performed separately, the manufacturing method is simplified, and thus the manufacturing cost can be reduced.

[0116] The amount of donor ions implanted per unit area in the common donor adding step is lower than the amount of acceptor ions implanted per unit area in the common acceptor adding step. + Anode contact layer 24b is provided with p-type.

[0117] p + The anode contact layer 24b has a ratio of p ++ The anode contact layer 24a has a low net concentration. ++ Anode contact layer 24a and p + Adjustment of the arrangement of the anode contact layer 24 b can further reduce the recovery loss of the diode region 20 .

[0118] p + The anode contact layer 24b has a ratio of p ++ The anode contact layer 24a has a high donor concentration. + The net concentration of the anode contact layer 24b relative to p ++The difference in the net concentration of the anode contact layer 24a is adjusted.

[0119] The upper surface F1 does not have an n-type in the diode region 20. This can suppress a decrease in RRSOA (Reverse Recovery Safe Operating Area) due to the formation of a parasitic npn transistor.

[0120] The p-type anode layer 25 constitutes a part of the upper surface F1 , thereby reducing the hole injection efficiency and thus reducing the recovery loss of the diode region 20 .

[0121] The net peak concentration of the p-type anode layer 25 is greater than or equal to 1×10 16 / cm 3 . Thus, the reduction of RRSOA can be suppressed.

[0122] p + The net peak concentration of the anode contact layer 24b is greater than or equal to 1×10 18 / cm 3 Thus, the on-voltage of the diode region 20 can be suppressed to be low.

[0123] (Variation Example)

[0124] Fig.16 Yes means Figure 1 FIG. 1 is a top view of a modified example of FIG. 1 . In this modified example, the diode regions 20 are arranged in a plurality in the longitudinal direction and in the transverse direction. The diode regions 20 are surrounded by the IGBT region 10. That is, within the IGBT region 10, the plurality of diode regions 20 are arranged in an island shape. Fig.16 In the figure, the diode regions 20 are arranged in a matrix shape with 4 columns in the horizontal direction of the paper and 2 rows in the vertical direction of the paper. However, the number and arrangement of the diode regions 20 are not limited thereto, and a structure in which one or more diode regions 20 are surrounded by the IGBT region 10 can be applied.

[0125] <Implementation Method 2>

[0126] Fig.17 So with Figure 2 The same view schematically shows a partial top view of the structure of the RC-IGBT 102 (reverse conducting semiconductor device) according to the second embodiment, as viewed along the upper surface (first main surface) of the semiconductor substrate 50. Figure 2 ) is different, p + The anode contact layer 24b is formed by ++ The anode contact layer 24a is arranged to surround the p ++The inside of anode contact layer 24a. Since the other structures are substantially the same as those of the first embodiment, the same or corresponding elements are denoted by the same reference numerals and their description will not be repeated.

[0127] Similar to the first and second embodiments, + The anode contact layer 24b is given a p-type by further adding an acceptor to the region where the donor is added. Therefore, due to the formation fluctuation of the implantation mask for adding impurities, the p-type on the upper surface F1 is + A part of the region of the anode contact layer 24b may be n-type. When the n-type region constitutes a parasitic npn transistor, RRSOA is reduced.

[0128] According to this embodiment 2 ( Fig.17 ), and implementation mode 1 ( Figure 2 ) compared to p + The size of each of the anode contact layers 24b is smaller, and the p + The dimensional fluctuation of anode contact layer 24b also becomes smaller. Therefore, it is possible to suppress the reduction of RRSOA caused by manufacturing fluctuation.

[0129] <Implementation Method 3>

[0130] Fig.18 So with Fig.17 The same view schematically shows a partial top view of the structure of the RC-IGBT 103 (reverse conducting semiconductor device) according to the third embodiment, as viewed along the upper surface (first main surface) of the semiconductor substrate 50. Fig.17 ) is different, and is p ++ The anode contact layer 24a surrounds the p + Anode contact layer 24b is dispersedly arranged in a zigzag pattern. In addition, since the structure other than this is substantially the same as that of the above-mentioned second embodiment, the same or corresponding elements are denoted by the same reference numerals and their description will not be repeated.

[0131] According to this embodiment 3 ( Fig.18 ), and implementation mode 2 ( Fig.17 ), the hole current density in the diode region 20 becomes more uniform. As a result, the heat dissipation of the diode region 20 can be improved.

[0132] <Implementation Method 4>

[0133] Fig.19 So with Figure 2The same view schematically shows a partial top view of the structure of the RC-IGBT 104 (reverse conducting semiconductor device) according to the fourth embodiment, as viewed along the upper surface (first main surface) of the semiconductor substrate 50. Figure 2 ) is different, through p + The anode contact layer 24b is arranged so as to be separated from the p-type anode layer 25. ++ Anode contact layer 24a. Since the other structures are substantially the same as those of the first embodiment, the same or corresponding elements are denoted by the same reference numerals and their description will not be repeated.

[0134] According to this embodiment 4 ( Fig.19 ), and implementation mode 1 ( Figure 2 ), the density of holes injected into the p-type anode layer 25 is lowered. Thus, the recovery loss can be reduced.

[0135] <Implementation method 5>

[0136] Fig. 20 So with Fig.17 The same view schematically shows a partial top view of the structure of the RC-IGBT 105 (reverse conducting semiconductor device) according to the fifth embodiment, as viewed along the upper surface (first main surface) of the semiconductor substrate 50. Fig.17 ) is different, p ++ The anode contact layer 24a is formed by + The anode contact layer 24b is arranged to surround the p + In other words, the p ++ Anode contact layer 24a and p + Configuration of anode contact layer 24b Since the other configurations are substantially the same as those of the second embodiment, the same or corresponding elements are denoted by the same reference numerals and their description will not be repeated.

[0137] According to the present embodiment, the density of holes injected into the p-type anode layer 25 is reduced, thereby reducing the recovery loss.

[0138] <Implementation Method 6>

[0139] Fig.21 So with Figure 2 The same view schematically shows a partial top view of the structure of the RC-IGBT 106 (reverse conducting semiconductor device) according to the sixth embodiment, as viewed along the upper surface (first main surface) of the semiconductor substrate 50. Fig. 20 ) is different, and is p + The anode contact layer 24b surrounds the p ++Anode contact layer 24a is dispersedly arranged in a zigzag shape. In addition, since the structure other than this is substantially the same as that of the above-mentioned Embodiment 5, the same reference numerals are attached to the same or corresponding elements, and the description thereof will not be repeated.

[0140] According to this embodiment 6 ( Fig.21 ), and implementation mode 5 ( Fig. 20 ), the hole current density in the diode region 20 becomes more uniform. As a result, the heat dissipation of the diode region 20 can be improved.

[0141] <Implementation Method 7>

[0142] Fig. 22 So with Figure 2 The same view schematically shows a partial top view of the structure of the RC-IGBT 107 (reverse conducting semiconductor device) according to the seventh embodiment, as viewed along the upper surface (first main surface) of the semiconductor substrate 50. Figure 2 ) is different from that in which only the p-type anode layer 25 is disposed on the upper surface of a part of the mesa regions of the semiconductor substrate 50 divided by the diode trench gate 21, and no p-type anode layer 25 is disposed. ++ Anode contact layer 24a and p + The anode contact layer 24b is only provided with p ++ Anode contact layer 24a and p + The anode contact layer 24b is not provided with the p-type anode layer 25. Since the structure other than this is substantially the same as that of the first embodiment, the same or corresponding elements are denoted by the same reference numerals and their description will not be repeated.

[0143] According to this embodiment, it is possible to reduce p ++ Anode contact layer 24a and p + The influence of the dimensional fluctuation of the anode contact layer 24b in the X direction (a direction parallel to the extending direction of the groove).

[0144] <Implementation Method 8>

[0145] Fig.23 So with Figure 2 The same view schematically shows a partial top view of the structure of the RC-IGBT 108 (reverse conducting semiconductor device) according to the eighth embodiment, as viewed along the upper surface (first main surface) of the semiconductor substrate 50. Figure 2 ) is different, p is omitted ++ Thus, in each of the plurality of mesa regions of the semiconductor substrate 50 divided by the diode trench gate 21, the p+ Anode contact layers 24b and p-type anode layers 25 are arranged alternately and in contact with each other. Since the other structures are substantially the same as those of the first embodiment, the same or corresponding elements are denoted by the same reference numerals and their description will not be repeated.

[0146] According to this embodiment 8 ( Fig.23 ), the density of holes injected into the p-type anode layer 25 is reduced. This can reduce the recovery loss.

[0147] <Implementation Method 9>

[0148] Fig.24 So with Figure 2 The same view schematically shows a partial top view of the structure of the RC-IGBT 109 (reverse conducting semiconductor device) of the ninth embodiment observed along the upper surface (first main surface) of the semiconductor substrate 50. In the ninth embodiment, the same Fig.23 ) is the same, omitting p ++ Anode contact layer 24a (see Figure 2 ). Moreover, in the ninth embodiment, unlike the eighth embodiment, only the p-type anode layer 25 is disposed on the upper surface of a part of the mesa regions of the semiconductor substrate 50 divided by the diode trench gate 21, and no p-type anode layer 25 is disposed. + The anode contact layer 24b is only provided with p + The anode contact layer 24b is not provided with the p-type anode layer 25. Since the structure other than this is substantially the same as that of the first embodiment, the same or corresponding elements are denoted by the same reference numerals and their description will not be repeated.

[0149] According to this embodiment, it is possible to reduce p + The influence of the dimensional fluctuation of the anode contact layer 24b in the X direction (a direction parallel to the extending direction of the groove).

[0150] <Implementation Method 10>

[0151] In the tenth embodiment, the impurity concentration distribution of the semiconductor substrate 50 included in the RC-IGBT 100 described in the first embodiment will be described in more detail.

[0152] Fig.25 It is on the single-point dash line DD( Figure 3 ) is a graph showing an example of the concentration distribution of the semiconductor substrate 50 of the RC-IGBT 100 in the present embodiment 10. In this graph, the concentration Na1 represents the acceptor injection distribution for forming the p-type anode layer 25. The concentration Na1+the concentration Na2 represents the acceptor injection distribution for forming the p-type anode layer 25.+ The acceptor injection distribution of the anode contact layer 24b. The concentration Nd2 represents the acceptor injection distribution for forming p + Donor injection distribution of anode contact layer 24b: Net concentration Nn represents the net concentration obtained from concentration Na1+acceptor concentration Na2 and donor concentration Nd2.

[0153] The peak concentration of the net concentration Nn of the p-type anode layer 25 (region with a depth of about 2 μm or more) is greater than or equal to 1×10 16 / cm 3 . p + The peak concentration of the net concentration Nn of the anode contact layer 24b (region at a depth of less than or equal to about 2 μm) is greater than or equal to 1×10 18 / cm 3 .

[0154] Fig.26 : is a graph showing the relationship between the net peak concentration of the p-type anode layer 25 of the RC-IGBT 100 of the present embodiment 10 and the controllable Vcc measured in the RRSOA test. In addition, Vcc is a DC power supply voltage applied between the collector and the emitter, and the controllable Vcc is the maximum Vcc that does not cause device damage in the RRSOA test. The value of the net peak concentration ( / cm 3 ) is 2.5×10 15 5.0×10 15 , 1.2×10 16 , 2.0×10 16 , 2.5×10 16 , and 5.0×10 16 From this result, it can be seen that by setting the net peak concentration of the p-type anode layer 25 to be greater than or equal to 1.2×10 16 / cm 3 , the decrease in RRSOA can be suppressed. In addition, according to the overall tendency of the plotted graph, it can be considered that by setting the net peak concentration of the p-type anode layer 25 to be approximately greater than or equal to 1×10 16 / cm 3 , which can inhibit the decrease of RRSOA.

[0155] Fig. 27 is a graph showing the p of the RC-IGBT 100 of the tenth embodiment. + A graph showing an example of the measurement results of the relationship between the net peak concentration of the anode contact layer 24b (first anode contact layer) and the on-voltage of the diode formed by the diode region 20. The values ​​of the net peak concentration ( / cm 3 ) is 1.0×10 17 , 3.5×10 185.0×10 18 , 1.0×10 19 , and 2.0×10 19 According to this result, it can be seen that by + The net peak concentration of the anode contact layer 24b is set to be greater than or equal to 3.5×10 18 , which can significantly reduce the diode's on-state voltage. In addition, based on the overall trend of the plotted graph, it can be considered that by reducing p + The net peak concentration of the anode contact layer 24b is set to be approximately greater than or equal to 1×10 18 / cm 3 , which can suppress the on-state voltage of the diode. It is believed that the reduction in the on-state voltage is caused by the emitter electrode 5 and the p + This is caused by a reduction in the contact resistance of the anode contact layer 24b.

[0156] <Implementation Method 11>

[0157] Fig.28 yes Fig.25 The modified example of the embodiment 10 shows the impurity concentration distribution of the semiconductor substrate 50 in the embodiment 11. In the embodiment 11, in the diode region 20, the semiconductor substrate 50 has a p + The depth position between the anode contact layer 24b (the left region in the figure) and the p-type anode layer 25 (the right region in the figure) has a minimum value of the distribution of the net concentration Nn in the thickness direction. As a result, the hole injection efficiency at the diode region 20 is reduced. Therefore, the recovery loss of the diode region 20 can be reduced.

[0158] <Implementation Method 12>

[0159] Fig.29 yes Fig.25 A modification of the tenth embodiment shows the impurity concentration distribution of the semiconductor substrate 50 of the twelfth embodiment. In the twelfth embodiment, p + The anode contact layer 24b (the area on the left side in the figure) has a peak value of the distribution of the net concentration Nn in the thickness direction at a depth position away from the upper surface (zero depth position). As a result, the hole injection efficiency at the diode region 20 is reduced. Therefore, the recovery loss of the diode region 20 can be reduced.

[0160] <Implementation Method 13>

[0161] Fig.30 yes Fig.25 The modified example of the tenth embodiment shows the impurity concentration distribution of the semiconductor substrate 50 of the thirteenth embodiment. In the thirteenth embodiment, the semiconductor substrate 50 has a thickness in the direction of p in the diode region 20. +An n-type intermediate layer 29 is included between the anode contact layer 24b and the p-type anode layer 25. This reduces the hole injection efficiency of the diode region 20. Therefore, the recovery loss of the diode region 20 can be reduced.

[0162] Furthermore, the various embodiments may be freely combined, and the various embodiments may be appropriately modified or omitted. In addition, a certain embodiment may be partially applied to other embodiments.

[0163] Description of the label

[0164] 1n - Drift layer, 2n-type carrier storage layer, 3n-type buffer layer, 4 interlayer insulating film, 5 emitter electrode, 5a electrode layer, 5b barrier metal layer, 7 collector electrode, 10 IGBT region, 11 active trench gate, 11a active gate electrode, 11b gate insulating film, 13n-type emitter layer, 14 base contact layer, 15 p-type base layer, 16 p-type collector layer, 20 diode region, 24 p-type anode contact region, 24a p ++ Anode contact layer (second anode contact layer), 24 bp + Anode contact layer (first anode contact layer), 24bD temporary region, 25 p-type anode layer, 26 n-type cathode layer, 29 intermediate layer, 50 semiconductor substrate, 61, 62 implantation masks, 100 to 109 RC-IGBT (reverse conducting semiconductor device).

Claims

1. A reverse conducting semiconductor device comprising an insulated gate bipolar transistor region and a diode region, In this reverse conducting semiconductor device, A semiconductor substrate is included in the IGBT region and the diode region, and has a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate comprises: a drift layer, which spans the IGBT region and the diode region and is of a first conductivity type; a base layer, which is arranged between the drift layer and the first main surface in the insulated gate bipolar transistor region and has a second conductivity type different from the first conductivity type; an emitter layer, which is arranged between the base layer and the first main surface in the insulated gate bipolar transistor region and has the first conductivity type; a base contact layer, which is arranged between the base layer and the first main surface in the insulated gate bipolar transistor region and constitutes a part of the first main surface, and the base contact layer is of the second conductivity type; a collector layer, which is arranged between the drift layer and the second main surface in the insulated gate bipolar transistor region and has the second conductivity type; an anode layer, which is arranged between the drift layer and the first main surface in the diode region and has the second conductivity type; an anode contact region, which is arranged between the anode layer and the first main surface in the diode region and constitutes a part of the first main surface, and has a second conductivity type impurity concentration peak value higher than that of the anode layer and is of the second conductivity type; as well as a cathode layer, which is arranged between the drift layer and the second main surface in the diode region and has the first conductivity type, The reverse conducting semiconductor device further comprises: an insulating gate structure for forming a channel for controlling an electrical path between the emitter layer and the drift layer through the base layer; a collector electrode electrically connected to the collector layer and the cathode layer; as well as an emitter electrode, which contacts the base contact layer and the anode contact region, The anode contact region includes a first anode contact layer having a lower net concentration than the base contact layer and a higher first conductivity type impurity concentration than the base contact layer, The net concentration is the absolute value of the difference between the donor concentration and the acceptor concentration.

2. The reverse conducting semiconductor device according to claim 1, in, The anode contact region includes a second anode contact layer, and the first anode contact layer has a lower net concentration than that of the second anode contact layer.

3. The reverse conducting semiconductor device according to claim 2, in, The first anode contact layer has a higher first conductivity type impurity concentration than the second anode contact layer.

4. The reverse conducting semiconductor device according to any one of claims 1 to 3, in, The first main surface does not have the first conductivity type in the diode region.

5. The reverse conducting semiconductor device according to any one of claims 1 to 3, in, The anode layer constitutes a part of the first main surface.

6. The reverse conducting semiconductor device according to any one of claims 1 to 3, in, The peak value of the net concentration of the anode layer, i.e., the net peak concentration, is greater than or equal to 1×10 16 / cm 3 .

7. The reverse conducting semiconductor device according to any one of claims 1 to 3, in, The peak value of the net concentration of the first anode contact layer, i.e., the net peak concentration, is greater than or equal to 1×10 18 / cm 3 .

8. The reverse conducting semiconductor device according to any one of claims 1 to 3, in, In the diode region, the semiconductor substrate has a minimum value of a net concentration distribution in a thickness direction at a depth position between the first anode contact layer and the anode layer.

9. The reverse conducting semiconductor device according to any one of claims 1 to 3, in, The first anode contact layer has a peak value of a net concentration distribution in a thickness direction at a depth position away from the first main surface.

10. The reverse conducting semiconductor device according to any one of claims 1 to 3, in, The semiconductor substrate includes an intermediate layer having a first conductivity type between the first anode contact layer and the anode layer in a thickness direction of the diode region.

11. A method for manufacturing a reverse conducting semiconductor device, the method being used to manufacture the reverse conducting semiconductor device according to any one of claims 1 to 10, The method for manufacturing the reverse conducting semiconductor device comprises the following steps: adding a first conductivity type impurity to the emitter layer by ion implantation onto the first main surface of the semiconductor substrate; and adding a first conductivity type impurity to the first anode contact layer by ion implantation onto the first main surface of the semiconductor substrate, The step of adding the first conductivity type impurity to the emitter layer and the step of adding the first conductivity type impurity to the first anode contact layer are simultaneously performed as a common first conductivity type impurity adding step.

12. The method for manufacturing a reverse conducting semiconductor device according to claim 11, in, It also has the following processes: adding a second conductivity type impurity to the base contact layer by ion implantation onto the first main surface of the semiconductor substrate; and adding a second conductivity type impurity to the first anode contact layer by ion implantation onto the first main surface of the semiconductor substrate, The step of adding the second conductivity type impurity to the base contact layer and the step of adding the second conductivity type impurity to the first anode contact layer are simultaneously performed as a common second conductivity type impurity adding step.

13. The method for manufacturing a reverse conducting semiconductor device according to claim 12, in, An implantation amount of the first conductive type impurity ions per unit area in the common first conductive type impurity adding step is lower than an implantation amount of the second conductive type impurity ions per unit area in the common second conductive type impurity adding step.

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