Synchronous rectifier driver circuit, integrated circuit, resonant converter and method

Abstract

The synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. The second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and the third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure a voltage between the second terminal and the first terminal and detect a turn-on time when the measured voltage reaches a first threshold and a turn-off time when the measured voltage reaches a second threshold. Based on the measured voltage, the synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal.

Description

Technical Field

[0001] Embodiments of the present description relate to a synchronous rectifier driver circuit for two synchronous rectifier switches, such as the synchronous rectifier switches of a switched-mode resonant converter. Background Art

[0002] Resonant converters are a broad category of switching converters characterized by the presence of a resonant circuit, which plays an active role in determining the input-output power flow. Considering the most common implementation, in these converters, a full-bridge (or half-bridge) consisting of four (or two) power switches (usually power field-effect transistors (FETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs)), supplied by a DC voltage, generates a voltage square wave that is applied to a resonant circuit tuned to a frequency close to the fundamental frequency of the square wave. Thus, due to its selective characteristics, the resonant circuit responds primarily to the fundamental frequency component, while ignoring the higher harmonics of the square wave.

[0003] Thus, the circulating power can be modulated by varying the frequency of the square wave while keeping the duty cycle fixed at 50%.Furthermore, depending on the resonant circuit configuration, the current and / or voltage associated with the power flow has a sinusoidal or segmented sinusoidal shape.

[0004] These voltages are rectified and filtered to provide DC power to the load. In offline applications, to comply with safety regulations, the rectification and filtering systems that power the load are usually coupled to the resonant circuit via a transformer. The transformer provides the isolation between the source and the load, which is required by the regulations. As with all isolated network converters, in this case, a distinction is made between the primary side (associated with the primary winding of the transformer), which is connected to the input source, and the secondary side (associated with the secondary winding of the transformer), which supplies power to the load via the rectification and filtering system.

[0005] Among the many types of resonant converters currently in use is the so-called LLC resonant converter, particularly in its half-bridge form. The LLC name comes from the resonant circuit that uses two inductors (L) and a capacitor (C). Summary of the Invention

[0006] In summary, various embodiments of the present disclosure provide a novel driver circuit for two synchronous rectifier switches, especially for the turn-off condition of the synchronous rectifier switches.

[0007] According to one or more embodiments, one or more of the above technical advantages are achieved by a synchronous rectifier driver circuit having unique elements as described herein. Embodiments also relate to related integrated circuits, electronic resonant converters, and methods.

[0008] The claims form an integral part of the technical teaching of the description provided herein.

[0009] As previously described, various embodiments of the present disclosure relate to a synchronous rectifier driver circuit configured to drive a synchronous rectifier FET including drain, source, and gate terminals. In various embodiments, the synchronous rectifier driver circuit (e.g., in the form of an integrated circuit) includes a first terminal configured to be connected to the source terminal of the synchronous rectifier FET, a second terminal configured to be connected to the drain terminal of the synchronous rectifier FET, and a third terminal configured to be connected to the gate terminal of the synchronous rectifier FET.

[0010] In various embodiments, the synchronous rectifier driver circuit is configured to measure a voltage between the second terminal and the first terminal and detect a turn-on time when the measured voltage reaches a first threshold and a turn-off time when the measured voltage reaches a second threshold.

[0011] In various embodiments, the synchronous rectifier driver circuit is configured to generate a drive signal between the third terminal and the first terminal based on the measured voltage by:

[0012] - between the other instant and the switch-off instant, varying the drive signal according to the instantaneous value of the measured voltage; and

[0013] Between the switch-off instant and the next switch-on instant, the drive signal is set to a second value.

[0014] In various embodiments, the synchronous rectifier driver circuit may be further configured to change the drive signal based on the instantaneous value of the measured voltage between the turn-on moment and another moment. Alternatively, the synchronous rectifier driver circuit may be configured to set the drive signal to a second value between the turn-on moment and another moment. For example, the another moment may be determined by:

[0015] - determining the moment when the measured voltage reaches its peak between the turn-on moment and the turn-off moment;

[0016] - Wait a given time relative to the moment of switch-on; or

[0017] - Determine the moment when the measured voltage reaches a given threshold.

[0018] For example, in various embodiments, by determining the duration between a previous turn-on instant and a corresponding previous turn-off instant, and estimating another instant at half the duration, the instant at which the measured voltage peaks may be determined.

[0019] According to a first aspect, the synchronous rectifier driver circuit can be configured to change the drive signal between another moment and a turn-off moment by setting the drive signal to a voltage corresponding to the sum of a constant voltage and a voltage proportional to a given proportionality constant of the instantaneous value of the measured voltage.

[0020] In various embodiments, the synchronous rectifier driver circuit includes a sample-and-hold circuit configured to store a peak value. In this case, the synchronous rectifier driver circuit can be configured to determine a second value based on the stored peak value. For example, the second value can correspond to the sum of a constant voltage and a voltage proportional to a given proportionality constant of the stored peak value.

[0021] For example, in various embodiments, the synchronous rectifier driver may include a fourth terminal and a variable current generator configured to generate a variable current applied to the fourth terminal, wherein the variable current is proportional to a voltage received at an input of the variable current generator. Thus, the control circuit may be configured to set the input of the variable current generator to:

[0022] - between the moment of conduction and another moment, connected to the stored peak value,

[0023] - between another instant and the instant of switch-off, connected to the voltage being measured, or

[0024] Between the switch-off moment and the next switch-on moment, connected to the first terminal.

[0025] As will be explained in more detail below, in various embodiments, the voltage at the fourth terminal may be used to directly generate a drive signal for a gate terminal of a synchronous rectifier driver, eg, via a voltage follower.

[0026] However, in various embodiments, the synchronous rectifier driver circuit may further include a fifth terminal, a constant current generator configured to generate a constant current applied to the fifth terminal, and a summing circuit configured to generate a drive signal by summing the voltage at the fourth terminal and the voltage at the fifth terminal.

[0027] According to a second aspect, the synchronous rectifier driver circuit can be configured to change the drive signal between another moment and the turn-off moment to directly adjust the measured voltage to a given (constant) reference value. For example, for this purpose, the synchronous rectifier driver circuit may include a regulator circuit that is configured to receive the measured voltage and a given reference value and generate a regulation signal. Specifically, in various embodiments, the regulator circuit includes or implements at least one integral component. Therefore, in this case, the drive signal can be determined according to (or can correspond to) the regulation signal (at least) between another moment and the turn-off moment.

[0028] Various embodiments also relate to an electronic resonant converter, including:

[0029] - two input terminals for receiving an input voltage and two output terminals for providing an output voltage or an output current;

[0030] - a transformer comprising a primary winding and first and second secondary windings;

[0031] - a switching stage connected to the primary winding via a resonant tank;

[0032] - a first synchronous rectifier FET connected in series with the first secondary winding between the two output terminals;

[0033] - a second synchronous rectifier FET connected in series with the second secondary winding between the two output terminals; and

[0034] - Two synchronous rectifier driver circuits as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting examples and in which:

[0036] The characteristics and advantages of the present disclosure will become apparent from the following detailed description of practical embodiments thereof, which are illustrated by way of non-limiting example in the accompanying drawings, in which:

[0037] - Figure 1 shows a circuit schematic diagram of an LLC resonant converter according to a comparative example;

[0038] - Figure 2 Shown Figure 1 Block diagram of the control circuit of the resonant converter;

[0039] - Figure 3 A circuit diagram of an LLC resonant converter is shown, wherein the resonant converter includes a synchronous rectifier, and the synchronous rectifier includes two synchronous rectifier switches and a synchronous rectifier driver circuit;

[0040] - Figure 4 and Figure 5 Shown Figure 3 Typical operating waveforms of the synchronous rectifier driver circuit;

[0041] - Figure 6 Shows the control Figure 3 Detailed view of the synchronous rectifier switching signals;

[0042] - Figure 7 、 Figure 8 、 Figure 9 and Figure 10 Shown by Figure 6 The expected effects of stray inductance introduced into the circuit;

[0043] -Figure 11, Figure 12 、 Figure 13 、 Figure 14 and Figure 15 Various embodiments of a synchronous rectifier capable of compensating for an expected effect according to the first aspect of the present disclosure are shown; and

[0044] - Figure 16 and Figure 17 Various embodiments of a synchronous rectifier capable of compensating for the expected effect according to the second aspect of the present disclosure are shown. DETAILED DESCRIPTION

[0045] In the following description, various specific details are illustrated to provide a deeper understanding of the embodiments. The embodiments may be provided without one or more of the specific details or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0046] References to "an embodiment" or "one embodiment" throughout this specification are intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," and the like that may appear at various points in this specification are not necessarily referring to the same embodiment. Furthermore, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0047] The reference signs used herein are for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0048] Figure 1 An example of an LLC resonant converter 20 is shown. Typically, the electronic converter 20 comprises:

[0049] - a positive input terminal 200a and a negative input terminal 200b for receiving a DC input voltage Vin; and

[0050] A positive output terminal 202a and a negative output terminal 202b for providing a regulated (DC) output voltage Vout or an output current Iout.

[0051] For example, the input voltage Vin can be provided by a DC voltage generator 10 (such as a battery). However, the input voltage Vin can also be obtained from an AC voltage, for example, by means of a rectifier circuit (such as a bridge rectifier) and an optional filter circuit (such as a capacitor). Conversely, the regulated output voltage Vout or output current Iout can be used to power the load 30.

[0052] In the example considered, the electronic converter 20 comprises a half-bridge comprising two electronic switches SW1 and SW2, such as FETs, such as n-channel FETs, for example NMOS, which are connected in series (e.g., directly) between input terminals 200a and 200b, wherein the negative input terminal 200b generally represents the first ground GND1. For example, in the example considered, the drain terminal of the transistor SW1 is directly connected to the terminal 200a, the source terminal of the transistor SW1 is directly connected to the drain terminal of the transistor SW2, and the source terminal of the transistor SW2 is directly connected to the terminal 200b.

[0053] Hence, the half-bridge SW1 , SW2 is powered via the input voltage Vin and the intermediate node between the electronic switches SW1 and SW2 (eg the drain terminal of the transistor SW1 ) represents the switching node HB.

[0054] In the example considered, the switching node HB between the electronic switches SW1 and SW2 is connected to a (resonant) circuit block.

[0055] In particular, in the example considered, the circuit comprises a transformer T comprising a primary winding T1 and a center-tapped secondary winding comprising a first secondary winding T2a and a second secondary winding T2b connected in series.

[0056] In the example considered, the primary winding T1 of the transformer T is connected (e.g., directly) to the capacitor Cr and the first inductor Ls between the switching node HB and the negative terminal 200b. In addition, the second inductor Lp is connected (e.g., directly) in parallel with the primary winding T1. Thus, in the example considering the capacitor Cr, the first inductor Ls and the second inductor Lp are connected in series (hence the name LLC converter), and the inductor Lp is connected in parallel to the primary winding T1. For example, in Figure 1 , a first terminal of capacitor Cr is (e.g., directly) connected to switching node HB, a second terminal of capacitor Cr is (e.g., directly) connected to a first terminal of primary winding T1 via inductor Ls, and a second terminal of primary winding T1 is (e.g., directly) connected to terminal 200b.

[0057] In a real transformer T, the two windings T1 and T2 are not perfectly coupled anyway, and the transformer T also includes leakage inductance and magnetizing inductance. Basically, such leakage inductance can be modeled via an inductor connected in series with the primary winding T1. Conversely, the magnetizing inductance of the transformer T (used to model the magnetic flux) can be modeled using an inductor connected in parallel with the primary winding T1. Therefore, the inductance Ls can lie in the leakage inductance of the transformer T, can be implemented using an inductor connected in series with the primary winding T1, or can be generated by both the leakage inductance of the transformer T and such an inductor. Similarly, the inductance Lp can lie in the magnetizing inductance of the transformer T, can be implemented using an inductor connected in parallel with the primary winding T1, or can be generated by both the magnetizing inductance of the transformer T and such an inductor. Therefore, in general, the inductors Lp and Ls and the transformer T can be integrated in a single component.

[0058] As mentioned earlier, in Figure 1 In the example, a center tap arrangement is used on the secondary side, i.e., the secondary winding includes first, second, and center tap terminals. Specifically, in the example considered, the center tap terminal is connected (e.g., directly) to one of the output terminals 202a / 202b, and the first and second terminals of the secondary winding T2 are connected (e.g., directly) to the other output terminal 202a / 202b via respective diodes D2 and D1. For example, in the example considered, the center tap terminal is connected (e.g., directly) to the output terminal 202b, and the first and second terminals of the secondary winding T2 are connected (e.g., directly) to the anodes of respective diodes D1 and D2, and the cathodes of diodes D1 and D2 are connected (e.g., directly) to terminal 202a. Therefore, due to the rectifying function of diodes D1 and D2, terminal 202a corresponds to the positive output terminal, and terminal 202b corresponds to the negative output terminal, which typically corresponds to the second ground GND2. However, by reversing the orientation of diodes D1 and D2, terminal 202b would correspond to the positive output terminal.

[0059] Typically, the electronic converter 20 may also include an output filter connected between the rectifier and the output terminals 202a and 202b. Figure 1 , capacitor Cout is connected (eg, directly) between output terminals 202a and 202b.

[0060] In the considered example, the control terminals of the electronic switches SW1 and SW2 (eg gate terminals of respective FETs) are driven via a driver circuit 210 which is configured to generate respective drive signals HSGD and LSGD for the electronic switches SW1 and SW2 .

[0061] As previously mentioned, driver circuit 210 typically drives switches SW1 and SW2 to apply a square wave with a frequency close to the resonant circuit frequency to switching node HB. In this way, the resonant tank (Lp, Ls, and Cr) acts as a tuned filter, and the current is formed by a single harmonic of the fundamental frequency developed by the Fourier series and is therefore effectively sinusoidal.

[0062] More specifically, the driver circuit 210 is generally configured to generate the drive signals HSGD and LSGD to repeat the following four phases for each switching cycle:

[0063] During a first time interval, the first electronic switch SW1 is closed and the second electronic switch SW2 is open, whereby the switching node HB is connected to the positive input node 200 a , ie the input voltage Vin;

[0064] - during a second time interval, opening the first and second electronic switches SW1 / SW2;

[0065] - during a third time interval, opening the first electronic switch SW1 and closing the second electronic switch SW2, whereby the switching node HB is connected to the negative input node 200a, eg to the ground GND1; and

[0066] - During a fourth time interval, the first and second electronic switches SW1 / SW2 are opened.

[0067] The second and fourth time intervals may be useful in order to implement soft switching using the resonance of the resonant circuit. Figure 1 The LLC topology shown in allows ZVS (zero voltage switching) of the primary side switches SW1 and SW2 and ZCS (zero current switching) of the secondary side diodes D1 and D2, thus allowing operation of the converter at high switching frequencies with high efficiency.

[0068] Thus, in the example considered, the electronic converter provides a voltage Vout and a current Iout via output terminals 202a and 202b. Typically, a closed loop (typically implemented using a negative feedback control system) thus maintains the converter's output voltage Vout or output current Iout constant when operating conditions change (e.g., changes in the input voltage Vin and / or the output load 30). As previously described, regulation of the converter's output voltage Vout or output current Iout is achieved by varying the switching frequency of the square wave at the input of the switching node HB / resonant tank.

[0069] For example, Figure 2 An example of a control circuit for a general half-bridge resonant converter 20 is shown.

[0070] As previously described, the half-bridge resonant converter 20 includes a half-bridge including two electronic switches connected in series between input terminals 200a and 200b of the electronic converter 20. Furthermore, the converter 20 includes a circuit 204 including a resonant tank (e.g., capacitor Cr, inductors Ls and Lp, and transformer T), a rectifier circuit (e.g., diodes Da and Db), and an optional filter circuit (e.g., capacitor Cout). Specifically, the circuit 204 is connected on one side to the switching node HB (between electronic switches SW1 and SW2) and the negative input terminal 200b (or alternatively, the positive input terminal 200a) to receive a substantially square wave signal, and on the other side to the output terminals 202a and 202b to provide an output voltage Vout or an output current Iout.

[0071] To implement closed-loop control, the converter 20 includes a sensor 212 configured to monitor the output voltage Vout (for a voltage source) or the output current Iout (for a current source). Figure 2 In the embodiment, the converter 20 is configured to provide a regulated voltage. Therefore, the sensor 212 may be a voltage sensor configured to monitor the output voltage Vout. For example, in Figure 2 In , a voltage divider comprising two resistors R1 and R2 is used, which are connected between terminals 202a and 202b, whereby the voltage sensor provides a measurement signal proportional to the output voltage Vout.

[0072] The measurement signal provided by the sensor 212 (indicative of the current Iout or the voltage Vout) is provided to an error amplifier, which is configured to generate an error signal Er. For example, the error amplifier may compare the measurement signal with a reference signal, such as a reference voltage Vref, and generate an error signal Er indicative of the difference between the measurement signal and the reference voltage Vref.

[0073] In the example considered, the error signal Er is then provided to the driver circuit 210 to modify a given controlled variable x, wherein the energy transferred during each switching cycle is substantially dependent on the controlled variable x (e.g., the switching frequency of the switches SW1 and SW2). Typically, the error signal Er can be provided to the driver circuit 210 directly or indirectly, for example, via an optocoupler 218 (which is typically used in the case of isolated electronic converters). Furthermore, the error signal Er provided to the driver circuit 210 or a signal indicative of (e.g., proportional to) the error signal Er (e.g., in the case where an optocoupler 218 is also used) can be any suitable control signal, such as a voltage Vc or a current Ic.

[0074] Typically, the error amplifier is implemented using an operational amplifier 214 that receives a measurement signal (e.g., at an inverting / negative input) and a reference signal (e.g., at a non-inverting / positive input) at its inputs. Furthermore, the operational amplifier 214 has an associated feedback network 216 connected between the output of the operational amplifier and one of its input terminals (typically the inverting input terminal). For example, the feedback network 216 may include components for implementing the error amplifier as a regulator having a proportional (P) component (e.g., via a resistor) and / or an integral (I) component (e.g., via a capacitor). Thus, typically, the feedback network 216 implements a filter for the error amplifier. For example, such a filter 216 may be used to select an appropriate frequency response for the error amplifier, e.g., to ensure that:

[0075] - a stable control loop (i.e., when the operating conditions of the converter are disturbed, the output parameter Vout / Iout tends to return to a constant steady state once the transient caused by the disturbance subsides);

[0076] - good regulation (ie the new constant value recovered by the output parameter Vout / Iout after a disturbance is very close to the value before the disturbance); and

[0077] - Good dynamic performance (ie, during the transient period following a disturbance, the output parameter Vout / Iout does not deviate too much from the desired value and the transient itself is short).

[0078] like Figure 3 As shown, in order to improve the efficiency of the resonant converter, the diodes D1 and D2 on the secondary side ( Figure 1 ) are often replaced with synchronous rectification (SR) electronic switches SR1 and SR2, which are controlled by synchronous rectifier driver 222 to emulate ideal diodes.

[0079] To simplify driving of the synchronous rectifier switches SR1 and SR2 , one of the terminals of each synchronous rectifier switch SR1 and SR2 is typically connected to ground (eg, GND2 of the isolated converter).

[0080] For example, in Figure 3 In , the synchronous rectifier electronic switch is implemented using an n-channel FET (such as a MOSFET).

[0081] Therefore, in Figure 3 The remaining connections on the secondary side also change, namely:

[0082] - the center tap terminal of the transformer T is (eg directly) connected to the (positive) output terminal (202a);

[0083] a first terminal of the secondary winding T2 (terminal T2a of the winding) is connected (e.g. directly) to a first (drain) terminal of a synchronous rectifier FETSR2, and a second (source) terminal of the synchronous rectifier switch SR2 is connected (e.g. directly) to a (negative) terminal 202b, which represents ground GND2; and

[0084] - The second terminal of the secondary winding T2 (terminal T2b of the winding) is (e.g. directly) connected to the first (drain) terminal of the synchronous rectifier FETSR1, and the second (source) terminal of the synchronous rectifier switch SR1 is (e.g. directly) connected to the (negative) terminal 202b.

[0085] Likewise, capacitor Cout may be connected (eg, directly) between output terminals 202a and 202b.

[0086] Figure 3 It is also shown that the capacitor Cr may be connected not between the primary winding T1 and the switching node HB, but between the primary winding T1 and the terminal 200b (eg, ground GND1).

[0087] The core function of the synchronous rectifier driver 222 is to turn on each synchronous rectifier switch SR1 and SR2 whenever the corresponding transformer half-winding T2a or T2b starts conducting.

[0088] Specifically, when FETs are used, each of the synchronous rectifier switches SR1 and SR2 also has a body diode associated therewith. Typically, each synchronous rectifier switch SR1 and SR2 may therefore have an associated (particularly parallel-connected) diode. Therefore, in this case, the synchronous rectifier driver 222 should turn on a given synchronous rectifier switch SR1 and SR2 when the corresponding diode begins to conduct, and turn off the synchronous rectifier switch when the flowing current approaches zero.

[0089] To achieve high efficiency, the rectifier driver 222 may also control the channel conduction time to minimize the diode conduction time.

[0090] Several techniques have been proposed to control the synchronous rectifier switches SR1 and SR2 of a (e.g., LLC) resonant converter. The solutions can be grouped into two types: voltage-driven control and current-driven control. The latter group uses the current I flowing through the synchronous rectifier switches SR1 and SR2 to determine the current. SR1 and I SR2 . Usually, the current I SR1 and I SR2It can be measured directly via one or more current sensors connected in series with the synchronous rectifier switches SR1 and SR2, or it can be estimated by measuring the current flowing through the primary side via a current transformer. Both of these methods achieve high accuracy at the expense of additional components and require a large current transformer that affects efficiency.

[0091] The voltage driven solution is based on measuring the voltages DVS1 and DVS2 between the terminals of the current paths of the synchronous rectifier switches SR1 and SR2 (eg, between the drain and source terminals of the respective FETs).

[0092] For example, Figure 4 Possible waveforms for the following are shown: The current I flowing through the synchronous rectifier switches SR1 and SR2 SR1 and I SR2 , and voltages DVS1 and DVS2 at the synchronous rectifier switches SR1 and SR2 , and drive signals GD1 and GD2 of the synchronous rectifier switches SR1 and SR2 .

[0093] also, Figure 5 The current I flowing through one of the synchronous rectifier switches SR1 and SR2 is shown. SR1 and I SR2 and a detailed view of the corresponding voltage DVS and the drive signal GD.

[0094] The waveforms show that the secondary winding T2 provides a substantially sinusoidal wave, wherein during the first half cycle, the synchronous rectifier switch SR1 should be closed (SR2 open), and during the second half cycle, the synchronous rectifier switch SR2 should be closed (SR1 open).

[0095] Therefore, each half cycle can be divided into three regions (a), (b) and (c).

[0096] During the first region (a), i.e., before the synchronous rectifier switch is turned on (i.e., the corresponding signal GD is low), the voltage DVS drops, becomes negative, and the corresponding diode starts conducting at a given threshold VTH_ON (higher or lower than -0.7 V, corresponding to the forward voltage of the diode).

[0097] Once the synchronous rectifier switch SR is turned on at time t1, the following region (b) begins. During this region (b), the voltage DVS drops to:

[0098] DVS=R DSON I SR , (1)

[0099] where R DSONCorresponds to the on-resistance of the synchronous rectifier switch SR. Therefore, the voltage DVS has a sinusoidal characteristic during this region (and considering the current I RS and the direction of the voltage DVS, and the current I RS relatively).

[0100] Therefore, during region (b), the voltage drops and then rises again. RS When the voltage DVS reaches a given second threshold V TH_OFF When , the synchronous rectifier switch SR can be turned off.

[0101] Once the synchronous rectifier switch SR is turned off (and assuming the winding is still conducting), the voltage DVS drops again to the forward voltage of the diode (approximately -0.7 V). The voltage DVS then increases until the voltage at the transformer winding T2 reverses.

[0102] Therefore, the power loss during phases (a) and (c) is much higher than during phase (b) due to the higher voltage drop caused by the forward bias of the diode conduction (700mV) compared to the resistor voltage drop (typically in the range of 10-20mV).

[0103] Figure 6 The LLC converter schematic is shown again, where the voltage V at the primary winding t1 is P and the secondary winding t 2a and t 2b The voltage V Sa and V Sb is shown.

[0104] Typically, due to the coupling of the transformer, the voltage corresponds to V Sa and V Sb , that is, V Sa =V Sb =V S Specifically, assuming the primary winding has N P windings, the secondary winding has N S windings, the voltage V in each switching cycle S Can be determined as follows:

[0105]

[0106] Additionally, due to the connection, the following relationships apply:

[0107] -V Sa +DVS2=V Sb +DVS1. (3)

[0108] Therefore, under steady-state conditions, that is, when the capacitor C OUTis charged to the requested output voltage V OUT When the maximum values of voltages DVS1 and DVS2 are alternately:

[0109] During the first switching half-cycle, the voltage drop DVS1 is negligible and the voltage DVS2 corresponds to 2·V out ;as well as

[0110] During the second switching half-cycle, the voltage drop DVS2 is negligible and the voltage DVS1 corresponds to 2·V out .

[0111] Therefore, this maximum value must be considered to select the correct electronic switches for the synchronous rectifier switches SR1 and SR2.

[0112] Furthermore, in practice, spikes often occur during the switching activity of electronic converters. For example, such spikes are often generated by current reversal in the previous cycle and when the LLC converter operates above resonance. These spikes can mean, for example, that higher voltage class SR MOSFETs must be used, resulting in lower performance and higher cost.

[0113] In this respect, example solutions aim to limit voltage spikes by avoiding (or at least reducing) current reversals, which is however not always possible.

[0114] Described below Figures 7 to 17 In, referenced Figures 1 to 6 The parts, elements or components described are denoted by the same reference numerals used previously in these figures. The description of these elements has been made and will not be repeated below to avoid burdening this detailed description.

[0115] As described above, various embodiments of the present specification relate to solutions for determining a turn-off instant to turn off a synchronous rectifier switch.

[0116] As described with respect to equation (1), during each region / time interval (b), the respective voltages DVS1 and DVS2 measured by the synchronous rectifier controller 222 and the on-resistance R of the respective synchronous rectifier switches SR1 / SR2 are DSON Proportional.

[0117] However, the inventors have observed and also Figure 7 As shown, in fact, the electronic circuit also includes parasitic inductance, which can be realized by an inductor L connected in series with the synchronous rectifier switch SR1 / SR2 (the current path). SR To model, where the inductor L SR can be calculated as:

[0118] L RS =L DS +LTRACE (4)

[0119] Among them, L DS represents the inductance of the synchronous rectifier switches SR1 / SR2 between the terminals (of the current path), for example, between the drain and source terminals of the respective FETs, and L TRACE represents the added inductance of the printed circuit board traces connecting the synchronous rectifier switches SR1 / SR2 to the synchronous rectifier controller 222 .

[0120] Thus, the synchronous rectifier controller 222 does monitor a voltage DVS′ that does not exactly correspond to the voltage DVS at the terminals of the synchronous rectifier switches SR1 / SR2 , but:

[0121]

[0122] The inventors have observed and also Figure 8 As shown, the synchronous rectifier controller 222 determines with respect to the beginning of region (b) (ie, with respect to the rising edge of the signal GD): when the voltage DUS does reach the turn-off threshold V TH_OFF When the measured voltage DUS' reaches the turn-off threshold V after the time ΔT', rather than after the expected time ΔT TH_OFF (See also Figure 5 ), where ΔT = ΔT′ + T LSRAY , that is, the zero crossing of the voltage DUS′ occurs before the zero crossing of the voltage DVS, and the inductor L SR The anticipation effect is introduced within the above range.

[0123] In a first approximation, we can assume that this expected effect is constant, that is, we can assume that T LSRAY However, as will be described in more detail below, this approximation may not be accurate enough.

[0124] Possible approximations of this expected effect are discussed below.

[0125] Specifically, it will be assumed below that the current I S =I RS1 +I RS2 During (at least the last part of) the switching period, i.e. at least at the end of region / interval (b), has a substantially sinusoidal shape, i.e.:

[0126] I SR (t) = I PK ·sin(ω SW t), (6)

[0127] Among them I PKFor example, as mentioned above, this is often the case for a (eg LLC) resonant converter, in particular when operating near the fundamental resonant frequency of the resonant tank of the converter.

[0128] In this case, the measured voltage DVS′ can be written (at least at the end of region (b)):

[0129] DVS′=R DSON I PK ·sin(ω SW ·t)+L RS ·ω SW I PK ·cos(ω SW ·t). (7)

[0130] The inventors have observed that this expression can be rewritten by splitting the time component and the phase shift component as:

[0131]

[0132] The time T LRS Indicates L RS expected:

[0133]

[0134] Equation (8) can be further reformulated as:

[0135]

[0136] Finally, by comparing Equation (7) and Equation (10), we can observe that:

[0137]

[0138] This allows to obtain the expression for the phase shift:

[0139]

[0140] Therefore, equation (9) can be restated as follows:

[0141]

[0142] Assume L RS / R DSON Usually significantly less than 1 / ω SR And assume that the expected time T LRS is a constant, equation (12) can be approximated as:

[0143]

[0144] Figure 9 For the exemplary case L SR =4nH and R DSON =4mΩ, expected time T LRS and the switching frequency f SW Specifically, line 100 shows the behavior of the approximation of equation (13), while line 102 shows the behavior of equation (12), thus also taking into account the switching frequency f SW , where ω SR =2πf SW .

[0145] Thus, in general, for each frequency, there is an error ΔT between the actual value (line 102) and the approximate value (line 100). LSR .

[0146] Figure 10 In this respect it is shown that for different values of T' LSR =L RS / R DSON The error ΔT LSR For example, lines 104, 106, 108, and 110 respectively show T' LSR =Behavior at 250ns, 1μs, 2μs, and 4μs.

[0147] Figure 10 Also emphasized on duty T' LSR When increases, simple approximations may lead to very high errors.

[0148] For example, after a transient from a high load current to a low load current, the primary loop of the LLC converter (see e.g. Figure 2 ) may increase the frequency to compensate for the output voltage V out This frequency variation may result in a change in the switching frequency of the order of 10%-15%, leading to a value of ΔT LSR Changes have occurred.

[0149] The inventors have observed that this variable expected effect should be taken into account when driving the synchronous rectifier switches SR1 and SR2.

[0150] An embodiment of a novel driving method implemented in a synchronous rectifier controller / driver circuit 222a, which is configured to drive two synchronous rectifier switches SR1 and SR2, such as with respect to FIG. Figures 1 to 6 The synchronous rectifier switches SR1 and SR2 of the (eg, LLC) resonant converter are described.

[0151] Specifically, in various embodiments, the synchronous rectifier driver circuit 222a is configured to provide a current i supplied to the load 30 by also taking into account the load current of the electronic (eg, LLC) converter. out (See Figure 1 ) to drive the synchronous rectifier switches SR1 and SR2.

[0152] In general, other solutions exist that take load current into account. For example, reference can be made to US 2017 / 0085188 A1, which discloses a driver circuit for two synchronous rectifier switches SR1 and SR2. Essentially, this document describes a gate drive strategy for two synchronous rectifier MOSFETs that optimizes conversion efficiency under all load conditions, with a constant voltage applied across all conduction windows.

[0153] In contrast, various embodiments of the present disclosure propose a new gate driving strategy, hereinafter identified as “DVS Shaping Gate Driving” (abbreviated as DVS SGD), which attempts to reduce current reversal as much as possible.

[0154] Specifically, in various embodiments, the synchronous rectifier driver circuit 222a is configured to change the drive voltage of the synchronous rectifier switches SR1 and SR2, such as the gate voltage of the corresponding (e.g., n-channel) FET, based on the instantaneous value of the voltage DVS rather than the average value of the voltage DVS as described in document US2017 / 0085188 A1.

[0155] Specifically, by changing the amplitude of the drive signal GD (ie, GD1 or GD2), the synchronous rectifier driver circuit 222a is able to change the on-resistance R of the corresponding synchronous rectifier FET SR1 or SR2. DSON Specifically, as shown in equations (12) and (13), when the on-resistance R DSON When it increases, the expected time T LRS reduce.

[0156] Therefore, in various embodiments, the synchronous rectifier driver circuit 222a is configured to change the drive signal GD when a given synchronous rectifier FET SR1 or SR2 is turned on so that the on-resistance R of the corresponding synchronous rectifier FET SR1 or SR2 is DSON At the end of the on-pulse, i.e. at the end of the interval / region (b) (see also Figure 5 )Increase.

[0157] Specifically, if Figure 11AAs shown, in various embodiments, the synchronous rectifier driver circuit 222a can be configured to directly change the drive signal GD according to the voltage DVS (or more accurately, the measured voltage DVS′):

[0158] GD=V x +K·|DVS′|. (14)

[0159] The above equation can be restated according to equation (5):

[0160]

[0161] The inventors have observed that when the current I SR When approaching zero, the resistance R DSON should be changed to obtain a trend towards the (constant offset) value V x voltage GD.

[0162] When the current I SR When the inductance L is close to zero, SR The effect of this helps to reduce the voltage GD, thereby increasing the resistance R DSON This allows to avoid (or at least reduce) the current reversal at the expense of a small reduction in conversion efficiency.

[0163] In order to provide a non-dependant L SR The design index of the value, which will be assumed to be zero in the following text, is:

[0164] GD=V x +K·R DSON I SR (16)

[0165] This assumption is not without generality, but actually helps to improve immunity to parasitic effects, resulting in the expected switching of the synchronous rectifier FET. In fact, the inductor L SR only results in a lower GD value than that shown in equation (16), so that for a given current I SR , increases the actual on-resistance R DSON and voltage |DVS|.

[0166] Figure 11A An embodiment of the operation of the synchronous rectifier driver circuit 222a for each of the synchronous rectifier FETs SR1 or SR2 is shown.

[0167] Typically, the voltage DVS at a given synchronous rectifier FET SR1 or SR2 will go negative at time t0 due to the switching activity at the primary winding T1 .

[0168] In various embodiments, during this phase (a), the synchronous rectifier driver circuit 222a is configured to separate the voltage DVS from the threshold voltage V TH_ON The comparison is performed. Considering the direction of the voltage DVS, the threshold voltage has a negative value. For example, for this purpose, the synchronous rectifier driver circuit 222a may include an analog comparator.

[0169] In the embodiment considered, when the voltage DVS reaches the threshold voltage V at time t1 TH_ON When , the synchronous rectifier driver circuit 222a generates a drive signal GD to close the synchronous rectifier FET SR1 or SR2.

[0170] As mentioned above, the disclosed control method is mainly used to determine the switch-off instant t2.

[0171] Typically, the synchronous rectifier driver circuit 222 can use equation (14) for the entire duration between times t1 and t2. However, to reduce switching losses, the synchronous rectifier driver circuit 222 can use a portion of phase (b) during which the synchronous rectifier driver circuit 222 uses a constant or predetermined value for the drive signal GD.

[0172] For example, in various embodiments, the synchronous rectifier driver circuit 222 is configured to use:

[0173] a first mode M1 in which the synchronous rectifier driver circuit 222 sets the drive signal GD to a given (constant or predetermined) value; and

[0174] - A second mode, in which the synchronous rectifier driver circuit 222 changes the drive signal GD according to the signal DVS.

[0175] Specifically, in various embodiments, the synchronous rectifier driver circuit 222 uses mode M2 between time t3 and time t2 during phase (b). Conversely, the synchronous rectifier driver circuit 222 can be configured to use:

[0176] - mode M1 only (between times t1 and t3), or

[0177] - A first mode M2 (between instant t1 and instant t4 ), followed by mode M1 (between instant t4 and t3 ).

[0178] For example, in various embodiments, the synchronous rectifier driver circuit 222 may be configured to determine the time t3 by:

[0179] - adding a constant or predetermined time interval to time t1; or

[0180] - Determining when the absolute value of the voltage DVS decreases and reaches a given threshold.

[0181] Similarly, the synchronous rectifier driver circuit 222 may be configured to determine the time t4 by:

[0182] - adding a constant or predetermined time interval to time t1; or

[0183] - Determining when the absolute value of the voltage DVS increases and reaches a given threshold.

[0184] For example, Figure 11B As shown, between time t1 and t2, the current I SR will have a sinusoidal or partially sinusoidal behavior and will reach a peak value at the instant t3. Likewise, the measured voltage DVS will reach a peak value DVS at a given instant PK .

[0185] Specifically, in the embodiment under consideration, the synchronous rectifier driver circuit 222a uses this moment for the moment t3. Therefore, in various embodiments, the synchronous rectifier driver circuit 222a is configured to determine or estimate this moment t3. For example, the synchronous rectifier driver circuit 222a can be configured to:

[0186] - By detecting that the signal DVS reaches its peak value DVS PK to determine time t3; or

[0187] - determine the middle value of a given switching half-cycle and use this time instant for time instant t3; or

[0188] - The instant t3 is determined by detecting the instant when the signal DVS reaches a given (preferably fixed) threshold voltage, such as 40 mV.

[0189] For example, the synchronous rectifier driver circuit 222a may determine the middle value of a given switching half-cycle by:

[0190] - receiving a trigger signal from circuit 210;

[0191] - monitoring the drive signals for switches SW1 and SW2; or

[0192] - Determine the duration between the switch-on instant t1 and the switch-off instant t2 and calculate the instant t3(k) for a given period k as:

[0193] t3(k)=t1(k)+(t2(k-1)–t1(k-1)) / 2.

[0194] Specifically, in the embodiment considered, the synchronous rectifier driver circuit 222a is configured to generate a drive signal GD having two modes:

[0195] - between the switch-on instant t1 and the detected / estimated instant t3, a first mode M1, and

[0196] Between the detected / estimated instant t3 and the switch-off instant t2 there is a second mode M2 .

[0197] Specifically, as previously described, in various embodiments, the synchronous rectifier driver circuit 222a sets the drive signal GD to a given constant voltage, such as 3V or a voltage generally greater than the turn-off threshold V of the synchronous rectifier FET SR1 or SR2, during the first mode M1. TH_OFF voltage.

[0198] Specifically, in various embodiments, the synchronous rectifier driver circuit 222a sets the drive signal GD during the first mode M1 to:

[0199] GD=V x +K·|DVS′ PK |.

[0200] In various embodiments, the value DVS′ PK Can correspond to one of the following:

[0201] - Peak DVS of the previous switching cycle PK or a filtered version thereof, such as the peak DVS over multiple switching cycles PK the average value of

[0202] a sampled version of the signal DVS at the instant t3 of the previous switching cycle, or a filtered version thereof, such as the average value of the values DVS(t3) of a plurality of switching cycles.

[0203] In contrast, during the second mode M2, the synchronous rectifier driver circuit 222a changes the signal GD as shown in equation (15).

[0204] The above operation is also like Figure 11B As shown, where:

[0205] - the voltage GD is constant between the switch-on instant t1 and the detected / estimated instant t3,

[0206] - Voltage GD then decreases in proportion to voltage DVS until voltage DVS reaches the threshold voltage V of synchronous rectifier FET SR1 or SR2 at time t2 TH And the synchronous rectifier FET SR1 or SR2 is turned off.

[0207] Figure 11B Also shown is the on-resistance RDS of the synchronous rectifier FET SR1 or SR ON It remains substantially constant between the turn-on instant t1 and the instant t4 , and then increases significantly near the turn-off instant t2 .

[0208] As previously mentioned, in various embodiments, the synchronous rectifier driver circuit 222a is switched on when the voltage DVS reaches the threshold V TH_OFF After the instant t2, the signal GD is set to zero. SR To process the turn-off phase before it becomes positive, equation (14) can be modified to include the term ΔV:

[0209] GD=V x -ΔV+K·|DVS′|. (17)

[0210] Therefore, in various embodiments, three variables V must be selected x , K, and ΔV. For example, in various embodiments, a series of design indicators are considered.

[0211] Usually, when the current I SR When approaching zero, the on-resistance R DSON The value of must increase. Therefore, in essence, when I SR Close to zero (I SR →0), the voltage GD should correspond to the given value V TH , this value is sufficient to use high R SDSON to switch the synchronous rectifier FET, that is:

[0212] GD=V TH =V x (18)

[0213] When the FET threshold voltage V TH With minimum value V TH，min This condition should also be met in the worst case. For example, the minimum value V TH，min Temperature drift and technology spread must be taken into account, namely:

[0214] GD=V TH,min =V x (19)

[0215] In addition, in order to TH,min To ensure adequate parasitic immunity, the amplitude of the voltage DVS (i.e., |DVS|) should not be less than a given minimum value DVS sat , that is, in the worst case:

[0216] GD=V TH,min -ΔV+K·|DVS sat |. (20)

[0217] Therefore, by combining equations (18) and (20):

[0218] ΔV=K·|DVS sat |. (21)

[0219] The inventors have observed that the value DVS sat Should be chosen as a compromise between noise immunity and circuit speed. Higher DVS sat A value of 0 provides better noise immunity (less expected shutoffs) and it requires a lower rate of change of signal GD.

[0220] Furthermore, when the voltage |DVS| becomes higher than a given maximum value |DVS max The signal GD should have its maximum value GD when the ratio ɑ of | max , to maximize the converter efficiency. Typically, the maximum value GD max The power supply voltage VCC of the synchronous rectifier driver circuit 222a and the possible voltage drop V used to generate the signal GD are DROP Related, i.e., GD max =VCC-V DROP .

[0221] In various embodiments, considering the on-resistance R DSON and maximum power supply to determine the value of DVS max .

[0222] For example, based on equations (17), (18), and (20):

[0223] GD max =V TH,min -ΔV+K·|α·DVS max | (22)

[0224] GD max =V TH,min -K·|DVS sat |+K·|α·DVS max | (23)

[0225] GD max =V TH，min +K·(|α·DVS max |-|DVS sat |). (24)

[0226] Therefore, the parameter K can be calculated as:

[0227]

[0228] In summary, in various embodiments, the parameter Vx , K, and ΔV are chosen as follows:

[0229] V x =V TH,min

[0230]

[0231] ΔV=K·|DVS sat |. (26)

[0232] For example, assume that the synchronous rectifier MOSFETs SR1 and SR2 are IPP084N06L4 transistors, which have an on-resistance R of 8.1 mΩ. DSON and a typical threshold V of 2.7V TH_TYP , typical threshold has an extended ΔV of 0.5V spread_from_DS Therefore, the minimum threshold V TH,min It can be calculated as 2.7V–0.5V=2.2V(V TH_TYP- ΔV spread_from_DS ).

[0233] Furthermore, assuming that the power supply voltage VCC is 12V and the voltage drop V DROP is 1V, the maximum driving voltage GD max is 11V.

[0234] Finally, by adding |DVS sat |Select 4mV, and set |DVS max | is chosen to be 100mV and α is chosen to be 0.5, the parameters can be calculated according to equation (26): V x =2.2VK=191 and ΔV=764mV.

[0235] As mentioned above, most of the parameters used depend on the application, i.e., the operating parameters of the electronic converter, such as the supply voltage VCC, the voltage drop V in the synchronous rectifier driver circuit 222a, and the DROP , and there are parameters |DVS sat | and |DVS max | can be fixed. Therefore, in various embodiments, the driver circuit 222a is configured to allow the minimum threshold V TH,min Setting / programming is performed, for example, to allow the use of different synchronous rectifier FETs.

[0236] In fact, assuming that the maximum threshold of the transistor (V TH_TYP+ ΔV spread_from_DS ) is 3.2V, and the above parameters V x , K and ΔV, the driver circuit will be in |DVS sat|The minimum value is 9.2mV (and the maximum value GD max remains unchanged), which is still acceptable for proper FET turn-off and conversion efficiency.

[0237] Thus, as previously described, in various embodiments, the driver circuit 222a is configured to allow for setting a minimum threshold V of at least one (and preferably both) of the synchronous rectifier switches SR1 and SR2. TH,min .

[0238] Examples of simulation solutions are available in Figure 12 、 Figure 13 and Figure 14 The choice of one of the embodiments may depend on, for example, the number of pins used in the package of the synchronous rectifier driver 222a and the minimum value of the parameter V that can be set. TH,min .

[0239] Generally, in the illustrated embodiment, the synchronous rectifier driver circuit 222a is configured to generate a signal GD based on a voltage DVS (or more accurately, a measured voltage DVS′) between the drain and source terminals of a synchronous rectifier switch (e.g., SR1). CTRL , which indicates (e.g., is proportional to or corresponds to) the amplitude of the signal GD to be applied to the gate terminal of the synchronous rectifier switch (e.g., SR1). Accordingly, when using a synchronous rectifier driver circuit 222a integrated in an integrated circuit, the integrated circuit may include:

[0240] - Terminal 2232, configured to be connected to ground, such as Figure 3 The ground shown is GND2;

[0241] - a terminal 2234 configured to be connected to a power supply voltage VCC;

[0242] - a terminal 2226 configured to be connected to the drain terminal of the synchronous rectifier switch, thereby receiving the voltage DVS if the source terminal of the synchronous rectifier switch is connected to ground, ie, terminal 2232; and

[0243] a terminal configured to be connected to the gate terminal of the synchronous rectifier switch (see also Figure 3 ), whereby the signal GD is applied to this terminal.

[0244] Therefore, when the same synchronous rectifier driver circuit 222a is used to drive two synchronous rectifier switches SR1 and SR2, the circuit 222a includes Figure 12 and Figure 13 The two circuits shown in .

[0245] In an embodiment, the synchronous rectifier driver circuit 222a includes a variable current generator 2220 configured to generate a current I1 according to (the instantaneous value of) a voltage DVS (DVS′), for example, a voltage received at a terminal 2226. Specifically, in various embodiments, the current I1 is proportional to the voltage DVS:

[0246]

[0247] As previously mentioned, the synchronous rectifier driver circuit 222a can indeed use two modes M1 and M2 during a given period of phase (b). Figure 15 As shown, the synchronous rectifier driver circuit 222a may include for this purpose:

[0248] - Sample and hold circuit 2240, configured to hold the value DVS' PK 'Sampling;

[0249] - an electronic switch 2242 configured to selectively provide a current value DVS, a value DVS′ to the variable current generator 2220 PK or zero voltage; and

[0250] A control circuit 2244 configured to drive the electronic switch 2242 .

[0251] For example, the sample-and-hold circuit 2240 may be implemented using an analog peak detector, or the sample-and-hold circuit may be configured to sample the signal DVS in response to a trigger signal provided by the control circuit 2244 , where the trigger signal signals the time instant t3 .

[0252] As previously described, the control circuit 2244 may be configured to provide the following to the variable current generator 2220 via the electronic switch 2242:

[0253] - Between time t1 and t3, the value DVS' provided by the sample-and-hold circuit 2240 PK ;

[0254] - the value DVS received at the pin 2226 between the instant t3 and the instant t2; and

[0255] After this instant t2 (and until the next instant t1 ), zero voltage.

[0256] To this end, the control circuit 2244 may be configured to:

[0257] - For example, by comparing the signal DVS with a threshold value V via a first comparator TH_ON 'Compare to determine the conduction time t1;

[0258] - determining the time t3 as described above; and

[0259] - For example, by a second comparator, the signal DVS is compared with the threshold value V TH_OFF The comparison is performed to determine the switch-off instant t2.

[0260] The speed of the second comparator should be high to avoid the current I SR In fact, due to I SR The expected decrease, the turn-off instant t2 is now very close to the current I SR of zero crossing.

[0261] exist Figure 12 , the output of current generator 2220 is connected (e.g., directly connected) to node 2228, which in turn is connected (e.g., directly connected) to a first terminal of resistor R2, and a second terminal of resistor R2 is connected (e.g., directly connected) to ground / terminal 2232 via Zener diode Dz. In various embodiments, resistor R2 and / or Zener diode Dz can be external to the integrated circuit of synchronous rectifier driver circuit 222a. For example, for this purpose, node 2228 can be a terminal of such an integrated circuit, and resistor R2 and Zener diode Dz can be connected in series between terminal 2228 and terminal 2232.

[0262] Therefore, in Figure 12 Medium, signal GD CTRL corresponds to:

[0263]

[0264] Where V DZ Corresponds to the Zener voltage of diode Dz.

[0265] In this case, by comparing equations (28) and (26), the following relationship can be obtained:

[0266]

[0267] For example, for the example values above, V Dz Must correspond to 1.436V.

[0268] On the contrary, Figure 13, the output of current generator 2220 is in turn connected (e.g., directly connected) to node 2228, which in turn is connected (e.g., directly connected) to a first terminal of resistor R2, and a second terminal of resistor R2 is connected (e.g., directly connected) to ground / terminal 2232. Also in this case, resistor R2 can be external to the integrated circuit of the synchronous rectifier driver circuit 222a, i.e., node 2228 can be a terminal of such an integrated circuit, and resistor R2 can be connected between terminal 2228 and terminal 2232.

[0269] Therefore, in the embodiment considered, the following voltage V REF_DVS Generated at node 2228:

[0270]

[0271] Furthermore, in the considered embodiment, the synchronous rectifier driver circuit 222a comprises a second current generator 2222 configured to generate a (constant, but optionally settable / programmable) current I2.

[0272] In the embodiment under consideration, the output of the current generator 2222 is connected (e.g., directly connected) to a node 2230, which in turn is connected (e.g., directly connected) to a first terminal of a resistor R3, and a second terminal of the resistor R3 is connected (e.g., directly connected) to ground / terminal 2232. Furthermore, the resistor R3 may be external to the integrated circuit of the synchronous rectifier driver circuit 222 a, i.e., the node 2230 may be a terminal of such an integrated circuit, and the resistor R3 may be connected between the terminals 2230 and 2232.

[0273] Therefore, in the embodiment considered, the following voltage V REF_VTH Generated at node 2230:

[0274] V REF_VTH =R3·I2. (31)

[0275] In the embodiment considered, the voltage V REF_DVS and V REF_VTH is provided to a voltage adder circuit 2224 which provides a signal GD at its output. CTRL ,Right now:

[0276] GD CTRL =V REF_DVS +V REF_VTH (32)

[0277]

[0278] Therefore, assuming that the current I2 is constant, the following relationship can be obtained:

[0279]

[0280] For example, for the example values above, R3·I2 must correspond to 1.436V.

[0281] Finally, in Figure 14 In the embodiment shown, the output of current generator 2220 is in turn connected (e.g., directly) to node 2228. In the embodiment under consideration, node 2228 is connected (e.g., directly) to output voltage Vout / node 202a via a first resistor R2 and to ground, e.g., node 202b, via a second resistor R3. In various embodiments, resistors R2 and / or R3 may be external to the integrated circuit of synchronous rectifier driver circuit 222a. For example, for this purpose, node 2228 may be a terminal of such an integrated circuit, and resistors R2 and R3 may be connected in series between terminals 202a and 202b, with the intermediate node between resistors R2 and R3 being connected to terminal 2228. In general, instead of using output voltage Vout, resistors R2 and R3 may also be connected between any other (substantially) constant voltage.

[0282] Therefore, in the embodiment considered, the voltage at the node 2228 (corresponding to the voltage GD CTRL ) can be expressed similarly to equation (32) as follows:

[0283] GD CTRL =V REF_DVS +V REF_VTH (35)

[0284] The first one V REF_DVS can be solved as:

[0285] V REF_DVS =V out ·R3(R2+R3) (36)

[0286] And the second term V REF_DTH can be solved as:

[0287] V REF_DTH =I1·(R2 / / R3)=(DVS / R1)(R2 / / R3). (37)

[0288] Therefore, given equation (14), the following correspondence can be determined:

[0289] V x =V out ·R3(R2+R3) (38)

[0290] as well as

[0291] K=(R2 / / R3) / R1. (39)

[0292] Therefore, from the circuit point of view, Figure 14 The integrated circuit of the synchronous rectifier driver circuit 222a shown may correspond to Figure 12 The integrated circuit of the synchronous rectifier driver circuit 222a shown in FIG. 1 is the same as that of the synchronous rectifier driver circuit 222a, except that the connection of the external components may be changed. Therefore, the integrated circuit can support two connections.

[0293] Accordingly, regarding Figures 12 to 15 The circuit shown provides a low complexity solution for varying the signal GD in dependence on the voltage DVS, wherein the signal GD can optionally be set to a constant value, for example, in dependence on the peak value DVS. PK to confirm.

[0294] The DVS SGD technique has several advantages, such as:

[0295] - The occurrence of current reversal is reduced because when the synchronous rectifier FET is driven close to the threshold voltage V TH When the on-resistance R DSON increases, thereby reducing the inductance L RS The expected effect is that the voltage zero crossing moment of the signal DVS corresponds to the zero current moment of the current flowing through the synchronous rectifier FET;

[0296] - Current reversal related effects, such as DVS spikes, are reduced, e.g. because even if the synchronous rectifier FET is turned off with delay (i.e. in case of current reversal):

[0297] 1) High on-resistance R DSON High reverse currents in the transformer secondary winding are also not permitted; and

[0298] 2) Load current I out Still flows through the synchronous rectifier FET channel, but not through the diode associated with the synchronous rectifier FET body diode, ie, there is no diode reverse recovery charge, which would act to reverse charge the transformer secondary winding.

[0299] The above-described shutdown methods have some disadvantages that should be considered.

[0300] The DVS SGD technique is not intended to obtain a signal GD capable of operating at current I SRThis approach maintains a nearly constant shape of voltage DVS near zero. Such an approach requires a "true" closed-loop drive of the synchronous rectifier switches. The DVS SGD technique simply requires that voltage GD be determined based on (the instantaneous value of) signal DVS. However, this change in signal GD implies a change in on-resistance, and therefore also in signal DVS itself. In fact, as shown in Figure 11, a feedback loop does exist and is closed via synchronous rectifier switch SR. This loop means that any change in signal GD (or DVS) also affects signal DVS (or GD).

[0301] This may result in oscillations (noise) propagating from signal DVS to signal GD. In various embodiments, a (e.g. low-pass) filter circuit may therefore be provided in:

[0302] - between the drain terminal of the synchronous rectifier switch SR and the input node 2226 of the driver circuit 22a; and / or

[0303] - between the signal GD and the gate terminal of the synchronous rectifier switch SR.

[0304] Generally, the amount of filtering should not be too high, otherwise a high delay would be introduced between, for example, the actual voltage DVS (pre-filter) and the measured voltage DVS' (post-filter).

[0305] In addition, when the stray inductance L SR When the synchronous rectifier switch SR is large, it may still turn off prematurely, resulting in a large current I SR Flowing through the diode associated with the synchronous rectifier switch SR results in diode reverse recovery charge and subsequent DVS spikes. However, this effect is still reduced compared to the solution of the comparative example, and by choosing a lower value for the parameter K, loop stability can be improved.

[0306] However, reducing the parameter K means that a smaller voltage GD must be used (higher R DSON value) to obtain the desired final value DVS sat (E.g., 4 mV for the previous design example.) Such a lower voltage GD may require a more complex driver circuit for the synchronous rectifier switch SR.

[0307] Figure 16 Another embodiment is shown in which the synchronous rectifier driver circuit 222a uses closed-loop control of the voltage DVS.

[0308] As previously described, the synchronous rectifier driver circuit 222a is configured to use mode M1 at least during the last part of phase (b), in which the synchronous rectifier driver circuit 222a changes the voltage GD according to the voltage DVS. For example, in the embodiment considered, the synchronous rectifier driver circuit 222a again uses two modes:

[0309] - between the start of phase (b) at time t1 and time t3, mode M2 is used; and

[0310] Between the instant t3 and the end of phase (b) at the instant t2, mode M1 is used.

[0311] Specifically, during mode M2, the synchronous rectifier driver circuit 222a sets the voltage GD to a given constant (fixed or predetermined) value. Therefore, in this case, the voltage DVS will have a value similar to the current I SR The corresponding shape.

[0312] In the embodiment considered, the synchronous rectifier driver circuit 222a is configured to detect whether the absolute value of the voltage DVS decreases and reaches a given threshold voltage V REF Specifically, once the voltage DVS decreases and reaches a given threshold voltage V REF , the synchronous rectifier driver circuit 222 a switches to the mode M1 , in which the synchronous rectifier driver circuit 222 a changes the voltage GD according to the voltage DVS.

[0313] Specifically, in the embodiment considered, the synchronous rectifier driver circuit 222a is configured to vary the voltage GD to keep the voltage DVS constant, ie, to keep the voltage DVS at V REF Generally speaking, due to the current I SR As the current continues to decrease, the synchronous rectifier driver circuit 222a must increase the on-resistance R DSON , that is, the synchronous rectifier driver circuit 222a must reduce the drive signal GD until the drive signal GD drops to the threshold voltage V TH Following this, the FET is turned off, which corresponds to time t2.

[0314] Figure 17 Shown as Figure 16 A possible embodiment of a synchronous rectifier driver circuit 222a is shown operating.

[0315] As previously mentioned, in this case, the synchronous rectifier driver circuit 222a is configured to maintain the voltage DVS constant using closed-loop control of the drive signal GD during mode M1. In order to maintain the voltage DVS constant, the synchronous rectifier driver circuit 222a therefore includes a closed feedback loop that compares the voltage DVS with the threshold voltage V REF The feedback loop voltage V REF Adjust at the voltage 0>V REF >DVS PK range selection, for example, in DVS PK For example, the reference / threshold voltage V REF It can be provided by the voltage reference 2254. The reference voltage V REG It can also be used as the maximum DVS voltage during phase b. PK A small portion of the current is obtained via the digital core and digital-to-analog converter, an external reference power supply, components externally connected to the integrated circuit including the synchronous rectifier driver circuit 222a, etc.

[0316] For example, in the embodiment considered, the feedback loop comprises a (digital and / or analog) regulator circuit 2250 which receives at input the signals DVS and V REF , and generates a regulation signal REG at the output. Specifically, in various embodiments, the regulator circuit 2250 includes at least an integral (I) component and optionally includes a proportional (P) and / or differential (D) component. For example, the analog regulator circuit 2250 can be implemented using an operational amplifier having an associated corresponding feedback network, for example, including at least one capacitor for the integral component. In various embodiments, the input and / or output of the regulator circuit 2250 can have an associated filter circuit, for example, a low-pass filter configured to filter noise in the voltage DVS measurement and / or signal GD. The speed of the filter should be selected so that the dynamics of the gate voltage control can be maintained.

[0317] Thus, in the embodiment under consideration, the signal GD may be generated from the signal REG. For example, in the case where the synchronous rectifier driver circuit 222a also supports the mode M2, the synchronous rectifier driver circuit 222a may be configured to use the following as the voltage GD:

[0318] - in mode M2, a constant voltage, such as Vcc; and

[0319] - In mode M1, the signal REG.

[0320] Specifically, as previously described, once phase (b) ends, i.e., when voltage DVS drops to zero, control circuit 2244 should also be able to set signal GD to zero. Therefore, in various embodiments, synchronous rectifier driver circuit 222a is configured to selectively apply the following to terminal GD:

[0321] - Constant voltage (mode M2), when the voltage DVS reaches the turn-on threshold V TH_ON Time (t1);

[0322] -Signal REG voltage (mode M1), when the voltage DVS reaches the threshold V REF time (time t3); or

[0323] - Zero (in response to detecting time instant t2).

[0324] For example, in the embodiment under consideration, the synchronous rectifier driver circuit 222a includes, for this purpose, switching circuits 2256 and 2258, and a control circuit 2244. For example, in various embodiments, the control circuit 2244 is configured to monitor the voltage DVS and drive the switching circuits 2256 and 2258 to select (in order):

[0325] - Constant voltage (mode M2), when the voltage DVS reaches the turn-on threshold V TH_ON Time (t1);

[0326] -Signal REG (mode M1), when the voltage DVS reaches the threshold V REF time (time t3); and

[0327] - zero, when the voltage DVS reaches zero (instant t2).

[0328] For example, as schematically shown, the last condition may be verified via a zero voltage comparator 2252 .

[0329] Figure 17 A possible embodiment of the switching circuit is also shown. Specifically, in the embodiment considered, the switching circuit includes a multiplexer 2258, schematically shown via an electronic switch. Thus, in the embodiment considered, the control circuit 2244 can drive the multiplexer 2256 to switch between modes M1 and M2. In the embodiment considered, the signal at the output of the multiplexer 2256 is therefore not directly used as the signal GD, but the synchronous rectifier driver circuit 222a includes a circuit 2256 configured to select the signal at the output of the multiplexer 2256 or zero voltage.

[0330] For example, in the embodiment considered, the synchronous rectifier driver circuit 222a includes a driver circuit 2256, wherein the driver circuit 2256 receives the signal at the output of the multiplexer 2256 as a supply voltage, which therefore corresponds to the maximum output voltage of the driver circuit 2256, and the input of the driver circuit 2256 is driven by the control circuit 2244, which can therefore set the signal GD to zero or the signal at the output of the multiplexer 2256.

[0331] Therefore, once the control circuit 2244 detects that the voltage DVS reaches the threshold V TH_ON At time t1, the control circuit 2244 drives the switching circuits 2256 / 2258 to apply a constant voltage (full drive voltage) to the terminal GD. Next, when the control circuit 2244 detects that the voltage DVS reaches the voltage V REF At time t3, the control circuit 2244 drives the switching circuits 2256 and 2258 to apply the signal REG to the terminal GD, thereby activating the gate voltage shaping. Finally, once the control circuit 2244 detects that the voltage DVS reaches zero (time t2), the control circuit 2244 drives the switching circuits 2256 and 2258 to apply zero voltage to the terminal GD.

[0332] Therefore, from time t3 onwards, the voltage DVS is kept constant by decreasing the signal GD. As previously described, the control circuit 2244 can also be configured to detect time t3 in the following manner:

[0333] - Determine if the voltage DVS reaches the peak value DVS PK moment, or

[0334] - Wait for a given time relative to time t1.

[0335] Alternatively, the synchronous rectifier driver circuit 222 a may only support the mode M1 and always use gate voltage shaping, thereby reducing circuit complexity.

[0336] Of course, without prejudice to the principle of the present disclosure and without departing from the scope of the present disclosure, the details of construction and embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example.

[0337] A synchronous rectifier driver circuit (222a) is configured to drive a synchronous rectifier FET (SR1, SR2) including a drain, a source, and a gate terminal. The synchronous rectifier driver circuit can be summarized as comprising: a first terminal (2232) configured to be connected to the source terminal of the synchronous rectifier FET (SR1, SR2); a second terminal (2226) configured to be connected to the drain terminal of the synchronous rectifier FET (SR1, SR2); and a third terminal (GD) configured to be connected to the gate terminal of the synchronous rectifier FET (SR1, SR2). The synchronous rectifier driver circuit (222a) can be configured to: measure a voltage (DVS) between the second terminal (2226) and the first terminal (2232); detect a turn-on time (t1) when the measured voltage (DVS) reaches a first threshold value (V TH_ON ); detecting a turn-off moment (t2), wherein the measured voltage (DVS) reaches a second threshold value (V TH_OFF ); generating a drive signal (GD) between the third terminal (GD) and the first terminal (2232) according to the measured voltage (DVS) in the following manner: between another moment (t3) and the turn-off moment (t2), changing the drive signal (GD) according to the instantaneous value of the measured voltage (DVS); and setting the drive signal (GD) to a first value between the turn-off moment (t2) and the next turn-on moment (t1).

[0338] The synchronous rectifier driver circuit (222a) may be configured to set the drive signal (GD) to a second value between the turn-on time (t1) and the further time (t3). The synchronous rectifier driver circuit (222a) may be configured to determine the further time (t3) by determining that the measured voltage (DVS) reaches a peak value (DVS) between the turn-on time (t1) and the turn-off time (t2). PK ) moment (t3); wait for a given time from the conduction moment (t1); or determine that the measured voltage (DVS) reaches a given threshold (V REF ) at a moment (t3). The synchronous rectifier driver circuit (222a) may be configured to determine that the measured voltage reaches the peak value (DVS) by the following means: PK) moment: determining a duration between a previous turn-on moment (t1) and a corresponding previous turn-off moment (t2); and estimating the further moment (t3) at half the duration. The synchronous rectifier driver circuit (222a) may be configured to vary the drive signal (GD) between the further moment (t3) and the turn-off moment (t2) by setting the drive signal (GD) to a voltage corresponding to the sum of: a constant voltage (V x , ΔV), and a voltage proportional to a given proportionality constant (K) of the instantaneous value of the measured voltage (DVS). The synchronous rectifier driver circuit (222a) may include a circuit configured to store the peak value (DVS PK ) of the sample and hold circuit (2240), and wherein the synchronous rectifier driver circuit (222a) is configured to generate a current according to the stored peak value (DVS PK ) to determine the second value. The second value may correspond to the constant voltage (V x , ΔV) and the stored peak value (DVS PK ) is the sum of voltages proportional to the given proportionality constant (K).

[0339] A synchronous rectifier driver circuit may include: a fourth terminal (2228); a variable current generator (2220) configured to generate a variable current (I1) applied to the fourth terminal (2228), wherein the variable current (I1) may be proportional to a voltage received at an input of the variable current generator (2220); and a control circuit (2242, 2244) configured to connect the input of the variable current generator (2220): between the turn-on instant (t1) and the further instant (t3) to the stored peak value (DVS PK ); connected to the measured voltage (DVS) between the measured another moment (t3) and the turn-off moment (t2); and connected to the first terminal (2232) between the turn-off moment (t2) and the next turn-on moment (t1).

[0340] The voltage at the fourth terminal (2228) can reproduce the driving signal (GD).

[0341] The synchronous rectifier driver circuit (222a) may include: a fifth terminal (2230); a constant current generator (2220) configured to generate a constant current (I2) applied to the fifth terminal (2230); and a summing circuit (2224) configured to generate the drive signal (GD) by summing the voltage at the fourth terminal (2228) and the voltage at the fifth terminal (2230). The synchronous rectifier driver circuit (222a) may be configured to change the drive signal (GD) between the further time (t3) and the turn-off time (t2) to adjust (2250) the measured voltage (DVS) to a given reference value (V REF The synchronous rectifier driver circuit (222a) may include a regulator circuit (2250) configured to receive the measured voltage (DVS) and the given reference value (V REF ), and generating a regulation signal (REG) at an output, wherein the regulator circuit (2250) may include at least one integrating component, and wherein the drive signal (GD) is determined (2244, 2256, 2258) between the further instant (t3) and the switch-off instant (t2) as a function of the regulation signal (REG).

[0342] The integrated circuit may be summarized as the synchronous rectifier driver circuit (222a) described above.

[0343] An electronic resonant converter (20) can be summarized as comprising two input terminals (200a, 200b) for receiving an input voltage and a resonant converter (200b) for providing an output voltage (V out ) or output current (i out ) two output terminals (202a, 202b); a transformer (T) including a primary winding and first (T2a) and second (T2b) secondary windings; a summing stage (SW1, SW2) connected via a resonant tank (C r 、L s 、L p ) and connected to the primary winding; a first synchronous rectifier FET (SR1) connected in series with the first secondary winding (T2a) between the two output terminals (202a, 202b); a second synchronous rectifier FET (SR1) connected in series with the second secondary winding (T2b) between the two output terminals (202a, 202b); and two synchronous rectifier driver circuits (222a).

[0344] A method of operating a synchronous rectifier driver circuit (222a) can be summarized as comprising: measuring a voltage (DVS) between the second terminal (2226) and the first terminal (2232); detecting a turn-on instant (t1) wherein the measured voltage (DVS) reaches a first threshold (V TH_ON ); detecting a turn-off moment (t2), wherein the measured voltage (DVS) may reach a second threshold value (V TH_OFF ); generating a drive signal (GD) between the third terminal (GD) and the first terminal (2232) according to the measured voltage (DVS) in the following manner: between another moment (t3) and the turn-off moment (t2), changing the drive signal (GD) according to the instantaneous value of the measured voltage (DVS); and setting the drive signal (GD) to a first value between the turn-off moment (t2) and the next turn-on moment (t1).

[0345] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments claimed and the full scope of their equivalents. Therefore, the claims are not limited by the present disclosure.

Claims

1. A synchronous rectifier driver circuit configured to drive a synchronous rectifier FET including drain, source, and gate terminals, the synchronous rectifier driver circuit comprising: a first terminal configured to be connected to the source terminal of the synchronous rectifier FET; a second terminal configured to be connected to the drain terminal of the synchronous rectifier FET; a third terminal configured to be connected to the gate terminal of the synchronous rectifier FET; wherein the synchronous rectifier driver circuit is configured as: measuring a voltage between the second terminal and the first terminal; detecting a turn-on moment at which the measured voltage reaches a first threshold; detecting a switch-off moment at which the measured voltage reaches a second threshold; Generating a driving signal between the third terminal and the first terminal according to the measured voltage in the following manner: between another moment and the shut-off moment, changing the drive signal according to the measured instantaneous value of the voltage; as well as Between the turn-off moment and the next turn-on moment, the drive signal is set to a first value, The synchronous rectifier driver circuit is configured to determine the another time in the following manner: determining a time at which the measured voltage reaches a peak value between the turn-on time and the turn-off time; as well as Between the turn-on moment and the another moment, the drive signal is set to a second value, wherein the synchronous rectifier driver circuit includes: a sample-and-hold circuit configured to store the peak value, and wherein the synchronous rectifier driver circuit is configured to determine the second value based on the stored peak value.

2. The synchronous rectifier driver circuit according to claim 1 , wherein the synchronous rectifier driver circuit is configured to: Between the turn-on moment and the another moment, the drive signal is set to a second value.

3. The synchronous rectifier driver circuit according to claim 1 , wherein, corresponding to the synchronous rectifier driver circuit determining the another time by determining a time at which the measured voltage reaches a peak value between the turn-on time and the turn-off time, the synchronous rectifier driver circuit is configured to: A duration between a previous switch-on instant and a corresponding previous switch-off instant is determined, and at half of the duration the further instant is estimated.

4. The synchronous rectifier driver circuit of claim 1 , wherein the synchronous rectifier driver circuit is configured to change the drive signal between the another instant and the turn-off instant by setting the drive signal to a voltage corresponding to the sum of: a constant voltage and a voltage proportional to a given proportionality constant of the instantaneous value of the measured voltage. 5 . The synchronous rectifier driver circuit of claim 1 , wherein the second value corresponds to a sum of a constant voltage and a voltage proportional to a given proportionality constant of the stored peak value.

6. The synchronous rectifier driver circuit according to claim 1 , comprising: Fourth terminal; a variable current generator configured to generate a variable current applied to the fourth terminal, wherein the variable current is proportional to a voltage received at an input of the variable current generator; as well as A control circuit is configured to: between said turn-on moment and said another moment, connected to said stored peak value, Between the further instant and the switch-off instant, connecting to the measured voltage; and Between the turn-off timing and the next turn-on timing, the first terminal is connected. 7 . The synchronous rectifier driver circuit of claim 6 , wherein the voltage at the fourth terminal reproduces the drive signal.

8. The synchronous rectifier driver circuit according to claim 6, comprising: Fifth terminal; a constant current generator configured to generate a constant current applied to the fifth terminal; as well as The summing circuit is configured to generate the driving signal by summing the voltage at the fourth terminal and the voltage at the fifth terminal. 9 . The synchronous rectifier driver circuit of claim 1 , wherein the synchronous rectifier driver circuit is configured to change the drive signal between the another instant and the turn-off instant so as to regulate the measured voltage to a given reference value.

10. The synchronous rectifier driver circuit according to claim 9, wherein the synchronous rectifier driver circuit comprises: a regulator circuit configured to receive the measured voltage and the given reference value at an input and to generate a regulation signal at an output, wherein the regulator circuit comprises at least one integrating component, and wherein between the further instant and the switch-off instant, the drive signal is determined as a function of the regulation signal.

11. An integrated circuit comprising the synchronous rectifier driver circuit according to claim 1.

12. An electronic resonant converter comprising: two input terminals for receiving an input voltage and two output terminals for providing an output voltage or an output current; a transformer comprising a primary winding and first and second secondary windings; a switching stage connected to the primary winding via a resonant tank; a first synchronous rectifier FET connected in series with the first secondary winding between the two output terminals; a second synchronous rectifier FET connected in series with the second secondary winding between the two output terminals; and two synchronous rectifier driver circuits, each of the synchronous rectifier driver circuits being configured to drive a corresponding one of the first synchronous rectifier FET or the second synchronous rectifier FET including drain, source, and gate terminals, and comprising: a first terminal configured to be connected to the source terminal of the synchronous rectifier FET; a second terminal configured to be connected to the drain terminal of the synchronous rectifier FET; a third terminal configured to be connected to the gate terminal of the synchronous rectifier FET; wherein the synchronous rectifier driver circuit is configured as: measuring a voltage between the second terminal and the first terminal; detecting a turn-on moment at which the measured voltage reaches a first threshold; detecting a switch-off moment at which the measured voltage reaches a second threshold; Generating a driving signal between the third terminal and the first terminal according to the measured voltage in the following manner: between another moment and the turn-off moment, changing the drive signal according to the measured instantaneous value of the voltage; and Between the turn-off moment and the next turn-on moment, the drive signal is set to a first value, and The synchronous rectifier driver circuit is configured to determine the another time in the following manner: determining a time at which the measured voltage reaches a peak value between the turn-on time and the turn-off time; and Between the turn-on moment and the another moment, the drive signal is set to a second value, wherein the synchronous rectifier driver circuit includes: a sample-and-hold circuit configured to store the peak value, and wherein the synchronous rectifier driver circuit is configured to determine the second value based on the stored peak value.

13. The electronic resonant converter of claim 12 , wherein the synchronous rectifier driver circuit is configured to: Between the turn-on moment and the another moment, the drive signal is set to a second value.

14. The electronic resonant converter of claim 12 , wherein corresponding to the synchronous rectifier driver circuit determining the another time by determining the time at which the measured voltage reaches a peak between the turn-on time and the turn-off time, the synchronous rectifier driver circuit is configured to: A duration between a previous switch-on instant and a corresponding previous switch-off instant is determined, and at half of the duration the further instant is estimated.

15. A method of operating the synchronous rectifier driver circuit according to claim 1, the method comprising: measuring the voltage between the second terminal and the first terminal; detecting a turn-on moment at which the measured voltage reaches a first threshold; as well as detecting a switch-off moment at which the measured voltage reaches a second threshold; Generating a driving signal between the third terminal and the first terminal according to the measured voltage in the following manner: between another moment and the shut-off moment, changing the drive signal according to the measured instantaneous value of the voltage; as well as Between the turn-off moment and the next turn-on moment, the drive signal is set to a first value, determining the further time by determining a time at which the measured voltage reaches a peak value between the turn-on time and the turn-off time; between the turn-on moment and the another moment, setting the drive signal to a second value; storing the peak value by a sample-and-hold circuit of the synchronous rectifier driver circuit; as well as The second value is determined based on the stored peak value.

16. The method according to claim 15, further comprising: A duration between a previous switch-on instant and a corresponding previous switch-off instant is determined, and at half of the duration the further instant is estimated.

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