Module substrate and semiconductor module including the same

Abstract

A module substrate and a semiconductor module including the same can be provided. The module substrate includes a wiring substrate having upper and lower surfaces opposite to each other and including wirings formed therein, the wiring substrate having at least one through slot located in at least one sidewall and extending in a thickness direction, and a through slot test terminal including at least one contact pad, a surface of the contact pad being exposed from an inner wall of the through slot, the contact pad being spaced apart from a vertical plane extending from the sidewall of the wiring substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0135836, filed with the Korean Intellectual Property Office (KIPO) on October 20, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The example embodiments relate to a module substrate and / or a semiconductor module including the module substrate. More specifically, the example embodiments relate to a module substrate for a storage module such as a solid-state drive (SSD) and / or a semiconductor module including the module substrate. Background Technology

[0004] Storage modules, such as card-type SSDs, can be connected to a host system via connectors. The module substrate for the storage module may include test terminals as debug pads. However, as the number of electronic components mounted on the module substrate increases and the module substrate has a small form factor, it may be difficult to ensure sufficient design space for the test terminals and meet design specifications. Summary of the Invention

[0005] Some example embodiments provide module substrates that can easily ensure design space for test pads.

[0006] Some example embodiments provide a semiconductor module including a module substrate.

[0007] According to some example embodiments, a module substrate for a semiconductor module may include: a wiring substrate having upper and lower surfaces opposite each other and including wiring formed therein, the wiring substrate having at least one through-slot located in at least one sidewall and extending in the thickness direction; and a through-slot test terminal including at least one contact pad, the surface of the contact pad being exposed from the inner wall of the through-slot. The contact pad is spaced apart from a vertical plane extending from the sidewall of the wiring substrate.

[0008] According to some example embodiments, a module substrate for a semiconductor module may include: a wiring substrate including a first insulating layer to a fifth insulating layer and a first conductive pattern to a fourth conductive pattern located between the first insulating layer to the fifth insulating layer, the wiring substrate having at least one through-slot located in at least one sidewall of the wiring substrate and extending in a stacking direction of the first insulating layer to the fifth insulating layer; and a through-slot test terminal including a first contact pad to a fourth contact pad, the first contact pad to the fourth contact pad being electrically connected to the first conductive pattern to the fourth conductive pattern respectively, the surfaces of the first contact pad to the fourth contact pad being exposed from the inner wall of the through-slot. The first contact pad to the fourth contact pad are spaced apart from a vertical plane extending from the sidewall of the wiring substrate. The first distance between the two ends of the inner wall of the through groove that contact the side wall of the wiring substrate is in the range of 200 μm to 800 μm, and the second distance between each of the first to fourth contact pads and the vertical plane is in the range of 80 μm to 320 μm.

[0009] According to some example embodiments, a semiconductor module may include: a wiring substrate including a plurality of insulating layers and a plurality of conductive patterns respectively located on the plurality of insulating layers, the wiring substrate having at least one through-slot located in at least one sidewall and extending in a stacking direction of the insulating layers; a semiconductor device located on an upper or lower surface of the wiring substrate; and a through-slot test terminal electrically connected to the plurality of conductive patterns to electrically inspect the semiconductor device, the through-slot test terminal including a plurality of contact pads, the surfaces of the plurality of contact pads being exposed from an inner wall of the through-slot. The exposed surfaces of the plurality of contact pads may be arranged along the inner wall of the through-slot and may be spaced apart from a vertical plane extending from the sidewall of the wiring substrate.

[0010] According to some example embodiments, a semiconductor module may include a module substrate and semiconductor devices located on the module substrate. The module substrate may include a wiring substrate and a through-slot test terminal, the wiring substrate having at least one through-slot located in a sidewall and extending in the thickness direction, and the through-slot test terminal having at least one contact pad exposed from the inner wall of the through-slot.

[0011] The through-slot test terminal may include a plurality of contact pads located on the inner wall of the through-slot and spaced apart from each other in the thickness direction. The through-slot test terminal may be spaced apart from a vertical plane extending from the sidewall of the wiring substrate. The through-slot test terminal may be spaced apart from a horizontal plane extending from the upper or lower surface of the wiring substrate.

[0012] Therefore, the interface signal connection terminals used for inspecting semiconductor devices can be arranged in the sidewalls of a wiring substrate with a small or minute shape factor, thereby ensuring design space for the test pads. Furthermore, because the copper contact pads are not exposed from the sidewalls of the wiring substrate, the contact reliability with the inspection spring pins can be improved while meeting PCB design specifications. Attached Figure Description

[0013] Some exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 14 This refers to non-limiting example embodiments as described herein.

[0014] Figure 1 This is a top view showing a storage module according to some example embodiments.

[0015] Figure 2 yes Figure 1 Enlarged perspective view of the central "I".

[0016] Figure 3 This is a top view showing a portion of the inspection pad section of a storage module according to some example embodiments.

[0017] Figure 4 It is along Figure 3 The cross-sectional view taken by line A-A' in the diagram.

[0018] Figure 5 It is shown Figure 3 A perspective view of the through-slot test terminals in the inspection pad area.

[0019] Figure 6 yes Figure 5 A top view of the fourth contact pad of the through-slot test terminal in the middle.

[0020] Figure 7 yes Figure 5 A front view of the through-slot test terminal.

[0021] Figure 8 This is a top view showing a portion of the inspection pad section of a storage module according to some example embodiments.

[0022] Figure 9 It is along Figure 8 The cross-sectional view taken by line B-B' in the diagram.

[0023] Figure 10 It is shown Figure 8 A perspective view of the through-slot test terminals in the inspection pad area.

[0024] Figure 11 It is shown Figure 10 A top view of the fourth contact pad and plating pattern of the through-slot test terminal.

[0025] Figure 12 It is shown Figure 10 A front view of the through-slot test terminal.

[0026] Figure 13 This is a cross-sectional view showing a through-slot test terminal formed in a wiring substrate according to some example embodiments.

[0027] Figure 14 This is a top view showing a storage module according to some example embodiments. Detailed Implementation

[0028] In the following text, some exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a top view showing a storage module according to some example embodiments. Figure 2 yes Figure 1 Enlarged perspective view of the central "I".

[0030] Reference Figure 1 and Figure 2 The storage module 10 may include a module substrate 100, semiconductor devices 200 mounted on the module substrate 100, and inspection pad portions 300 disposed in the peripheral region of the module substrate 100. Furthermore, the storage module 10 may also include passive devices 210 disposed on the module substrate 100.

[0031] In some example embodiments, module substrate 100 may be a multilayer circuit substrate having upper and lower surfaces opposite each other. For example, module substrate 100 may be a printed circuit board (PCB). As described later, a PCB may include wiring on or in its surfaces and pathways connected to the wiring. The wiring may include conductive patterns for interconnecting semiconductor devices and passive devices.

[0032] The module substrate 100 may extend in a first direction (X direction). The module substrate 100 may be rectangular or square. The module substrate 100 may have a first sidewall S1 and a second sidewall S2 opposite to each other, a third sidewall S3 adjacent to the first sidewall S1, and a fourth sidewall S4 opposite to the third sidewall S3. A connector 150 having connection terminals for connection with a host system (not shown) may be provided in the third sidewall S3 of the module substrate 100.

[0033] The module substrate 100 may have a small or minute shape factor (F / F). The module substrate 100 can provide a design space of 22 × 30 F / F. The length L1 of the module substrate 100 in the first direction may be 30 mm, and the length L2 of the module substrate 100 in the second direction (Y direction) may be 22 mm. However, it will be understood that the size of the module substrate is not limited to these.

[0034] In some example embodiments, semiconductor device 200 may include a BGA-type multi-chip package comprising an SSD controller, a non-volatile memory device, and a buffer memory device. Semiconductor device 200 may be mounted on module substrate 100 such that storage module 10 is provided as a solid-state drive (SSD). SSDs can be used to replace hard drives in personal computers (PCs), laptops, etc. SSDs can be used in mobile devices such as smartphones, tablet PCs, digital cameras, MP3 players, or PDAs.

[0035] SSD controllers can use a host interface to transmit signals to the host. The host interface can include Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI) Fast, Advanced Technology Attached (ATA), Parallel ATA, Serial ATA, Serial Attached SCSI, etc. The signals transmitted between the SSD controller and the host can include commands, addresses, data, etc. The SSD controller can analyze and process the signals input from the host.

[0036] Multiple non-volatile storage devices can be used as the storage medium of an SSD. For example, non-volatile storage devices can include NAND flash memory. Non-volatile storage devices can be connected to the SSD controller via at least one channel (CH). SSDs can use non-volatile memory such as phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM) as the storage medium instead of flash memory.

[0037] Buffer storage devices can be used as buffers to temporarily store data received from the host or temporarily store data read from non-volatile storage devices. Furthermore, buffer storage devices can be used to drive software services for efficient management of non-volatile storage devices. Additionally, buffer storage devices can be used to store metadata received from the host and / or can be used to store cached data.

[0038] For example, a buffer storage device may include at least one dynamic RAM (DRAM) chip. An SSD can be implemented by replacing DRAM with volatile memory (e.g., static RAM (SRAM)) or non-volatile memory (e.g., flash memory, FRAM, MRAM, ReRAM, or FRAM).

[0039] In some example embodiments, passive devices may be disposed on the upper or lower surface of the module substrate 100. Passive devices may include inductors, capacitors, registers, etc.

[0040] The storage module 10 may also include a power management integrated circuit (IC) (PMIC) for adjusting the power applied to the semiconductor device.

[0041] In some example embodiments, inspecting the pad portion 300 may include test terminals 312, 322 disposed in the peripheral area of ​​the module substrate 100 for electrically testing the semiconductor device 200. The test terminals may be electrically connected to the semiconductor device 200 via wiring such as signal lines. The semiconductor device 200 may be electrically tested by connecting the test terminals to pogo pins (not shown) that serve as connection terminals for a tester.

[0042] For example, the inspection pad portion 300 may include 12 test terminals 312 and 322 (2×6 pins). The inspection pad portion 300 may include two through-slot test terminals 312 and ten through-hole test terminals 322. In this case, the tester's connection terminals may include 12 spring pins corresponding to the test terminals. The test terminals 312 and 322 of the inspection pad portion 300 can be used to debug the firmware code of the semiconductor device 200. For example, during the research and development and mass production phases of SSD products, the test terminals 312 and 322 can be used as input / output signal pins to perform testing tasks to detect and correct logic errors or abnormal operation (bugs) when driving the semiconductor device 200.

[0043] As described later, the slot test terminal 312 may be configured to be exposed to the inner wall of the slot 120 formed in the first sidewall S1 of the module substrate 100. The through-hole test terminal 322 may be formed on the inner wall of the through-hole 122 penetrating the module substrate 100. The through-hole test terminal 322 may include a through-hole.

[0044] The following section will describe the through-slot test terminals for inspecting the pad portion.

[0045] Figure 3 This is a top view showing a portion of the inspection pad section of a storage module according to some example embodiments. Figure 4 It is along Figure 3 The cross-sectional view taken by line A-A' in the diagram. Figure 5 It is shown Figure 3 A perspective view of the through-slot test terminals in the inspection pad area. Figure 6 yes Figure 5 A top view of the fourth contact pad of the through-slot test terminal in the middle. Figure 7 yes Figure 5 A front view of the through-slot test terminal.

[0046] Reference Figures 3 to 7 The module substrate 100 may include a wiring substrate and a through-slot test terminal 312 disposed in the inner wall of a through-slot 120 of the wiring substrate. The through-slot test terminal 312 may include at least one contact pad disposed in the inner wall of the through-slot 120. Throughout this disclosure, the module substrate 100 may be interchangeably referred to as a wiring substrate.

[0047] In some example embodiments, the wiring substrate may include a plurality of stacked insulating layers and conductive patterns disposed in the insulating layers respectively.

[0048] For example, the first insulating layer 110a, the second insulating layer 110b, the third insulating layer 110c, the fourth insulating layer 110d, and the fifth insulating layer 110e can be stacked sequentially on top of each other. The first insulating layer 110a can be a lower cover insulating layer, the second insulating layer 110b can be a lower insulating layer, the third insulating layer 110c can be a core layer, the fourth insulating layer 110d can be an upper insulating layer, and the fifth insulating layer 110e can be an upper cover insulating layer.

[0049] For example, the insulation layer may include an insulating material having a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. The insulation layer may include a resin with a core material such as organic fibers (glass fiber), such as prepreg, FR-4, or bismaleimide triazine (BT).

[0050] The first conductive pattern 310a may be formed on the lower surface of the second insulating layer 110b, and the second conductive pattern 310b may be formed on the upper surface of the second insulating layer 110b. The third conductive pattern 310c may be formed on the lower surface of the fourth insulating layer 110d, and the fourth conductive pattern 310d may be formed on the upper surface of the fourth insulating layer 110d. For example, the conductive patterns may include metallic materials such as copper or aluminum.

[0051] It will be understood that the arrangement and number of insulating layers and conductive patterns are exemplary and not limited thereto.

[0052] At least one through-slot 120 may be disposed in the first sidewall S1 of the module substrate 100. The through-slot 120 may extend in the thickness direction of the module substrate 100, that is, in the stacking direction (Z direction) of the insulating layer. When viewed in a top view, the through-slot 120 may have a shape that is recessed inward from the first sidewall S1. For example, when viewed in a top view, the through-slot 120 may have a semi-circular, semi-elliptical, or trapezoidal shape.

[0053] like Figure 4 and Figure 5 As shown, the first insulating layer 110a, the second insulating layer 110b, the third insulating layer 110c, the fourth insulating layer 110d, and the fifth insulating layer 110e may each have a first semi-circular hole 120a, a second semi-circular hole 120b, a third semi-circular hole 120c, a fourth semi-circular hole 120d, and a fifth semi-circular hole 120e disposed in their sidewalls. The through groove 120 may include the first semi-circular hole 120a, the second semi-circular hole 120b, the third semi-circular hole 120c, the fourth semi-circular hole 120d, and the fifth semi-circular hole 120e.

[0054] A first conductive pattern 310a may be disposed on the lower surface of the second insulating layer 110b to extend toward the inner wall of the through-slot 120 in a second direction, and the end of the first conductive pattern 310a may be exposed from the inner wall of the through-slot 120. The end of the first conductive pattern 310a exposed from the inner wall of the through-slot 120 may be referred to as a first contact pad 312a. The first contact pad 312a may be integrally formed with the first conductive pattern 310a. The width of the first contact pad 312a may be greater than the width of the first conductive pattern 310a (e.g., the width of the portion other than the end of the first conductive pattern 310a). In this case, the first contact pad 312a may extend along the inner wall of the second semi-circular hole 120b for a desired (or alternatively, predetermined) length.

[0055] The second conductive pattern 310b may be disposed on the upper surface of the second insulating layer 110b to extend toward the inner wall of the through-slot 120 in a second direction, and the end of the second conductive pattern 310b may be exposed from the inner wall of the through-slot 120. The end of the second conductive pattern 310b exposed from the inner wall of the through-slot 120 may be referred to as the second contact pad 312b. The second contact pad 312b may be integrally formed with the second conductive pattern 310b. The width of the second contact pad 312b may be greater than the width of the second conductive pattern 310b (e.g., the width of the portion other than the end of the second conductive pattern 310b). In this case, the second contact pad 312b may extend along the inner wall of the second semi-circular hole 120b for a desired (or alternatively, predetermined) length.

[0056] A third conductive pattern 310c may be disposed on the lower surface of the fourth insulating layer 110d to extend toward the inner wall of the through-slot 120 in a second direction, and the end of the third conductive pattern 310c may be exposed from the inner wall of the through-slot 120. The end of the third conductive pattern 310c exposed from the inner wall of the through-slot 120 may be referred to as a third contact pad 312c. The third contact pad 312c may be integrally formed with the third conductive pattern 310c. The width of the third contact pad 312c may be greater than the width of the third conductive pattern 310c (e.g., the width of the portion other than the end of the third conductive pattern 310c). In this case, the third contact pad 312c may extend along the inner wall of the fourth semi-circular hole 120d for a desired (or alternatively, predetermined) length.

[0057] A fourth conductive pattern 310d may be disposed on the upper surface of the fourth insulating layer 110d to extend toward the inner wall of the through-slot 120 in a second direction, and the end of the fourth conductive pattern 310d may be exposed from the inner wall of the through-slot 120. The end of the fourth conductive pattern 310d exposed from the inner wall of the through-slot 120 may be referred to as a fourth contact pad 312d. The fourth contact pad 312d may be integrally formed with the fourth conductive pattern 310d. The width V of the fourth contact pad 312d may be greater than the width W of the fourth conductive pattern 310d (e.g., the width of the portion other than the end of the fourth conductive pattern 310d). In this case, the fourth contact pad 312d may extend along the inner wall of the fourth semi-circular hole 120d for a desired (or alternatively, a predetermined) length V.

[0058] Therefore, the through-slot test terminal 312 may include a first contact pad 312a, a second contact pad 312b, a third contact pad 312c, and a fourth contact pad 312d, the surface of each contact pad being exposed from the inner wall of the through-slot 120. The first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d may be spaced apart from each other in the stacking direction. A spring pin of the tester may be inserted into the through-slot 120 to simultaneously contact the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d.

[0059] The first conductive pattern 310a, the second conductive pattern 310b, the third conductive pattern 310c, and the fourth conductive pattern 310d can be connected to a path 324. The path 324 can be electrically connected to the semiconductor device 200 via a signal line 311. Therefore, the through-slot test terminal 312 can be electrically connected to the semiconductor device 200 via the path 324 and the signal line 311.

[0060] like Figure 6 and Figure 7 As shown, the through-slot test terminal 312 can be spaced apart from the vertical plane M extending from the first sidewall S1 by a desired (or alternatively, predetermined) distance D1. The exposed surfaces of the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d can be spaced apart from the vertical plane M by a desired (or alternatively, predetermined) distance D1.

[0061] For example, the distance between the two ends of the inner wall of the through groove 120 that contact the first sidewall S1, i.e., the diameter D of the through groove 120, can be in the range of 200 μm to 800 μm. The spacing between the contact pad and the vertical plane M can be in the range of 80 μm to 320 μm.

[0062] Furthermore, the through-slot test terminal 312 may be spaced apart from each or either of the first horizontal plane N1 and the second horizontal plane N2 by a desired (or alternatively, predetermined) distance D2, the first horizontal plane N1 being a plane extending from the lower surface 104 of the wiring substrate, and the second horizontal plane N2 being a plane extending from the upper surface 102 of the wiring substrate. The exposed surface of the first contact pad 312a may be spaced apart from the first horizontal plane N1 by a desired (or alternatively, predetermined) distance D2. The exposed surface of the fourth contact pad 312d may be spaced apart from the second horizontal plane N2 by a desired (or alternatively, predetermined) distance D2.

[0063] For example, the thickness of the wiring substrate can be in the range of 400 μm to 1600 μm, and the distance between the first contact pad 312a and the first horizontal plane N1 and the distance between the fourth contact pad 312d and the second horizontal plane N2 can be in the range of 50 μm to 200 μm.

[0064] The through-slot test terminal 312 may occupy a portion of the inner wall area of ​​the through-slot 120. For example, the exposed surfaces of the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d may occupy at least 20% of the inner wall area of ​​the through-slot 120.

[0065] As described above, the semiconductor module 10 may include a module substrate 100 and a semiconductor device 200 mounted on the module substrate 100. The module substrate 100 may include a wiring substrate having at least one through-slot 120 located in its sidewalls and extending in its thickness direction, and a through-slot test terminal 312 having at least one contact pad exposed from the inner wall of the through-slot 120.

[0066] The through-slot test terminal 312 may include a first contact pad 312a, a second contact pad 312b, a third contact pad 312c, and a fourth contact pad 312d, which are spaced apart from each other on the inner wall of the through-slot 120 in the thickness direction of the wiring substrate. The through-slot test terminal 312 may be spaced apart from the vertical plane M extending from the first sidewall S1 by a desired (or alternatively, predetermined) distance D1. The through-slot test terminal 312 may be spaced apart from the first horizontal plane N1 and the second horizontal plane N2 extending from the upper surface 102 and the lower surface 104 of the wiring substrate by a desired (or alternatively, predetermined) distance D2.

[0067] Therefore, the interface signal connection terminals used for inspecting semiconductor devices can be arranged in the sidewalls of the wiring substrate with a small or minute form factor, thereby ensuring design space for the test pads. Furthermore, because the copper contact pads are not exposed from the sidewalls of the wiring substrate, the contact reliability with the inspection spring pins can be improved while meeting PCB design specifications.

[0068] Figure 8 This is a top view showing a portion of the inspection pad section of a storage module according to some example embodiments. Figure 9 It is along Figure 8 The cross-sectional view taken by line B-B' in the diagram. Figure 10 It is shown Figure 8 A perspective view of the through-slot test terminals in the inspection pad area. Figure 11 It is shown Figure 10 A top view of the fourth contact pad and plating pattern of the through-slot test terminal. Figure 12 yes Figure 10 A front view of the through-slot test terminal. In addition to the configuration with an additional plating pattern, the through-slot test terminal can be used with a reference... Figures 3 to 7 The described through-slot test terminals are the same or substantially similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repetitive descriptions of the aforementioned elements will be omitted.

[0069] Reference Figures 8 to 12 The through-slot test terminal may include at least one contact pad disposed in the inner wall of the through-slot 120 and a plating pattern 314 located on the inner wall of the through-slot 120 to cover the contact pad.

[0070] In some example embodiments, the plating pattern 314 may be disposed on the inner wall of the through groove 120 and extend a desired (or alternatively, predetermined) length in the thickness direction (Z direction) of the wiring substrate.

[0071] like Figure 9 and Figure 10 As shown, the plating pattern 314 can contact the exposed surfaces of the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d. The plating pattern 314 can cover a portion of the exposed surfaces of the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d, as well as a portion of the surfaces of the second insulating layer 110b, the third insulating layer 110c, and the fourth insulating layer 110d located between them.

[0072] The plated pattern 314 can be electrically connected to the first conductive pattern 310a, the second conductive pattern 310b, the third conductive pattern 310c, and the fourth conductive pattern 310d via the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d. The first conductive pattern 310a, the second conductive pattern 310b, the third conductive pattern 310c, and the fourth conductive pattern 310d can be connected to a path 324. Therefore, the through-slot test terminal can be electrically connected to the semiconductor device 200 via the path 324 and the signal line 311.

[0073] A plating layer can be formed on the inner wall of the channel 120 by an electroplating process, and then the plating layer can be patterned by an etching process or a drilling process to form a plating pattern 314. For example, the plating pattern may include a metallic material such as copper or nickel.

[0074] like Figure 11 and Figure 12As shown, the plating pattern 314 can be spaced from the vertical plane M extending from the first sidewall S1 by a desired (or alternatively, predetermined) distance D3. The plating pattern 314 can have a central angle θ relative to the center of the through groove 120. The central angle θ can have an angle range of 30 degrees to 70 degrees.

[0075] For example, the distance between the two ends of the inner wall of the through groove 120 that contact the first side wall S1, i.e., the diameter D of the through groove 120, can be in the range of 200 μm to 800 μm. The spacing between the plating pattern and the vertical plane M can be in the range of 60 μm to 300 μm.

[0076] Furthermore, the plating pattern 314 may be spaced apart from each of the first horizontal plane N1 and the second horizontal plane N2, or either horizontal plane, by a desired (or alternatively, predetermined) distance D4. The first horizontal plane N1 is a plane extending from the lower surface 104 of the wiring substrate, and the second horizontal plane N2 is a plane extending from the upper surface 102 of the wiring substrate. The lower surface of the plating pattern 314 may be spaced apart from the first horizontal plane N1 by a distance D4. The upper surface of the plating pattern 314 may be spaced apart from the second horizontal plane N2 by a desired (or alternatively, predetermined) distance D4.

[0077] For example, the thickness of the wiring substrate can be in the range of 400μm to 1600μm, and the distance between the lower surface of the plating pattern 314 and the first horizontal plane N1 and the distance between the upper surface of the plating pattern 314 and the second horizontal plane N2 can be in the range of 50μm to 200μm.

[0078] The plating pattern 314 may occupy a portion of the inner wall area of ​​the channel 120. For example, the plating pattern 314 may occupy at least 40% of the inner wall area of ​​the channel 120.

[0079] Figure 13 This is a cross-sectional view showing a through-slot test terminal formed in a wiring substrate according to some example embodiments.

[0080] Reference Figure 13 The through-slot test terminal may include a first contact pad 312a, a second contact pad 312b, a third contact pad 312c, and a fourth contact pad 312d exposed from the inner wall of the through-slot 120, and the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d may be connected to the first conductive pattern 310a, the second conductive pattern 310b, the third conductive pattern 310c, and the fourth conductive pattern 310d, respectively.

[0081] In some example embodiments, the third conductive pattern 310c and the fourth conductive pattern 310d can be connected to the first path 324a, and the first path 324a can be electrically connected to the semiconductor device 200 via the first signal line 311a. The first conductive pattern 310a and the second conductive pattern 310b can be connected to the second path 324b, and the second path 324b can be electrically connected to the semiconductor device 200 via the second signal line 311b.

[0082] For example, the first pathway 324a and the second pathway 324b may include blind pathways or buried pathways.

[0083] Therefore, when the tester's spring pin is inserted into the through slot 120 to simultaneously contact the first contact pad 312a, the second contact pad 312b, the third contact pad 312c, and the fourth contact pad 312d, the inspection mode or the operation mode (debugging mode or running mode) can be controlled according to the internal signal connection status from the first contact pad to the fourth contact pad.

[0084] Figure 14 This is a top view illustrating a storage module according to some example embodiments. Besides examining the configuration of the pad portions, the storage module can be compared with reference to... Figure 1 The described storage modules are the same or substantially similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repetitive descriptions of the aforementioned elements will be omitted.

[0085] Reference Figure 14 The inspection pad portion 300 of the storage module 11 may be disposed in a through-slot 120 formed in at least one sidewall of the module substrate 100. The inspection pad portion 300 may include through-slot test terminals 312 respectively disposed in the through-slot 120. The through-slot test terminals may be connected to a reference... Figures 3 to 7 The described through-slot test terminals are the same or substantially similar.

[0086] In some example embodiments, the test terminals for inspecting the pad portion 300 may be provided only in the through slots 120 formed in the sidewalls of the wiring substrate.

[0087] For example, through-slots 120 can be formed in the first sidewall S1 to be spaced apart from each other along a first direction (X direction). Through-slot test terminals can be respectively disposed on the inner wall of the through-slots 120. For example, inspecting the pad portion may include 10 through-slot test terminals. However, the arrangement and number of through-slot test terminals are not limited to this.

[0088] Therefore, since the test pads are only located on the sidewalls of the wiring substrate, sufficient design space can be ensured for pads used for connecting electronic components and interface signals.

[0089] The storage module according to some example embodiments has been described for use with SSDs, but is not limited thereto, and the storage module can be implemented as a semiconductor module including multiple storage devices.

[0090] The host (or host system) and storage module disclosed in this disclosure can be implemented as processing circuitry, such as hardware including logic circuitry or a combination of hardware and software, such as a processor executing software. For example, the processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0091] The foregoing description provides some exemplary embodiments and should not be construed as limiting these embodiments. Although several exemplary embodiments have been described, it will be readily understood by those skilled in the art that many modifications can be made to the disclosed exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications to the disclosed exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A module substrate for a semiconductor module, the module substrate comprising: A wiring substrate having an upper surface and a lower surface opposite to each other and including wiring formed therein, the wiring substrate having at least one through groove located in at least one sidewall and extending in the thickness direction. as well as A through-slot test terminal, the through-slot test terminal including at least one contact pad, the surface of the contact pad being exposed from the inner wall of the through-slot. The contact pads are spaced apart from a vertical plane extending from the sidewall of the wiring substrate.

2. The module substrate for a semiconductor module according to claim 1, wherein, The at least one contact pad is a plurality of contact pads, and the wiring substrate includes a plurality of stacked insulating layers, a plurality of conductive patterns disposed on the plurality of insulating layers, and the plurality of contact pads electrically connected to the plurality of conductive patterns.

3. The module substrate for a semiconductor module according to claim 2, wherein, The plurality of contact pads are spaced apart from each other along the stacking direction of the insulating layer.

4. The module substrate for a semiconductor module according to claim 2, wherein, The plurality of contact pads occupy at least 20% of the area of ​​the inner wall of the through groove.

5. The module substrate for a semiconductor module according to claim 1, wherein, The through-slot test terminal also includes a plating pattern located on the inner wall of the through-slot, the plating pattern being configured to cover the exposed surface of the contact pad and spaced apart from the vertical plane by a certain distance.

6. The module substrate for a semiconductor module according to claim 5, wherein, The at least one contact pad is a plurality of contact pads, the plurality of contact pads are electrically connected to a plurality of conductive patterns respectively, and the plating pattern covers the surface of the plurality of contact pads.

7. The module substrate for a semiconductor module according to claim 5, wherein, The plating pattern occupies at least 40% of the area of ​​the inner wall of the channel.

8. The module substrate for a semiconductor module according to claim 1, wherein, The first distance between the two ends of the inner wall of the through groove that contact the side wall is in the range of 200 μm to 800 μm, and the second distance between the contact pad and the vertical plane is in the range of 80 μm to 320 μm.

9. The module substrate for a semiconductor module according to claim 1, wherein, The contact pads are spaced apart from a horizontal plane extending from the upper or lower surface of the wiring substrate by a certain distance.

10. The module substrate for a semiconductor module according to claim 9, wherein, The thickness of the wiring substrate is in the range of 400μm to 1600μm, and the distance between the contact pad and the horizontal plane is in the range of 50μm to 200μm.

11. A module substrate for a semiconductor module, the module substrate comprising: A wiring substrate, the wiring substrate including a first insulating layer to a fifth insulating layer and a first conductive pattern to a fourth conductive pattern located between the first insulating layer to the fifth insulating layer, the wiring substrate having at least one through slot located in at least one sidewall of the wiring substrate and extending in the stacking direction of the first insulating layer to the fifth insulating layer. as well as A through-slot test terminal, comprising a first contact pad to a fourth contact pad, wherein the first contact pad to the fourth contact pad are electrically connected to a first conductive pattern to the fourth conductive pattern respectively, and the surfaces of the first contact pad to the fourth contact pad are exposed from the inner wall of the through-slot. Wherein, the first contact pad to the fourth contact pad are spaced apart from the vertical plane extending from the sidewall of the wiring substrate, and The first distance between the two ends of the inner wall of the through groove that contact the side wall of the wiring substrate is in the range of 200 μm to 800 μm, and the second distance between each of the first to fourth contact pads and the vertical plane is in the range of 80 μm to 320 μm.

12. The module substrate for a semiconductor module according to claim 11, wherein, The through-slot test terminal occupies at least 20% of the area of ​​the inner wall of the through-slot.

13. The module substrate for a semiconductor module according to claim 11, wherein, The through-slot test terminal also includes a plating pattern located on the inner wall of the through-slot, the plating pattern being configured to cover the exposed surfaces of the first contact pad to the fourth contact pad and spaced a third distance from the vertical plane.

14. The module substrate for a semiconductor module according to claim 11, wherein, The first conductive pattern to the fourth conductive pattern are connected to a pathway that penetrates at least a portion of the wiring substrate.

15. The module substrate for a semiconductor module according to claim 11, wherein, Some of the conductive patterns from the first conductive pattern to the fourth conductive pattern are connected to a first path that penetrates at least a portion of the wiring substrate, and other conductive patterns from the first conductive pattern to the fourth conductive pattern are connected to a second path that penetrates another portion of the wiring substrate.

16. A semiconductor module, the semiconductor module comprising: A wiring substrate comprising a plurality of insulating layers and a plurality of conductive patterns respectively located on the plurality of insulating layers, the wiring substrate having at least one through slot located in at least one sidewall and extending in the stacking direction of the insulating layers; A semiconductor device located on the upper or lower surface of the wiring substrate; as well as Through-slot test terminals, electrically connected to the plurality of conductive patterns for electrical inspection of the semiconductor device, the through-slot test terminals including a plurality of contact pads, the surfaces of the plurality of contact pads being exposed from the inner wall of the through-slot. The exposed surfaces of the plurality of contact pads are arranged along the inner wall of the through slot and spaced apart from a vertical plane extending from the side wall of the wiring substrate.

17. The semiconductor module according to claim 16, wherein, The semiconductor device includes a non-volatile memory device and a controller connected to the non-volatile memory device.

18. The semiconductor module according to claim 16, wherein, The plurality of contact pads occupy at least 20% of the area of ​​the inner wall of the through groove.

19. The semiconductor module according to claim 16, wherein, The through-slot test terminal also includes a plating pattern located on the inner wall of the through-slot and configured to cover the exposed surfaces of the plurality of contact pads.

20. The semiconductor module according to claim 19, wherein, The plating pattern occupies at least 40% of the area of ​​the inner wall of the channel.

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