Semiconductor device and power conversion device

Abstract

The present invention provides a semiconductor device with high cutoff tolerance that can suppress local electric field concentration and current concentration at the chip terminal caused by electric field deviation between IGBT units due to shape deviation and impurity deviation during manufacturing. The device is characterized by comprising: an emitter electrode formed on the surface of a semiconductor substrate via an interlayer insulating film; a collector formed on the back surface of the semiconductor substrate; a first semiconductor layer of a first conductivity type, which is in contact with the collector and formed on the back surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is formed on the inner side than the first semiconductor layer; a central region unit, which is arranged along the surface of the semiconductor substrate; and a peripheral region unit, which is located on the outer side than the central region unit in the plane direction of the semiconductor substrate and is arranged between the central region unit and the chip terminal guard ring region.

Description

Technical Field

[0001] The present invention relates to the structure of a semiconductor device, and more particularly to a technology that is effective when applied to an insulated gate bipolar transistor (IGBT) mounted in a power conversion device. Background Art

[0002] IGBT modules (Insulated Gate Bipolar Transistor: hereinafter referred to as IGBT), which are the main components of power converters such as inverters, are required to be low-cost and small-sized. Similarly, power device chips in power modules are also required to be low-cost and small-sized, and new technologies are required to achieve high output current density of IGBT chips.

[0003] If the output current density is high, the loss per unit chip area of ​​the power device increases and the chip temperature rises. Therefore, in the IGBT chip, it is necessary to expand the safe operating area (Reverse BiasSafe Operating Area: hereinafter also referred to as RBSOA) when shutting down at high output current. In other words, the IGBT needs to have sufficient current cut-off tolerance so that it will not be destroyed even at higher currents, voltages, and temperatures.

[0004] Under such circumstances, as a technology for improving the current cutoff capability, for example, Patent Document 1 proposes a technology for reducing hole injection in the p-type collector layer of the peripheral guard ring portion of the IGBT chip and suppressing current concentration in the cell portion functioning as an active region. This can suppress the parasitic bipolar transistor action of the IGBT cell caused by current concentration and improve the current cutoff capability.

[0005] In addition, Patent Document 2 proposes a structure in which the avalanche resistance of the terminal region is higher than that of the IGBT cell by removing the trench structure of the terminal region of the IGBT chip and making the opening area of ​​the contact hole of the terminal region equal to or smaller than that of the central region. This can suppress the concentration of electric field in the terminal region, and even when a high surge voltage is generated, the element will not be damaged, and the RBSOA can be improved.

[0006] Patent Document 3 proposes a technology in which an electric field concentration region formed by a PN junction is provided in the center between trenches of an IGBT cell, electron injection by impact ionization at turn-off is uniformly generated between cells, current concentration is suppressed, and turn-off tolerance is improved.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2003-133556

[0010] Patent Document 2: Japanese Patent Application Publication No. 2011-100877

[0011] Patent Document 3: Japanese Patent Application Publication No. 2016-012581 Summary of the invention

[0012] Problems to be solved by the invention

[0013] However, in the prior art of Patent Documents 1 and 2, when electric field deviation occurs among a plurality of IGBT cells due to shape deviation or impurity deviation during manufacture of the IGBT cells, current electric field concentration may occur in cells with strong electric field, thereby reducing the cutoff withstand capability.

[0014] Furthermore, in the prior art of Patent Document 3, hole current from the chip terminal portion concentrates in cells at the chip periphery and the chip corners, which may hinder the improvement of the shutdown withstand capability.

[0015] Therefore, the object of the present invention is to provide a semiconductor device with high cutoff tolerance that can suppress local current electric field concentration and current concentration at the chip terminal caused by electric field deviation between IGBT cells due to shape deviation and impurity deviation during manufacturing, and a power conversion device using the semiconductor device.

[0016] Means for solving problems

[0017] In order to solve the above-mentioned problems, the semiconductor device of the present invention comprises: an emitter electrode, which is formed on the surface of a semiconductor substrate via an interlayer insulating film; a collector electrode, which is formed on the back side of the semiconductor substrate; a first semiconductor layer of a first conductivity type, which is in contact with the collector electrode and is formed on the back side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is formed on the inner side than the first semiconductor layer; a central area unit, which is arranged along the surface of the semiconductor substrate; a peripheral area unit, which is located on the outer side than the central area unit in the plane direction of the semiconductor substrate, and is arranged between the central area unit and a chip terminal protection ring area, wherein the central area unit includes: a groove, which is formed between the emitter electrode and the semiconductor substrate; a gate electrode, which is formed on the inner side of the groove via a gate insulating film and is insulated from the emitter electrode via the interlayer insulating film; a third semiconductor layer of a second conductivity type, which is formed to be in contact with the gate insulating film and has an impurity concentration higher than that of the semiconductor substrate. high; a fourth semiconductor layer of the first conductivity type, which is formed to be in contact with the semiconductor substrate side of the emitter electrode via an emitter contact portion, and has a higher impurity concentration than the first semiconductor layer; a fifth semiconductor layer of the first conductivity type, which is in contact with the gate insulating film and formed on the semiconductor substrate side of the second semiconductor layer, and has a lower impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the first conductivity type, which is in contact with the surface of the semiconductor substrate side of the fourth semiconductor layer and is formed to protrude from the fifth semiconductor layer to the semiconductor substrate side, and has a lower carrier concentration than the fourth semiconductor layer; a seventh semiconductor layer of the second conductivity type, which is formed to be in contact with the collector side surface of the sixth semiconductor layer, and has a higher impurity concentration than the semiconductor substrate, the peripheral area unit comprises the groove, the gate electrode, the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer, and the peripheral area unit does not have at least one of the third semiconductor layer and the seventh semiconductor layer.

[0018] In addition, the present invention is an electric power conversion device comprising: a pair of DC terminals; an AC terminal having the same number as the number of AC phases; a switching bridge arm connected between the pair of DC terminals, connecting in series a parallel circuit of two diodes having opposite polarities to the switching elements, wherein the interconnection points of the parallel circuits constitute an electric power conversion unit having the same number as the number of AC phases connected to different AC terminals, and characterized in that the switching element is the semiconductor device described above.

[0019] Effects of the Invention

[0020] According to the present invention, a semiconductor device with high cutoff tolerance that can suppress local current electric field concentration and current concentration at the chip terminal caused by electric field deviation between IGBT cells due to shape deviation and impurity deviation during manufacturing, and a power conversion device using the semiconductor device can be realized.

[0021] This makes it possible to realize a higher current density of the IGBT chip, and contribute to miniaturization of a power conversion device equipped with the IGBT chip.

[0022] Other problems, structures, and effects than those described above will become apparent from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A It is a top view of the IGBT semiconductor chip according to the first embodiment of the present invention.

[0024] Figure 1B yes Figure 1A An enlarged view of the cell terminal area 105.

[0025] Figure 2 yes Figure 1B Cross-sectional view of the AA' portion.

[0026] Figure 3 This is a cross-sectional view of a conventional IGBT semiconductor chip.

[0027] Figure 4 It is a diagram showing a manufacturing process of the IGBT semiconductor chip according to the first embodiment of the present invention.

[0028] Figure 5 This is a diagram showing a turn-off waveform (normal waveform) of an IGBT semiconductor chip.

[0029] Figure 6 This is a schematic diagram showing the internal state of a conventional IGBT semiconductor chip when it is turned off.

[0030] Figure 7 This is a schematic diagram showing the internal state of a conventional IGBT semiconductor chip when it is turned off.

[0031] Figure 8 It is a diagram showing changes in the impact ionization coefficient α and the electric field when the IGBT semiconductor chip is turned off.

[0032] Fig. 9 This is a schematic diagram showing the internal state of the IGBT semiconductor chip according to the first embodiment of the present invention when it is turned off.

[0033] Fig.10 It is a cross-sectional view of an IGBT semiconductor chip according to the second embodiment of the present invention.

[0034] Fig.11 It is a cross-sectional view of an IGBT semiconductor chip according to a third embodiment of the present invention.

[0035] Fig.12 It is a cross-sectional view of an IGBT semiconductor chip according to a fourth embodiment of the present invention.

[0036] Fig.13 It is a cross-sectional view of an IGBT semiconductor chip according to a fifth embodiment of the present invention.

[0037] Fig.14 It is a top view of a cell terminal region of an IGBT semiconductor chip according to a sixth embodiment of the present invention.

[0038] Fig.15 This is a bird's-eye view of an IGBT semiconductor chip according to a sixth embodiment of the present invention.

[0039] Fig.16 This is a bird's-eye view of an IGBT semiconductor chip according to a seventh embodiment of the present invention.

[0040] Fig.17 This is a bird's-eye view of an IGBT semiconductor chip according to an eighth embodiment of the present invention.

[0041] Fig.18 It is a top view of a cell terminal region of an IGBT semiconductor chip according to a ninth embodiment of the present invention.

[0042] Fig.19 This is a bird's-eye view of an IGBT semiconductor chip according to a ninth embodiment of the present invention.

[0043] Fig. 20 This is a circuit block diagram of a power conversion device according to a tenth embodiment of the present invention. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in each figure, elements with the same reference numerals represent the same constituent elements or constituent elements with similar functions. In addition, p-, p, and p+ indicate that the conductivity type of the semiconductor layer is p-type, and the relative impurity concentration increases in this order. Moreover, n-, n, and n+ indicate that the conductivity type of the semiconductor layer is n-type, and the relative impurity concentration increases in this order.

[0045] Example 1

[0046] Reference Figures 1A to 9 , a semiconductor device and a method for manufacturing the same according to the first embodiment of the present invention are described. In addition, Figure 3 , Figure 6 , Figure 7This is a diagram showing a conventional IGBT semiconductor chip shown as a comparative example to facilitate understanding of the present invention.

[0047] Figure 1A 1 is a top view of an IGBT semiconductor chip 101. A cell region 103 in which a plurality of IGBT unit cells are arranged is provided in the center of the chip. In addition, a gate electrode PAD 104 for applying a gate voltage to the IGBT is provided. In addition, a chip terminal guard ring region 102 is provided on the periphery of the IGBT semiconductor chip 101.

[0048] Figure 1B This is an enlarged view of the cell terminal region 105 of the IGBT semiconductor chip 101, and is a schematic diagram showing a surface structure without an emitter electrode. A plurality of cell parts with trench gates 204 periodically arranged are arranged in the cell region 103, and an emitter contact part 203 is provided in the center of the cell part. The cell part is provided with a central region cell 201 and a peripheral region cell 202 of the IGBT semiconductor chip 101, and the peripheral region cell 202 is located outside the plane direction of the IGBT semiconductor chip 101 than the central region cell 201, and is located between the chip terminal guard ring region 102.

[0049] Figure 2 yes Figure 1B The central region unit 201 is formed to include: a groove (described later) Figure 4501), which is formed between the emitter electrode 301 and the semiconductor substrate 308; a gate electrode (trench gate 204), which is formed on the inner side of the trench and is insulated from the emitter electrode 301 via an insulating layer (interlayer insulating film 302); a gate insulating film 310, which is formed in the trench; a third semiconductor layer (n+ source layer) 303 of the second conductivity type, which is formed to be in contact with the gate insulating film 310 and has an impurity concentration higher than that of the semiconductor substrate 308; a fourth semiconductor layer (shallow p+ layer) 304 of the first conductivity type, which is formed to be in contact with the surface of the semiconductor substrate 308 side of the emitter electrode 301 via the emitter contact portion 203 and has an impurity concentration higher than that of the first semiconductor layer (p-type collector layer) 312; a fifth semiconductor layer (p-base) of the first conductivity type The fourth semiconductor layer (shallow p+ layer) 304 has an impurity concentration lower than that of the fourth semiconductor layer (shallow p+ layer) 304; the sixth semiconductor layer (deep p+ layer) 306 of the first conductivity type is formed to be in contact with the surface of the fourth semiconductor layer (shallow p+ layer) 304 on the semiconductor substrate 308 side and protrudes from the fifth semiconductor layer (p base layer) 305 to the semiconductor substrate 308 side, and has a carrier concentration lower than that of the fourth semiconductor substrate (shallow p+ layer) 304; the seventh semiconductor layer (deep n layer) 307 of the second conductivity type is formed to be in contact with the surface on the collector electrode 313 side of the sixth semiconductor layer (deep p+ layer) 306, and has an impurity concentration higher than that of the semiconductor substrate 308.

[0050] The peripheral region unit 202 outside the central region unit 201 in the plane direction of the IGBT semiconductor chip 101 is formed with a groove (described later) Figure 4501), which is formed between the emitter electrode 301 and the semiconductor substrate 308; a gate electrode (trench gate 204), which is formed on the inner side of the trench and is insulated from the emitter electrode 301 via an insulating layer (interlayer insulating film 302); a gate insulating film 310, which is formed in the trench; a third semiconductor layer (n+ source layer) 303 of the second conductivity type, which is formed to be in contact with the gate insulating film 310 and has a higher impurity concentration than the semiconductor substrate 308; a fourth semiconductor layer (shallow p+ layer) 304 of the first conductivity type, which is formed to be in contact with the surface of the semiconductor substrate 308 side of the emitter electrode 301 and has an impurity concentration higher than the first semiconductor layer. The body layer (p-type collector layer) 312 is high; the fifth semiconductor layer (p base layer) 305 of the first conductivity type is connected to the gate insulating film 310 and is formed on the semiconductor substrate 308 side of the third semiconductor layer (n+ source layer) 303, and the impurity concentration is lower than the fourth semiconductor layer (shallow p+ layer) 304; the sixth semiconductor layer (deep p+ layer) 306 of the first conductivity type is formed to be connected to the surface of the semiconductor substrate 308 side of the fourth semiconductor layer (shallow p+ layer) 304 and protrude from the fifth semiconductor layer (p base layer) 305 to the semiconductor substrate 308 side, and the carrier concentration is lower than the fourth semiconductor layer (shallow p+ layer) 304.

[0051] Figure 4 This embodiment ( Figure 2 ) is a diagram of the manufacturing process of the IGBT semiconductor chip 101.

[0052] 《(a) Trench Gate Formation》

[0053] First, an n-semiconductor substrate 308 (for example, a semiconductor wafer such as a Si wafer) is prepared.

[0054] Next, the insulating film (eg, SiO 2 ) formed on the n − semiconductor substrate 308 is patterned by photolithography for forming a trench.

[0055] Next, the trench 501 is formed by anisotropic etching using the patterned insulating film as a mask.

[0056] 《(b) Formation of p base layer and n+ source layer》

[0057] Next, a gate insulating film is formed, a polysilicon film is deposited, and after exposure by photolithography, a trench gate 204 is formed by processing.

[0058] Next, using the photoresist patterned for forming the p-base layer 305 as a mask, ion implantation of p-type impurities is performed, and heat treatment is performed, thereby forming the fifth semiconductor layer (p-base layer) 305 .

[0059] Next, using the photoresist patterned for forming the n + source layer 303 as a mask, ion implantation of n-type impurities is performed to form the third semiconductor layer (n + source layer) 303 .

[0060] 《(c) Contact formation》

[0061] Next, an interlayer insulating film 302 is deposited on the entire surface of the n- semiconductor substrate 308. The interlayer insulating film 302 is planarized by, for example, reflow of a BPSG (Boron-Phosphors Silicate Glass) film, CMP (Chemical Mechanical Polishing) or other planarization means.

[0062] After the interlayer insulating film 302 is planarized, the contact hole 502 is formed by photolithography and anisotropic etching. At this time, the contact hole 502 penetrates the interlayer insulating film 302 and reaches the fifth semiconductor layer (p base layer) 305. Thus, when the p base layer 305 is observed in cross section, a pair of n+ source layers are formed, and a groove portion that contacts a contact metal layer formed in a subsequent process is formed.

[0063] 《(d) Shallow p-layer formation, deep p-layer formation》

[0064] Next, using the interlayer insulating film 302 as a mask, ion implantation is performed in the shallow p+ layer 304 and the deep p+ layer 306 in sequence to form a fourth semiconductor layer (shallow p+ layer) 304 and a sixth semiconductor layer (deep p+ layer) 306, respectively.

[0065] 《(e) Deep n+ layer formation》

[0066] Next, an anti-etching agent 503 is applied to the entire surface of the n-semiconductor substrate 308, and the anti-etching agent 503 is opened only in the central area through photolithography. The seventh semiconductor layer (deep n layer) 307 is formed by ion implantation. After removing the anti-etching agent, heat treatment is performed to form a p+ contact and an n+ source contact in a self-aligned manner relative to the contact hole 502.

[0067] 《(f) Emitter electrode, back side n buffer, p collector layer, collector formation》

[0068] Next, the contact hole 502 is filled with a stacked metal film made of a high melting point metal such as Ti, TiN, or W, and planarized by etching or CMP to form a contact metal layer (emitter contact portion 203). Then, a metal layer made of aluminum or the like is deposited, and an emitter electrode 301 and a gate electrode PAD104 (not shown) are formed by photolithography and etching. After that, although not shown, a surface protection film made of polyimide or the like is formed and patterned.

[0069] The above steps are surface processing of the semiconductor substrate 308 .

[0070] Next, n-type and p-type impurity ions are implanted into the semiconductor substrate 308 from the back side of the semiconductor substrate 308 , and laser annealing is performed to form a second semiconductor layer (n-type buffer layer) 311 and a first semiconductor layer (p-type collector layer) 312 .

[0071] In addition, by appropriately adjusting the acceleration energy during ion implantation, it is possible to form an n-type buffer layer 311 and a p-type collector layer 312 at different depths from the back surface of the semiconductor substrate 308. Then, on the back surface side of the semiconductor substrate 308, a stacked metal layer, such as an Al-Ti-Ni-Au film, is formed by sputtering to form a collector 313.

[0072] The feature of the embodiment 1 is that the central region unit 201 in the plane direction of the IGBT semiconductor chip 101 forms a pn junction where the electric field is easily concentrated in the sixth semiconductor layer 306 and the seventh semiconductor layer 307, and the unit (peripheral region unit 202) outside the central region unit 201 in the plane direction of the IGBT semiconductor chip 101 has a structure without the seventh semiconductor layer 307 compared with the central region unit 201. The effect is that the cut-off tolerance at the time of shutdown is improved. The principle is described as follows.

[0073] Figure 5 This is an example of the turn-off waveform of an IGBT semiconductor chip. When the gate voltage becomes below the threshold voltage during the turn-off of the IGBT semiconductor chip, the active electron injection from the trench gate disappears, so the path of the hole current becomes unstable (easy to move). At this time, due to deviations in the size and shape of the trench, it is inevitable that a slightly stronger local electric field is generated. In such a location, the electron injection based on impact ionization becomes relatively more, so the hole current begins to concentrate.

[0074] Figure 8 The relationship between the impact ionization coefficient α and the electric field in the shutdown of the prior art and the present invention is shown. Impact ionization is very dependent on the electric field. Figure 3 In the case of the prior art shown, there is no Figure 2 The electric field concentration layer pn junction formed by the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307 as shown in the present embodiment has a lower electric field during the turn-off period t1 to t2, so the impact ionization coefficient changes greatly during t1 to t2.

[0075] That is, the number of carriers impact-ionized during shutdown is small. Figure 6As shown, even when the electric field is slightly uneven locally due to deviations in the size and shape of the trench, impact ionization will also vary, and due to current concentration and local heating, the parasitic thyristor (n + Source / p Base / n - Current flows through the substrate / p-type collector layer, causing latch-up that cannot be turned off, resulting in thermal destruction and reduced cutoff tolerance during shutdown.

[0076] The hole current from the chip terminal guard ring region 102 is also applied to the peripheral region cell 202 , so the current is further concentrated, which becomes a factor causing the shutdown withstand capability to decrease.

[0077] exist Figure 7 In the case of the conventional IGBT semiconductor chip shown, when the electric field concentration pn junction is formed by the sixth semiconductor layer (deep p+ layer) and the seventh semiconductor layer (deep n layer) in the IGBT cell, the electric field during the off period t1 to t2 is high, and the change in the impact ionization coefficient during t1 to t2 is small. Therefore, electron injection based on impact ionization is generated evenly between cells, and hole current flows evenly through the IGBT cell, suppressing current concentration. Therefore, the cut-off tolerance during the off period is improved.

[0078] However, the seventh semiconductor layer (deep n layer) becomes a blocking layer for holes, so it is difficult for hole current to pass through the unit having the seventh semiconductor layer (deep n layer), and the peripheral area unit 202 is added with the hole current from the chip terminal guard ring area 102, thereby causing current concentration, which becomes an obstacle to further improving the cut-off tolerance.

[0079] Therefore, in this embodiment, if Fig. 9 As shown, the central area unit 201 has the following effects: an electric field concentration pn junction is formed in the sixth semiconductor layer (deep p+ layer) and the seventh semiconductor layer (deep n layer), electron injection based on collision ionization is generated evenly between the units, the hole current is equalized, and the cut-off tolerance can be improved.

[0080] On the other hand, the peripheral area unit 202 is configured without the seventh semiconductor layer (deep n layer), so that the hole current added from the chip terminal guard ring area 102 can be efficiently extracted in the peripheral area unit 202, thereby having the effect of suppressing current concentration in the peripheral area unit 202.

[0081] Thus, an IGBT semiconductor chip having excellent shutdown resistance can be provided.

[0082] Example 2

[0083] Reference Fig.10 , a semiconductor device according to a second embodiment of the present invention is described. Fig.10is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is equivalent to that of Embodiment 1 ( Figure 2 ) is a variation of .

[0084] The structure of the central area unit 201 of this embodiment is similar to that of the embodiment 1 ( Figure 2 ) are the same, and repeated descriptions are omitted.

[0085] On the other hand, the peripheral area unit 202 of this embodiment is different from that of the embodiment 1 ( Figure 2 ) is that the third semiconductor layer (n+ source layer) 303 is not formed in the region between the emitter contact portion 203 and the gate insulating film 310. Therefore, in the region between the emitter contact portion 203 and the gate insulating film 310, the interlayer insulating film 302 is formed in contact with the surface of the fifth semiconductor layer (p base layer) 305.

[0086] In this embodiment, the structure of the central area unit 201 is the same as that of the embodiment 1 ( Fig. 9 ) are the same and can achieve the same effect.

[0087] On the other hand, compared with Example 1 ( Fig. 9 ), the peripheral region unit 202 has no third semiconductor layer (n+ source layer) 303, so there is no parasitic thyristor (n + Source / p Base / n - In addition to the effects of Embodiment 1, the structure of the substrate / p-type collector layer can prevent latch-up. Thus, an IGBT semiconductor chip having excellent turn-off tolerance can be provided.

[0088] Example 3

[0089] Reference Fig.11 , a semiconductor device according to a third embodiment of the present invention is described. Fig.11 is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is equivalent to that of Embodiment 2 ( Fig.10 ) is a variation of .

[0090] The structure of the central area unit 201 of this embodiment is similar to that of the embodiment 2 ( Fig.10 ) are the same, and repeated descriptions are omitted.

[0091] On the other hand, compared with Example 2 ( Fig.10 ) of the peripheral area unit 202, the peripheral area unit 202 of this embodiment is different from the peripheral area unit 202 of the embodiment 2 ( Fig.10 ) is that a seventh semiconductor layer (deep n layer) 307 of the second conductivity type is formed, and the seventh semiconductor layer 307 is formed to be in contact with the side surface of the collector 313 of the sixth semiconductor layer (deep p+ layer) 306 and has an impurity concentration higher than that of the semiconductor substrate 308.

[0092] In this embodiment, both the central area unit 201 and the peripheral area unit 202 form an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on collision ionization is evenly generated between the units, which has the effect of equalizing the hole current and improving the cut-off tolerance.

[0093] On the other hand, the peripheral area unit 202 is different from the embodiment 2 ( Fig.10 ) Similarly, since there is no third semiconductor layer (n+ source layer) 303, there is no parasitic thyristor (n + Source / p Base / n - Substrate / p-type collector layer) structure can prevent latch-up.

[0094] In addition, since the peripheral region unit 202 does not have the third semiconductor layer (n+ source layer) 303, there is no electron injection when turned on, and the amount of holes is reduced compared to the central region unit 201. Therefore, the hole density is also low when turned off, which can prevent current concentration and latch-up. As a result, an IGBT semiconductor chip with excellent cut-off tolerance can be provided.

[0095] Example 4

[0096] Reference Fig.12 , a semiconductor device according to a fourth embodiment of the present invention is described. Fig.12 is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is equivalent to that of Embodiment 2 ( Fig.10 ) is a variation of .

[0097] The structures of the central area unit 201 and the peripheral area unit 202 of this embodiment are similar to those of the embodiment 2 ( Fig.10 ) are the same, and repeated descriptions are omitted.

[0098] On the other hand, in this embodiment, the intermediate region unit 1201 is arranged at the intermediate position in the plane direction between the central region unit 201 and the peripheral region unit 202 of the IGBT semiconductor chip 101, which is different from the embodiment 2 ( Fig.10 ) has a different structure.

[0099] The structure of the middle area unit 1201 of this embodiment is similar to that of the embodiment 3 ( Fig.11 ) has the same structure as the peripheral region unit 202. Therefore, in the middle region unit 1201, a seventh semiconductor layer (deep n layer) 307 of the second conductivity type is formed, and the seventh semiconductor layer 307 is formed to be in contact with the collector electrode 313 side surface of the sixth semiconductor layer (deep p+ layer) 306 and has an impurity concentration higher than that of the semiconductor substrate 308.

[0100] In addition, the third semiconductor layer (n + source layer) 303 is not formed in the region between the emitter contact portion 203 and the gate insulating film 310 .

[0101] In this embodiment, the central area unit 201 and the middle area unit 1201 both form an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and generate electron injection based on collision ionization evenly between the units, which has the effect of equalizing the hole current and improving the cut-off tolerance.

[0102] In particular, since there is no third semiconductor layer (n+ source layer) 303 in the middle region unit 1201, there is no parasitic thyristor (n + Source / p Base / n - The structure of substrate / p-type collector layer) extracts impact-ionized carriers, thereby alleviating the difference in carrier density generated between the central region unit 201 and the peripheral region unit 202, thereby suppressing local current concentration.

[0103] In addition, the outer peripheral region unit 202 has a structure capable of efficiently extracting hole current added from the chip terminal guard ring region 102 by removing the seventh semiconductor layer (deep n layer) 307 , which has the effect of suppressing current concentration in the outer peripheral region unit 202 .

[0104] In addition, the middle region unit 1201 and the peripheral region unit 202 do not have the third semiconductor layer (n+ source layer) 303, and therefore do not have a parasitic thyristor (n + Source / p Base / n - The invention relates to a semiconductor chip having a substrate / p-type collector layer, which can prevent latch-up. Thus, an IGBT semiconductor chip having excellent turn-off tolerance can be provided.

[0105] Example 5

[0106] Reference Fig.13 , a semiconductor device according to a fifth embodiment of the present invention is described. Fig.13 is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is equivalent to Embodiment 4 ( Fig.12 ) is a variation of .

[0107] The basic structure of the IGBT semiconductor chip of this embodiment is similar to that of the embodiment 4 ( Fig.12 ) are the same, and repeated descriptions are omitted.

[0108] In Example 4 ( Fig.12), in the entire regions of the central region unit 201, the peripheral region unit 202, and the intermediate region unit 1201, the gate electrode is formed with a trench structure (the trench gate 204 and the gate insulating film 310), whereas in the present embodiment ( Fig.13 ), in the entire region of the central region unit 201, the peripheral region unit 202, and the intermediate region unit 1201, a side gate structure (side gate 1301, Poly-Si field plate 1302, gate insulating film 310) is formed, which is different from Example 4 ( Fig.12 ) has a different structure.

[0109] like Fig.13 As shown, the gate electrode of this embodiment is composed of: a groove, which is formed between the emitter electrode 301 and the semiconductor substrate 308; a gate electrode (side gate 1301), which is formed on the inner side of the groove and insulated from the emitter electrode 301 via an insulating layer (interlayer insulating film 302); a Poly-Si field plate 1302, which is formed on the inner side of the groove and connected to the emitter electrode 301 via an emitter contact portion 203.

[0110] In this embodiment, the IGBT unit is formed by a side gate structure, has a small feedback capacitance, and can achieve high switching and low loss.

[0111] In addition, the effects of the electric field concentration pn junction formed in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307 in the central region unit 201 and the intermediate region unit 1201, the effects of the absence of the seventh semiconductor layer (deep n layer) 307 in the peripheral region unit 202, and the effects of the absence of the third semiconductor layer (n+ source layer) 303 in the intermediate region unit 1201 and the peripheral region unit 202 are similar to those in Example 4 ( Fig.12 )same.

[0112] The side gate structure of this embodiment includes Embodiments 6 to 10 described later and can be similarly applied to all the embodiments.

[0113] Example 6

[0114] Reference Fig.14 and Fig.15 , a semiconductor device according to a sixth embodiment of the present invention is described. Fig.14 The cell terminal region ( Figure 1A A top view of the IGBT is shown in FIG. 105 . The trench gate of the unit part of the IGBT is configured in a stripe shape. Fig.15 FIG. 1 is a bird's-eye view of the IGBT semiconductor chip of this embodiment.

[0115] In this embodiment, if Fig.14As shown, the stripe-shaped trench gates 204 are arranged in the y direction to form the peripheral region unit 202. The central region unit 201 is the same as that in the embodiment 1 ( Figure 2 ) and Example 5 ( Fig.13 )Same structure.

[0116] The peripheral region unit 202 is formed similarly to that in Example 1 ( Figure 2 ) and Example 2 ( Fig.10 ) The same structure. Even when the IGBT cells are arranged in stripes, such as Fig.15 As shown, since the central area unit 201 and the peripheral area unit 202 are configured in the depth direction of the groove, an electric field concentration pn junction is formed in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on collision ionization is generated evenly between the units, which has the effect of equalizing the hole current and improving the cut-off tolerance.

[0117] In addition, the outer peripheral region unit 202 has a structure capable of efficiently extracting hole current added from the chip terminal guard ring region 102 by removing the seventh semiconductor layer (deep n layer) 307 , which has the effect of suppressing current concentration in the outer peripheral region unit 202 .

[0118] In addition, the peripheral region unit 202 has no third semiconductor layer (n+ source layer) 303, and thus has no parasitic thyristor (n+ source / p base / n- substrate / p type collector layer), which can prevent latch-up. Thus, an IGBT semiconductor chip with excellent turn-off tolerance can be provided.

[0119] Example 7

[0120] Reference Fig.16 , a semiconductor device according to a seventh embodiment of the present invention is described. Fig.16 is a bird's-eye view of the IGBT semiconductor chip of this embodiment, which is equivalent to Embodiment 6 ( Fig.15 ) is a variation of the above. The trench gate of the cell part of the IGBT is configured in a stripe shape.

[0121] In this embodiment, if Fig.16 As shown, in the groove depth direction, the structure is the same as that of Example 3 ( Fig.11 ) The same peripheral region unit 202. Even when the IGBT units are arranged in a stripe shape, the central region unit 201 and the peripheral region unit 202 form an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on impact ionization is generated evenly between the units, which has the effect of equalizing the hole current and improving the cutoff tolerance.

[0122] On the other hand, the peripheral area unit 202 is different from the embodiment 3 ( Fig.11 ) Similarly, since there is no third semiconductor layer (n+ source layer) 303, there is no parasitic thyristor (n+ source / p base / n- substrate / p-type collector layer) structure, which can prevent latch-up.

[0123] In addition, since the peripheral region unit 202 does not have the third semiconductor layer (n+ source layer) 303, there is no electron injection when turned on, and the amount of holes is reduced compared to the central region unit 201. Therefore, the hole density is also low when turned off, which can prevent current concentration and latch-up. As a result, an IGBT semiconductor chip with excellent cut-off tolerance can be provided.

[0124] Example 8

[0125] Reference Fig.17 , a semiconductor device according to an eighth embodiment of the present invention is described. Fig.17 is a bird's-eye view of the IGBT semiconductor chip of this embodiment, which is equivalent to Embodiment 7 ( Fig.16 ) is a modified example. The trench gate of the unit part of the IGBT is configured in a stripe shape.

[0126] Even when the IGBT cells are arranged in stripes, the same as in Example 4 ( Fig.12 ) Similarly, in the depth direction, the central area unit 201 and the middle area unit 1201 both form an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on collision ionization is evenly generated between the units, which has the effect of equalizing the hole current and improving the cut-off tolerance.

[0127] In particular, since there is no third semiconductor layer (n+ source layer) 303 in the middle region unit 1201, there is no parasitic thyristor (n + Source / p Base / n - The structure of substrate / p-type collector layer extracts carriers generated by impact ionization, thereby alleviating the difference in carrier density generated between the central region unit 201 and the peripheral region unit 202 and suppressing local current concentration.

[0128] In addition, the outer peripheral region unit 202 has a structure capable of efficiently extracting hole current added from the chip terminal guard ring region 102 by removing the seventh semiconductor layer (deep n layer) 307 , which has the effect of suppressing current concentration in the outer peripheral region unit 202 .

[0129] In addition, the middle region unit 1201 and the peripheral region unit 202 do not have the third semiconductor layer (n+ source layer) 303, and therefore do not have a parasitic thyristor (n + Source / p Base / n- The invention relates to a semiconductor chip having a substrate / p-type collector layer, which can prevent latch-up. Thus, an IGBT semiconductor chip having excellent turn-off tolerance can be provided.

[0130] Example 9

[0131] Reference Fig.18 and Fig.19 , a semiconductor device according to a ninth embodiment of the present invention is described. Fig.18 The cell terminal region ( Figure 1A A top view of the IGBT is shown in FIG. 105 . The trench gate of the unit part of the IGBT is configured in a stripe shape. Fig.19 FIG. 1 is a bird's-eye view of the IGBT semiconductor chip of this embodiment.

[0132] In the stripe-shaped configuration of the IGBT, a central region unit 201 and a peripheral region unit 202 are also configured in the y direction and the x direction. In the central region unit 201, an electric field concentration pn junction is formed in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on collision ionization is generated evenly between the units, which has the effect of equalizing the hole current and improving the cut-off tolerance.

[0133] On the other hand, in the peripheral area unit 202, by removing the seventh semiconductor layer (deep n layer) 307, a structure is formed that can efficiently extract the hole current added from the chip terminal guard ring area 102, which has the effect of suppressing current concentration in the peripheral area unit 202.

[0134] In addition, the peripheral region unit 202 has no third semiconductor layer (n+ source layer) 303, and thus has no parasitic thyristor (n+ source / p base / n- substrate / p type collector layer), which can prevent latch-up. Thus, an IGBT semiconductor chip with excellent turn-off tolerance can be provided.

[0135] Example 10

[0136] Reference Fig. 20 , an example of an embodiment in which the semiconductor device of the present invention is applied to a power conversion device is described. Fig. 20 1 is a circuit block diagram showing a power conversion device 600 using the semiconductor devices of Embodiments 1 to 9 of the present invention as constituent elements. Fig. 20 The circuit configuration of the power conversion device 600 according to the present embodiment and the connection relationship between a DC power supply and a three-phase AC motor (AC load) are shown.

[0137] In the power conversion device 600 of the present embodiment, the semiconductor devices of Embodiments 1 to 9 are used as power switching elements 601 to 606. The power switching elements 601 to 606 are, for example, IGBTs.

[0138] like Fig. 20 As shown, the power conversion device 600 of this embodiment includes a pair of DC terminals, namely, a P terminal 631 and an N terminal 632, and AC terminals, namely, a U terminal 633, a V terminal 634, and a W terminal 635, which are the same number as the number of phases of the AC output.

[0139] The switching bridge arm is composed of a pair of power switching elements 601 and 602 connected in series, and a U terminal 633 connected to the series connection point is used as an output. In addition, the switching bridge arm is composed of a pair of power switching elements 603 and 604 of the same structure connected in series, and a V terminal 634 connected to the series connection point is used as an output. In addition, the switching bridge arm is composed of a pair of power switching elements 605 and 606 of the same structure connected in series, and a W terminal 635 connected to the series connection point is used as an output.

[0140] The three-phase switch bridge arms composed of the power switch elements 601 to 606 are connected between the DC terminals of the P terminal 631 and the N terminal 632, and DC power is supplied from a DC power supply not shown. The three-phase AC terminals of the power conversion device 600, namely the U terminal 633, the V terminal 634, and the W terminal 635, are connected to a three-phase AC motor not shown as a three-phase AC power supply.

[0141] Diodes 621 to 626 are connected in antiparallel to the power switching elements 601 to 606 , respectively. Gate drive circuits 611 to 616 are connected to gate input terminals of the power switching elements 601 to 606 , which are formed of IGBTs, and are driven and controlled by the gate drive circuits 611 to 616 .

[0142] That is, the power conversion device 600 of the present embodiment is a power conversion device that inputs DC power from the outside and converts the input DC power into AC power for output, and has the following structure: a pair of DC terminals 631, 632 for inputting DC power, and AC terminals 633 to 635 for outputting AC power, the number of which is the same as the number of AC phases involved in the AC power, and for each of the AC terminals 633 to 635 for the number of phases, between one terminal (P terminal 631) of the pair of DC terminals 631, 632 and the other terminal (N terminal 632), a connection is made. A series circuit (for example, a series circuit of a parallel circuit of power switching element 601 and diode 621 and a parallel circuit of power switching element 602 and diode 622) is formed by connecting two parallel circuits (for example, a parallel circuit of power switching element 601 and diode 621) in series, in which a switching element (for example, power switching element 601) and a diode of opposite polarity to the switching element (for example, diode 621) are connected in parallel, and the interconnection point of the two parallel circuits constituting the series circuit is connected to an AC terminal (for example, U terminal 633) corresponding to a phase (for example, U phase) of the series circuit.

[0143] According to the IGBT semiconductor chip 101 described in each of the first to ninth embodiments, local electric field concentration caused by electric field variations between IGBT cells due to shape variations and impurity variations during manufacturing and current concentration at the chip terminal can be suppressed, thereby improving the shutdown withstand capability.

[0144] Therefore, the IGBT semiconductor chip 101 of each of Examples 1 to 9 can realize a higher current density of the IGBT chip, and can realize a smaller power conversion device equipped with the IGBT chip.

[0145] In addition, the present invention is not limited to the above-mentioned embodiments, and includes various modifications. For example, the above-mentioned embodiments are embodiments described in detail in order to explain the present invention in an easy-to-understand manner, and are not limited to all the structures described. A part of the structure of a certain embodiment can be replaced with the structure of other embodiments, and the structure of other embodiments can be added to the structure of a certain embodiment. In addition, for a part of the structure of each embodiment, other structures can also be added, deleted, or replaced.

[0146] Description of Reference Numerals

[0147] 101…IGBT semiconductor chip, 102…chip terminal guard ring region, 103…cell region, 104…gate electrode PAD, 105…cell terminal region, 201…central region cell, 202…peripheral region cell, 203…emitter contact portion, 204…trench gate, 301…emitter electrode, 302…interlayer insulating film, 303…third semiconductor layer (n+ source layer), 304…fourth semiconductor layer (shallow p+ layer), 305…fifth semiconductor layer (p base layer), 306…sixth semiconductor layer (deep p+ layer), 307…seventh semiconductor layer (deep n layer), 308… 8…semiconductor substrate (n-semiconductor substrate), 310…gate insulating film, 311…second semiconductor layer (n-type buffer layer), 312…first semiconductor layer (p-type collector layer), 313…collector, 501…groove, 502…contact hole, 503…resist, 600…power conversion device, 601~606…power switching element, 621~626…diode, 611~616…gate driving circuit, 631, 632…DC terminal, 633~635…AC terminal, 1201…intermediate region unit, 1301…side gate, 1302…Poly-Si field plate.

Claims

1. A semiconductor device, characterized in that: have: an emitter electrode formed on the surface of the semiconductor substrate via an interlayer insulating film; a collector electrode formed on the back side of the semiconductor substrate; A first semiconductor layer of a first conductivity type, which is in contact with the collector and formed on the back side of the semiconductor substrate; A second semiconductor layer of a second conductivity type, formed on an inner side than the first semiconductor layer; a central region unit, which is arranged along the surface of the semiconductor substrate; The peripheral region unit is located outside the central region unit in the plane direction of the semiconductor substrate and is arranged between the central region unit and the chip terminal guard ring region. The central area unit comprises: a trench formed between the emitter electrode and the semiconductor substrate; a gate electrode formed inside the trench via a gate insulating film and insulated from the emitter electrode via the interlayer insulating film; a third semiconductor layer of the second conductivity type, formed to be in contact with the gate insulating film and having an impurity concentration higher than that of the semiconductor substrate; a fourth semiconductor layer of the first conductivity type, formed to be in contact with the semiconductor substrate side of the emitter electrode via an emitter contact portion, and having an impurity concentration higher than that of the first semiconductor layer; a fifth semiconductor layer of the first conductivity type, which is in contact with the gate insulating film and is formed on the semiconductor substrate side of the third semiconductor layer and has a lower impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the first conductivity type, which is in contact with a surface of the fourth semiconductor layer on the semiconductor substrate side and is formed to protrude from the fifth semiconductor layer toward the semiconductor substrate side, and has a lower carrier concentration than the fourth semiconductor layer; a seventh semiconductor layer of the second conductivity type, which is formed to be in contact with the collector-side surface of the sixth semiconductor layer and has an impurity concentration higher than that of the semiconductor substrate, The peripheral region unit includes the trench, the gate electrode, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and does not include at least one of the third semiconductor layer and the seventh semiconductor layer.

2. The semiconductor device according to claim 1, wherein: The peripheral region unit includes a third semiconductor layer of the second conductivity type, which is formed to be in contact with the gate insulating film and has an impurity concentration higher than that of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein: The peripheral region unit includes a seventh semiconductor layer of the second conductivity type, which is formed to be in contact with the collector-side surface of the sixth semiconductor layer and has an impurity concentration higher than that of the semiconductor substrate and lower than that of the second semiconductor layer.

4. The semiconductor device according to claim 1, wherein: In the plane direction of the semiconductor substrate, an intermediate region unit is provided between the central region unit and the peripheral region unit. The middle region unit has the trench, the gate electrode, the fourth semiconductor layer, the fifth semiconductor layer, the sixth semiconductor layer, and the seventh semiconductor layer, but does not have the third semiconductor layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The gate electrode is a trench gate electrode formed inside the trench along the shape of the trench.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that: The gate electrode is a side gate electrode having a sidewall shape formed along the sidewall of the trench inside the trench. The semiconductor device further includes a Poly-Si field plate connected to the emitter electrode via an emitter contact portion inside the trench.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that: The gate electrodes are arranged in a stripe shape in a planar direction of the semiconductor substrate.

8. A power conversion device comprising: A pair of DC terminals; The same number of AC terminals as the number of AC phases; A switch bridge arm is connected between the pair of DC terminals and connects in series two parallel circuits of diodes having opposite polarities to the switching element. The interconnection points of the parallel circuits constitute the same number of power conversion units as the number of AC phases connected to different AC terminals, characterized in that: The switching element is the semiconductor device according to any one of claims 1 to 7.

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