A memory application method, device and computing equipment using memory bandwidth

Abstract

The application discloses a memory application method, device and computing equipment using memory bandwidth. The method comprises the following steps: in a multi-memory node system of NUMA architecture, when the size of memory data to be used by a user state program is greater than or equal to a preset threshold, the memory data to be used by the user state program is divided into a plurality of data blocks supporting parallel processing; one or more target memory nodes are determined based on at least the distance of a memory node corresponding to the memory data to be used by the user state program; one or more data blocks are reserved in the memory node corresponding to the user state program, and the remaining data blocks are allocated to the one or more target memory nodes. The application also discloses corresponding device and computing equipment.

Description

Technical Field

[0001] This invention relates to the field of process scheduling technology, and in particular to a memory application method, apparatus and computing device that utilizes memory bandwidth. Background Technology

[0002] In scenarios with limited memory bandwidth, single-process operations on large amounts of data are constrained by memory access speed, resulting in poor performance. On NUMA (Non-Uniform Memory Access) architecture servers, a NUMA system node (NODE) ​​consists of a set of CPUs and local memory. Each NODE has its own local memory, and the latency of accessing local memory is lower than accessing the remote memory of other NODEs. Therefore, on Linux systems, processes tend to request memory on their local NODEs. While accessing local data is faster, when large amounts of data access are required (such as operations on large arrays), the memory bandwidth on the same NODE can actually limit performance.

[0003] like Figure 1 As shown, in a multi-node system, processes allocate memory based on proximity. Therefore, when a process runs on the CPU corresponding to node 0, the large array memory it allocates will also be on node 0. If array copying is performed, the main operation is memory access on node 0. In this case, computational performance is affected by memory bandwidth; higher bandwidth results in better performance. On some server devices with limited bandwidth, performance is poor and computation time is long. Summary of the Invention

[0004] Therefore, the present invention provides a memory application method, apparatus and computing device that utilize memory bandwidth, in an attempt to solve or at least alleviate at least one of the problems mentioned above.

[0005] According to one aspect of the present invention, a memory application method utilizing memory bandwidth is provided, comprising the steps of: in a NUMA architecture multi-memory node system, when the size of memory data to be used by a user-mode program is greater than or equal to a preset threshold, dividing the memory data to be used by the user-mode program into multiple data blocks supporting parallel processing; determining one or more target memory nodes based at least on the distance to the memory node corresponding to the memory data to be used by the user-mode program; retaining one or more data blocks on the memory node corresponding to the user-mode program, and allocating the remaining data blocks to the one or more target memory nodes.

[0006] Optionally, in the application method according to the present invention, the step of dividing the memory data to be used by the user-mode program into multiple data blocks that support parallel processing includes: dividing the memory data to be used by the user-mode program into multiple data blocks that support parallel processing according to array names or pointer names.

[0007] Optionally, in the application method according to the present application, the step of determining one or more target memory nodes based on at least the distance of the memory node corresponding to the memory data to be used by the user-mode program comprises: determining, among all the memory nodes, the memory nodes with a distance less than or equal to a distance threshold to the memory node corresponding to the user-mode program as candidate nodes, and determining the target memory nodes corresponding to the number of divided data blocks from the candidate nodes.

[0008] Optionally, in the application method according to the present application, the step of determining the target memory nodes corresponding to the number of divided data blocks from the candidate nodes comprises: determining one or more of the candidate nodes with a memory capacity greater than or equal to a preset capacity threshold as the target memory nodes.

[0009] Optionally, in the application method according to the present application, the step of reserving one or more data blocks in the memory node corresponding to the user-mode program comprises: reserving one or more data blocks first used and / or to be used by the user-mode program in the memory node where the memory data is located; or reserving one or more data blocks first saved in the memory data to be used by the user-mode program in the memory node corresponding to the user-mode program.

[0010] According to another aspect of the present application, there is also provided a memory application device utilizing memory bandwidth, comprising: a division module adapted to divide, in a multi-memory node system of NUMA architecture, memory data to be used by a user-mode program into a plurality of data blocks supporting parallel processing when the size of the memory data to be used by the user-mode program is greater than or equal to a preset threshold; a selection module adapted to determine one or more target memory nodes based on at least the distance of the memory node corresponding to the memory data to be used by the user-mode program; and an allocation module adapted to reserve one or more data blocks in the memory node corresponding to the user-mode program and allocate the remaining data blocks to the one or more target memory nodes.

[0011] Optionally, in the application device according to the present application, the division module is adapted to divide the memory data to be used by the user-mode program into a plurality of data blocks supporting parallel processing according to array names or pointer names.

[0012] Optionally, in the application device according to the present application, the selection module is adapted to determine, among all the memory nodes, the memory nodes with a distance less than or equal to a distance threshold to the memory node corresponding to the user-mode program as candidate nodes, and determine the target memory nodes corresponding to the number of divided data blocks from the candidate nodes.

[0013] According to another aspect of the present application, there is also provided a computing device comprising at least one processor and a memory having stored thereon program instructions; the program instructions, when read and executed by the processor, causing the computing device to perform the memory application method utilizing memory bandwidth as above.

[0014] According to still another aspect of the present application, there is also provided a readable storage medium having stored thereon program instructions, the program instructions, when read and executed by a computing device, causing the computing device to perform the memory application method utilizing memory bandwidth as above.

[0015] The memory application method utilizing memory bandwidth, the apparatus and the computing device according to the present application can achieve the following beneficial effects:

[0016] In the big data operation scenario, the present application can significantly improve the performance of the big data operation by allocating the memory to the memory of the adjacent nodes and fully utilizing the memory bandwidth of the plurality of nodes. BRIEF DESCRIPTION OF DRAWINGS

[0017] To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings. These aspects are indicative of various ways in which the principles disclosed herein can be practiced and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of one or more aspects and as illustrated in the accompanying drawings. The same reference numbers in different drawings identify the same components or elements.

[0018] Figure 1 A structural diagram of a NUMA architecture according to one embodiment of the present application is shown;

[0019] Figure 2 A diagram of a computing device 200 according to one embodiment of the present application is shown;

[0020] Figure 3 A flowchart of a memory application method utilizing memory bandwidth 300 according to one embodiment of the present application is shown;

[0021] Figure 4 A flowchart of a memory application method of a large array copy operation according to one embodiment of the present application is shown;

[0022] Figure 5 A flowchart of a memory application method of a large array copy operation according to one embodiment of the present application is shown;

[0023] Figure 6 A structural diagram of a memory application apparatus 600 utilizing memory bandwidth according to one embodiment of the present application is shown;

[0024] Figure 7 is a schematic structural block diagram of a first computer readable storage medium according to an embodiment of the present application;

[0025] Figure 8 is a schematic structural block diagram of a second computer readable storage medium according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0027] Figure 1 is a schematic diagram of the framework of the NUMA architecture of the embodiments of the present application; it is assumed that a process runs on CPU 0, for example, the process performs an array copy operation, when the process is executed, the array is first initialized, at this time, there is memory data allocated on the memory 0 closest to the NODE 0 in the array, then the array copy operation is performed, at this time, the main operation is the memory 0 access on the NODE 0, since the memory bandwidth is limited, the performance is not optimal at this time.

[0028] As shown in Figure 1 , since the user state program is running on a certain CPU, at this time, in the case where the local memory is sufficient, the memory corresponding to the current NODE is used, the present application considers from the perspective of fully utilizing the multi-NODE memory. In the common large data operation scene (such as large array copy), the data memory is allocated to multiple NODEs in a manner to optimize, so as to achieve the effect of memory parallel access.

[0029] The memory application method using memory bandwidth of the present application is executed in a computing device. The computing device can be any device with storage and computing capabilities, which can be implemented as a server, a workstation, etc., can also be implemented as a desktop computer, a notebook computer, etc. personal computer, or a terminal device such as a mobile phone, a tablet computer, a smart wearable device, an Internet of Things device, but is not limited thereto.

[0030] Figure 2 shows a schematic diagram of a computing device 200 according to an embodiment of the present application. It should be noted that, Figure 2 the computing device 200 shown is only an example, in practice, the computing device used to implement the memory application method using memory bandwidth of the present application can be any model of device, and its hardware configuration can be the same as that of the computing device 200 shown in Figure 2 , or can be different from that of the computing device 200 shown in Figure 2The computing device 200 shown is different. In practice, the computing device used to implement the memory application method utilizing memory bandwidth of the present invention can... Figure 2 The hardware components of the computing device 200 shown can be added or removed. This invention does not limit the specific hardware configuration of the computing device.

[0031] like Figure 2 As shown, in the basic configuration 202, the computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 can be used for communication between the processors 204 and the system memory 206.

[0032] Depending on the desired configuration, processor 204 can be any type of processor, including but not limited to: microprocessor (UP), microcontroller (UC), digital information processor (DSP), or any combination thereof. Processor 204 may include one or more levels of cache such as L1 cache 210 and L2 cache 212, processor core 214, and registers 216. Example processor core 214 may include an arithmetic logic unit (ALU), floating-point unit (FPU), digital signal processing core (DSP core), or any combination thereof. Example memory controller 218 may be used with processor 204, or in some implementations, memory controller 218 may be an internal part of processor 204.

[0033] Depending on the desired configuration, system memory 206 can be any type of memory, including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. System memory 206 may include operating system 220, one or more applications 222, and program data 224. Application 222 is actually a set of program instructions that instruct processor 204 to perform corresponding operations. In some embodiments, application 222 may be arranged to cause processor 204 to operate using program data 224 on the operating system.

[0034] The computing device 200 may also include a storage interface bus 234. The storage interface bus 234 enables communication from storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to the basic configuration 202 via the bus / interface controller 230. At least a portion of the operating system 220, applications 222, and data 224 may be stored on the removable storage 236 and / or the non-removable storage 238, and loaded into system memory 206 via the storage interface bus 234 when the computing device 200 is powered on or when the application 222 is to be executed, and executed by one or more processors 204.

[0035] The computing device 200 can also include an interface bus 240 for facilitating communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus / interface controller 230. Example output devices 242 include a graphics processing unit 248 and an audio processing unit 250, which can be configured to facilitate communication to various external devices such as a display or speakers via one or more A / V ports 252. Example peripheral interfaces 244 include a serial interface controller 254 or a parallel interface controller 256, which can be configured to facilitate communication to various external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripheral devices (e.g., printer, scanner) via one or more I / O ports 258. An example

[0036] Network communication links can be one example of communication media. Communication media can typically be embodied by computer readable instructions, data structures, program modules, and other data in a modulated data signal, such as a carrier wave or other transport mechanism, and can include any information delivery media. "Modulated data signal" can be a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media can include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), microwave, infrared (IR) and other wireless media. The term computer readable media as used herein can include both storage media and communication media.

[0037] In the computing device 200 according to the present application, the application 222 includes a plurality of program instructions for performing the memory application method with memory bandwidth 300, which can instruct the processor 204 to perform the memory application method with memory bandwidth 300 of the present application, so that the computing device 200 performs the memory application method with memory bandwidth 300 of the present application.

[0038] Figure 3 A flow chart of the memory application method with memory bandwidth 300 according to one embodiment of the present application is shown. The memory application method with memory bandwidth 300 is performed in a computing device (e.g., the aforementioned computing device 200), and the memory application method with memory bandwidth 300 of the present application is used to solve the performance loss problem of the aforementioned scheme due to the influence of memory bandwidth. As shown in the flow chart of the memory application method with memory bandwidth 300, the memory application method with memory bandwidth 300 of the present application includes the following steps. Figure 3As shown, the memory application method 300 using memory bandwidth can include steps S310 to S330.

[0039] In step S310, in a multi-memory node system of NUMA architecture, when the size of memory data to be used by a user state program is greater than or equal to a preset threshold, the memory data to be used by the user state program is divided into a plurality of data blocks supporting parallel processing.

[0040] The memory application method of the embodiment of the present application is for a user state program, not a kernel state program or a kernel state process. For a user state program, when writing program code, a variable needs to be allocated memory, and therefore the size of data accessed by the user state process (a user state program in running) is known. For example, an alloc (memory allocation) of a 1G memory block is used to store data, and at this time, the size of memory accessed by the user state process is known. When the memory data to be used by the user state program is divided into a plurality of data blocks supporting parallel processing, the main basis is the local memory bandwidth and the speed of cross-NODE access. When the parallel optimization effect is greater than the loss of cross-NODE access, the memory data can be divided into a plurality of data blocks supporting parallel processing and allocated on a plurality of NODEs in turn. The embodiment of the present application can divide the memory data to be used into M blocks, M being a positive integer greater than 1, and the number of division is determined according to the parallel optimization effect. In the case that the performance loss of cross-NODE access memory is not large, generally, 2-4 data blocks can be divided, that is, M=2, 3 or 4.

[0041] According to an implementation manner, the step of dividing the memory data to be used by the user state program into a plurality of data blocks supporting parallel processing in step S310 includes: dividing the memory data to be used by the user state program into a plurality of data blocks supporting parallel processing according to array names or pointer names.

[0042] The user state program capable of being optimized by parallel operation in the embodiment of the present application can be optimized by the memory division manner, that is, when CPU waits for memory operation data 1, data 2 on another block of memory can be operated first. For example, the read-write operation between a plurality of blocks of memory data. The embodiment of the present application is for the scene that the read-write speed is limited due to slow memory bandwidth. In this way, a plurality of blocks of memory data can be divided into a plurality of NODEs. Because after division, the corresponding memory needs to be initialized to the corresponding NODE, from the perspective of easy implementation, the read-write operation between a plurality of blocks of memory regions can be applied to the technical solution provided by the present application.

[0043] The embodiment of the present application divides the memory data blocks, and different data in the memory data has different variable storage in the code of the user mode program, such as array name and pointer name, so that the array name and the pointer name can be distinguished, for example, c array=a array+b array, at this time, the memory data can be divided into three data blocks of c, a and b, or the area allocated by malloc (dynamic memory allocation) also has a pointer pointing to the corresponding memory.

[0044] In step S320, one or more target memory nodes are determined based on at least the distance of the memory node corresponding to the memory data to be used by the user mode program.

[0045] According to an implementation, the step of determining one or more target memory nodes based on at least the distance of the memory node corresponding to the memory data to be used by the user mode program in step S320 includes: determining, among all the memory nodes, the memory nodes whose distance to the memory node corresponding to the user mode program is less than or equal to a distance threshold as candidate nodes, and determining the target memory nodes corresponding to the number of divided data blocks from the candidate nodes.

[0046] In the embodiment of the present application, the step of determining the target memory nodes corresponding to the number of divided data blocks from the candidate nodes includes: determining one or more of the candidate nodes whose memory capacity is greater than or equal to a preset capacity threshold as the target memory nodes.

[0047] In the embodiment of the present application, the principle of determining the target memory nodes is to have sufficient memory capacity, and when the target memory nodes are determined by the method of the present application, the factors of memory capacity and NODE distance are considered; the nearest NODE can be found in sequence, and the mechanism of selecting the memory node that meets the capacity requirement is not only to find the memory node with the maximum capacity (among all the nodes), but also to select the memory node that is nearest to the memory node corresponding to the user mode program and has the most appropriate capacity, so that the performance of the NODE reaches the best state when multiple data blocks are processed in parallel.

[0048] The candidate nodes can include all the nodes, or a few nodes, for example, the nodes whose distance to the memory data to be used by the user mode program is less than or equal to a distance threshold, or only one node, for example, the node adjacent to the node corresponding to the memory data to be used by the user mode program, when the node corresponding to the memory data to be used by the user mode program is an edge node, the number of adjacent nodes is one, and when the node corresponding to the memory data to be used by the user mode program is not an edge node, the number of adjacent nodes is two.

[0049] The method of the application considers distance and capacity when selecting a target memory node (i.e. assigning a memory node to a running user mode program); if the user mode process runs on CPU 0 of NODE 0, memory is preferentially applied on memory 0, and then on memory 1 closest to NODE 0 (except memory 0), and the capacity is not required to be the largest memory node in all nodes, but a mechanism for selecting a memory node that meets the capacity requirement is selected, if the capacity of memory 1 does not meet the requirement, whether the capacity of memory 2 slightly farther away meets the capacity requirement, if the capacity of memory 2 slightly farther away does not meet the capacity requirement, then the remaining NODEs in the candidate node (the candidate node can include one node, can include multiple nodes, and can include all nodes) are sequentially traversed according to the distance order, until the memory node closest to the user mode program corresponding to the memory node is found and the capacity is most appropriate, so that the performance of multiple data blocks parallel processing reaches the best state.

[0050] If no memory node that meets the capacity requirement is found in all NODEs of the candidate node, or no memory node that meets the capacity requirement is found in the NODEs within a certain distance range, the remaining data blocks are allocated to the memory node closest to the memory node or the memory node with the largest capacity in the candidate node.

[0051] In the embodiment of the application, in order to avoid the performance loss caused by accessing the memory of a distant NODE, the range of the candidate node selected is the node whose distance to the memory node corresponding to the memory data to be used by the user mode program is less than or equal to the distance threshold, and the adjacent node is preferred. Then the target memory node corresponding to the number of divided data blocks is determined from the candidate node, for example, when the memory data to be used by the user mode program is divided into 2 data blocks, a target memory node needs to be found from the nodes (candidate nodes) that meet the distance requirement, at this time, the one with the largest memory capacity in the candidate node is determined as the target memory node, or the one closest to the target memory node that meets the capacity requirement is determined as the target memory node. For example, when the memory data to be used by the user mode program is divided into 4 data blocks, three target memory nodes need to be found from the nodes (candidate nodes) that meet the distance requirement, at this time, the three memories with the largest memory capacity in the candidate node can be determined as the target memory nodes, or the three memories closest to the target memory node that meet the capacity requirement can be determined as the target memory nodes.

[0052] In the detection process, the number N of the target memory nodes whose memory capacity is greater than or equal to the preset capacity threshold is possibly M-1, possibly less than M-1, or greater than M-1. When N=M-1, one data block can be reserved in the memory node corresponding to the user-mode program, and the remaining M-1 data blocks can be allocated to the N target memory nodes. In the embodiment of the present application, when the detected number N is greater than or equal to M-1, the M-1 memory nodes with the largest memory capacity can be selected, or the first M-1 memory nodes can be selected, that is, the capacity of all memory nodes in the candidate node is detected in a certain order, and after M-1 memory nodes meeting the requirements are detected, the capacity detection of the subsequent memory nodes is stopped, M-1 target memory nodes are obtained, or the capacity detection of all memory nodes in the candidate node is completed, and M-1 target memory nodes with the largest memory capacity are selected from all the memory nodes meeting the requirements. When the detected number N is less than M-1, the number of target memory nodes can be supplemented to M-1 according to the actual detected number of memory nodes meeting the capacity requirements, or the target memory nodes can be supplemented to M-1 according to the order from large to small of the memory capacity or the order from small to large of the distance between the nodes corresponding to the memory data to be used by the user-mode program. When the detected number N is less than M-1, one data block can be allocated to each target memory node, M-N data blocks can be reserved in the memory node where the memory data to be used by the user-mode program is located, or M data blocks can be as evenly as possible allocated to the nodes corresponding to the memory data to be used by the user-mode program and the target memory nodes.

[0053] When the number N of the memory nodes whose memory capacity is greater than or equal to the preset capacity threshold in the candidate node is greater than or equal to M-1, for the candidate node including all nodes, determining the target memory nodes includes: the M-1 memory nodes with the largest memory capacity in all nodes as the target memory nodes, N is a positive integer greater than or equal to 1, and M is the number of data blocks into which the memory data to be used by the user-mode program is divided. For the candidate node including a plurality of nodes whose distance from the node corresponding to the memory data to be used by the user-mode program is less than or equal to the distance threshold, determining the target memory nodes includes: the M-1 memory nodes with the largest memory capacity in the nodes whose distance from the node corresponding to the memory data to be used by the user-mode program is less than or equal to the distance threshold as the target memory nodes, N is a positive integer greater than or equal to 1, and M is the number of data blocks into which the memory data to be used by the user-mode program is divided. For the candidate node including one node adjacent to the node corresponding to the memory data to be used by the user-mode program in all nodes, determining the target memory nodes includes: determining the memory node corresponding to the adjacent node as the target memory node, and at this time, the memory data to be used by the user-mode program is divided into 2 data blocks supporting parallel processing, and M=2.

[0054] In step S330, one or more data blocks are kept in the memory node corresponding to the user-mode program, and the remaining data blocks are allocated to one or more target memory nodes.

[0055] In the embodiment of the present application, the step of keeping one or more data blocks in the memory node corresponding to the user-mode program in step S330 includes: keeping one or more data blocks first used and / or to be used by the user-mode program in the memory node where the memory data is stored; or keeping one or more data blocks first stored in the memory node where the memory data to be used by the user-mode program is stored in the memory node corresponding to the user-mode program.

[0056] In the embodiment of the present application, the data block allocation can be performed according to the order of use of the memory data to be used by the user-mode program, or according to the order of data storage. One or more data blocks first used and to be used by the user-mode program are kept in the memory node where the memory data is stored, and one or more data blocks used later are allocated to the target memory node. One or more data blocks first stored in the memory node where the memory data is stored are kept in the memory node where the memory data is stored, and one or more data blocks stored later are migrated to the target memory node.

[0057] In the embodiment of the present application, the data blocks are allocated to all target memory nodes as much as possible. There can be a case that one target memory node is allocated or corresponds to multiple data blocks. If the number N of target memory nodes is less than M-1, one data block can be allocated to each target memory node, and the remaining M-N data blocks are kept in the memory node where the memory data to be used by the user-mode program is stored. The M data blocks can be allocated as evenly as possible to the memory node where the memory data to be used by the user-mode program is stored and the target memory nodes. When the allocation is not even, the data blocks can be allocated or corresponded according to the principle that the closer the target memory node to the node corresponding to the memory data to be used by the user-mode program, the more data blocks the target memory node corresponds to, so that the distance between the node corresponding to the user-mode program and the target memory node is as small as possible after the data blocks are allocated or corresponded to the target memory nodes. The data blocks can also be allocated or corresponded according to the principle that the smaller the capacity of the target memory node, the more data blocks the target memory node corresponds to, so that the difference between the load of the memory node corresponding to the user-mode program and the load of the target memory node is as small as possible after the data blocks are allocated or corresponded to the target memory nodes, and load balancing is achieved as much as possible.

[0058] As Figure 4As shown, the embodiment of the present application takes a large array copy as an example to illustrate the process of memory application method which fully utilizes memory bandwidth when large data volume is calculated:

[0059] First, after the process is created, the process runs on the local NODE node (such as NODE 0 in Figure 1 ) and under the condition that the memory is sufficient, the process applies for the memory on NODE 0; when the array 1 memory is allocated on the local NODE, the array initialization is allocated on the current NODE by default.

[0060] Then, the array 2 memory is allocated on the adjacent NODE (such as NODE 1 in Figure 1 ), which can be realized by various ways, for example, setting the memory application strategy of the process or binding the core, and so on, so that the memory applied is on the adjacent NODE.

[0061] Finally, the array copy operation is performed, at this time, the memory on NODE 1 is read first, and then written to the corresponding memory on NODE 0, at this time, the memory on the two NODEs can be fully utilized, and the effect of memory parallelism is achieved.

[0062] The above is the optimization process of two array calculations, under the condition that the distance between NODEs allows, multiple array calculations can also be optimized in the same way, as shown in Figure 5 , for the operation between multiple arrays, the array memory is allocated on different adjacent NODEs respectively, so as to achieve the effect of memory access parallelism and improve the speed of array calculation.

[0063] For example, the array copy operation is performed, and the loop assignment is performed as follows:

[0064] for(i=0;i<10000;i++){a[i]=b[i]}

[0065] In the prior art, since the array memory of a and b is on the same NODE, under the condition that the memory bandwidth is limited, the assignment operation is basically serial at this time, and the performance is low.

[0066] The scheme of the embodiment of the present application is that the a and b array memory allocation is on different NODEs, and the flow is optimized from reading the b array, writing the a array, reading the b array, writing the a array to reading the b array, writing the a array (while reading the next element of the b array), and writing the a array (while reading the next element of the b array). It can be seen that theoretically, there is a performance improvement of nearly 50%. Since the process crosses the NODE to access the memory, there is a certain performance loss, so the multiple arrays need to be placed on the NODEs with a distance less than or equal to a preset distance threshold. However, even so, the performance improvement is obvious. In addition to improving performance, the embodiment of the present application can also be used to test the memory bandwidth bottleneck. When the scheme can achieve the optimization effect, it means that the memory bandwidth has become the performance bottleneck of large data operation.

[0067] As shown in Figure 6 The embodiment of the present application also provides a memory application device 600 using memory bandwidth, which comprises a division module 610, a selection module 620 and an allocation module 630.

[0068] The division module 610 is adapted to divide the memory data to be used by the user state program into a plurality of data blocks supporting parallel processing when the size of the memory data to be used by the user state program is greater than or equal to a preset threshold in a multi-memory node system of NUMA architecture. The selection module 620 is adapted to determine one or more target memory nodes based on at least the distance of the memory node corresponding to the memory data to be used by the user state program. The allocation module 630 is adapted to retain one or more data blocks in the memory node corresponding to the user state program and allocate the remaining data blocks to one or more target memory nodes.

[0069] In the embodiment of the present application, the division module 610 is adapted to divide the memory data to be used by the user state program into a plurality of data blocks supporting parallel processing by dividing the memory data to be used by the user state program into a plurality of data blocks supporting parallel processing according to the array name or pointer name.

[0070] In the embodiment of the present application, the selection module 620 is adapted to determine one or more target memory nodes based on at least the distance of the memory node corresponding to the memory data to be used by the user state program by determining the memory nodes with a distance less than or equal to the distance threshold from the memory node corresponding to the user state program as candidate nodes in all memory nodes, and determining the target memory nodes corresponding to the number of divided data blocks from the candidate nodes.

[0071] Specifically, the selection module 620 is adapted to determine one or more target memory nodes corresponding to the number of divided data blocks from the candidate nodes by determining one or more of the candidate nodes with a memory capacity greater than or equal to a preset capacity threshold as target memory nodes.

[0072] In the embodiment of the present application, the allocation module 630 retains one or more data blocks in the memory node corresponding to the user mode program, and the memory node is adapted to retain one or more data blocks first used by the user mode program and / or waiting to be used by the user mode program; or retain one or more data blocks of the memory data first saved by the user mode program in the memory node corresponding to the user mode program.

[0073] In the embodiment of the present application, the memory application method fully utilizing the memory bandwidth during large data volume operation can be realized through the following functions:

[0074] int sched_setaffinity(pid_t pid,size_t cpusetsize,cpu_set_t*mask);

[0075] The process with the specified pid is bound to the CPU corresponding to the mask. After the process affinity is set to the specified CPU, the memory allocated to the process is also allocated to the NODE where the CPU of the process is located by default, so that the purpose of setting the NODE where the memory of the process is located is achieved.

[0076] long set_mempolicy(int mode,const unsigned long*nmask,unsigned longmaxnode);

[0077] The memory allocation strategy is set. When mode is MPOL_BIND, nmask specifies the NODE where the memory of the current process is allocated, so that the purpose of limiting the NODE of the process memory is directly achieved.

[0078] Stream is a typical tool for testing memory performance, mainly for copying, calculating and other operations of multiple arrays. On a domestic Feiteng S2500128 core server, when a single process is started and the memory size occupied by each array is set to 500M, the array copying test results are as follows by using different schemes:

[0079] Original scheme This scheme Score 6500 M / S 9000 M / S

[0080] As shown in the above table, the scheme can significantly improve the performance of array operation.

[0081] Part of the example code involved in the scheme is as follows:

[0082]

[0083]

[0084] At this time, the a and c arrays are stored in memory on NODE 0 and NODE 1 respectively, and according to the above analysis, there is a parallel optimization effect, and the performance is improved.

[0085] The embodiments of the present application also provide a computing device, referring to Figure 7 The computing device comprises a memory 1120, a processor 1110, and a computer program stored in the memory 1120 and executable by the processor 1110, a space for program code 1130 stored in the memory 1120, and the computer program implements the method steps according to the present application when executed by the processor 1110.

[0086] The embodiments of the present application also provide a computer readable storage medium. Referring to Figure 8 The computer readable storage medium comprises a storage unit for program code, and the storage unit is provided with a program 1131' for executing the method steps according to the present application, and the program is executed by the processor.

[0087] The various techniques described herein can be implemented in connection with hardware or software, or combinations thereof. Thus, the methods and apparatus of the present application, or certain aspects or portions thereof, can take the form of program code (i.e., instructions) embodied in tangible media, such as removable hard disks, USB (universal serial bus) drives, floppy disks, CD-ROMs, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the application.

[0088] Where the program code is executed on a programmable computer, the computing device generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The storage medium is configured to store program code, which is executed by the processor for implementing this application's memory application method using memory bandwidth.

[0089] In a non-limiting example, the readable medium includes a readable storage medium and a communication medium. The readable storage medium stores information such as computer readable instructions, data structures, program modules or other data. The communication medium generally embodies computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and includes any information transmission medium. The combination of any of the above is also included in the scope of the readable medium.

[0090] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order to not obscure the understanding of this description.

[0091] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order to not obscure the understanding of this description.

[0092] Similarly, it is to be understood that the mechanical features of the application can be positioned in any of the devices, or in one or more devices, different from those described in the examples, as long as the mechanical features of the application are implemented. Similarly, it is to be understood that, in the description of the exemplary embodiments of the application above, the various features of the application are sometimes grouped together in a single embodiment, figure or description of the application for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the inventive aspects. However, the disclosure of these features of the application together should not be interpreted as reflecting a necessity of the application to more features than are explicitly recited in each of the claims.

[0093] Those skilled in the art will understand that the modules, or units, or components of the devices in the examples disclosed herein can be arranged in the devices as described in the examples, or alternatively can be located in one or more devices different from the devices in the examples. The modules in the foregoing examples can be combined into one module or further divided into multiple sub-modules.

[0094] Those skilled in the art will understand that the modules in the devices in the examples can be adaptively changed and disposed in one or more devices different from the examples. The modules or units or components in the examples can be combined into one module or unit or component, and further can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, all combinations of all features disclosed in this specification (including the accompanying claims, abstract and drawings) and all processes or units of any methods or apparatuses so disclosed can be used in combination with one another. Unless explicitly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) can be replaced by alternative features providing the same, equivalent or similar functionality.

[0095] Furthermore, to the extent that the terms "comprises", "comprising", "includes", "including" and "has" or any variation thereof are used in the following description and / or claims, such terms are intended to include a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0096] Furthermore, some of the embodiments described herein are of a "method" or a "process" that can be embodied in software, firmware or hardware, and / or a combination of both software and hardware. Furthermore, the embodiments described herein can be implemented by hardware, software, firmware or a combination of hardware and software and / or firmware. For example, the embodiments described herein can be implemented in hardware, software or a combination of software and firmware. In this description and in the following claims, the terms "comprise" and "include" and variations thereof mean "open-ended" and do not exclude additional, unrecited elements or method steps. The terms "a," "an" and "the" mean "one or more," unless expressly specified otherwise. The terms "comprise", "comprising", "include", "including" and "the comprising" when used in this description and in the following claims specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0097] As used herein, the terms "first", "second", "third", etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0098] While the application has been described in connection with limited number of embodiments, it will be evident that many variations in the application are possible, and that the application is not limited to what is described and / or claimed, but is intended to cover all changes and modifications of the application which fall within the scope of the application. Furthermore, it is to be noted that the language used in the specification has been chosen for readability and instructional purposes and can not have been chosen to convey 100% of the intended meaning.

Claims

1. A memory application method utilizing memory bandwidth, comprising the steps of: In a NUMA-based multi-memory node system, when the size of the memory data to be used by a user-mode program is greater than or equal to a preset threshold, the memory data to be used by the user-mode program is divided into multiple data blocks that support parallel processing. At least one or more target memory nodes are determined based on the distance to the memory node corresponding to the memory data to be used by the user-mode program; One or more data blocks are retained in the memory node corresponding to the user-mode program, and the remaining data blocks are allocated to the one or more target memory nodes; The step of determining one or more target memory nodes based at least on the distance to the memory node corresponding to the memory data to be used by the user-mode program includes: among all memory nodes, determining memory nodes whose distance to the memory node corresponding to the user-mode program is less than or equal to a distance threshold as candidate nodes, and determining target memory nodes from the candidate nodes corresponding to the number of data blocks to be divided; and the step of determining target memory nodes from the candidate nodes corresponding to the number of data blocks to be divided includes: among the candidate nodes, determining one or more of them whose memory capacity is greater than or equal to a preset capacity threshold as target memory nodes; The step of retaining one or more data blocks in the memory node corresponding to the user-mode program includes: retaining one or more data blocks that the user-mode program uses first and / or is waiting to use in the memory node where the memory data is located; or retaining one or more data blocks that are first stored in the memory data to be used by the user-mode program in the memory node corresponding to the user-mode program.

2. The application method as described in claim 1, wherein, The step of dividing the memory data to be used by the user-mode program into multiple data blocks that support parallel processing includes: The memory data to be used by the user-mode program is divided into multiple data blocks that support parallel processing according to array names or pointer names.

3. A memory application device utilizing memory bandwidth, comprising: The partitioning module is suitable for use in a NUMA architecture multi-memory node system, where, when the size of the memory data to be used by the user-mode program is greater than or equal to a preset threshold, the memory data to be used by the user-mode program is divided into multiple data blocks that support parallel processing. The selection module is adapted to determine one or more target memory nodes based at least on the distance to the memory node corresponding to the memory data to be used by the user-mode program; The allocation module is adapted to retain one or more data blocks in the memory node corresponding to the user-mode program, and to allocate the remaining data blocks to the one or more target memory nodes; The selection module is adapted to: among all memory nodes, determine memory nodes whose distance to the memory node corresponding to the user-mode program is less than or equal to a distance threshold as candidate nodes, and determine target memory nodes from the candidate nodes corresponding to the number of data blocks to be divided; and the selection module is adapted to determine target memory nodes from the candidate nodes corresponding to the number of data blocks to be divided as follows: among the candidate nodes, determine one or more of them whose memory capacity is greater than or equal to a preset capacity threshold as target memory nodes; The allocation module may retain one or more data blocks in the memory node corresponding to the user-mode program in the following ways: First, it may retain one or more data blocks that the user-mode program uses first and / or is waiting to use in the memory node where the memory data is located; or, it may retain one or more data blocks that are initially stored in the memory data to be used by the user-mode program in the memory node corresponding to the user-mode program.

4. The application device as described in claim 3, wherein, Modular division is suitable for: The memory data to be used by the user-mode program is divided into multiple data blocks that support parallel processing according to array names or pointer names.

5. A computing device, comprising: At least one processor and a memory storing program instructions; When the program instructions are read and executed by the processor, the computing device performs the memory application method utilizing memory bandwidth as described in claim 1 or 2.

6. A readable storage medium storing program instructions, which, when read and executed by a computing device, cause the computing device to perform the memory application method utilizing memory bandwidth as described in claim 1 or 2.

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