A method, device and medium for digital phase-locked loop locking

Abstract

The present application provides a method, device and medium for digital phase-locked loop locking, which relates to the field of phase-locked loops. In this method, the control voltage is used to control the phase of the OCXO clock so that the phase difference between the OCXO clock and the reference clock is maintained at the initial state. The adjustment method of the control voltage is as follows: obtain the adjacent two phase differences between the OCXO clock and the reference clock; determine the difference between the previous phase difference and the next phase difference; calculate the control voltage according to the positive or negative of the difference to reduce the difference between the adjacent two phase differences. The control voltage can change rapidly to achieve the rapid locking of the phase-locked loop and avoid the overshoot phenomenon. In addition, when acc_flag is 0, the increment of the integral term of the control voltage is zero, that is, when the control voltage is greater than the preset maximum voltage value, the integral term of the control voltage no longer accumulates positively, and when the control voltage is less than the preset minimum voltage value, the integral term of the control voltage no longer accumulates negatively, which can achieve anti-integral saturation.

Description

Technical Field

[0001] The present application relates to the field of phase-locked loops, and in particular, to a method, device, and medium for locking a digital phase-locked loop. Background Art

[0002] With the continuous development of integrated circuit technology, analog phase-locked loops have begun to evolve towards digital phase-locked loops, and thus a digital phase-locked loop implemented by software has emerged. This kind of phase-locked loop has strong scalability and can greatly shorten the development cycle and development cost. Currently, in order to achieve fast locking of the phase-locked loop, the commonly used method is to first increase the bandwidth to enhance the control effect of the control voltage and quickly achieve the locking of the phase-locked loop. After the difference between two adjacent phase differences is within a small range, the bandwidth is then reduced to lower the control effect of the control voltage. Here, the phase difference is the phase difference between the clock of an oven controlled crystal oscillator (OCXO) and the reference clock.

[0003] However, at the initial state of the OCXO, the difference between two adjacent phase differences is very large. At this time, increasing the bandwidth is very likely to cause overshoot, which will result in the phase-locked loop taking a long time to enter the locked state.

[0004] Therefore, it is an urgent problem for those skilled in the art to solve how to prevent overshoot when achieving fast locking of the phase-locked loop. Summary of the Invention

[0005] The purpose of the present application is to provide a method, device, and medium for locking a digital phase-locked loop to prevent overshoot when achieving fast locking of the phase-locked loop.

[0006] To solve the above technical problems, the present application provides a method for locking a digital phase-locked loop, including:

[0007] Obtain two adjacent phase differences between the clock of the OCXO and the reference clock;

[0008] Determine the difference between the previous phase difference and the latter phase difference;

[0009] Calculate a control voltage based on the difference to reduce the difference between the two adjacent phase differences. The control voltage is the voltage for controlling the clock phase of the OCXO;

[0010] When the absolute value of the difference is greater than a preset value, the control voltage is equal to a first control voltage. The calculation formula of the first control voltage is as follows:

[0011]

[0012] Among them, the BBVolC is the first control voltage, the cent_voltage is the initial value of the control voltage, the absolute value of the △VolC is positively correlated with the absolute value of the difference, and the sign of the △VolC is opposite to the sign of the difference;

[0013] When the absolute value of the difference is less than the preset value, the control voltage is equal to the second control voltage. The calculation formula of the second control voltage is as follows:

[0014]

[0015] Among them, the Fre is the difference, the α is the frequency control coefficient, the β is the phase control coefficient, the VolC is the second control voltage, and the determination method of the acc_flag is as follows: by judging whether the previously output control voltage is greater than the set preset maximum voltage value. If the previously output control voltage is greater than the set preset maximum voltage value, then continue to judge whether the current difference is greater than 0. If the current difference is greater than 0, set the acc_flag to 1. If the current difference is less than or equal to 0, set the acc_flag to 0; if the previously output control voltage does not exceed the set preset maximum voltage value, then start to judge whether the previously output control voltage is less than the set preset minimum voltage value; if the previously output control voltage is less than the set preset minimum voltage value, then start to judge whether the current difference is less than 0. If the current difference is less than 0, set the acc_flag to 1. If the current difference is greater than or equal to 0, set the acc_flag to 0. If the control voltage is between the preset maximum voltage value and the preset minimum voltage value, set the acc_flag to 1.

[0016] Preferably, the absolute value of the △VolC is positively correlated with the absolute value of the difference, and the sign of the △VolC is opposite to the sign of the difference specifically as follows:

[0017] Determine the preset range where the difference is located, and there are multiple preset ranges;

[0018] If the difference is positive, then the △VolC is negative;

[0019] If the difference is negative, then the △VolC is positive, and the larger the absolute value of the critical value of the preset range, the larger the absolute value of the corresponding △VolC.

[0020] Preferably, the calculation formula of the initial value of the control voltage is as follows:

[0021]

[0022] Wherein, U0 is the minimum value of the control voltage, freq_offset0 is the difference corresponding to the minimum value of the control voltage, U1 is the maximum value of the control voltage, and freq_offset1 is the difference corresponding to the maximum value of the control voltage.

[0023] Preferably, before obtaining the two adjacent phase differences between the clock of the OCXO and the reference clock, it further includes:

[0024] Setting the initial phase difference between the clock of the OCXO and the reference clock to zero.

[0025] Preferably, the control voltage acts on the OCXO through a first-order Kalman filter.

[0026] To solve the above technical problems, the present application also provides a device for locking a digital phase-locked loop, including:

[0027] An acquisition module for acquiring two adjacent phase differences between the clock of the OCXO and the reference clock;

[0028] A determination module for determining the difference between the previous phase difference and the next phase difference;

[0029] A calculation module for calculating a control voltage based on the difference to reduce the difference between the two adjacent phase differences, where the control voltage is the voltage for controlling the clock phase of the OCXO;

[0030] When the absolute value of the difference is greater than a preset value, the control voltage is equal to a first control voltage, and the calculation formula of the first control voltage is as follows:

[0031]

[0032] Wherein, BBVolC is the first control voltage, cent_voltage is the initial value of the control voltage, the absolute value of △VolC is positively correlated with the absolute value of the difference, and the positive and negative of △VolC are opposite to the positive and negative of the difference;

[0033] When the absolute value of the difference is less than the preset value, the control voltage is equal to a second control voltage, and the calculation formula of the second control voltage is as follows:

[0034]

[0035] Wherein, Fre is the difference value, α is the frequency control coefficient, β is the phase control coefficient, VolC is the second control voltage, and the determination method of acc_flag is as follows: By judging whether the control voltage output last time is greater than the set preset maximum voltage value. If the control voltage output last time is greater than the set preset maximum voltage value, then continue to judge whether the current difference value is greater than 0. If the current difference value is greater than 0, then set acc_flag to 1. If the current difference value is less than or equal to 0, then set acc_flag to 0; If the control voltage output last time does not exceed the set preset maximum voltage value, then start to judge whether the control voltage output last time is less than the set preset minimum voltage value; If the control voltage output last time is less than the set preset minimum voltage value, then start to judge whether the current difference value is less than 0. If the current difference value is less than 0, then set acc_flag to 1. If the current difference value is greater than or equal to 0, then set acc_flag to 0. If the control voltage is between the preset maximum voltage value and the preset minimum voltage value, then set acc_flag to 1.

[0036] To solve the above technical problems, the present application further provides a device for locking a digital phase-locked loop, including: a memory for storing a computer program;

[0037] a processor for implementing the steps of the above method for locking a digital phase-locked loop when executing the computer program.

[0038] To solve the above technical problems, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above method for locking a digital phase-locked loop are implemented.

[0039] In the digital phase-locked loop locking method provided by the present application, the function of the control voltage is to control the phase of the OCXO clock so that the phase difference between the OCXO clock and the reference clock is maintained in the initial state. If the control voltage is too large or too small, it will cause the phase of the OCXO clock to be inaccurate. Therefore, it is necessary to adjust the control voltage. The specific adjustment method is as follows: Obtain the adjacent two phase differences between the OCXO clock and the reference clock; Determine the difference between the previous phase difference and the next phase difference; Calculate the control voltage according to the positive and negative of the difference value to reduce the difference between the adjacent two phase differences. Calculate the control voltage according to the difference value to reduce the difference between the adjacent two phase differences. The control voltage is the voltage for controlling the phase of the OCXO clock; When the absolute value of the difference value is greater than the preset value, the control voltage is equal to the first control voltage. The calculation formula of the first control voltage is as follows:

[0040]

[0041] Among them, BBVolC is the first control voltage, cent_voltage is the initial value of the control voltage, the absolute value of △VolC is positively correlated with the absolute value of the difference, and the positive and negative of △VolC are opposite to the positive and negative of the difference; at this time, if the difference is positive, the control voltage decreases, if the difference is negative, the control voltage increases, and the greater the absolute value of the difference, the greater the change amount of the control voltage, which can quickly adjust the control voltage to reduce the difference.

[0042] When the absolute value of the difference is less than the preset value, the control voltage is equal to the second control voltage, and the calculation formula of the second control voltage is as follows:

[0043]

[0044] Among them, Fre is the difference, α is the frequency control coefficient, β is the phase control coefficient, VolC is the second control voltage, and the determination method of acc_flag is as follows: by judging whether the previously output control voltage is greater than the set preset maximum voltage value, if the previously output control voltage is greater than the set preset maximum voltage value, then continue to judge whether the current difference is greater than 0, if the current difference is greater than 0, set acc_flag to 1, if the current difference is less than or equal to 0, set acc_flag to 0; if the previously output control voltage does not exceed the set preset maximum voltage value, then start to judge whether the previously output control voltage is less than the set preset minimum voltage value; if the previously output control voltage is less than the set preset minimum voltage value, then start to judge whether the current difference is less than 0, if the current difference is less than 0, set acc_flag to 1, if the current difference is greater than or equal to 0, set acc_flag to 0, and if the control voltage is between the preset maximum voltage value and the preset minimum voltage value, set acc_flag to 1.

[0045] The control voltage can change rapidly to achieve the rapid locking of the phase-locked loop. Because the bandwidth is not increased, the overshoot phenomenon can be avoided. In addition, when acc_flag is 0, the integral term increment of the control voltage is zero, that is, the

[0046]

[0047] is 0. When the control voltage is greater than the preset maximum voltage value, the integral term of the control voltage no longer accumulates positively, and when the control voltage is less than the preset minimum voltage value, the integral term of the control voltage no longer accumulates negatively, which can achieve anti-integral saturation.

[0048] The present application also provides a digital phase-locked loop locking device and medium, which correspond to the above method, so it has the same beneficial effects as the above method. Brief Description of the Drawings

[0049] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0050] Figure 1 It is a flowchart of a method for locking a digital phase-locked loop provided by an embodiment of the present application;

[0051] Figure 2 It is a structural diagram of a device for locking a digital phase-locked loop provided by an embodiment of the present application;

[0052] Figure 3 It is a structural diagram of a device for locking a digital phase-locked loop provided by another embodiment of the present application. Specific Embodiments

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0054] The core of the present application is to provide a method, device and medium for locking a digital phase-locked loop.

[0055] To enable those skilled in the art to better understand the solution of the present application, the following will further elaborate on the present application in combination with the accompanying drawings and specific embodiments.

[0056] Figure 1 It is a flowchart of a method for locking a digital phase-locked loop provided by an embodiment of the present application. As shown in the figure, the method includes the following steps:

[0057] S10: Obtain the two adjacent phase differences between the clock of the OCXO and the reference clock.

[0058] Here, the method for obtaining the phase difference is not limited. One way is as follows: The clock signal output by the OCXO is sent to an input time-to-digital converter (TDC) through a frequency divider for time-to-digital conversion, converting the clock signal into a digital signal, and subtracting the value of the OCXO clock obtained from the value of the reference clock to obtain the value of the phase difference.

[0059] S11: Determine the difference between the previous phase difference and the next phase difference.

[0060] There is no limit to the frequency of obtaining the phase difference. The phase difference can be obtained once every 1 ms. The difference between the previous phase difference and the next phase difference is the previous phase difference minus the next phase difference. The obtained difference may be positive or negative. It is necessary to adjust the control voltage to change the difference. The absolute value of the difference represents the gap between two adjacent phase differences.

[0061] S12: Calculate the control voltage according to the difference to reduce the difference between two adjacent phase differences. The control voltage is the voltage for controlling the clock phase of the OCXO;

[0062] When the absolute value of the difference is greater than the preset value, the control voltage is equal to the first control voltage. The calculation of the first control voltage is as shown in formula (1) for the calculation of BBVolC.

[0063]

[0064] Among them, BBVolC is the first control voltage, cent_voltage is the initial value of the control voltage, the absolute value of △VolC is positively correlated with the absolute value of the difference, and the positive and negative of △VolC are opposite to the positive and negative of the difference;

[0065] When the absolute value of the difference is less than the preset value, the control voltage is equal to the second control voltage. The calculation of the second control voltage is as shown in formula (2):

[0066]

[0067] Among them, Fre is the difference, α is the frequency control coefficient, β is the phase control coefficient, VolC is the control voltage, and the determination method of acc_flag is as follows: By judging whether the previously output control voltage is greater than the set preset maximum voltage value. If the previously output control voltage is greater than the set preset maximum voltage value, then continue to judge whether the current difference is greater than 0. If the current difference is greater than 0, set acc_flag to 1. If the current difference is less than or equal to 0, set acc_flag to 0; If the previously output control voltage does not exceed the set preset maximum voltage value, then start to judge whether the previously output control voltage is less than the set preset minimum voltage value; If the previously output control voltage is less than the set preset minimum voltage value, then start to judge whether the current difference is less than 0. If the current difference is less than 0, set acc_flag to 1. If the current difference is greater than or equal to 0, set acc_flag to 0. If the control voltage is between the preset maximum voltage value and the preset minimum voltage value, set acc_flag to 1.

[0068] In practical applications, the control voltage has an initial value. Each time a difference is obtained, the control voltage will change. The function of the control voltage is to control the phase of the OCXO clock so that the phase difference between the OCXO clock and the reference clock is maintained at the initial state, that is, to synchronize the OCXO clock with the reference clock. The phase difference in the initial state may be zero or non-zero. If the control voltage is too large or too small, the phase of the OCXO clock will be inaccurate. If the difference is positive, the voltage value of the control voltage should be reduced, and the difference in the positive direction between two adjacent phase differences can be reduced; if the difference is negative, the voltage value of the control voltage should be increased, and the difference in the negative direction between two adjacent phase differences can be reduced. When the difference is greater than the preset value, the control voltage is equal to the first control voltage. Specifically, in implementation, the first control voltage is increased or decreased by △VolC. Here, neither the magnitude nor the sign of △VolC is limited, but △VolC is positively correlated with the absolute value of the difference, and the sign of △VolC needs to consider the sign of the difference and whether the control voltage is increased or decreased by △VolC; below, taking △VolC as a positive number as an example, when the difference is positive, the larger the difference, the larger △VolC, and the control voltage will subtract this larger △VolC; the smaller the difference, the smaller △VolC, and the control voltage will subtract this smaller △VolC; when the difference is negative, the larger the difference, the larger △VolC, and the control voltage will increase this larger △VolC; the smaller the difference, the smaller △VolC, and the control voltage will increase this smaller △VolC. The situation where △VolC is negative is opposite to the situation where it is positive, aiming to reduce the absolute value of the difference so that the phase difference between the OCXO clock and the reference clock is maintained at the initial state. In fact, in the traditional method, increasing the bandwidth is equivalent to enhancing the control effect of the control voltage, and reducing the bandwidth is equivalent to weakening the control effect of the control voltage. However, increasing the bandwidth is likely to cause fluctuations in the control voltage and form an overshoot phenomenon. The solution provided by the embodiments of the present application does not cause an overshoot phenomenon by adding a fixed △VolC to the control, and △VolC is positively correlated with the absolute value of the difference, and fast locking of the phase-locked loop can be achieved. Specifically, in implementation, the clock signal output by the OCXO can be sent to the input TDC through a frequency divider for time-to-digital conversion. The obtained clock is subtracted from the reference clock to obtain a phase difference, and then the phase difference is sent to a loop filter to adjust the control voltage of the OCXO. This process is repeated continuously to control the control voltage so that the phase difference between the OCXO clock and the reference clock is maintained at the initial state. The loop filter, as a low-pass filter, removes the high-frequency noise of the signal, and the frequency divider converts the high-frequency signal (generally 10 MHz) output by the OCXO into a signal with the same frequency as the reference clock.

[0069] The digital phase-locked loop locking method provided by this application, the function of the control voltage is to control the phase of the OCXO clock so that the phase difference between the OCXO clock and the reference clock is maintained in the initial state. If the control voltage is too large or too small, the phase of the OCXO clock will be inaccurate. Therefore, it is necessary to adjust the control voltage. The specific adjustment method is as follows: Obtain the phase differences of two adjacent phases between the OCXO clock and the reference clock; Determine the difference between the previous phase difference and the next phase difference; Calculate the control voltage according to the positive or negative of the difference to reduce the difference between the two adjacent phase differences. Calculate the control voltage according to the difference to reduce the difference between the two adjacent phase differences. The control voltage is the voltage for controlling the phase of the OCXO clock; When the absolute value of the difference is greater than the preset value, the control voltage is equal to the first control voltage. The calculation of the first control voltage is as shown in formula (1):

[0070]

[0071] Among them, BBVolC is the first control voltage, cent_voltage is the initial value of the control voltage, the absolute value of △VolC is positively correlated with the absolute value of the difference, and the positive or negative of △VolC is opposite to the positive or negative of the difference; At this time, if the difference is positive, the control voltage decreases. If the difference is negative, the control voltage increases. Moreover, the greater the absolute value of the difference, the greater the change in the control voltage, and the control voltage can be quickly adjusted to reduce the difference.

[0072] When the absolute value of the difference is less than the preset value, the control voltage is equal to the second control voltage. The calculation of the second control voltage is as shown in formula (2):

[0073]

[0074] Among them, Fre is the difference, α is the frequency control coefficient, β is the phase control coefficient, VolC is the second control voltage, and the determination method of acc_flag is as follows: By judging whether the previously output control voltage is greater than the set preset maximum voltage value. If the previously output control voltage is greater than the set preset maximum voltage value, then continue to judge whether the current difference is greater than 0. If the current difference is greater than 0, set acc_flag to 1. If the current difference is less than or equal to 0, set acc_flag to 0; If the previously output control voltage does not exceed the set preset maximum voltage value, then start to judge whether the previously output control voltage is less than the set preset minimum voltage value; If the previously output control voltage is less than the set preset minimum voltage value, then start to judge whether the current difference is less than 0. If the current difference is less than 0, set acc_flag to 1. If the current difference is greater than or equal to 0, set acc_flag to 0. If the control voltage is between the preset maximum voltage value and the preset minimum voltage value, set acc_flag to 1.

[0075] The control voltage can change rapidly to achieve fast locking of the phase-locked loop. Since the bandwidth is not increased, overshoot can be avoided. Additionally, when acc_flag is 0, the increment of the integral term of the control voltage is zero, that is, for this time

[0076]

[0077] is 0. When the control voltage is greater than the preset maximum voltage value, the integral term of the control voltage no longer accumulates positively. When the control voltage is less than the preset minimum voltage value, the integral term of the control voltage no longer accumulates negatively, enabling anti-integral saturation.

[0078] As mentioned in the above embodiment, the absolute value of △VolC is positively correlated with the absolute value of the difference. In practical applications, the magnitude of △VolC can be determined by using the range of the difference. The absolute value of △VolC is positively correlated with the absolute value of the difference, and the positive and negative of △VolC are opposite to those of the difference. Specifically: according to the positive and negative of the difference, increase or decrease the control voltage by △VolC, and determine the preset range where the difference is located. There are multiple preset ranges; if the difference is positive, decrease the control voltage by △VolC; if the difference is negative, increase the control voltage by △VolC, where △VolC is a positive number. The larger the absolute value of the critical value of the preset range, the larger the corresponding △VolC.

[0079] In the embodiment of the present application, taking two preset ranges as an example, |Fre| is the absolute value of the difference, a is the critical value of the first preset range, and a / 4 is the critical value of the second preset range. The magnitude of a is not limited. When the difference range is as shown in formula (3),

[0080] a < |Fre| (3)

[0081] Set △VolC = ±b.

[0082] When the difference range is as shown in formula (4),

[0083]

[0084] Set △VolC = ±c, where b is greater than c. The difference between b and c is not limited. Generally, b can be ten times larger than c. The positive and negative of △VolC are subject to the actual situation, which has been introduced in the above embodiment and will not be elaborated here. Additionally, the magnitude of the preset value is not limited. a / 4 can be used as the preset value, as shown in formula (5):

[0085]

[0086] When the magnitude of the difference satisfies formula (5), the control voltage is equal to the second control voltage.

[0087] The magnitude of the initial control voltage also affects the control effect. Therefore, an initial center voltage is generally calculated in advance as the initial value of the control voltage. The specific calculation method of the initial center voltage is not limited here. The embodiments of the present application provide a preferred solution. When first obtaining an OCXO, the TDC is used to measure the corresponding differences at the minimum and maximum values of the control voltage respectively. By calculation, the calibrated initial center voltage can be obtained. The specific setting of the initial value of the control voltage is as follows: Obtain the difference corresponding to the minimum and maximum values of the control voltage, where the minimum and maximum values are obtained in advance; obtain the initial value of the control voltage according to the minimum and maximum values and the corresponding difference between them. The minimum and maximum values of the control voltage can be obtained from the factory manual of the OCXO. The specific calculation is shown in formula (6):

[0088]

[0089] cent_voltage is the obtained initial value of the control voltage, U0 is the minimum value of the control voltage, freq_offset0 is the difference corresponding to the minimum value of the control voltage, U1 is the maximum value of the control voltage, and freq_offset1 is the difference corresponding to the maximum value of the control voltage.

[0090] At the initial moment, there may already be a phase difference between the clock of the OCXO and the reference clock. If a large phase difference is directly added when starting the calculation, a very long adjustment time is required. Therefore, before obtaining two adjacent phase differences between the clock of the OCXO and the reference clock, it further includes: setting the initial phase difference between the clock of the OCXO and the reference clock to zero. That is, the function of the control voltage is to control the phase of the OCXO clock so that the phase difference between the clock of the OCXO and the reference clock is maintained at the initial state of zero, which can avoid a long adjustment time.

[0091] In addition, in order to filter out high-frequency noise, the control voltage acts on the OCXO through a first-order Kalman filter. The bandwidth of the Kalman filter can be set to more than 10 times the bandwidth of the loop filter to better expose the high-frequency noise of the loop.

[0092] In the above embodiments, the method for locking the digital phase-locked loop is described in detail. The present application also provides embodiments corresponding to the device for locking the digital phase-locked loop. It should be noted that the present application describes the embodiments of the device part from two perspectives, one is from the perspective of functional modules, and the other is from the perspective of hardware.

[0093] From the perspective of functional modules, the present embodiment provides a device for locking a digital phase-locked loop, Figure 2 which is the structural diagram of the device for locking the digital phase-locked loop provided by the embodiments of the present application. As Figure 2 shown, the device includes:

[0094] An acquisition module 10 for acquiring two adjacent phase differences between the clock of the OCXO and the reference clock;

[0095] A determination module 11 for determining the difference between the previous phase difference and the subsequent phase difference;

[0096] A calculation module 12 for calculating a control voltage according to the difference to reduce the difference between two adjacent phase differences, where the control voltage is the voltage for controlling the clock phase of the OCXO;

[0097] When the absolute value of the difference is greater than a preset value, the control voltage is equal to the first control voltage, and the calculation formula of the first control voltage is as follows: The calculation formula of formula BBVolC is as follows:

[0098]

[0099] Where cent_voltage is the initial value of the control voltage, the absolute value of △VolC is positively correlated with the absolute value of the difference, and the positive and negative of △VolC are opposite to the positive and negative of the difference;

[0100] When the absolute value of the difference is less than a preset value, the control voltage is equal to the second control voltage, and the calculation formula of the second control voltage is as follows:

[0101]

[0102] Where Fre is the difference, α is the frequency control coefficient, β is the phase control coefficient, VolC is the control voltage, and the determination method of acc_flag is as follows: By judging whether the previously output control voltage is greater than the set preset maximum voltage value. If the previously output control voltage is greater than the set preset maximum voltage value, then continue to judge whether the current difference is greater than 0. If the current difference is greater than 0, then set acc_flag to 1. If the current difference is less than or equal to 0, then set acc_flag to 0; If the previously output control voltage does not exceed the set preset maximum voltage value, then start to judge whether the previously output control voltage is less than the set preset minimum voltage value; If the previously output control voltage is less than the set preset minimum voltage value, then start to judge whether the current difference is less than 0. If the current difference is less than 0, then set acc_flag to 1. If the current difference is greater than or equal to 0, then set acc_flag to 0. If the control voltage is between the preset maximum voltage value and the preset minimum voltage value, then set acc_flag to 1.

[0103] Since the embodiments of the device part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be elaborated here for the time being.

[0104] The digital phase-locked loop locking device provided in this embodiment corresponds to the above method, so it has the same beneficial effects as the above method.

[0105] From a hardware perspective, this embodiment provides another digital phase-locked loop locking device. Figure 3 As shown in the structure diagram of the digital phase-locked loop locking device provided in another embodiment of this application, Figure 3 as shown, the digital phase-locked loop locking device includes: a memory 20 for storing computer programs;

[0106] a processor 21 for implementing the steps of the digital phase-locked loop locking method mentioned in the above embodiment when executing the computer program.

[0107] The digital phase-locked loop locking device provided in this embodiment may include, but is not limited to, smart phones, tablet computers, laptop computers, desktop computers, etc.

[0108] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0109] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201. After the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the digital phase-locked loop locking method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the digital phase-locked loop locking method.

[0110] In some embodiments, the digital phase-locked loop locking device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0111] Those skilled in the art can understand that the structure shown in the figure does not constitute a limitation on the digital phase-locked loop locking device, and it may include more or fewer components than those shown.

[0112] The digital phase-locked loop locking device provided by the embodiment of the present application includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: the digital phase-locked loop locking method.

[0113] The digital phase-locked loop locking device provided by this embodiment corresponds to the above method, so it has the same beneficial effects as the above method.

[0114] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the steps recorded in the above method embodiment.

[0115] It can be understood that if the methods in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0116] The computer-readable storage medium provided in this embodiment corresponds to the above method, and thus has the same beneficial effects as the above method.

[0117] The above has provided a detailed introduction to a method, device, and medium for digital phase-locked loop locking provided by the present application. The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For the relevant parts, refer to the description of the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0118] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitations, the element defined by the statement "including an..." does not exclude the existence of additional identical elements in the process, method, article, or device including the above element.

Claims

1. A method for locking a digital phase-locked loop, characterized in that Including: Obtain the adjacent two phase differences between the clock of the OCXO and the reference clock; Determine the difference between the previous phase difference and the latter phase difference; Calculate a control voltage according to the difference to reduce the difference between the adjacent two phase differences, and the control voltage is the voltage for controlling the clock phase of the OCXO; When the absolute value of the difference is greater than a preset value, the control voltage is equal to a first control voltage, and the calculation formula of the first control voltage is as follows: Wherein, the BBVolC is the first control voltage, the cent_voltage is the initial value of the control voltage, the absolute value of the △VolC is positively correlated with the absolute value of the difference, and the positive and negative of the △VolC are opposite to the positive and negative of the difference; When the absolute value of the difference is less than the preset value, the control voltage is equal to a second control voltage, and the calculation formula of the second control voltage is as follows: Wherein, the Fre is the difference, the α is the frequency control coefficient, the β is the phase control coefficient, the VolC is the second control voltage, and the determination method of the acc_flag is as follows: by judging whether the previously output control voltage is greater than the set preset maximum voltage value, if the previously output control voltage is greater than the set preset maximum voltage value, then continue to judge whether the current difference is greater than 0, if the current difference is greater than 0, then set the acc_flag to 1, if the current difference is less than or equal to 0, then set the acc_flag to 0; if the previously output control voltage does not exceed the set preset maximum voltage value, then start to judge whether the previously output control voltage is less than the set preset minimum voltage value; if the previously output control voltage is less than the set preset minimum voltage value, then start to judge whether the current difference is less than 0, if the current difference is less than 0, then set the acc_flag to 1, if the current difference is greater than or equal to 0, then set the acc_flag to 0, and if the control voltage is between the preset maximum voltage value and the preset minimum voltage value, then set the acc_flag to 1.

2. The method for locking a digital phase-locked loop according to claim 1, characterized in that, The absolute value of the △VolC is positively correlated with the absolute value of the difference, and the positive and negative of the △VolC are opposite to the positive and negative of the difference specifically as follows: Determine the preset range where the difference is located, and there are multiple preset ranges; If the difference is positive, then the △VolC is negative; If the difference is negative, then the △VolC is positive, and the larger the absolute value of the critical value of the preset range, the larger the absolute value of the corresponding △VolC.

3. The method for locking a digital phase-locked loop according to claim 1, wherein The calculation formula of the initial value of the control voltage is as follows: Wherein, the U0 is the minimum value of the control voltage, the freq_offset0 is the difference corresponding to the minimum value of the control voltage, the U1 is the maximum value of the control voltage, and the freq_offset1 is the difference corresponding to the maximum value of the control voltage.

4. The method for locking a digital phase-locked loop according to any one of claims 1 to 3, characterized in that, Before obtaining the adjacent two phase differences between the clock of the OCXO and the reference clock, it further includes: Set the initial phase difference between the clock of the OCXO and the reference clock to zero.

5. The method for locking a digital phase-locked loop according to claim 4, characterized in that, The control voltage acts on the OCXO through a first-order Kalman filter.

6. A device for locking a digital phase-locked loop, characterized in that, It includes: An acquisition module for acquiring the adjacent two phase differences between the clock of the OCXO and the reference clock; A determination module for determining the difference between the previous phase difference and the subsequent phase difference; A calculation module for calculating a control voltage according to the difference to reduce the difference between the adjacent two phase differences, where the control voltage is the voltage for controlling the clock phase of the OCXO; When the absolute value of the difference is greater than a preset value, the control voltage is equal to the first control voltage, and the calculation formula of the first control voltage is as follows: Wherein, the BBVolC is the first control voltage, the cent_voltage is the initial value of the control voltage, the absolute value of the △VolC is positively correlated with the absolute value of the difference, and the positive and negative of the △VolC are opposite to the positive and negative of the difference; When the absolute value of the difference is less than the preset value, the control voltage is equal to the second control voltage, and the calculation formula of the second control voltage is as follows: Wherein, the Fre is the difference, the α is the frequency control coefficient, the β is the phase control coefficient, the VolC is the second control voltage, and the determination method of the acc_flag is as follows: by judging whether the previously output control voltage is greater than the set preset maximum voltage value, if the previously output control voltage is greater than the set preset maximum voltage value, then continue to judge whether the current difference is greater than 0, if the current difference is greater than 0, then set the acc_flag to 1, if the current difference is less than or equal to 0, then set the acc_flag to 0; if the previously output control voltage does not exceed the set preset maximum voltage value, then start to judge whether the previously output control voltage is less than the set preset minimum voltage value; if the previously output control voltage is less than the set preset minimum voltage value, then start to judge whether the current difference is less than 0, if the current difference is less than 0, then set the acc_flag to 1, if the current difference is greater than or equal to 0, then set the acc_flag to 0, and if the control voltage is between the preset maximum voltage value and the preset minimum voltage value, then set the acc_flag to 1.

7. A device for locking a digital phase-locked loop, characterized in that, It includes a memory for storing a computer program; A processor for implementing the steps of the method for locking a digital phase-locked loop as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for locking a digital phase-locked loop as described in any one of claims 1 to 5 are implemented.

Images