Sample-and-hold amplifier

Abstract

The application discloses a sample-and-hold amplifier, which has an intrinsic offset voltage elimination capability by adjusting a feedback path between two working stages, and extra noise generated by a sampling capacitor can be reduced by maximizing the sampling capacitor, and by adding a dummy device at the sampling capacitor, the system loop still has good stability in the case that the sampling capacitor is very large.

Description

TECHNICAL FIELD

[0001] The present application relates to power electronics, more particularly, to a sample-and-hold amplifier. BACKGROUND

[0002] It is known that the offset voltage and low frequency noise of a sample-and-hold amplifier are the key factors affecting the accuracy of the sample-and-hold amplifier. In the prior art, there are mainly two methods to eliminate the offset voltage:

[0003] In the self-zeroing method, a sampling capacitor is connected in series with the input terminal of the sample-and-hold amplifier, and a switch is connected between the input terminal and the output terminal. Under the control of a clock signal of "two-phase non-overlap clock", the sample-and-hold amplifier alternately works in a sampling phase and a holding phase. In the sampling phase, the switch is turned on, the input terminal and the output terminal of the sample-and-hold amplifier are short-circuited, and the DC offset voltage and the low frequency noise of the sample-and-hold amplifier are stored on the sampling capacitor. In the holding phase, the switch is turned off, the sample-and-hold amplifier is in a normal open-loop working mode, and the DC offset voltage and the low frequency noise of the sample-and-hold amplifier are offset at the input terminal, thereby achieving the purpose of dynamically eliminating the DC offset voltage and the low frequency noise. However, this traditional self-zeroing type sample-and-hold circuit has two main shortcomings. One is that the input current is large, because the sampling capacitor is directly driven by the input terminal. The other is that due to the limitation of the input current, the sampling capacitor cannot be too large, and thus the noise is high.

[0004] In the chopping method, a first switch and a second switch are respectively connected to the input terminal and the output terminal of the sample-and-hold amplifier, and the control signals of the first switch and the second switch have the same phase and frequency, and are respectively used for differential signal cross-inversion of the input voltage signal and the output voltage signal. Since the input voltage signal is twice chopped to generate a DC signal, and the DC offset voltage of the sample-and-hold amplifier itself is once chopped to generate a high-frequency square wave signal, a low-pass filter (LPF) can be used to filter out the DC offset voltage. The sample-and-hold amplifier in the chopping scheme needs to be connected with an additional low-frequency filter at the output terminal of the sample-and-hold amplifier, thereby limiting the bandwidth of the sample-and-hold amplifier.

[0005] Therefore, it is desirable to further improve the method of suppressing the DC offset voltage and the low frequency noise of the sample-and-hold amplifier. SUMMARY

[0006] In view of this, the present application provides a sample-and-hold amplifier to solve the problem of high offset voltage and noise in the existing sample-and-hold amplifier.

[0007] The present application provides a sample-and-hold amplifier, characterized in that the sample-and-hold amplifier comprises:

[0008] an operational amplifier;

[0009] a sampling capacitor, a first end coupled to an inverting input of the operational amplifier, a second end coupled to a reference ground;

[0010] a switching circuit, configured to at least partially cancel an offset voltage of the operational amplifier by switching a feedback path of the sample-and-hold amplifier between a first phase and a second phase.

[0011] Preferably, the switching circuit is configured to, in the first phase, configure the operational amplifier in a unity-gain mode such that an input voltage of the sample-and-hold amplifier and the offset voltage are tracked onto the sampling capacitor, and in the second phase, configure the operational amplifier in an inverting hold mode to transfer a sampled voltage on the sampling capacitor to an output of the operational amplifier.

[0012] Preferably, the switching circuit comprises:

[0013] a first switch, a first end connected to an input voltage of the sample-and-hold amplifier, a second end connected to a non-inverting input of the operational amplifier;

[0014] a second switch, connected across an inverting input and an output of the operational amplifier;

[0015] a third switch, connected across the non-inverting input and the output of the operational amplifier;

[0016] wherein, in the first phase, the first switch and the second switch are turned on, and the third switch is turned off; and in the second phase, the first switch and the second switch are turned off, and the third switch is turned on.

[0017] Preferably, the output of the operational amplifier is at different circuit nodes within an internal structure of the operational amplifier in the first phase and the second phase.

[0018] Preferably, the operational amplifier comprises:

[0019] a current mirror circuit, comprising a first transistor and a second transistor, both having their control terminals connected together and both having their first power terminals connected together;

[0020] a signal input circuit, comprising a third transistor and a fourth transistor, wherein the third transistor has a control terminal connected to a non-inverting input of the operational amplifier, and has a first power terminal connected to a second power terminal of the first transistor; and the fourth transistor has a control terminal connected to an inverting input of the operational amplifier, and has a first power terminal connected to a second power terminal of the second transistor;

[0021] a current source coupled between a common node of the second power terminal of the third transistor and the second power terminal of the fourth transistor and a ground terminal.

[0022] Preferably, by changing the on-off state of each switch in the switch circuit, the output terminal of the operational amplifier is coupled to the first power terminal of the fourth transistor in the first phase, and the output terminal of the operational amplifier is coupled to the first power terminal of the third transistor in the second phase.

[0023] Preferably, the switch circuit comprises:

[0024] a fifth switch, a first terminal of which is connected to a common node of the first power terminal of the third transistor and the second power terminal of the first transistor, and a second terminal of which is connected to a common node of the control terminals of the first transistor and the second transistor,

[0025] a sixth switch, a first terminal of which is configured as the output terminal of the operational amplifier, and a second terminal of which is connected to a common node of the first power terminal of the fourth transistor and the second power terminal of the second transistor,

[0026] a seventh switch, a first terminal of which is connected to the second terminal of the fifth switch, and a second terminal of which is connected to the second terminal of the sixth switch,

[0027] an eighth switch, a first terminal of which is configured as the output terminal of the operational amplifier, and a second terminal of which is connected to the first terminal of the fifth switch,

[0028] wherein the fifth switch and the sixth switch are only turned on in the first phase, and the seventh switch and the eighth switch are only turned on in the second phase.

[0029] Preferably, the sample-and-hold amplifier further comprises a ninth switch, which is used to generate a zero point with the sampling capacitor to compensate for a pole generated by the second switch and the sampling capacitor, thereby improving the stability of the system, and the ninth switch is connected in series with the sampling capacitor.

[0030] Preferably, the sample-and-hold amplifier further comprises a first resistor, which is used to generate a zero point with the sampling capacitor to compensate for a pole generated by the second switch and the sampling capacitor, thereby improving the stability of the system, and the first resistor is connected in series with the sampling capacitor.

[0031] Preferably, the ninth switch is configured to be always on.

[0032] Preferably, the size of the ninth switch is approximately or identical to that of the second switch, so that the on-resistance of the ninth switch is the same as that of the second switch.

[0033] Preferably, the first resistor has the same resistance as the on-resistance of the second switch.

[0034] The sample-and-hold amplifier according to the present application has the ability to eliminate the intrinsic offset voltage and low-frequency noise by adjusting the feedback path between two working stages, and the input current of the sample-and-hold amplifier according to the present application can be greatly reduced because the sampling capacitor is directly driven by the operational amplifier instead of the input terminal. The additional sampling noise caused by the input sampling capacitor can also be reduced by maximizing the sampling capacitor, and the system loop still has good stability in the case of a large sampling capacitor by adding dummy devices at the sampling capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0036] Figure 1 The circuit schematic diagram of the sample-and-hold amplifier according to the present application in the first stage;

[0037] Figure 2 The circuit schematic diagram of the sample-and-hold amplifier according to the present application in the second stage;

[0038] Figure 3 The circuit structure diagram of the operational amplifier according to the present application. DETAILED DESCRIPTION

[0039] The present application will be described below based on the embodiments, but the present application is not limited to only these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can also be completely understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, the well-known methods, processes, procedures, elements and circuits are not described in detail.

[0040] In addition, those skilled in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0041] Meanwhile, it should be understood that in the following description, "circuitry" refers to an electrical circuit that is constructed from at least one element or sub-circuitry and is connected electrically or electromagnetically. When an element or a circuit is said to be "connected to" another element or said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element.

[0042] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

[0043] In the description of the present application, it should be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not intended to indicate or imply relative importance. In addition, in the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0044] Figure 1 Circuit schematic diagram of the sample-and-hold amplifier according to the present application in the first stage; Figure 2 Circuit schematic diagram of the sample-and-hold amplifier according to the present application in the second stage. Reference Figure 1 The sample-and-hold amplifier of the present embodiment includes an operational amplifier AMP, a sampling capacitor C, and a switching circuit 11. Specifically, a first end of the sampling capacitor C is coupled to an inverting input terminal of the operational amplifier AMP, and a second end is coupled to a reference ground GND1. The sampling capacitor C is used to store the offset voltage Vos of the sample-and-hold amplifier. The switching circuit 11 is used to switch the feedback path of the sample-and-hold amplifier between the first stage and the second stage, so that the offset voltage Vos of the operational amplifier AMP is inherently cancelled.

[0045] It should be noted that here, the sampling capacitor C can be an independent capacitor device, or an equivalent capacitor composed of a plurality of capacitor devices connected in at least one of series or parallel connection.

[0046] Preferably, the switching circuit 11 is configured to, in the first phase, configure the feedback path of the sample-and-hold amplifier as the first path and allow the input voltage Vin to access one end of the operational amplifier AMP to configure the operational amplifier AMP as a unity-gain mode, so that the input voltage Vin and the offset voltage Vos of the sample-and-hold amplifier are sampled onto the sampling capacitor C; and in the second phase, configure the feedback path of the sample-and-hold amplifier as the second path and do not allow the input voltage Vin to access any end of the operational amplifier AMP, and the output of the operational amplifier AMP is chopped to configure the operational amplifier AMP as an inverting hold mode, so as to transfer the sampled voltage on the sampling capacitor C to the output end of the operational amplifier AMP.

[0047] Preferably, the switching circuit 11 comprises a first switch S1, a second switch S2 and a third switch S3. Referring to Figure 1 and Figure 2 , in particular, the first switch S1 has a first end connected to the input voltage Vin of the sample-and-hold amplifier and a second end connected to the non-inverting input end of the operational amplifier AMP; the second switch S2 is connected across the inverting input end and the output end of the operational amplifier AMP; and the third switch S3 is connected across the non-inverting input end and the output end of the operational amplifier AMP. Referring to Figure 1 and Figure 2 , in the switching circuit 11, in the first phase, the first switch S1 and the second switch S2 are turned on, and the third switch S3 is turned off, to configure the operational amplifier AMP as a unity-gain mode, so that the input voltage Vin and the offset voltage Vos of the sample-and-hold amplifier are sampled onto the sampling capacitor C; and in the second phase, the first switch S1 and the second switch S2 are turned off, and the third switch S3 is turned on, and the output of the operational amplifier AMP is chopped to configure the operational amplifier AMP as an inverting hold mode, so as to transfer the sampled voltage on the sampling capacitor C to the output end of the operational amplifier AMP.

[0048] Here, the switching circuit 11 can be any suitable path selection circuit, which can be implemented in any known or unknown manner, and will not be exemplified here.

[0049] It should be noted that, since the feedback path of the sample-and-hold amplifier is configured as different paths in the first phase and the second phase, and in order to achieve negative feedback of the closed loop, the output end of the operational amplifier AMP needs to be located at different circuit nodes in the internal structure of the operational amplifier AMP in the first phase and the second phase, i.e., the output end of the operational amplifier AMP needs to be switched in the first phase and the second phase, so that the output end of the operational amplifier AMP is chopped, therefore, here, a specific circuit structure diagram of an operational amplifier is taken as an example to illustrate the difference in selection of the different circuit nodes.

[0050] refer to Figure 3 Here is a circuit diagram of an operational amplifier according to the present invention. The operational amplifier AMP includes a current mirror circuit 31, a signal input circuit 32, and a current source Ic.

[0051] The current mirror circuit 31 includes a first transistor M1 and a second transistor M2. The control terminals of the first transistor M1 and the second transistor M2 are connected together, and the first power terminals of the first transistor M1 and the second transistor M2 are also connected together. The first power terminals are also connected to the power supply voltage VDD.

[0052] The signal input circuit 32 includes a third transistor Q1 and a fourth transistor Q2. The control terminal of the third transistor Q1 is the non-inverting input terminal of the operational amplifier AMP, and the first power terminal of the third transistor Q1 is coupled to the second power terminal of the first transistor M1. The control terminal of the fourth transistor Q2 is the inverting input terminal of the operational amplifier AMP, and the first power terminal of the fourth transistor Q2 is coupled to the second power terminal of the second transistor M2.

[0053] The current source Ic is coupled between the common node of the second power terminal of the third transistor Q1 and the second power terminal of the fourth transistor Q2, and the ground terminal GND2.

[0054] Furthermore, in Figure 1 In the first stage shown, the control terminals of the first transistor M1 and the second transistor M2 are also connected to the common node of the first power terminal of the third transistor Q1 and the second power terminal of the first transistor M1, and the output terminal of the operational amplifier AMP is coupled to the first power terminal of the fourth transistor Q2; Figure 2 In the second stage shown, the control terminals of the first transistor M1 and the second transistor M2 are also connected to the common node of the first power terminal of the fourth transistor Q2 and the second power terminal of the second transistor M2, and the output terminal of the operational amplifier AMP is coupled to the first power terminal of the third transistor Q1.

[0055] Here, the structure of the operational amplifier AMP is not limited to this; it can be any known or unknown implementation, and no further examples will be given here.

[0056] Optionally, in this embodiment, the first transistor M1 and the second transistor M2 are both P-type field-effect transistors, and the third transistor Q1 and the fourth transistor Q2 are both N-type field-effect transistors. Of course, in other embodiments, the first transistor M1 and the second transistor M2, as well as the third transistor Q1 and the fourth transistor Q2, can be either P-type or N-type field-effect transistors, and this application embodiment does not limit this.

[0057] Optionally, the first transistor M and the second transistor M2, and the third transistor Q1 and the fourth transistor Q2 can be Junction Field-Effect Transistors (JFETs), and in other embodiments, the first transistor M and the second transistor M2, and the third transistor Q1 and the fourth transistor Q2 can also be other types of field-effect transistors, which are not limited in the embodiments of the present application.

[0058] Further, in the operational amplifier AMP, a switch circuit 33 is further included, by changing the on-off state of each switch in the switch circuit 33, so that in the first stage, the output end of the operational amplifier AMP is coupled with the first power end of the fourth transistor Q2; and in the second stage, the output end of the operational amplifier AMP is coupled with the first power end of the third transistor Q1.

[0059] In a preferred embodiment, the switch circuit 33 includes four switches S5-S8. Specifically, the fifth switch S5 has a first end connected to a common node of the first power end of the third transistor Q1 and the second power end of the first transistor M1, and a second end connected to a common node of the control ends of the first transistor M1 and the second transistor M2; the sixth switch S6 has a first end configured as the output end of the operational amplifier AMP, and a second end connected to a common node of the first power end of the fourth transistor Q2 and the second power end of the second transistor M2; the seventh switch S7 has a first end connected to the second end of the fifth switch S5, and a second end connected to the second end of the sixth switch S6; and the eighth switch S8 has a first end configured as the output end of the operational amplifier AMP, and a second end connected to the first end of the fifth switch S5.

[0060] In the first stage, the fifth switch S5 and the sixth switch S6 are turned on, and the seventh switch S7 and the eighth switch S8 are turned off; and in the second stage, the fifth switch S5 and the sixth switch S6 are turned off, and the seventh switch S7 and the eighth switch S8 are turned on, so that the operational amplifier AMP is coupled with the first power end of the third transistor Q1 and the first power end of the fourth transistor Q2, respectively. Figure 1 and Figure 2 The structure in the rectangular dashed box shown on the right side of the above formula corresponds to the structure in the rectangular dashed box shown on the right side of the above formula.

[0061] In summary, the sample-and-hold amplifier of the present application has the following advantages: Figure 1 In the sampling stage shown in the above formula, the first switch S1 and the second switch S2 are turned on, and the operational amplifier AMP is configured in a unity-gain mode, at this time, the input voltage Vin and the offset voltage Vos are tracked to the sampling capacitor C, so the sampling voltage V on the sampling capacitor C is Vin+Vos;

[0062] In the hold stage shown in the above formula, the first switch S1 and the second switch S2 are turned off, and the operational amplifier AMP is configured in a high-gain mode, at this time, the input voltage Vin is amplified to the output voltage Vout, and the offset voltage Vos is not amplified, so the output voltage Vout is Vin+Vos. Figure 2In the holding phase, the third switch S3 is turned on, the output voltage of the operational amplifier AMP is chopped, and then the sampled voltage V on the sampling capacitor C is transferred to the output. At this time, the output voltage Vout of the operational amplifier AMP is Vin+Vos-Vos=Vin. Thus, by switching the feedback path of the sample-and-hold amplifier, the offset voltage Vos of the operational amplifier AMP is inherently cancelled.

[0063] It can be seen that, by adjusting the feedback path between the two working phases, the sample-and-hold amplifier has an inherent offset voltage cancellation capability. Meanwhile, the additional noise generated by the sampling capacitor can be reduced by maximizing the sampling capacitor.

[0064] With reference to the foregoing description, in a preferred embodiment, in order to minimize the charge injection of the sampling capacitor C during the switching process of the second switch S2, the second switch S2 is preferably a switch with the smallest size, and a dummy device, here the ninth switch Sdmy, is added to the sampling capacitor C. Thus, the sample-and-hold amplifier further comprises the ninth switch Sdmy connected in series with the sampling capacitor C, for generating a zero point with the sampling capacitor C and thereby compensating for the pole generated by the second switch S2 and the sampling capacitor C, so as to improve the stability of the system. Figure 1 Figure 2 Preferably, the ninth switch Sdmy is always on, and the size of the ninth switch Sdmy is similar to or the same as that of the second switch S2, so that their on resistances are the same.

[0065] In order to minimize the additional noise sampled in the sampling capacitor C, the capacitance value of the sampling capacitor C is generally as large as possible, which will reduce the non-main pole (generated by the on resistance of the second switch S2 and the sampling capacitor C). If the pole frequency is too low, the system stability will be poor, thereby leaving less phase margin. Therefore, the ninth switch Sdmy is needed to be connected in series with the sampling capacitor C to generate a zero point to compensate for the non-main pole. By generating the zero point with the ninth switch Sdmy to track the pole generated by the second switch S2 and the sampling capacitor C, the zero point and the pole can cancel each other out, thereby ensuring that the system loop still has good stability even in the case of a large sampling capacitor C.

[0066] In other embodiments, the dummy device, i.e., the ninth switch Sdmy described above, can be replaced by a first resistor for generating a zero point with the sampling capacitor C and thereby compensating for the pole generated by the second switch S2 and the sampling capacitor C, so as to improve the stability of the system.

[0067] In other embodiments, the dummy device, i.e., the ninth switch Sdmy described above, can be replaced by a first resistor for generating a zero point with the sampling capacitor C and thereby compensating for the pole generated by the second switch S2 and the sampling capacitor C, so as to improve the stability of the system.

[0068] ​It can be seen that the sample-and-hold amplifier has the ability to eliminate the intrinsic offset voltage and low-frequency noise by adjusting the feedback path between two working stages, and the input current of the sample-and-hold amplifier can be greatly reduced because the sampling capacitor is directly driven by the operational amplifier instead of the input end; the additional sampling noise introduced by the input sampling capacitor can also be reduced by maximizing the sampling capacitor, and the system loop still has good stability under the condition of large sampling capacitor by adding dummy devices at the sampling capacitor.

[0069] The above only describes the preferred embodiments of the present application and is not used to limit the present application, and the present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A sample-and-hold amplifier characterized by, The sample-and-hold amplifier comprises: an operational amplifier; a sampling capacitor, a first end of which is coupled to an inverting input of the operational amplifier, and a second end of which is coupled to a reference ground; a switching circuit, configured to switch a feedback path of the sample-and-hold amplifier between a first phase and a second phase, so that a mismatch voltage of the operational amplifier is at least partially self-cancelled.

2. The sample-and-hold amplifier of claim 1, wherein, The switching circuit comprises a second switch connected in series between the inverting input and the output of the operational amplifier, a first switch connected between an input voltage of the sample-and-hold amplifier and a non-inverting input of the operational amplifier, a third switch connected in series between the non-inverting input and the output of the operational amplifier, and a dummy device connected in series with the sampling capacitor, configured to generate a zero point with the sampling capacitor to compensate for a pole generated by the second switch and the sampling capacitor; wherein in the first phase, the first switch and the second switch are turned on, and the third switch is turned off; in the second phase, the first switch and the second switch are turned off, and the third switch is turned on.

3. The sample-and-hold amplifier of claim 1, wherein, The switching circuit is configured to configure the operational amplifier in a unity gain mode in the first phase, so that the input voltage of the sample-and-hold amplifier and the mismatch voltage are tracked onto the sampling capacitor, and configure the operational amplifier in an inverting hold mode in the second phase, so as to transfer a sampling voltage on the sampling capacitor to the output of the operational amplifier.

4. The sample-and-hold amplifier of claim 1, wherein, The output of the operational amplifier is located at different circuit nodes in the internal structure of the operational amplifier in the first phase and the second phase. The operational amplifier comprises: a current mirror circuit comprising a first transistor and a second transistor, both of which have their control terminals connected together and both of which have their first power terminals connected together; a signal input circuit comprising a third transistor and a fourth transistor, wherein the control terminal of the third transistor is the non-inverting input of the operational amplifier, and the first power terminal of the third transistor is coupled to the second power terminal of the first transistor; the control terminal of the fourth transistor is the inverting input of the operational amplifier, and the first power terminal of the fourth transistor is coupled to the second power terminal of the second transistor; 5. The sample-and-hold amplifier of claim 4, wherein, a current source coupled between the common node of the second power terminal of the third transistor and the second power terminal of the fourth transistor, and a ground terminal.

6. The sample-and-hold amplifier of claim 5, wherein, By changing the on-off state of each switch in the switching circuit, the output of the operational amplifier is coupled to the first power terminal of the fourth transistor in the first phase, and the output of the operational amplifier is coupled to the first power terminal of the third transistor in the second phase. The switching circuit comprises: a fifth switch, a first end of which is connected to the common node of the first power terminal of the third transistor and the second power terminal of the first transistor, and a second end of which is connected to the common node of the control terminals of the first transistor and the second transistor; a sixth switch, a first end of which is configured as the output of the operational amplifier, and a second end of which is connected to the common node of the first power terminal of the fourth transistor and the second power terminal of the second transistor, a seventh switch, a first end of which is connected to a second end of the fifth switch, and a second end of which is connected to a second end of the sixth switch, an eighth switch, a first end of which is configured as an output end of the operational amplifier, and a second end of which is connected to a first end of the fifth switch, wherein the fifth switch and the sixth switch are only turned on in the first phase, and the seventh switch and the eighth switch are only turned on in the second phase.

7. The sample-and-hold amplifier of claim 1, wherein, The dummy device is a ninth switch, which is used to generate a zero point with the sampling capacitor, thereby compensating for a pole generated by the second switch and the sampling capacitor, so as to improve the stability of the system. The ninth switch is connected in series with the sampling capacitor.

8. The sample-and-hold amplifier of claim 1, wherein, The dummy device is a first resistor, which is used to generate a zero point with the sampling capacitor, thereby compensating for a pole generated by the second switch and the sampling capacitor, so as to improve the stability of the system. The first resistor is connected in series with the sampling capacitor.

9. The sample-and-hold amplifier of claim 7, wherein, The ninth switch is configured to be always turned on.

10. The sample-and-hold amplifier of claim 7, wherein, The size of the ninth switch is consistent with the size of the second switch, so that the on-resistance of the ninth switch is the same as the on-resistance of the second switch.

11. The sample-and-hold amplifier of claim 8, wherein, The resistance of the first resistor is the same as the on-resistance of the second switch.

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