A multi-processor load balancing method, computing device and storage medium

Abstract

The application discloses a kind of multi-processor load balancing method, computing device and storage medium, and include steps: the load value of each processor is obtained, and the processor with the highest load value is taken as target processor;From the multiple processes included in target processor, determine the process with the least number of internal memory accesses, to obtain target process;Target process is migrated to other processor to run, to reduce the load value of target processor.The application considers the number of internal memory accesses of the process in the processor when balancing the load of processor, migrates the process with less number of accesses, can reduce the probability of migrated process accessing remote memory, while reducing the load of processor, improve the overall operation efficiency of system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of operating systems, and in particular, to a multi-processor load balancing method, a computing device and a storage medium. BACKGROUND

[0002] With the development of computer technology, in order to realize the deployment of high-performance computers, multiple processors will be deployed in the computer, and each processor also corresponds to the deployment of an internal memory. In order to enable each processor to efficiently access the internal memory without being limited by the total access bandwidth of the memory, a non-uniform memory access architecture (NUMA: Non Uniform Memory Access Architecture) for processors and internal memories is developed.

[0003] In the prior art, the non-uniform memory access architecture allows each processor to access the internal memory using a separate memory channel. Each processor can access local memory and remote memory. The local memory is the memory that the processor can directly access through the connection with the internal memory; and the remote memory needs to be accessed through the connection with other processors. The speed of the processor accessing the local memory is faster, and the speed of the processor accessing the remote memory is faster. In order to fully utilize the computing power of the processor, the NUMA will migrate processes to different processors, increase the probability of process accessing remote memory, and consume a large amount of performance of the processor, resulting in a decline in the overall performance of the system.

[0004] Therefore, a new multi-processor load balancing method is needed. SUMMARY

[0005] Therefore, the present application provides a multi-processor load balancing method to try to solve or at least alleviate the above problems.

[0006] According to one aspect of the present application, a multi-processor load balancing method is provided, which is suitable for being executed in a computing device including a plurality of processors and a plurality of internal memories, and the method comprises the steps of: obtaining a load value of each processor, taking the processor with the highest load value as a target processor; determining a process with the least number of accesses to the internal memory from a plurality of processes included in the target processor to obtain a target process; and migrating the target process to another processor for running to reduce the load value of the target processor.

[0007] Optionally, in the method according to the present application, further comprising the steps of: modifying a page parameter of a memory page accessed by the process in the internal memory; triggering a number of times of page fault interrupts according to the modified page parameter when determining that the process accesses the memory page; and taking the number of times of triggering as the number of accesses of the process to the internal memory.

[0008] Optionally, the method according to the present application further comprises the step of: setting the access times of the new process when the new process is established; and adding a node corresponding to the new process in the red-black tree according to the access times of the new process.

[0009] Optionally, the method according to the present application further comprises the step of: when the access times of the process to the internal memory change, re-determining the color and the parent node of the node corresponding to the process in the red-black tree to obtain a new red-black tree.

[0010] Optionally, the method according to the present application further comprises the step of: obtaining the red-black tree of the process of the target processor; and determining the target process in the target processor according to the red-black tree of the process of the target processor.

[0011] Optionally, the method according to the present application further comprises the step of: traversing the red-black tree to determine the node with the least access times in the red-black tree; and determining the process corresponding to the node with the least access times as the target process in the target processor.

[0012] Optionally, the method according to the present application further comprises the step of: obtaining the red-black tree of the process of the target processor; and determining the target process in the target processor according to the red-black tree of the process of the target processor.

[0013] Optionally, the method according to the present application further comprises the step of: removing the node corresponding to the target process in the red-black tree to obtain a new red-black tree after the target process is migrated to another processor to execute; and re-determining the process with the least access times to the internal memory in the target processor according to the new red-black tree.

[0014] According to another aspect of the present application, there is provided a computing device comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs comprise instructions for performing the method for load balancing of multiple processors according to the present application.

[0015] According to another aspect of the present application, there is provided a computer readable storage medium storing one or more programs, the one or more programs comprising instructions that, when executed by a computing device, cause the computing device to perform the method for load balancing of multiple processors according to the present application.

[0016] The application discloses a kind of multi-processor load balancing method, suitable for being executed in computing device.The computing device includes internal memory, and the application is by obtaining the load value of each processor, the processor with the highest load value is regarded as target processor, so that the processor with high load value is balanced, and the processor with low load rate executes more processing tasks, to realize the improvement of system performance.Then from the multiple processes included in target processor, the process with least internal memory access frequency is determined to obtain target process.Through the migration of the process with least access frequency, the probability of increasing remote memory access after the target process is migrated can be reduced.The target process is migrated to other processor to run, to reduce the load value of target processor, so as to improve the overall operation efficiency of system.In the application, when balancing the load of processor, the processor with high load is balanced, and the access frequency of process in processor to internal memory is fully considered, the process with less access frequency is migrated, which can reduce the probability of remote memory access of the migrated process, reduce the load of processor, and improve the overall operation efficiency of system. BRIEF DESCRIPTION OF DRAWINGS

[0017] To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings. These aspects are indicative of various ways in which the principles disclosed herein can be practiced and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The above-described and other aspects of the application disclosed herein will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals refer to like elements throughout. The application disclosure set forth herein describes and illustrates various aspects of the present application and is not intended to be limited to the specific embodiments

[0018] Figure 1 A schematic diagram showing running application and operating system in computing device according to one exemplary embodiment of the application is shown;

[0019] Figure 2 A structural block diagram of computing device 200 according to one exemplary embodiment of the application is shown; and

[0020] Figure 3 A flowchart showing multi-processor load balancing method 300 according to one exemplary embodiment of the application is shown. DETAILED DESCRIPTION

[0021] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are illustrated, it is to be understood that the present application is not limited to the embodiments described herein, but can be practiced with variation within the scope and spirit of the present application. Rather, the embodiments are provided as exemplary of the application so as to convey the scope of the present application to those skilled in the art. The same reference numbers in different drawings identify the same or similar elements.

[0022] Figure 1 A schematic diagram of a computing device including multiple processors is shown according to an exemplary embodiment of the present application. As shown in Figure 1 The computing device 200 includes processors, a first processor 111 to a fourth processor 114. Figure 1 The number of processors included in the computing device 200 shown is only an example, and the present application does not limit the number of processors in the computing device 200.

[0023] Each processor is directly connected with a local memory, and can access a remote memory through other processors, and each remote memory is the local memory of a corresponding processor. In the NUMA mode, the storage space contributed by all internal memories in the computing device is evenly distributed to all processors in the computing device. Each processor is directly connected with the distributed internal memory, and forms a NUMA node with the directly connected internal memory. The memory in the NUMA node where the processor is located is the local memory, and the memory in other external NUMA nodes is the remote memory. When the processor accesses the directly connected local memory in the NUMA node, the speed is faster; when accessing other remote memories, communication through other processors is required, and access is therefore slower.

[0024] As shown in Figure 1 The computing device 200 includes multiple internal memories, a first internal memory 115 to a fourth internal memory 118. The first internal memory 115 is connected to the first processor 111 and serves as the local memory of the first processor 111. The second internal memory 116 is connected to the second processor 112 and serves as the local memory of the second processor 112. The third internal memory 117 is connected to the third processor 113 and serves as the local memory of the third processor 113. The fourth internal memory 118 is connected to the fourth processor 114 and serves as the local memory of the fourth processor 114. In the computing device 200, the second internal memory 116 to the fourth internal memory 118 are remote memories of the first processor 111. When the first processor 111 wants to access the remote memories, it must access the corresponding directly connected processors of the remote memories. For example, when the first processor 111 wants to access the remote memory, the second internal memory 116, it needs to communicate through the second processor 112 to access the data in the second internal memory 116, which is slower.

[0025] The first processor 111 to the fourth processor 114, the first internal memory 115 to the fourth internal memory 118, and the communication resources between the components together form a multi-core architecture 110 of the computing device 200. The computing device 200 also includes an operating system 120, and the present application does not limit the type of the operating system 120.

[0026] Figure 2 A structural block diagram of a computing device 200 in accordance with one exemplary embodiment of the present application is shown. As shown, in a basic configuration 202, the computing device 200 typically includes at least one processing unit 204 and system memory 206. A memory bus 208 can be used for communicating between the processing unit 204 and the system memory 206. Figure 2

[0027] Depending on the desired configuration, the processing unit 204 can be of any type, including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. The processing unit 204 can include one more levels of caching, such as a level one cache 210 and a level two cache 212, a processor core 214, and registers 216. The example processor core 214 can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP Core), or any combination thereof. An memory controller 218 can also be used with the processing unit 204, or in some implementations, the memory controller 218 can be an internal part of the processing unit 204.

[0028] Depending on the desired configuration, the system memory 206 can be of any type, including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.) or any combination thereof. The system memory 206 can include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the programs 222 can include instructions 223 for implementing the method 300 according to the present application, which can be executed by the one or more processors 204 using the program data 228.

[0029] The computing device 200 can also include a storage interface bus 234. The storage interface bus 234 enables communication between the storage devices 232 (e.g., removable storage 236 and non-removable storage 238) and the basic configuration 202 via the bus / interface controller 230. The operating system 220, the one or more programs 222, and the program data 224 can be stored in the removable storage 236 and / or the non-removable storage 238 as described above. These elements can be loaded into the system memory 206 and executed by the one or more processors 204 as described above, using the operating system 220, the one or more programs 222, and the program data 224 stored in the removable storage 236 and / or the non-removable storage 238 as described above.

[0030] ​The computing device 200 can also include an interface bus 240 for facilitating communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus / interface controller 230. Example output devices 242 include a graphics processing unit 248 and an audio processing unit 250, which can be configured to facilitate communication to various external devices such as a display or speakers via one or more A / V ports 252. Example peripheral interfaces 244 include a serial interface controller 254 or a parallel interface controller 256, which can be configured to facilitate communication to various external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripheral devices (e.g., printer, scanner) via one or more I / O ports 258. An example communication device 246 includes a network controller 260, which can be arranged to facilitate communication to one or more other computing devices 200 over a network communication link via one or more communication ports 264.

[0031] The network communication link can be one example of a communication media. Communication media can typically be embodied by computer readable instructions, data structures, program modules, and / or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and can include any information delivery media. A "modulated data signal" can be a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media can include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), microwave, infrared (IR) and other wireless media. The term computer readable media as used herein can include both storage media and communication media.

[0032] In the computing device 200 according to the present application, the program 222 includes a plurality of program instructions of the multi-processor load balancing method 300, which can instruct the processor 204 to execute part of the steps in the multi-processor load balancing method 300 run in the computing device 200 of the present application, so that the parts in the computing device 200 implement load balancing for the multi-processor by executing the multi-processor load balancing method 300 of the present application.

[0033] The computing device 200 can be implemented as a server, e.g., a file server, a database server, an application server, etc., and the electronic device can be a personal digital assistant (PDA), a wireless web device, an application-specific device, or a hybrid device that can include any of the above functions. It can be implemented as a personal computer including desktop computer and notebook computer configurations, and in some embodiments, the computing device 200 is configured as the multi-processor load balancing method 300.

[0034] Figure 3 A flowchart of a multi-processor load balancing method 300 according to an exemplary embodiment of the present application is shown. The multi-processor load balancing method 300 is suitable for running in a computing device, such as the computing device 200 shown in FIG. 1. Figure 1 and Figure 2 The computing device 200 includes a plurality of processors and a plurality of internal memories.

[0035] According to an embodiment of the present application, the plurality of processors are constructed by a NUMA architecture, which allocates all memory resources in the computing device 200 to each processor, so that each processor is directly connected to one internal memory. Each processor, the internal memory directly connected to the processor, and the communication resources of the processor form a node, i.e., a NUMA node.

[0036] One or more NUMA nodes can form a primary scheduling domain, a plurality of primary scheduling domains can form a secondary scheduling domain, a plurality of secondary scheduling domains can form a tertiary scheduling domain, and so on. A plurality of hierarchical scheduling domains can be constructed by NUMA nodes, and a lower-level scheduling domain can form a higher-level scheduling domain.

[0037] Scheduling rules can be set in each scheduling domain, such as scheduling rules for processes or memory pages between a plurality of scheduling domains at a certain level. The scheduling rules refer to the conditions and ways of scheduling processes or memory pages. Different scheduling rules can be set for different levels of scheduling domains according to the multi-core architecture, which can maximize the overall performance of the computer.

[0038] The present application can balance the load of the processors at any level by the multi-processor load balancing method, and the present application does not limit the scheduling domains to which the multi-processor load balancing method is applied and the number of processors included.

[0039] First, step S310 is performed to obtain the load value of each processor, and the processor with the highest load value is taken as the target processor. According to the load value of each processor, the processor with the highest load value is determined, so that it is determined which processor needs to be balanced.

[0040] When determining the load value of the processor, the number of processes in the process queue of the processor can be used to determine the load value. If the number of processes in the process queue of the processor is large, it indicates that the load value of the processor is high, and if the number of processes in the process queue of the processor is small, it indicates that the load value of the processor is low. The present application does not limit the specific calculation method of the load value, and the load value can be calculated by the process queue and the number of cores of the processor, such as: if the process queue has 20 processes and the number of cores of the processor is 10, the load value of the processor can be calculated as 2.

[0041] Subsequently, step S320 is performed to determine a process with the least number of internal memory accesses from a plurality of processes included in the target processor to obtain a target process. After the processor with the largest load value is determined as the target processor, a process to be migrated is selected from the target processor.

[0042] The number of internal memory accesses of each process in each processor in the computing device is counted in advance. Specifically, the memory page accessed by the process in the internal memory is modified, and the page parameters of the memory page are modified. Then, when the process accesses the memory page, the number of times of triggering the page fault interrupt is triggered according to the modified page parameters, and the number of times of triggering the page fault interrupt is taken as the number of internal memory accesses of the process.

[0043] According to an embodiment of the present application, one or more memory pages accessed by the process in the internal memory are added to the page parameters of each memory page, and the table entry PAGE_NONE is added to the page parameters of each memory page to trigger the page fault interrupt when the process accesses the memory page. The number of times of triggering the page fault interrupt when the process is created is 0, and the number of internal memory accesses of the process is also 0. Each time the process triggers the page fault interrupt, the number of times of triggering the page fault interrupt is incremented by 1, and the number of internal memory accesses of the process is also incremented by 1. The number of times of triggering the page fault interrupt after the process is created is counted, and the number of times of triggering the page fault interrupt is taken as the number of internal memory accesses of the process.

[0044] When the page parameters of the memory page accessed by the process are modified, not only the page parameters of the local memory accessed by the process are modified, but also the page parameters of the remote memory accessed by the process are modified, so that the number of internal memory accesses of the process is comprehensively counted.

[0045] According to an embodiment of the present application, the number of internal memory accesses of each process in the processor is determined according to the mode, and a red-black tree is constructed according to each process and the corresponding number of internal memory accesses. Each node in the red-black tree corresponds to a process in the processor. The red-black tree is a self-balancing binary search tree, and the balance of the binary search tree is maintained through specific operations when insertion and deletion operations are performed, so that high search performance is obtained. The process with the least number of internal memory accesses in the processor is searched through the red-black tree, and high efficiency is obtained. The red-black tree ensures that no search path is longer than twice the length of other paths.

[0046] When the red-black tree is constructed, the number of internal memory accesses of each process is used for construction. In the constructed red-black tree, the number of internal memory accesses of the process corresponding to the root node is the median of the number of internal memory accesses of all processes in the processor. The number of internal memory accesses of all processes corresponding to the left child of the root node is greater than or equal to the number of internal memory accesses of the process corresponding to the root node. The number of internal memory accesses of all processes corresponding to the right child of the root node is less than or equal to the number of internal memory accesses of the process corresponding to the root node.

[0047] According to one embodiment of the present application, when a new process is established, the access times of the new process is set; and according to the access times of the new process, the node corresponding to the new process is added in the red-black tree. Specifically, the access times of the new process is set as 0, the parent node to which the node corresponding to the new process with the access times of 0 belongs is found in the red-black tree, and the new node corresponding to the new process is inserted after the parent node is found, and the color of the new node is set.

[0048] According to one embodiment of the present application, since the process continuously accesses the internal memory during the running process, when the page fault interrupt is triggered when the process accesses the internal memory, and the corresponding access times is updated, the position of the node of the process in the red-black tree also needs to be changed. When the access times of the process to the internal memory is changed, the color and the parent node to which the node of the process in the red-black tree belongs are re-determined to obtain a new red-black tree. If according to the changed access times, the node of the process still needs to be under the original parent node, the red-black tree is not changed. If according to the changed access times, the node needs to be moved, the new parent node and the color of the node are re-determined, and the color and the parent node to which the other nodes affected by the position change of the node belong are also re-determined to obtain a new red-black tree.

[0049] When the process with the least access times to the internal memory is determined from a plurality of processes included in the target processor, the red-black tree of the processes of the target processor is obtained; and then the target process in the target processor is determined according to the red-black tree of the processes of the target processor. Specifically, the red-black tree is traversed to determine the node with the least access times in the red-black tree, and the process corresponding to the node with the least access times is taken as the target process in the target processor.

[0050] Subsequently, step S330 is performed to migrate the target process to other processors to run, so as to reduce the load value of the target processor. Since the target process to be migrated has the least access times to the internal memory, the probability of accessing the remote memory is the lowest, so that the running efficiency of the processor is guaranteed to the maximum extent while the load of the processor is reduced.

[0051] According to one embodiment of the present application, after the target process is migrated to other processors to execute, the node corresponding to the target process in the red-black tree is removed to obtain a new red-black tree, so as to re-determine the process with the least access times to the internal memory in the target processor according to the new red-black tree. After the node corresponding to the target process in the red-black tree is removed, the parent node of the node corresponding to the target process has a vacancy, and the child nodes under the node corresponding to the target process need to re-determine the parent node and the color to obtain a new red-black tree.

[0052] The application discloses a kind of multi-processor load balancing method, suitable for being executed in computing device. Computing device includes internal memory, the application is by obtaining the load value of each processor, the processor with the highest load value is as target processor, so that the processor with high load value is balanced, let the processor with low load rate execute more processing tasks, realize the improvement of system performance. Then from the target processor includes multiple processes, determine the process with least internal memory access frequency, obtain target process. By the least process migration of access frequency, the probability of increasing remote memory access of target process after migration can be reduced. Target process is migrated to other processor and runs, reduce the load value of target processor, so as to improve the overall operation efficiency of system. In the application, when the processor is balanced, the processor with high load is balanced, and the access frequency of process in the processor to internal memory is fully considered, the process with less access frequency is migrated, the probability of remote memory access of migrated process can be reduced, the load of processor is reduced, and the overall operation efficiency of system is improved.

[0053] In the description provided herein, a large number of specific details are illustrated. It is understood, however, that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0054] Similarly, it is to be understood that the features of the present application that are of a functionally technical nature can be performed by any technical means, for example hardware components or software components, including ones that are not explicitly described herein.

[0055] It should be understood by those skilled in the art that the modules or units or groups of the devices in the examples disclosed herein can be arranged in the device as described in the examples, or alternatively can be located in one or more devices different from the device in the examples. The modules in the foregoing examples can be combined as one module or can be further divided into multiple sub-modules.

[0056] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adapted and placed in one or more apparatuses other than the embodiments. The modules or units or inter-group combinations in the embodiments can be combined into one module or unit or inter-group, and further can be divided into a plurality of sub-modules or sub-units or sub-groups. Any combination of all the features disclosed in the specification and any method or device so disclosed can be taken in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless explicitly stated otherwise, each feature disclosed in the specification can be replaced by an alternative feature serving the same, equivalent or similar purpose.

[0057] Furthermore, those skilled in the art will appreciate that different embodiments of the application have different features and thus not all embodiments will exhibit all of the features described herewith, or some embodiments will exhibit and / or will not exhibit a number of the features described herewith. It is, therefore, anticipated that various embodiments of the application will exhibit different combinations of the features described herewith and / or will exhibit a number of its own unique features, and such features, in their entirety, do not

[0058] Furthermore, some of the embodiments described herein are of a machine-implemented method or process that can be embodied in a device used for the performance of such method or process. Therefore, the machine-implemented method or process embodiments described herein are examples of apparatuses for performing such method or process.

[0059] The various techniques described herein can be implemented in connection with hardware or software or, where appropriate, with a combination of both. Thus, the methods and apparatus of the application, or certain aspects or portions thereof, can take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the subject application.

[0060] Where a method, process, or algorithm disclosed herein is implemented in code, the program code is stored in a storage medium associated with the process, or is stored in a storage medium that is transitory if required to be so by law. In either case, the storage medium is non-transitory in the sense that the program code is not a transitory propagating signal per se. In some embodiments, the storage medium is a machine-readable storage medium. In some embodiments, the storage medium is a machine- readable storage medium that is non-transitory.

[0061] By way of example, and not limitation, computer-readable media include computer storage media and communication media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer readable media modulated data signals carry computer readable program code in a carrier wave or other transport mechanism and includes any information delivery media. Combinations of the any of the above are also included within the scope of computer readable media.

[0062] As used herein, unless otherwise indicated, the use of the ordinal adjectives such as "first", "second", "third", etc., merely to distinguish different instances of an object and does not imply a time, spatial, ranking, or any other ordering of the objects.

[0063] Although the application has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the application. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the application. The embodiments were chosen and described in order to best explain the principles of the application and the information thus enables others skilled in the art to best utilize the application. Accordingly, the scope of the application is to be construed as encompassing all equivalents of the subject matter recited in the claims appended hereto met by any of the compositions, methods, and articles specifically discussed above and those with modifications as will be apparent to those with ordinary skill in the art, the equivalent ranges having been specifically indicated in the disclosure.

Claims

1.A method for load balancing of a plurality of processors, adapted to be executed in a computing device, the computing device comprising a plurality of processors and a plurality of internal memories, the processors, the corresponding directly connected internal memories and the communication resources of the processors form a node, one or more nodes form a primary scheduling domain, a plurality of primary scheduling domains form a secondary scheduling domain, and a plurality of secondary scheduling domains form a tertiary scheduling domain, the method comprising the steps of: setting scheduling rules of processes in each scheduling domain, including: obtaining a load value of each processor in a scheduling domain of a level, and taking the processor with the highest load value as a target processor; determining a process with the least access times to the internal memory from a plurality of processes included in the target processor to obtain a target process; and migrating the target process to other processors in the scheduling domain to reduce the load value of the target processor; wherein the method further comprises the steps of: modifying a page parameter of a memory page in the internal memory accessed by the process; triggering a number of times of triggering a page fault interrupt according to the modified page parameter when it is determined that the process accesses the memory page; and taking the number of times of triggering the page fault interrupt as the access times of the process to the internal memory; the method further comprises the steps of: determining the access times of each process in the processor to the internal memory; and constructing a red-black tree according to each process and the corresponding access times, each node in the red-black tree corresponding to a process in the processor; the step of determining the process with the least access times to the internal memory from the plurality of processes included in the target processor comprises the steps of: obtaining a red-black tree of processes of the target processor; and determining the target process in the target processor according to the red-black tree of processes of the target processor, including: traversing the red-black tree to determine a node with the least access times in the red-black tree; and taking a process corresponding to the node with the least access times as the target process in the target processor; the method further comprises the steps of: setting the access times of a new process when the new process is established; and adding a node corresponding to the new process in the red-black tree according to the access times of the new process; the method further comprises the steps of: when the access times of the process to the internal memory change, re-determining the color and the parent node of a node corresponding to a process in the red-black tree to obtain a new red-black tree; and the method further comprises the steps of: removing the node corresponding to the target process in the red-black tree to obtain a new red-black tree after the target process is migrated to other processors to execute, so as to re-determine the process with the least access times to the internal memory in the target processor according to the new red-black tree. 5.A computing device comprising: one or more processors; a memory; and one or more means comprising instructions for performing any one of the methods of claims 1-4. 6.A computer-readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform any one of the methods of claims 1-4. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The method of claim 1, wherein, ​ ​ ​ 3. The method of claim 2, wherein, ​ ​ 4. The method of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ ​

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