A CPU detection device with multifunctional applications

Abstract

The present invention discloses a multifunctional application CPU detection device, belonging to the field of CPU testing and application, including power module, clock module, power-on reset and configuration STM32, CPU and its peripheral function circuit; the peripheral function circuit of the CPU includes JTAG interface, serial port module, SD module, DDR3 storage module, SPI interface, I2C interface, EBC bus module, USB module, SATA module, GMAC network module, Rapid IO module and PCIE module; the power-on reset and configuration STM32 control the power-on timing of the CPU to meet the startup requirements of the CPU, and the system software supports multiple operating systems including Linux. The multifunctional application CPU detection device provided by the present invention can test all functional modules of the CPU with one click, and can also be used as a development board to realize function expansion development by accessing various devices, and debug and learn software.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU testing and application, and in particular to a multifunctional CPU detection device. Background Art

[0002] At present, with the rapid development of computer hardware integration technology, the functions of the core components of computers, such as motherboards and CPUs, are becoming increasingly sophisticated and complex. The CPU should undergo corresponding testing procedures before leaving the factory to test whether its quality is intact. The traditional approach is to design a real-installation test board, and all modules should try to follow the principle of easy testing and convenient operation. The board can only be used as a test board. After the chip test is completed, the board is idle. For the functional verification and learning and development needs of the CPU, another set of full-interface functional boards must be designed. In fact, most of the modules of these two boards are the same, so it is entirely possible to design a multi-functional detection device that not only meets the test screening requirements, but also has enough peripheral interfaces, can be connected to various devices to realize functional expansion and development, and can debug and learn software. One board has multiple uses, which makes the utilization rate of the board higher. Summary of the invention

[0003] The object of the present invention is to provide a CPU detection device with multifunctional applications to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a multifunctional application CPU detection device, including a power module, a clock module, a power-on reset and configuration STM32, a CPU and its peripheral function circuits;

[0005] The peripheral functional circuits of the CPU include a JTAG interface, a serial port module, an SD module, a DDR3 storage module, an SPI interface, an I2C interface, an EBC bus module, a USB module, a SATA module, a GMAC network module, a Rapid IO module and a PCIE module; the power-on reset and configuration STM32 control the power-on timing of the CPU to meet the startup requirements of the CPU, and the system software supports multiple operating systems including Linux.

[0006] Optionally, the JTAG interface is a standard interface, which is connected to the downloader for program downloading and debugging; channel 0 of the serial port module views the system print information through the DB9 serial port socket, and channels 1 / 2 are interconnected for transceiver testing; the SD module provides two 8-bit wide SD signals, one of which is equipped with a 256G EMMC chip to increase storage, and the other is connected to the card slot to insert an SD card.

[0007] Optionally, the DDR3 storage module uses 2GB DDR3 memory particles as main memory for storing program code, data, and operating system; the two I2C interfaces can select interconnection testing, or access external EEPROM chips and other chips with I2C interfaces, such as clock chips and IO expansion chips.

[0008] Optionally, the SPI Flash mounted on the SPI interface and the Nor Flash on the EBC interface can both be used to place system programs, and the software determines the Flash used to load the program by reading specific flag information.

[0009] Optionally, the USB module has two USB3.0 interfaces, and data is stored by plugging in a USB flash drive; the SATA module has four SATA3.0 interfaces, and storage is increased by placing a solid-state drive; the PCIE module has three PCIE3.0 interfaces, and expansion is performed by inserting a standard PCIE device card; the QSFP interface of the Rapid IO module and the SFP+ interface of the 10 Gigabit network communicate with the outside world through cables.

[0010] Optionally, the GMAC network module is connected to the RJ45 interface through the Gigabit network PHY chip 88E1111, a Gigabit network cable is used externally, and the TCP or UDP protocol is used on the software for communication testing. In the test mode, the two RJ45s are interconnected for mutual testing.

[0011] Optionally, the Nor Flash of the EBC bus module adopts the 16-bit width Nor Flash of Micron's S29GL512T.

[0012] Optionally, the model adopted by the power-on reset and configuration STM32 is the STM32F103 series of ST company, which has abundant peripherals including timer, ADC, DAC, SPI, I2C, UART, and IO port, and has a built-in standard JTAG interface. Online programming is achieved through the JTAG interface, and its embedded Flash ensures that the programmed data will not be lost due to power failure.

[0013] Optionally, the power module is powered by an ATX power supply, providing four voltages of 12V, 5V, 3.3V, and 5VSB, and generating multiple voltages required by the CPU and other peripheral circuits through a power chip; the clock module uses IDT's 9FGV0841 clock chip, providing 8-channel LP-HCSL level 100M differential clocks, and converting the LP-HCSL level into LVDS level through a matching circuit.

[0014] Optionally, the power module, the clock module, the power-on reset and configuration STM32, the CPU and its peripheral functional circuits are all integrated and mounted on a circuit board.

[0015] The multifunctional CPU detection device provided by the present invention can test all functional modules of the CPU with one click, and display the test results through the serial port and the test result indicator light, so as to screen chips, improve the stability and effectiveness of CPU use and screening, effectively shorten the test time, and reduce the test difficulty and the complexity of test operations; the multifunctional CPU detection device provided by the present invention can also be used as a development board, and the system software supports multiple operating systems such as Linux, and provides a standard PCIE3.0 slot, USB3.0 socket, SATA socket, MSATA socket, SD card slot, Gigabit RJ45 network port, SFP+ interface, QSFP interface, DB9 serial port and other rich peripheral interfaces, which can realize function expansion development by connecting to various devices, and perform software debugging and learning. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a CPU detection device for multifunctional applications provided by the present invention;

[0017] Figure 2 A topological block diagram of the power system in a CPU detection device for multifunctional applications;

[0018] Figure 3 A topological block diagram of the clock system in a CPU detection device for multi-functional applications;

[0019] Figure 4 The schematic diagram of the DDR3 memory module in the CPU detection device for multi-functional applications;

[0020] Figure 5 The schematic diagram of the USB module in the CPU detection device for multi-functional applications;

[0021] Figure 6 The schematic diagram of the SATA module in the CPU detection device for multi-functional applications;

[0022] Figure 7 The schematic diagram of the Rapid IO module in the CPU detection device for multi-functional applications;

[0023] Figure 8 The schematic diagram of the XGMII module in the CPU detection device for multi-function applications;

[0024] Fig. 9 Schematic diagram of CPU power consumption test of a CPU detection device for multi-function applications. DETAILED DESCRIPTION

[0025] The following is a further detailed description of a multifunctional CPU detection device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0026] like Figure 1 The schematic diagram of the principle of a multifunctional CPU detection device provided by the present invention is shown, which includes a power module (i.e., a power system), a clock module (i.e., a clock system), a power-on reset and configuration STM32, a CPU and its peripheral functional circuits. The peripheral functional circuits of the CPU include a JTAG interface, a DDR3 storage module, a GMAC network module, an EBC bus module, a PCIE module, a Rapid IO module, a SATA module, an SPI interface, a serial port module, etc. The power module, the clock module, the power-on reset and configuration STM32, the CPU and its peripheral functional circuits are all integrated and installed on a circuit board. The CPU detection device can have multiple uses: one is to place the CPU in a test socket on the circuit board, and all functional modules of the CPU can be tested with one click, and the test results can be displayed by connecting the test result LED indicator through power-on reset and configuration STM32, so as to screen the chip. The overall design structure is orderly, the functions are reasonable, and the results are displayed concisely and clearly, which improves the stability and effectiveness of CPU use and screening, can effectively shorten the test time, and reduce the test difficulty and complexity of test operations; the second is to directly use the CPU detection device as a development board. The system software supports multiple operating systems such as Linux. The device provides standard PCIE3.0 slots, USB3.0 female sockets, SATA sockets, MSATA sockets, SD card slots, Gigabit RJ45 network ports, SFP+ interfaces, QSFP interfaces, DB9 serial ports and other rich peripheral interfaces. Functional expansion development can be achieved by connecting to various devices, and software debugging and learning can be carried out.

[0027] See also Figure 2The power module is powered by an ATX power supply with a maximum power of 450W and an input voltage of 200-240V. It can provide four voltages of 12V, 5V, 3.3V, and 5VSB. The power chip generates multiple voltages required by the CPU and other peripheral circuits. The LTM4630 two-way DCDC power chip of LINEAR (Lingte Company) can provide a maximum current of 18A per channel, which is used to power the CPU core; the LTM4644 four-way DCDC power chip of LINEA can provide two groups of maximum 8A current by connecting two in parallel; the TPS54620 DCDC circuit of TI (Texas Instruments) can provide a maximum power supply of 6A; the TPS74401 LDO circuit of TI can provide a maximum power supply of 3A; the TPS2560 LDO circuit of TI can provide 5V voltage for USB; the TPS51200 power chip of TI is dedicated to DDR3VTT and VREF power supply.

[0028] See also Figure 3 The clock module adopts IDT's 9FGV0841 clock chip, which can provide 8 LP-HCSL level 100M differential clocks, and convert the LP-HCSL level into LVDS level through a matching circuit; it adopts Rena's 841N254B clock chip, which can provide 2 LVDS differential clocks and 2 HCSL differential clocks. Through configuration, it can output the 156.25M differential clock required by the CPU, and then convert the HCSL level into the LVDS level through a matching circuit.

[0029] The DDR3 memory module in the present invention uses Samsung's K4B4G1646E-BCMA 16-bit wide DDR3 particles. Figure 4 As shown, 64-bit data width and 8-bit ECC check require 5 DDR3 chips, and the capacity of each chip is 512MB.

[0030] like Figure 5 As shown, the USB module in the present invention adopts a standard USB3.0 female socket, and the signal is isolated and inserted for protection through a common mode inductor and an ESD protection chip.

[0031] See also Figure 6 In order to be compatible with testing and development learning, the SATA module of this CPU detection device provides two interfaces CONH2 and CONH8, both of which are connected to the SATA module. When doing CPU screening tests, the solid-state hard drive can be directly installed on the MSATA seat for data reading and writing tests. When doing development board software debugging and learning, a large-capacity mechanical hard drive can also be connected for storage through a conventional SATA cable.

[0032] See also Figure 7The Rapid IO module in the CPU detection device of the present invention adopts a QSFP interface. When performing a CPU screening test, the Loop Back module of the QSFP can be connected to perform a loopback test. When performing software debugging and learning on a development board, data communication can be performed with a switch through the optical fiber of the QSFP interface.

[0033] See also Figure 8 The XGAMC module in the CPU detection device of the present invention adopts an SFP+ interface. When performing CPU screening tests, the Loop Back module of the SFP+ can be connected to perform loopback tests. When performing development board software debugging and learning, data communication can be performed with the X86 10 Gigabit network card through the optical fiber of the SFP interface.

[0034] See also Fig. 9 In the present invention, LINEAR's LTC2991 monitoring chip is selected. The voltage, current and temperature values ​​monitored by the chip can be read through the I2C interface. The power consumption value of the CPU can be obtained through data analysis and conversion. A simple circuit can meet the chip power consumption evaluation requirements at three temperatures, high and low, during CPU test screening.

[0035] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A CPU detection device for multifunctional applications, characterized in that: Including power module, clock module, power-on reset and configuration of STM32, CPU and its peripheral function circuits; The peripheral function circuit of the CPU includes a JTAG interface, a serial port module, an SD module, a DDR3 storage module, an SPI interface, an I2C interface, an EBC bus module, a USB module, a SATA module, a GMAC network module, a RapidIO module and a PCIE module; the power-on reset and configuration STM32 control the power-on timing of the CPU to meet the startup requirements of the CPU, and the system software supports multiple operating systems including Linux; the CPU detection device can test all functional modules of the CPU, and display the test results by connecting the test result LED indicator through power-on reset and configuration STM32, so as to screen the chip; the CPU detection device or as a development board, the system software supports multiple operating systems, realizes function expansion development by accessing various devices, and performs software debugging and learning.

2. The CPU detection device for multifunctional applications as claimed in claim 1, characterized in that: The JTAG interface is a standard interface, which is connected to the downloader for program downloading and debugging; channel 0 of the serial port module views the system print information through the DB9 serial port, and channels 1 / 2 are interconnected for transceiver testing; the SD module provides two 8-bit wide SD signals, one of which is mounted with a 256G EMMC chip to increase storage, and the other is connected to the card slot to insert an SD card.

3. The CPU detection device for multifunctional applications as claimed in claim 2, characterized in that: The DDR3 storage module uses 2GB DDR3 memory particles as main memory for storing program code, data, and operating system; the two I2C interfaces can select interconnection testing, or access external EEPROM chips and other chips with I2C interfaces.

4. The CPU detection device for multifunctional applications as claimed in claim 3, characterized in that: The SPIFlash mounted on the SPI interface and the NorFlash of the EBC bus module can both be used to place system programs, and the software determines the Flash used to load the program by reading specific flag information.

5. The CPU detection device for multifunctional applications as claimed in claim 4, characterized in that: The USB module has two USB3.0 interfaces, which can be used to store data by plugging in a USB flash drive; the SATA module has four SATA3.0 interfaces, which can be used to increase storage by placing a solid-state drive; the PCIE module has three PCIE3.0 interfaces, which can be expanded by inserting a standard PCIE device card; the QSFP interface of the RapidIO module and the SFP+ interface of the 10G network communicate with the outside world through cables.

6. The CPU detection device for multifunctional applications as claimed in claim 5, characterized in that: The GMAC network module is connected to the RJ45 interface through the Gigabit network PHY chip 88E1111, a Gigabit network cable is used externally, and the TCP or UDP protocol is used on the software for communication testing. In the test mode, two RJ45s are interconnected for mutual testing.

7. The CPU detection device for multifunctional applications as claimed in claim 6, characterized in that: The Nor Flash of the EBC bus module adopts the 16-bit width Nor Flash of Micron's S29GL512T.

8. The CPU detection device for multifunctional applications as claimed in claim 7, characterized in that: The model adopted for the power-on reset and configuration STM32 is the STM32F103 series of ST Company, which has abundant peripherals including timer, ADC, DAC, SPI, I2C, UART, and IO port, and has a built-in standard JTAG interface. Online programming is realized through the JTAG interface, and its embedded Flash ensures that the programmed data will not be lost due to power failure.

9. The CPU detection device for multifunctional applications as claimed in claim 8, characterized in that: The power module adopts ATX power supply, provides four voltages of 12V, 5V, 3.3V, and 5VSB, and generates multiple voltages required by the CPU and other peripheral circuits through the power chip; the clock module adopts IDT's 9FGV0841 clock chip, provides 8 LP-HCSL level 100M differential clocks, and converts the LP-HCSL level into LVDS level through the matching circuit.

10. The CPU detection device for multifunctional applications according to any one of claims 1 to 9, characterized in that: The power supply module, the clock module, the power-on reset and configuration STM32, the CPU and its peripheral functional circuits are all integrated and mounted on a circuit board.

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