Chip package structure and electronic device

Abstract

The application provides a chip packaging structure and an electronic device. The chip packaging structure comprises a substrate, a DBC substrate and a switching device which are sequentially stacked, wherein the substrate comprises a base island and an insulating part, the base island is used for supporting the DBC substrate, the switching device comprises a body structure, a source electrode, a drain electrode and a gate electrode, the source electrode and the gate electrode are located on a surface of the body structure which is away from the DBC substrate, the drain electrode is located on a surface of the body structure which is in contact with the DBC substrate and is connected with the DBC substrate, and the source electrode is connected with the base island through a lead wire. In the chip packaging structure, the source electrode of the switching device is placed at the bottom of the chip packaging structure by connecting the source electrode and the base island through the lead wire without changing the positions of the source electrode, the drain electrode and the gate electrode of the switching device, so that the resistance between the source electrode and the drain electrode is reduced, the parasitic inductance is reduced, and the problem that the parasitic inductance of the packaging structure in the prior art is large and cannot meet the requirements of radio frequency application is solved.

Description

Technical Field

[0001] This application relates to the field of chip packaging, and more specifically, to a chip packaging structure and electronic device. Background Technology

[0002] In the prior art, the switching device is a vertical structure device, that is, the bottom of the chip is the drain of the device, and the top of the chip is the source and gate of the device. This kind of packaging structure has a large parasitic inductance, which can no longer meet the requirements of radio frequency applications.

[0003] Therefore, the existing packaging structure has a large parasitic inductance, which cannot meet the requirements of radio frequency applications.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main purpose of this application is to provide a chip packaging structure and electronic device to solve the problem that the existing packaging structure has large parasitic inductance and cannot meet the requirements of radio frequency applications.

[0006] According to one aspect of the present invention, a chip packaging structure is provided, comprising a substrate, a DBC substrate, and a switching device stacked sequentially, wherein the substrate includes at least one base island and an insulating portion, the insulating portion surrounding the sidewall of the base island, the base island supporting the DBC substrate, the switching device including a body structure, a source, a drain, and a gate, the source and the gate being located on the surface of the body structure away from the DBC substrate, the drain being located on the surface of the body structure in contact with the DBC substrate and connected to the DBC substrate, and the source being connected to the base island via a lead.

[0007] Optionally, the substrate further includes at least one lead region located on the base island, the lead region including a first metal layer located on the surface of the base island.

[0008] Optionally, there are two lead regions, namely a first lead region and a second lead region. The first lead region and the second lead region are located on both sides of the DBC substrate, and the first lead region and the second lead region are centrally symmetrical about the center of the base island.

[0009] Optionally, there are three base islands, namely a first base island, a second base island, and a third base island. The source is connected to the first base island by a lead, the gate is connected to the second base island by a lead, and the drain is connected to the third base island by a lead.

[0010] Optionally, the second base island and the third base island are located on opposite sides of the first base island, and the second base island and the third base island are centrally symmetrical about the center of the substrate.

[0011] Optionally, the DBC substrate includes a third lead region, the third lead region including a second metal layer, the second metal layer being located on the surface of the DBC substrate away from the substrate, and the third lead region being connected to the third base island via leads.

[0012] Optionally, the chip packaging structure includes a packaging cover, which covers the first surface of the substrate and forms a sealed space with the first surface of the substrate, wherein the DBC substrate and the switching device are both located within the sealed space.

[0013] Optionally, the switching device is a SiC JFET.

[0014] Optionally, the DBC substrate includes a third metal layer, a ceramic layer, and a fourth metal layer stacked sequentially, wherein the fourth metal layer is connected to the base island.

[0015] According to another aspect of the present invention, an electronic device is also provided, including a chip packaging structure, wherein the chip packaging structure is any of the chip packaging structures described above.

[0016] In this embodiment of the invention, the chip package structure includes a substrate, a DBC substrate, and a switching device stacked sequentially. The substrate includes a base island and an insulating portion. The base island supports the DBC substrate. The switching device includes a body structure, a source, a drain, and a gate. The source and gate are located on the surface of the body structure away from the DBC substrate, and the drain is located on the surface of the body structure in contact with the DBC substrate and connected to it. The source and base island are connected by leads. In this chip package structure, without changing the positions of the source, drain, and gate of the switching device, connecting the source and base island with leads places the source of the switching device at the bottom of the chip package structure. This reduces the resistance between the source and drain, thereby reducing parasitic inductance and solving the problem of high parasitic inductance in existing package structures that cannot meet the requirements of radio frequency applications. Furthermore, because the source is located at the bottom of the chip package structure, the heat dissipation area of ​​the source is greatly increased, reducing the thermal resistance of the chip and thus improving the chip's heat dissipation capacity and power. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A cross-sectional view of a chip packaging structure according to an embodiment of this application is shown;

[0019] Figure 2 A top view of a chip packaging structure according to an embodiment of this application is shown;

[0020] Figure 3 A cross-sectional view of another chip packaging structure according to an embodiment of this application is shown.

[0021] The above figures include the following reference numerals:

[0022] 10. Substrate; 11. DBC substrate; 12. Switching device; 13. Base island; 14. Insulating part; 15. First lead region; 16. Second lead region; 17. Second base island; 18. Third base island; 19. Third lead region; 20. Gate lead region; 21. Source lead region; 131. First base island. Detailed Implementation

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0027] As mentioned in the background section, the existing packaging structures have large parasitic inductance, which cannot meet the requirements of radio frequency applications. In order to solve the above problems, a typical embodiment of this application provides a chip packaging structure and electronic device.

[0028] According to an embodiment of this application, a chip packaging structure is provided. Figure 1 This is a cross-sectional view of the chip packaging structure according to an embodiment of this application. Figure 2 This is a top view of a chip package structure according to an embodiment of this application. (See attached image.) Figure 1 and Figure 2 As shown, the chip package structure includes a substrate 10, a DBC substrate 11, and a switching device 12 stacked sequentially. The substrate 10 includes at least one base island 13 and an insulating portion 14. The insulating portion 14 surrounds the sidewall of the base island 13, and the base island 13 supports the DBC substrate 11. The switching device 12 includes a body structure, a source, a drain, and a gate. The source and the gate are located on the surface of the body structure away from the DBC substrate 11. The drain is located on the surface of the body structure that contacts the DBC substrate 11 and is connected to the DBC substrate 11. The source is connected to the base island 13 by a lead.

[0029] The aforementioned chip packaging structure includes a substrate, a DBC substrate, and a switching device stacked sequentially. The substrate includes a base island and an insulating portion. The base island supports the DBC substrate. The switching device includes a body structure, a source, a drain, and a gate. The source and gate are located on the surface of the body structure away from the DBC substrate, while the drain is located on the surface of the body structure in contact with and connected to the DBC substrate. The source and base island are connected via leads. In this chip packaging structure, without changing the positions of the source, drain, and gate of the switching device, connecting the source and base island via leads places the source of the switching device at the bottom of the chip packaging structure. This reduces the resistance between the source and drain, thereby reducing parasitic inductance and solving the problem of high parasitic inductance in existing packaging structures that cannot meet the requirements of radio frequency applications. Furthermore, because the source is located at the bottom of the chip packaging structure, the heat dissipation area of ​​the source is greatly increased, reducing the thermal resistance of the chip and thus improving the chip's heat dissipation capacity and power.

[0030] In one specific embodiment, in order to achieve good mechanical and electrical properties, the substrate, the DBC substrate and the switching device are all soldered together. The solder can be copper, but is not limited to copper, and can also be other materials. Those skilled in the art can choose according to the actual situation.

[0031] In one embodiment of this application, such as Figure 2 As shown, the substrate 10 further includes at least one lead region located on the base island 13. The lead region includes a first metal layer located on the surface of the base island 13. To make the lead bonding between the base island and the source more robust, thereby further improving the electrical performance of the chip packaging structure, in this embodiment, at least one lead region is also provided on the surface of the base island. The lead region includes a first metal layer. The lead is bonded to the first metal layer of the lead region, so that the lead can be bonded more firmly to the lead region, avoiding the lead from breaking off from the base island due to weak bonding, which would cause the electronic device to malfunction, thereby further improving the reliability of the chip.

[0032] The material of the first metal layer can be not only copper, but also other materials, such as aluminum. Those skilled in the art can choose a suitable material according to the actual situation.

[0033] To further improve the electrical characteristics of the chip, in another embodiment of this application, such as... Figure 2 As shown, there are two lead regions, namely a first lead region 15 and a second lead region 16. The first lead region 15 and the second lead region 16 are located on opposite sides of the DBC substrate 11, and the first lead region 15 and the second lead region 16 are centrally symmetrical about the center of the base island 13. In this embodiment, there are two lead regions, both of which include a first metal layer. The two lead regions are centrally symmetrical about the center of the base island. Because of the symmetrical structure, the parasitic inductance of the chip is further reduced, thereby further improving the electrical performance of the chip.

[0034] Specifically, when the base island is circular, its center is the center of the circle; when the base island is rectangular, its center is the intersection of the two diagonals. Of course, in practical applications, the base island is not limited to circular or rectangular shapes; it can also be other shapes, and the center of the base island needs to be determined based on its shape.

[0035] In one specific embodiment of this application, in order to further reduce parasitic inductance, the number of leads in the two lead regions is the same.

[0036] In another embodiment of this application, such as Figure 3As shown, there are three base islands: a first base island 131, a second base island 17, and a third base island 18. The source is connected to the first base island 131 via a lead, the gate is connected to the second base island 17 via a lead, and the drain is connected to the third base island 18 via a lead. In this embodiment, the base islands of the source, drain, and gate are all located in the same plane. This allows multiple chips to be connected to the same circuit board layer during subsequent circuit design, thereby increasing the density of the circuit board.

[0037] To further improve the electrical characteristics of the chip, such as Figure 2 and Figure 3 As shown, in another embodiment of this application, the second base island 17 and the third base island 18 are respectively located on both sides of the first base island 131, and the second base island 17 and the third base island 18 are centrally symmetrical about the center of the substrate 10. Similarly, because the second base island and the third base island are centrally symmetrical about the center of the substrate, the parasitic inductance of the chip is further reduced, thereby further improving the electrical performance of the chip.

[0038] Specifically, when the substrate is circular, its center is the center of the circle; when the substrate is rectangular, its center is the intersection of the two diagonals. Of course, in practical applications, the substrate is not limited to circular or rectangular shapes; it can also be other shapes, and the center of the substrate needs to be determined based on its shape.

[0039] In another embodiment of this application, such as Figure 2 As shown, the DBC substrate 11 includes a third lead region 19, which includes a second metal layer located on the surface of the DBC substrate 11 away from the substrate 10. The third lead region 19 is connected to the third base island 18 via leads. To make the lead bonding between the DBC substrate and the drain more secure, thereby further improving the electrical performance of the chip packaging structure, in this embodiment, a third lead region is also provided on the surface of the DBC. The third lead region includes a second metal layer. The leads are bonded to the second metal layer of the lead region, which allows the leads to be bonded more securely to the lead region. This prevents the leads from breaking off due to weak bonding with the DBC substrate, which would cause the electronic device to malfunction, thereby further improving the reliability of the chip.

[0040] Similarly, the material of the second metal layer can be not only copper, but also other materials, such as aluminum. Those skilled in the art can choose a suitable material according to the actual situation.

[0041] In another embodiment of this application, the chip packaging structure includes a packaging cover, which is disposed on the first surface of the substrate 10 and forms a sealed space with the first surface of the substrate 10. The DBC substrate 11 and the switching device 12 are both located within the sealed space. In this embodiment, the packaging cover is disposed on the first surface of the substrate and forms a sealed space with the first surface of the substrate. The DBC substrate and the switching device are both located within the sealed space, which can reduce the interference of other components in the circuit to the chip, thereby further improving the reliability of the chip.

[0042] In one specific embodiment of this application, the material of the encapsulation cover can be plastic, but is not limited to plastic; it can also be ceramic. Those skilled in the art can choose according to the actual situation.

[0043] In another embodiment of this application, the switching device is a SiC JFET. SiC JFET devices have outstanding advantages such as higher saturation drift speed and higher critical breakdown voltage, making them suitable for high-power, high-temperature, high-frequency, and radiation-resistant applications, thus enabling chips including this SiC JFET to better meet the needs of radio frequency applications.

[0044] Of course, in practical applications, the above-mentioned switching devices can also be other switching devices, and the appropriate switching device can be selected according to the application scenario of the chip.

[0045] In another embodiment of this application, the DBC substrate includes a third metal layer, a ceramic layer, and a fourth metal layer stacked sequentially, with the fourth metal layer connected to the base island. To achieve better electrical connectivity, in this embodiment, the DBC substrate includes a third metal layer, a ceramic layer, and a fourth metal layer stacked sequentially. Because both the upper and lower surfaces of the DBC substrate are metal layers, solder can better connect it to the switching devices and the base island, thereby further improving the reliability of the chip and consequently enhancing its electrical performance.

[0046] The materials of the third and fourth metal layers can be copper or other materials. The materials of the third and fourth metal layers can be the same as or different from the first and second metal layers.

[0047] In one specific embodiment of this application, such as Figure 2 As shown, in order to further improve the electrical characteristics of the chip, the switching device further includes a source lead region 21 and a gate lead region 20. The source lead region 21 is connected to the first base island 131 by a lead, and the gate lead region 20 is connected to the second base island 17 by a lead.

[0048] According to an embodiment of this application, an electronic device is also provided, including a chip packaging structure, wherein the chip packaging structure is any of the above-described chip packaging structures.

[0049] The aforementioned electronic device includes a chip packaging structure, which can be any of the aforementioned chip packaging structures. The chip packaging structure includes a substrate, a DBC substrate, and a switching device stacked sequentially. The substrate includes a base island and an insulating portion. The base island supports the DBC substrate. The switching device includes a body structure, a source, a drain, and a gate. The source and gate are located on the surface of the body structure away from the DBC substrate, and the drain is located on the surface of the body structure in contact with the DBC substrate and connected to it. The source and base island are connected by leads. In this chip packaging structure, without changing the positions of the source, drain, and gate of the switching device, connecting the source and base island by leads places the source of the switching device at the bottom of the chip packaging structure. This reduces the resistance between the source and drain, thereby reducing parasitic inductance and solving the problem of large parasitic inductance in existing packaging structures that cannot meet the requirements of radio frequency applications. Furthermore, because the source is located at the bottom of the chip, the heat dissipation area of ​​the source is greatly increased, reducing the thermal resistance of the chip and thus improving the chip's heat dissipation capacity and power. Therefore, because the electronic device includes the aforementioned chip packaging structure, the parasitic inductance of the electronic device is small, and thus the electrical performance of the electronic device is good.

[0050] To enable those skilled in the art to better understand the technical solution of this application, the technical solution and technical effects of this application will be described below in conjunction with specific embodiments.

[0051] Example

[0052] The top view of the chip packaging structure in this embodiment is as follows: Figure 2As shown, the chip packaging structure includes a substrate 10, a DBC substrate 11, and a switching device 12 stacked sequentially. The substrate 10 includes a first base island 131, a second base island 17, a third base island 18, and an insulating portion 14. The first base island 131 supports the DBC substrate 11. The DBC substrate 11 includes a third metal layer, a ceramic layer, and a fourth metal layer stacked sequentially. The third metal layer is connected to the first base island 131. The switching device 12 includes a body structure, a gate lead region 20, a source lead region 21, and a drain. The gate lead region 20 and the source lead region 21 are located within the body structure. The drain is located on the surface of the body structure that is in contact with the fourth metal layer and is connected to the fourth metal layer. The first base island 131 includes a first lead region 15 and a second lead region 16. The source lead region 21 is connected to the first lead region 15 and the second lead region 16 by a lead. The gate lead region 20 is connected to the second base island 17 by a lead. The DBC substrate 11 also includes a third lead region 19, located on the surface of the fourth metal layer that is away from the ceramic layer. The third lead region 19 is connected to the third base island 18 by a lead.

[0053] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0054] 1) The chip packaging structure of this application includes a substrate, a DBC substrate, and a switching device stacked sequentially. The substrate includes a base island and an insulating portion. The base island supports the DBC substrate. The switching device includes a body structure, a source, a drain, and a gate. The source and gate are located on the surface of the body structure away from the DBC substrate, and the drain is located on the surface of the body structure in contact with the DBC substrate and connected to it. The source and base island are connected by leads. In this chip packaging structure, without changing the positions of the source, drain, and gate of the switching device, connecting the source and base island through leads places the source of the switching device at the bottom of the chip packaging structure. This reduces the resistance between the source and drain, thereby reducing parasitic inductance and solving the problem of large parasitic inductance in existing packaging structures that cannot meet the requirements of radio frequency applications. Furthermore, since the source is located at the bottom of the chip packaging structure, the heat dissipation area of ​​the source is greatly increased, reducing the thermal resistance of the chip and thus improving the chip's heat dissipation capacity and power.

[0055] 2) The electronic device of this application includes a chip packaging structure, which is any of the aforementioned chip packaging structures. The chip packaging structure includes a substrate, a DBC substrate, and a switching device stacked sequentially. The substrate includes a base island and an insulating portion. The base island supports the DBC substrate. The switching device includes a body structure, a source, a drain, and a gate. The source and gate are located on the surface of the body structure away from the DBC substrate, and the drain is located on the surface of the body structure in contact with the DBC substrate and connected to the DBC substrate. The source and base island are connected by leads. In this chip packaging structure, without changing the positions of the source, drain, and gate of the switching device, connecting the source and base island by leads places the source of the switching device at the bottom of the chip packaging structure. This reduces the resistance between the source and drain, thereby reducing parasitic inductance and solving the problem of large parasitic inductance in existing packaging structures that cannot meet the requirements of radio frequency applications. Furthermore, since the source is located at the bottom of the chip packaging structure, the heat dissipation area of ​​the source is greatly increased, reducing the thermal resistance of the chip and thus improving the chip's heat dissipation capacity and power. Therefore, because the electronic device includes the aforementioned chip packaging structure, the parasitic inductance of the electronic device is small, and thus the electrical performance of the electronic device is good.

[0056] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A chip package structure, characterized by, The chip package structure comprises a substrate, a DBC substrate and a switching device which are sequentially stacked, wherein the substrate comprises at least one base island and an insulating part which is arranged on the sidewall of the base island, the base island is used for supporting the DBC substrate, the switching device comprises a body structure, a source electrode, a drain electrode and a gate electrode, the source electrode and the gate electrode are located on the surface of the body structure which is away from the DBC substrate, the drain electrode is located on the surface of the body structure which is in contact with the DBC substrate and is connected with the DBC substrate, and the source electrode is connected with the base island through a lead wire.

2. The chip package structure of claim 1, wherein, The substrate further comprises at least one lead wire area which is located on the base island, and the lead wire area comprises a first metal layer which is located on the surface of the base island.

3. The chip package structure of claim 2, wherein, The lead wire area has two first and second lead wire areas which are respectively located on the two sides of the DBC substrate, and the first and second lead wire areas are centrally symmetric with the center of the base island.

4. The chip package structure of claim 1, wherein, The base island has three first, second and third base islands, the source electrode is connected with the first base island through a lead wire, the gate electrode is connected with the second base island through a lead wire, and the drain electrode is connected with the third base island through a lead wire.

5. The chip package structure of claim 4, wherein, The second and third base islands are respectively located on the two sides of the first base island, and the second and third base islands are centrally symmetric with the center of the substrate.

6. The chip package structure of claim 4, wherein, The DBC substrate comprises a third lead wire area which comprises a second metal layer, the second metal layer is located on the surface of the DBC substrate which is away from the substrate, and the third lead wire area is connected with the third base island through a lead wire.

7. The chip package structure of any one of claims 1-6, wherein, The chip package structure comprises a package cover which is arranged on the first surface of the substrate and forms a sealed space with the first surface of the substrate, and the DBC substrate and the switching device are located in the sealed space.

8. The chip package structure of any one of claims 1-6, wherein, The switching device is a SiCJFET.

9. The chip package structure of any one of claims 1-6, wherein, The DBC substrate comprises a third metal layer, a ceramic layer and a fourth metal layer which are sequentially stacked, and the fourth metal layer is connected with the base island.

10. An electronic device comprising a chip package structure, characterized by The chip package structure is the chip package structure according to any one of claims 1 to 9. The chip package structure is the chip package structure according to any one of claims 1 to 9.

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