Three-dimensional packaging structure, semiconductor device and packaging method

Abstract

The application discloses a three-dimensional packaging structure, a semiconductor device and a packaging method, wherein the three-dimensional packaging structure comprises: a first chip, a front surface of which is provided with a first pad and a chip connecting area formed on a side of the first pad; a second chip, a back surface of which is arranged on the chip connecting area and a front surface of which is provided with a second pad; a rewiring structure, which is arranged in a front surface direction of the second chip and is electrically connected with the second pad; and an electrical connecting element, which is arranged between the rewiring structure and the first pad and electrically connects the rewiring structure and the first pad. In the embodiment of the application, the electrical connecting element is used to connect the pad of the stacked chip and the rewiring structure, the electrical connecting element can be directly formed on the pad by using a ball mounting process, compared with the scheme of forming a metal bump by using electroplating in the prior art, the process is simpler, and the use of a large amount of photoresist material in the electroplating process is avoided, so that the cost can be better saved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a three-dimensional packaging structure, semiconductor device, and packaging method. Background Technology

[0002] 3D packaging, as an advanced packaging technology, is widely used in the IC manufacturing industry. It breaks through the traditional concept of planar packaging, allowing multiple chips to be stacked within a single package, thus doubling storage capacity and increasing assembly efficiency by over 200%. Simultaneously, 3D packaging directly interconnects chips, significantly shortening interconnect lengths, enabling faster signal transmission with less interference, and allowing a single package to perform more functions, thus forming a new approach to system-on-a-chip (SoC) packaging.

[0003] When connecting multiple stacked chips, wiring needs to be added on top of the chips. In order to achieve electrical connection between the wiring structure and the chip pads, it is usually necessary to fabricate copper pillars on the chip pads. In the prior art, copper pillars are generally formed by electroplating.

[0004] Due to the stacking of chips, the distance between the chip on the bottom and the redistribution structure is relatively large, generally exceeding 80μm. This necessitates a relatively large height for the copper pillars formed on the pads. In existing technologies, forming tall copper pillars requires a relatively thick photoresist layer during the electroplating process. This not only increases costs and prolongs plating time, but also complicates the process. Furthermore, defects in the plated copper pillars are difficult to rework. Summary of the Invention

[0005] The purpose of this invention is to provide a three-dimensional packaging structure to overcome the shortcomings of the prior art. It can simplify the process, reduce the use of photoresist materials, and lower production costs.

[0006] The present invention provides a three-dimensional packaging structure, comprising:

[0007] The first chip has a first pad and a chip connection area formed next to the first pad on its front side;

[0008] The second chip has a back side disposed on the chip connection area and a second pad disposed on the front side;

[0009] A redistribution structure is disposed on the front side of the second chip and electrically connected to the second pad;

[0010] An electrical connector is disposed between the redistribution structure and the first pad and electrically connects the redistribution structure and the first pad.

[0011] Furthermore, the electrical connector includes a core and a solder body disposed outside the core, the electrical connector being soldered onto the pads via the solder body, and the redistribution structure being electrically connected to the core.

[0012] Furthermore, the solder body covers the outside of the core and exposes the top of the core toward the redistribution structure for docking with the redistribution structure.

[0013] Furthermore, the top of the core and the top of the solder body are both planar and located on the same plane, and the solder body has a ring structure in the plane, and the shape of the core in the plane is adapted to the inner ring of the ring structure.

[0014] Furthermore, a passivation layer is provided between the top surface of the solder body and the redistribution structure, and the solder body is connected to the passivation layer through an IMC layer formed on top.

[0015] Furthermore, the minimum distance between any point on the top surface of the solder body and the core does not exceed 10 μm.

[0016] Furthermore, in any cross section of the electrical connector that is parallel to the top surface of the solder body and passes through the core, the minimum distance between any point of the solder body on that cross section and the core does not exceed 10 μm.

[0017] Furthermore, the core is a metal sphere with its top partially cut off.

[0018] Furthermore, the melting point of the core is higher than that of the solder body; the core is made of one of gold, copper, aluminum, and silver, and the solder body is made of tin or a tin alloy.

[0019] Furthermore, the solder body is a solder layer disposed between the core and the pad, and the height of the solder layer is not less than 1 / 3 of the core height and not more than 1 / 2 of the core height.

[0020] Furthermore, the distance between the first pad and the redistribution structure is greater than 80 μm.

[0021] Furthermore, the redistribution structure is electrically connected to the second pad via an electrical connection structure, which is a copper pillar or the electrical connector.

[0022] Furthermore, the three-dimensional packaging structure also has:

[0023] An encapsulation layer covers the front side of the chip, and an encapsulation notch is formed in the encapsulation layer at a position corresponding to the electrical connector and the electrical connection structure;

[0024] A passivation layer is provided on the encapsulation layer, and an opening is formed in the passivation layer at a position corresponding to the electrical connector and the electrical connection structure.

[0025] The rewiring structure is disposed on the upper side of the electrical connector, the upper side of the electrical connection structure, and the upper side of part of the passivation layer, and the rewiring structure passes through the encapsulation notch and the passivation layer opening to connect with the electrical connector and the electrical connection structure.

[0026] The present invention also discloses a semiconductor device, including the aforementioned three-dimensional packaging structure and a circuit board having substrate pads. A plurality of metal bumps are provided on the side of the redistribution structure opposite to the chip, and the metal bumps are soldered onto the substrate pads.

[0027] This invention also discloses a packaging method for a three-dimensional packaging structure, comprising the following steps:

[0028] A first chip and an electrical connector are provided, wherein the electrical connector is electrically connected to a first pad on the front side of the first chip;

[0029] A second chip is provided, and an electrical connection structure is formed on a second pad of the second chip;

[0030] The second chip is fixed to the front of the first chip;

[0031] Encapsulation layers are formed on the front sides of the first chip and the second chip;

[0032] Remove part of the encapsulation layer to simultaneously expose the electrical connection structure and electrical connector;

[0033] A redistribution structure is formed above the encapsulation layer, and the redistribution structure is electrically connected to the electrical connection structure and the electrical connector.

[0034] Furthermore, when the electrical connector is soldered onto the first pad on the front side of the first chip, the electrical connector has a spherical structure and is soldered onto the first pad using a ball-mounting process.

[0035] Furthermore, the electrical connector has a core and a solder body covering the core. When removing part of the encapsulation layer to expose both the electrical connection structure and the electrical connector, part of the solder body needs to be removed to expose both the core and the solder body.

[0036] Furthermore, a passivation layer is formed on the upper surface of the encapsulation layer before the rewiring structure is formed, and part of the passivation layer is removed to form an opening in the passivation layer.

[0037] The passivation layer opening is opposite to the exposed core position and the size of the passivation layer opening is not larger than the size of the exposed core. The passivation layer covers the upper side of the exposed solder body.

[0038] Another embodiment of the present invention discloses a packaging method for a three-dimensional packaging structure, comprising the following steps:

[0039] A first wafer is provided, wherein the first wafer includes a plurality of first chips; the first chips are provided with first pads;

[0040] Provide an electrical connector for electrically connecting the electrical connector to the first pad;

[0041] A second wafer is provided, wherein the second wafer includes a plurality of second chips, and an electrical connection structure is formed on a second pad of the second chips;

[0042] The second wafer is diced to cut out the second chip of the monomer, and the second chip of the monomer is stacked on the front side of the first chip, wherein the front side of the second chip of the monomer is aligned with the front side of the first chip.

[0043] An encapsulation layer is formed on the front side of the first chip and the front side of the second chip;

[0044] Remove part of the encapsulation layer to simultaneously expose the electrical connection structure and electrical connector;

[0045] A rewiring structure is formed above the encapsulation layer, and the rewiring structure is electrically connected to the electrical connection structure and the electrical connector. Further,

[0046] Furthermore, after forming the rewiring structure above the encapsulation layer, the packaging method for the three-dimensional packaging structure further includes:

[0047] Metal bumps for electrical connection to an external circuit board are formed on the redistribution structure; the metal bumps are disposed on the side of the redistribution structure opposite to the chip;

[0048] The first wafer is diced to form a packaged single chip.

[0049] Compared with the prior art, the present invention uses pre-made electrical connectors to connect the pads of stacked chips to the redistribution structure. The electrical connectors can be directly soldered onto the pads using a ball-mounting process. Compared with the prior art's method of using electroplated metal bumps, the process of this embodiment is simpler and avoids the large amount of photoresist material used in the electroplating process, thus saving costs. At the same time, since the electrical connectors are pre-made, visual inspection can be performed on the electrical connectors before they are soldered onto the pads, which can promptly identify defective electrical connectors and replace them for rework. Attached Figure Description

[0050] Figure 1-6 This is a schematic diagram of the packaging process of the three-dimensional packaging structure of the first embodiment disclosed in this invention;

[0051] Figure 7 This is a schematic diagram of the three-dimensional packaging structure of the second embodiment disclosed in this invention;

[0052] Figure 8 This is a schematic diagram of the structure in the first embodiment of the present invention, in which the core is exposed to the outside after the encapsulation layer and solder body are etched.

[0053] Figure 9 This is a schematic diagram of the structure in the first embodiment of the present invention, showing the passivation layer covering the encapsulation layer;

[0054] Explanation of reference numerals in the attached figures: 1-chip, 11-first chip, 111-first pad, 112-chip connection area, 12-second chip, 121-second pad, 2-rewiring structure, 3-electrical connector, 31-core, 32-solder body, 4-electrical connection structure, 5-encapsulation layer, 6-passivation layer, 60-passivation layer opening, 7-metal bump. Detailed Implementation

[0055] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0056] Embodiments of the present invention: such as Figure 6 and 7 As shown, a three-dimensional packaging structure is disclosed, which specifically includes: at least two chips 1 stacked sequentially, a redistribution structure 2, and an electrical connector 3, with the pads of the chips 1 all facing the same side; the redistribution structure 2 is disposed on the front side of the uppermost chip 1 and electrically connects the two stacked chips; the electrical connector 3 electrically connects the redistribution structure 2 and the pad of the lower chip, wherein the electrical connector 3 is pre-fabricated and soldered onto the pad. It should be noted that the pad of the lower chip is the chip located on the lower side of the two stacked chips; when multiple chips are stacked, the lower chip is the chip located on the bottom side relative to the uppermost chip; of course, in another embodiment, the lower chip can also be the chip located in the middle position after three chips are stacked.

[0057] In this embodiment, an electrical connector 3 is used to connect the pads of the stacked chips to the redistribution structure 2. The electrical connector 3 is prefabricated and can then be directly soldered onto the pads using a ball-mounting process. Compared with the existing technology that uses electroplating to form metal bumps, the process is simpler and avoids the large amount of photoresist material used in the electroplating process, thus saving costs.

[0058] As shown above, the three-dimensional packaging structure disclosed in this application can stack two chips or more chips. In this embodiment, the description is based on stacking two chips, the first chip 11 and the second chip 12.

[0059] The three-dimensional packaging structure includes:

[0060] The first chip 11 has a first pad 111 and a chip connection area 112 formed next to the first pad 111 on its front side.

[0061] The second chip 12 has a back side disposed on the chip connection area 112 and a second pad 121 disposed on the front side; the size of the first chip 11 is larger than the size of the second chip 12, so that the second chip 12 is stacked on the first chip 11; the back side of the second chip 12 can be directly attached to the first chip 11.

[0062] The rewiring structure 2 is disposed on the front side of the second chip 12 and electrically connected to the second pad 121;

[0063] Electrical connector 3 is disposed between the redistribution structure 2 and the first pad 111 and electrically connects the redistribution structure 3 and the first pad 111.

[0064] After chip stacking, the first chip 11 is located on the lower side, and the second chip 12 is located on the upper side. The redistribution structure 2 is located above the front of the second chip 12. Therefore, the redistribution structure 2 is relatively far away from the first pad 111. In this embodiment, the first pad 111 and the redistribution structure 2 are connected by an electrical connector 3, which can reduce the complexity of the process and avoid the use of a large amount of photoresist material, thus reducing costs.

[0065] In this embodiment, the redistribution structure 2 and the second pad 121 are electrically connected through an electrical connection structure 4. The electrical connection structure 4 can be a copper pillar, which is formed by electroplating. Alternatively, the electrical connection structure 4 can be an electrical connector, which is prefabricated and then soldered onto the pad using a ball-mounting process.

[0066] It is understood that the three-dimensional packaging structure also includes an encapsulation layer 5 and a passivation layer 6;

[0067] The encapsulation layer 5 covers the front side of the chip; the encapsulation layer 5 also covers all stacked chips to encapsulate and fix the stacked chips; an encapsulation notch is formed on the encapsulation layer 5 at a position corresponding to the electrical connector 3 and the electrical connection structure 4, and the electrical connector 3 and the electrical connection structure 4 are exposed to the outside of the encapsulation layer 5 from the encapsulation notch.

[0068] The encapsulation gap is actually the way the encapsulation layer 5 avoids the electrical connection structure 4 and the electrical connector 3, and is thus manifested at the top of the encapsulation layer 5;

[0069] Generally, the upper surface of the encapsulation layer 5 after initial molding is not lower than the front side of the chip in the vertical direction, so as to completely embed the chip within it. However, in order to facilitate the connection between the redistribution structure and the electrical connection structure 4 and the electrical connector 3, a portion of the encapsulation layer 5 needs to be etched away after molding to form the encapsulation gap. The encapsulation layer 5 is currently most commonly made of epoxy resin, phenolic resin, silicone resin and unsaturated polyester resin, with fillers such as silicon oxide and aluminum oxide added to improve the strength, electrical properties, viscosity and other properties of the encapsulation layer 5, and to enhance the thermomechanical reliability of the packaging structure. After curing, the encapsulation layer 5 can provide waterproofing, moisture protection, shockproofing, dustproofing, heat dissipation and insulation.

[0070] A passivation layer 6 covers the encapsulation layer 5, and a passivation layer opening 60 is formed on the passivation layer 6 at a position opposite to the electrical connector 3 and the electrical connection structure 4. The electrical connector 3 and the electrical connection structure 4 are exposed to the outside of the passivation layer 6 through the passivation layer opening 60. The position of the passivation layer opening 60 is opposite to the position of the encapsulation notch. The material of the passivation layer 6 is silicon oxide, silicon nitride, or a resin-based dielectric material.

[0071] The redistribution structure 2 is disposed on the upper side of the electrical connector 3, the upper side of the electrical connection structure 4, and part of the upper side of the passivation layer 6, and the redistribution structure 2 passes through the encapsulation notch and the passivation layer opening 60 to connect with the electrical connector and the electrical connection structure.

[0072] The material of the rewiring structure 2 includes, but is not limited to, copper. The rewiring structure 2 has an opening 60 that extends downward through the passivation layer and an enclosed notch for connection with the electrical connector 3 or the electrical connection structure 4. The rewiring structure 2 can be a single layer or multiple layers, depending on the actual needs.

[0073] In a specific embodiment, the rewiring structure 2 is formed by electroplating. In order to better realize the setting of the rewiring structure 2, seed layers are formed between the rewiring structure 2 and the electrical connector 3, between the rewiring structure 2 and the electrical connector 4, and between the rewiring structure 2 and the passivation layer 6. The rewiring structure 2 grows on the seed layers.

[0074] In this embodiment, the electrical connector 3 includes a core 31 and a solder body 32 disposed outside the core 31. The electrical connector 3 is soldered to the first pad 111 through the solder body 32, and the redistribution structure 2 is electrically connected to the core 31.

[0075] The melting point of the core 31 is higher than that of the solder body 32; the core 31 is made of one of gold, copper, aluminum, silver, etc., and the solder body 32 is made of tin or tin alloy.

[0076] When forming the redistribution structure 2, a high temperature is required. In order to avoid the high temperature affecting the stability of the electrical connector 3, the core 31 is made of a metal with a relatively high melting point. In order to facilitate the connection between the core 31 and the pad, the electrical connector 3 is also provided with a solder body 32. The solder body 32 is made of a material with a relatively low melting point to facilitate the connection with the pad.

[0077] In a specific embodiment, the solder body 32 of the electrical connector 3 is directly formed on the outside of the core 31. The solder body 32 covers the outside of the core 31, and exposes the top of the core 31 towards the redistribution structure 2 to dock with the redistribution structure 2. That is, the solder body 32 only covers the sidewalls and bottom wall of the core 31, and the top of the core 31 is not covered by the solder body 32.

[0078] In practical use, since the electrical connector 3 is pre-fabricated, to facilitate its fabrication, the solder body 32 often completely covers the core 31. Then, during use, a portion of the solder body 32 at the top of the electrical connector 3 is removed to expose the core 31. Specifically, after the electrical connector 3 is soldered to the pad, a portion of the solder body 32 is removed through physical abrasion to expose the core 31. During this process, a portion of the core 31 is also removed simultaneously to increase the exposed size of the core 31, thereby facilitating electrical connection with the rewiring structure 2 and improving connection stability.

[0079] Specifically, after the electrical connector 3 is soldered onto the pads, and after the encapsulation layer 5 is formed on top of the chip, part of the encapsulation layer 5 and part of the electrical connector 3 are etched away to expose the core 31; as shown Figure 8 As shown, after abrasion, the top of the core 31 and the top of the solder body 32 are both planar and located on the same plane, and the solder body 32 has an annular structure in the plane, and the shape of the core in the plane is adapted to the inner ring of the annular structure.

[0080] like Figure 9As shown, to ensure the stability of the redistribution structure 2 and the electrical connector 3, the redistribution structure 2 is configured to connect only to the core 31. Therefore, before the redistribution structure 2 is formed, the passivation layer 6 formed on the encapsulation layer 5 needs to cover the upper side of the solder body 32 to isolate the contact between the redistribution structure 2 and the solder body 32. In this process, the position of the passivation layer opening 60 formed on the passivation layer 6 needs to be opposite to the core 31, and the size of the passivation layer opening 60 is not greater than the size of the core 31 exposed outward. During the pre-forming of the electrical connector 3, the solder body 32 and the core 31 are two different metals. The part of the solder body 32 that contacts the core 31 will react with the core 31 to form an IMC layer. The formation of this IMC layer originates from the mutual combination, penetration, migration and diffusion between tin atoms and the metal atoms of the core 31 during the welding process, and a thin compound, i.e., the IMC layer, immediately appears after cooling and solidification. The degree of aging of the IMC layer is affected by the amount of interpenetration between tin atoms and metal atoms. Therefore, the IMC layer is mainly located in the solder body 32 near the core 31.

[0081] After the passivation layer 6 is applied to the solder body 32, delamination can easily form between the passivation layer 6 and the solder body 32 when subjected to high temperatures. The presence of this delamination can affect the stability of the connection between the redistribution structure 2 and the electrical connector 3.

[0082] To avoid delamination, the solder body 32 is connected to the passivation layer through the IMC layer formed on top. That is, the part where the top of the solder body 32 meets the passivation layer 6 needs to completely form an IMC layer during the interaction with the core 31. This requires that the outermost part of the top of the solder body 32 also reacts and forms an IMC layer. In other words, when the top surface of the solder body 32 has a ring structure, any point on the outer ring of the ring structure has formed an IMC layer, thereby ensuring that the passivation layer 6 directly covers the completely formed IMC layer on the top of the solder body 32.

[0083] If an IMC layer is not formed near the outer ring of the annular structure on the top surface of the solder body 32, this area will still be made of the solder body itself, i.e., tin and tin alloy. This will inevitably cause reflow and shrinkage at the edge of the top surface of the solder body 32 after subsequent high-temperature melting, resulting in instability in the bond with the passivation layer 6, and consequently, delamination between the passivation layer 6 and the top surface of the solder body 32. In this embodiment, an IMC layer is completely formed on the top surface of the solder body 32. The connection between the IMC layer and the passivation layer 6 avoids the aforementioned delamination problem.

[0084] To ensure the formation of an IMC layer on the top of the solder body 32, the minimum distance between any point on the solder body 32 and the core 31 within the plane containing the top of the solder body 32 shall not exceed 10 μm. As described above, the top surface of the solder body 32 has a ring structure, and the above configuration requires that the minimum distance between any point in the outer ring of the ring structure and the inner ring of the ring structure shall not exceed 10 μm.

[0085] The above-described structure ensures that the top reaction of the solder body 32 completely forms the IMC layer. If, within the plane containing the top of the solder body 32, there is a position on the solder body 32 where the minimum distance from the core 31 exceeds 10 μm, this position is prone to incomplete reaction between the solder body 32 and the core 31 during the formation of the electrical connector 3. In other words, pure tin is likely to form at the edge of the solder body 32. The presence of pure tin can easily cause shrinkage during high-temperature reflow, resulting in delamination between the solder body and the passivation layer 6.

[0086] Furthermore, in any cross-section of the electrical connector 3 parallel to the plane (i.e., the top surface of the solder body 32, which is also the top surface of the core 31) and passing through the core 31, the minimum distance between any point of the solder body on this cross-section and the core does not exceed 10 μm. This structure ensures that all positions on the solder body 32 corresponding to the core 31 react completely and that the entire solder body forms an IMC layer. Therefore, regardless of the position of the electrical connector 3 during use, or the extent to which the core 31 is exposed, delamination between the solder body 32 and the passivation layer 6 can be avoided, ensuring the stability of the contact area between the solder body 32 and the passivation layer 6 and improving the applicability of the electrical connector 3.

[0087] As a preferred option, the entire electrical connector 3 is prefabricated to form a sphere with a two-layer structure. This structure makes it easier to directly solder the electrical connector 3 onto the pads using a ball-mounting process, thus facilitating the connection and use of the electrical connector 3.

[0088] In the pre-fabricated electrical connector 3, the core 31 is a spherical metal sphere. However, after the electrical connector 3 connects the pads and the redistribution structure 2, the core 31 becomes a metal sphere with its top partially cut off. The top of the spherical core 31 is cut off during the removal of part of the solder body 32. Of course, in another embodiment, the core 31 in the pre-fabricated electrical connector 3 can also be a cylinder.

[0089] In the above embodiments, the solder body 32 covers the core 31. In another embodiment, the solder body 32 is disposed on the lower side of the core 31. The solder body 32 can be directly fixed to the core 31 to form a complete electrical connector 3, or the solder body 32 and the core 31 can be separately and independently disposed. In this embodiment, the solder body 32 and the core 31 are described as separate.

[0090] Specifically, the solder body 32 is a solder layer disposed between the core 31 and the pad. The solder layer is disposed on the pad and then the solder body 32 is soldered onto the solder layer. In order to ensure the stability of the overall structure, the height of the solder layer is set to be no less than 1 / 3 of the height of the core and no more than 1 / 2 of the height of the core.

[0091] In this embodiment, the distance between the first pad 111 and the redistribution structure 2 is greater than 80 μm, and the distance between the first pad 111 and the redistribution structure 2 is no higher than 750 μm. In the prior art, during the electroplating process to form metal bumps, if the distance between the pad 111 and the redistribution structure 2 exceeds 80 μm, it will increase the electroplating time and result in a larger photoresist layer height, leading to wasted photoresist. The solution in this embodiment can effectively avoid the waste of photoresist caused by the electroplating process.

[0092] Another embodiment of the present invention discloses a semiconductor device, including the aforementioned three-dimensional packaging structure and a circuit board having substrate pads. A plurality of metal bumps 7 are provided on the side of the redistribution structure opposite to the chip, and the metal bumps 7 are soldered onto the substrate pads.

[0093] Another embodiment of the present invention discloses a packaging method for a three-dimensional packaging structure, comprising the following steps:

[0094] like Figure 1 As shown, a first chip 11 and a pre-made electrical connector are provided, and the electrical connector is electrically connected to a first pad 111 on the front side of the first chip 11.

[0095] A second chip 12 is provided, and an electrical connection structure 4 is formed on the second pad 121 of the second chip 12;

[0096] like Figure 2 As shown, the second chip 12 is fixed to the front side of the first chip 12;

[0097] like Figure 3 As shown, an encapsulation layer 5 is formed on the front side of the first chip 11 and the front side of the second chip 12;

[0098] like Figure 4As shown, part of the encapsulation layer 5 is removed to simultaneously expose the electrical connection structure 4 and the electrical connector 3 to the outside;

[0099] like Figure 5 As shown, a redistribution structure 2 is formed above the encapsulation layer 6, and the redistribution structure 2 is electrically connected to the electrical connection structure 4 and the electrical connector 3.

[0100] In the specific wafer fab packaging process, in order to facilitate the formation of electrical connectors 3, multiple first chips 11 are operated together on a wafer before dicing when forming electrical connectors 3. Similarly, when forming electrical connection structure 4 on second chip 12, multiple second chips 11 are operated together on a wafer before dicing. After forming electrical connection structure 4 on second chip 12, the wafer carrying second chip 12 is diced to form a single second chip 12.

[0101] In this regard, another embodiment of the present invention discloses a packaging method for a three-dimensional packaging structure, comprising the following steps:

[0102] S100: A first wafer is provided, wherein the first wafer includes a plurality of first chips 11, and a plurality of first pads 111 are provided on the front side of the first chips 11;

[0103] A pre-fabricated electrical connector is provided, and the electrical connector is electrically connected to the first pad 111; specifically, the electrical connector 3 can be soldered to the first pad 111 using a ball-mounting process;

[0104] S200: A second wafer is provided, wherein the second wafer includes a plurality of second chips 12, and a plurality of second pads 121 are provided on the front side of the second chips 12, and an electrical connection structure 4 is formed on the second pads 121.

[0105] The electrical connection structure 4 can be a copper pillar electroplated and formed on the second pad 121 or an electrical connection 3 welded on the second pad using a ball-planting process.

[0106] S300: The second wafer is diced to cut out the second chip 12 of the unit, and the second chip 12 of the unit is stacked on the front side of the first chip 11, wherein the front side of the second chip 12 of the unit is aligned with the front side of the first chip 11.

[0107] Before cutting the second wafer, the back side of the second wafer also needs to be thinned. Specifically, the back side of the second wafer can be thinned by physical grinding. This structural design can reduce the thickness of the chip package after stacking.

[0108] The back of the second chip 12 of the unit is directly attached to the front of the first chip 11. A chip connection area is formed on the front of the first chip 11. The second chip 12 of the unit corresponds one-to-one with the first chip 11 and is attached to the chip connection area.

[0109] S400: An encapsulation layer 5 is formed on the front side of the first chip 11 and the front side of the second chip 12; the encapsulation layer 5 is formed by injection molding or film bonding.

[0110] Through injection molding, encapsulation material is first filled into the corresponding mold to cover the first chip 11 and the second chip 12. After heating and curing, the encapsulation body 5 is formed.

[0111] S500: Remove part of the encapsulation layer 5 to simultaneously expose the electrical connection structure 4 and the electrical connector 3; specifically, a thinning process is adopted, and the upper encapsulation layer 5 is removed by physical grinding. It can be understood that in order to expose the electrical connection structure 4 and the electrical connector 3, part of the electrical connection structure 4 and the electrical connector 3 will also be removed in this step.

[0112] In a specific embodiment, if the electrical connector 3 has a core 31 and a solder body 32 covering the core 31, when removing part of the encapsulation layer 5 to expose the electrical connection structure 4 and the electrical connector 3 to the outside at the same time, it is necessary to remove part of the solder body 32 to expose the core 31 and the solder body 32 to the outside at the same time.

[0113] S600: A redistribution structure is formed above the encapsulation layer 6, and the redistribution structure is electrically connected to the electrical connection structure and the electrical connector.

[0114] Specifically, S600: A redistribution structure 2 is formed above the encapsulation layer, and the redistribution structure 2 is electrically connected to the electrical connection structure 4 and the electrical connector 3; specifically including the following steps:

[0115] S601: A passivation layer is formed on the upper surface of the encapsulation layer, and a portion of the passivation layer is removed to form a passivation layer opening 60, through which the electrical connection structure 4 and the electrical connector are exposed. The specific method of removing a portion of the passivation layer to form the passivation layer opening 60 is based on existing exposure and development techniques, which will not be elaborated here.

[0116] In this embodiment, the passivation layer opening 60 is positioned opposite to the exposed core 31 and the size of the passivation layer opening 60 is not larger than the size of the exposed core 31. The passivation layer 6 covers the upper side of the exposed solder body 32.

[0117] S602: A seed layer is covered on the passivation layer, the electrical connection structure 4, and the electrical connector 3;

[0118] S603: A photoresist layer is covered on the seed layer, and part of the photoresist at the target location is removed to form an opening in the photoresist layer at the target location. The electrical connector 3 and the electrical connection structure 4 are both exposed outward from the opening in the photoresist layer. Specifically, the removal of the photoresist layer also uses existing technology, which will not be described again.

[0119] S604: Electroplating the rewiring structure 2 within the opening of the photoresist layer;

[0120] S605: Remove the seed layer outside the coverage area of ​​the photoresist layer and rewiring structure 2. The specific process is based on existing technology and will not be described again.

[0121] The above embodiment describes an electrical connector 3 with a core 31 covering a solder body 32, and it is soldered onto the first pad 111 using a ball-mounting process. In another embodiment, the electrical connector includes a metal connector and a solder layer disposed between the metal connector and the first pad 111. The specific steps for setting the electrical connector 3 on the first pad 111 on the front side of the first chip 11 include the following:

[0122] The solder layer is formed on the first pad 111.

[0123] The metal connector is welded onto the solder layer.

[0124] After forming the rewiring structure above the encapsulation layer 6, the packaging method of the three-dimensional packaging structure further includes:

[0125] S700: A metal bump is formed on the redistribution structure 2, the metal bump being used for electrical connection with an external circuit board; the metal bump is disposed on the side of the redistribution structure opposite to the chip;

[0126] S800: Thinning the back side of the first wafer and cutting the thinned first wafer to form a single chip.

[0127] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A three-dimensional package structure, comprising: The application relates to a three-dimensional packaging structure, which comprises: a first chip, the front surface of which is provided with a first pad and a chip connecting area formed beside the first pad; a second chip, the back surface of which is arranged on the chip connecting area and the front surface of which is provided with a second pad; a re-wiring structure, which is arranged in the front surface direction of the second chip and is electrically connected with the second pad; an electric connecting piece, which is arranged between the re-wiring structure and the first pad and electrically connects the re-wiring structure and the first pad; the electric connecting piece comprises a core and a solder body arranged outside the core, the electric connecting piece is welded on the pad through the solder body, and the re-wiring structure is electrically connected with the core; the top of the core and the top of the solder body are both flat and are located in the same plane, the solder body has a ring structure in the plane, and the shape of the core in the plane is matched with the inner ring of the ring structure; a passivation layer is arranged between the top surface of the solder body and the re-wiring structure, and the solder body is connected with the passivation layer through an IMC layer formed on the top; the minimum distance between any point on the top surface of the solder body and the core is not more than 10 mu m. The solder body covers the outside of the core and exposes the top of the core towards the direction of the re-wiring structure to be connected with the re-wiring structure. In any section parallel to the top surface of the solder body and passing through the core on the electric connecting piece, the minimum distance between any point on the section of the solder body and the core is not more than 10 mu m. The core is a metal ball with a top being partially cut. The melting point of the core is higher than that of the solder body; the material of the core is one of gold, copper, aluminum and silver, and the material of the solder body is tin or tin alloy. The distance between the first pad and the re-wiring structure is greater than 80 mu m. The re-wiring structure and the second pad are electrically connected through an electric connecting structure, and the electric connecting structure is a copper column or the electric connecting piece. The three-dimensional packaging structure further has: an encapsulation layer covering the front surface of the chip, the encapsulation layer is provided with an encapsulation gap at positions corresponding to the electric connecting piece and the electric connecting structure; a passivation layer covering the encapsulation layer, the passivation layer is provided with a passivation layer opening at positions corresponding to the electric connecting piece and the electric connecting structure; the re-wiring structure is arranged on the upper side of the electric connecting piece, the upper side of the electric connecting structure and part of the upper side of the passivation layer, and the re-wiring structure is connected with the electric connecting piece and the electric connecting structure through the encapsulation gap and the passivation layer opening.

2. The three-dimensional package structure of claim 1, wherein, The three-dimensional packaging structure comprises the three-dimensional packaging structure and a circuit substrate with a substrate pad, and a plurality of metal bumps are arranged on the side of the re-wiring structure away from the chip and are welded on the substrate pad.

3. The three-dimensional package structure of claim 2, wherein, The application further relates to a packaging method, which comprises the following steps: providing a first chip and an electric connecting piece, and electrically connecting the electric connecting piece on a first pad on the front surface of the first chip; providing a second chip and forming an electric connecting structure on a second pad of the second chip; fixing the second chip on the front surface of the first chip; forming an encapsulation layer on the front surface of the first chip and the front surface of the second chip; 4. The three-dimensional package structure of claim 1, wherein, ​ 5. The three-dimensional package structure of claim 1, wherein, ​ 6. The three-dimensional package structure of claim 1, wherein, ​ 7. The three-dimensional package structure of claim 1, wherein, ​ 8. The three-dimensional package structure of claim 7, wherein, ​ ​ ​ ​ 9. A semiconductor device, characterized by comprising: ​ 10. A packaging method of a three-dimensional package structure, characterized by, ​ ​ ​ ​ ​ Part of the encapsulation layer is removed to simultaneously expose the electrical connection structure and the electrical connection member outwardly; A re-wiring structure is formed above the encapsulation layer and is electrically connected with the electrical connection structure and the electrical connection member; The electrical connection member has a core and a solder body covering the core, and part of the solder body is removed to simultaneously expose the core and the solder body outwardly when part of the encapsulation layer is removed to simultaneously expose the electrical connection structure and the electrical connection member outwardly; A passivation layer is formed on the upper surface of the encapsulation layer before the re-wiring structure is formed, and part of the passivation layer is removed to form a passivation layer opening; The passivation layer opening is opposite to the position of the exposed core, and the size of the passivation layer opening is not greater than the size of the exposed core; the passivation layer covers the upper side of the exposed solder body; the solder body is connected with the passivation layer through an IMC layer formed on the top; the minimum distance between any point on the top surface of the solder body and the core is not more than 10 μm.

11. The packaging method of a three-dimensional package structure according to claim 10, wherein, The electrical connection member has a spherical structure, and the electrical connection member is welded on the first pad on the front surface of the first chip by a ball mounting process.

12. A packaging method of a three-dimensional package structure, characterized by, The method comprises the following steps: A first wafer is provided, wherein the first wafer comprises a plurality of first chips, and each first chip is provided with a first pad; An electrical connection member is provided, and the electrical connection member is electrically connected to the first pad; A second wafer is provided, wherein the second wafer comprises a plurality of second chips, and each second chip is provided with an electrical connection structure on a second pad of the second chip; The second wafer is cut to obtain single second chips, and the single second chips are stacked on the front surface of the first chip, wherein the front surface of the single second chip is consistent with the front surface of the first chip; An encapsulation layer is formed on the front surface of the first chip and the front surface of the second chip; Part of the encapsulation layer is removed to simultaneously expose the electrical connection structure and the electrical connection member outwardly; A re-wiring structure is formed above the encapsulation layer and is electrically connected with the electrical connection structure and the electrical connection member; the electrical connection member has a core and a solder body covering the core, and part of the solder body is removed to simultaneously expose the core and the solder body outwardly when part of the encapsulation layer is removed to simultaneously expose the electrical connection structure and the electrical connection member outwardly; A passivation layer is formed on the upper surface of the encapsulation layer before the re-wiring structure is formed, and part of the passivation layer is removed to form a passivation layer opening; the passivation layer opening is opposite to the position of the exposed core, and the size of the passivation layer opening is not greater than the size of the exposed core; the passivation layer covers the upper side of the exposed solder body; the solder body is connected with the passivation layer through an IMC layer formed on the top; the minimum distance between any point on the top surface of the solder body and the core is not more than 10 μm.

13. The packaging method of a three-dimensional package structure according to claim 12, wherein, After the re-wiring structure is formed above the encapsulation layer, the packaging method of the three-dimensional packaging structure further comprises: A metal bump for electrically connecting with an external circuit substrate is formed on the re-wiring structure; the metal bump is arranged on the side of the re-wiring structure away from the chip. The first wafer is cut to form post-encapsulation singulated chips.

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