A trench gate IGBT device

Abstract

The present invention provides a trench gate IGBT device, wherein an ohmic contact dielectric layer is introduced between a P+ ohmic contact region and an N+ ohmic contact region, and the P+ ohmic contact region and the N+ ohmic contact region are isolated by the ohmic contact dielectric layer, and after isolation, the P+ ohmic contact region and the N+ ohmic contact region can be effectively prevented from diffusing along the trench direction, thereby eliminating the restriction that the distance between the P+ ohmic contact region and the N+ ohmic contact region cannot be too small, reducing the risk of threshold voltage change, and improving the on-current and RBSOA capability of the device. At the same time, due to the presence of the ohmic contact dielectric layer, the design does not need to consider the influence of the diffusion of the P+ ohmic contact region and the N+ ohmic contact region of the device on the IGBT channel width, reducing the design difficulty and risk, and being able to solve the compromise relationship between the spacing between the P+ ohmic contact region and the N+ ohmic contact region and the IGBT device performance in the prior art, improving the performance of the IGBT device, and reducing the risk in the design of the IGBT.

Description

Technical Field

[0001] The invention belongs to the technical field of IGBT devices, and in particular relates to a trench gate IGBT device. Background Art

[0002] IGBT is a representative type of power semiconductor device. It has the advantages of high withstand voltage, low on-state voltage drop, easy drive, and fast switching speed. It has important applications in many power fields such as switching power supplies, variable frequency speed regulation, and new energy motor drives.

[0003] With the development of IGBT technology, trench gate IGBT devices have gradually become mainstream. In order to increase the current density of trench gate IGBT chips and reduce the loss of trench gate IGBT devices during on-time, the trench gate density of trench gate IGBT devices is getting higher and higher. Currently, micro-trench technology has become the mainstream technology cited in new products of various IGBT suppliers. In the current micro-trench technology, a common method for arranging the N+ ohmic contact and P+ ohmic contact in the channel region is to arrange them in intervals along the direction of the trench. This can effectively solve the problem of discrete threshold voltage VTH parameters caused by the traditional arrangement perpendicular to the trench direction, which results in the P+ ohmic contact area being too close to the trench gate.

[0004] Limitations of existing technologies:

[0005] The distance between the P+ ohmic contact area and the N+ ohmic contact area in this structure is a key technical parameter. If the distance is too small, the threshold voltage VTH parameter of the IGBT device will change, and the effective channel width will also decrease, affecting the current passing capacity of the IGBT. If the distance is too large, the RBSOA capability of the IGBT device will decrease, and the cell area will increase. Therefore, it is necessary to reasonably set the distance between the P+ ohmic contact area and the N+ ohmic contact area, and compromise the impact of the distance on the device performance. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a trench gate IGBT device. The trench gate IGBT device of the present invention introduces an ohmic contact dielectric layer between the P+ ohmic contact region and the N+ ohmic contact region, which can effectively eliminate the spacing restriction between the P+ ohmic contact region and the N+ ohmic contact region, reduce the risk of threshold voltage variation, and improve the on-current and RBSOA capability of the device. At the same time, the influence of the diffusion of the P+ ohmic contact region and the N+ ohmic contact region of the device on the IGBT channel width can be ignored during design, reducing the design difficulty and risk.

[0007] To achieve the above technical objectives, the technical solution adopted in the embodiment of the present invention is: a trench gate IGBT device, comprising an N-type base region, wherein an N-type buffer region and a P-type collector region are sequentially arranged on the back of the N-type base region, and an IGBT cell region is arranged on the front of the N-type base region, wherein the IGBT cell region comprises a plurality of IGBT cells, wherein the IGBT cell is a trench gate IGBT structure, wherein the IGBT cell comprises a trench gate, a P-type channel region, an N+ type ohmic contact region, a P+ type ohmic contact region, an ohmic contact dielectric layer and an emitter contact region;

[0008] The IGBT cell includes two parallel trench gates, the trench gates are arranged perpendicular to the N-type base region, and the bottoms of the trench gates are embedded in the N-type base region;

[0009] The P-type channel region is arranged between adjacent trench gates, an N+ type ohmic contact region and a P+ type ohmic contact region perpendicular to the trench gate are arranged on the surface of the P-type channel region, the N+ type ohmic contact region and the P+ type ohmic contact region are arranged alternately, and an ohmic contact dielectric layer parallel to each other is arranged between the N+ type ohmic contact region and the P+ type ohmic contact region;

[0010] The emitter contact region is arranged on the surface of the P-type channel region, and the emitter contact region is parallel to the trench gate and is not connected to the trench gate.

[0011] Furthermore, the distances between the ohmic contact dielectric layer and the adjacent N+ type ohmic contact region and the P+ type ohmic contact region are both 0-0.5 μm, and the width of the ohmic contact dielectric layer is 0.1-0.3 μm.

[0012] Furthermore, the depths of the ohmic contact dielectric layer, the N+ type ohmic contact region and the P+ type ohmic contact region are all set to 0.2~0.8μm, wherein the depths of the ohmic contact dielectric layer and the N+ type ohmic contact region are similar or the same, and the depth of the P+ type ohmic contact region is greater than the depth of the ohmic contact dielectric layer.

[0013] Further, the width of the N+ type ohmic contact region parallel to the trench gate meets the following condition: the ratio of the width of the N+ type ohmic contact region to the spacing between adjacent trench gates is less than 5.

[0014] Furthermore, the N+ type ohmic contact region, the P+ type ohmic contact region, the ohmic contact dielectric layer and the emitter contact region provided in some IGBT cells are reduced.

[0015] Furthermore, a portion of the emitter contact area is reduced.

[0016] Furthermore, the ohmic contact dielectric layer is made of insulating materials including SiO2.

[0017] The technical solution provided by the embodiment of the present invention has the following beneficial effects:

[0018] The present invention introduces an ohmic contact dielectric layer between the P+ ohmic contact area and the N+ ohmic contact area, and isolates the P+ ohmic contact area and the N+ ohmic contact area through the ohmic contact dielectric layer. After isolation, the P+ ohmic contact area and the N+ ohmic contact area can be effectively prevented from diffusing along the groove direction, thereby eliminating the restriction that the distance between the P+ ohmic contact area and the N+ ohmic contact area cannot be too small, reducing the risk of threshold voltage change, and improving the on-current and RBSOA capability of the device. At the same time, due to the presence of the ohmic contact dielectric layer, the design does not need to consider the influence of the diffusion of the P+ ohmic contact area and the N+ ohmic contact area of ​​the device on the IGBT channel width, reducing the design difficulty and risk, and can solve the compromise relationship between the spacing between the P+ ohmic contact area and the N+ ohmic contact area and the IGBT device performance in the prior art, improve the performance of the IGBT device, and reduce the risk in the design of the IGBT. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the structure of the trench gate IGBT device in Example 1 of the present invention.

[0020] Figure 2 yes Figure 1 Top view of a trench gate IGBT device.

[0021] Figure 3 It is a schematic diagram of the structure of the trench gate IGBT device in Example 2 of the present invention.

[0022] Figure 4 It is a schematic diagram of the structure of the trench gate IGBT device in Example 3 of the present invention.

[0023] Figure 5 It is a schematic diagram of the structure of an existing IGBT device.

[0024] Figure 6 yes Figure 3 Top view of the IGBT device.

[0025] Explanation of the accompanying drawings: 1. N-type base region; 2. N-type buffer region; 3. P-type collector region; 41. Trench gate; 42. P-type channel region; 43. N+ type ohmic contact region; 44. P+ type ohmic contact region; 45. Ohmic contact dielectric layer; 46. Emitter contact region. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0027] Example 1

[0028] like Figure 1 and 2 As shown, a trench gate IGBT device comprises an N-type base region 1, an N-type buffer region 2 and a P-type collector region 3 are sequentially arranged on the back of the N-type base region 1, an IGBT cell region is arranged on the front of the N-type base region 1, the IGBT cell region comprises a plurality of IGBT cells, the IGBT cell is a trench gate IGBT structure, the IGBT cell comprises a trench gate 41, a P-type channel region 42, an N+ type ohmic contact region 43, a P+ type ohmic contact region 44, an ohmic contact dielectric layer 45 and an emitter contact region 46;

[0029] The IGBT cell includes two adjacent parallel trench gates 41, which are arranged perpendicular to the base region and have their bottoms embedded in the N-type base region 1;

[0030] The P-type channel region 42 in the IGBT cell is arranged between adjacent trench gates 41, and an N+ type ohmic contact region 43 and a P+ type ohmic contact region 44 are arranged perpendicular to the trench gates 41 on the surface of the P-type channel region 42, the N+ type ohmic contact region 43 and the P+ type ohmic contact region 44 are arranged alternately, and a parallel ohmic contact dielectric layer 45 is arranged between the N+ type ohmic contact region 43 and the P+ type ohmic contact region 44;

[0031] The emitter contact region 46 in the IGBT cell is disposed on the surface of the P-type channel region 42 , parallel to the trench gate 41 , and not connected to the trench gate 41 .

[0032] The distances between the ohmic contact dielectric layer 45 and the N+ type ohmic contact region 43 and the P+ type ohmic contact region 44 are all 0.1 μm, and the width of the ohmic contact dielectric layer 45 is 0.15 μm.

[0033] The depth of the ohmic contact dielectric layer 45 and the depth of the N+ type ohmic contact region 43 are both 0.4 μm, and the depth of the P+ type ohmic contact region 44 is 0.6 μm.

[0034] The width of the N+ ohmic contact region 43 parallel to the trench gate 41 satisfies the following condition: the ratio of the width of the N+ ohmic contact region 43 to the distance between adjacent trench gates 41 is 3.

[0035] The ohmic contact dielectric layer 45 is made of insulating material, preferably SiO2.

[0036] Example 2

[0037] A trench gate IGBT device, such as Figure 3 As shown, compared with Example 1, the trench gate IGBT device of this embodiment reduces the N+ type ohmic contact region 43, the P+ type ohmic contact region 44, the ohmic contact dielectric layer 45 and the emitter contact region 46 set in some IGBT cells, and the rest of the structure is exactly the same.

[0038] Example 3

[0039] A trench gate IGBT device, such as Figure 4 As shown, compared with the embodiment 1, the trench gate IGBT device of this embodiment reduces part of the emitter contact region 46, and the rest of the structure is completely the same.

[0040] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A trench gate IGBT device, comprising an N-type base region (1), an N-type buffer region (2) and a P-type collector region (3) being sequentially arranged on the back side of the N-type base region (1), an IGBT cell region being arranged on the front side of the N-type base region (1), the IGBT cell region comprising a plurality of IGBT cells, characterized in that: The IGBT cell is a trench gate IGBT structure, and the IGBT cell comprises a trench gate (41), a P-type channel region (42), an N+ type ohmic contact region (43), a P+ type ohmic contact region (44), an ohmic contact dielectric layer (45), and an emitter contact region (46); The IGBT cell comprises two parallel trench gates (41), wherein the trench gates (41) are arranged perpendicular to the N-type base region (1), and the bottoms of the trench gates (41) are embedded in the N-type base region (1); The P-type channel region (42) is arranged between adjacent trench gates (41); an N+ type ohmic contact region (43) and a P+ type ohmic contact region (44) perpendicular to the trench gate (41) are arranged on the surface of the P-type channel region (42); the N+ type ohmic contact region (43) and the P+ type ohmic contact region (44) are arranged alternately; and a mutually parallel ohmic contact dielectric layer (45) is arranged between the N+ type ohmic contact region (43) and the P+ type ohmic contact region (44); The emitter contact region (46) is arranged on the surface of the P-type channel region (42), the emitter contact region (46) is parallel to the trench gate (41), and is not connected to the trench gate (41); The distances between the ohmic contact dielectric layer (45) and the adjacent N+ type ohmic contact region (43) and P+ type ohmic contact region (44) are both 0-0.5 μm, and the width of the ohmic contact dielectric layer (45) is 0.1-0.3 μm; The depths of the ohmic contact dielectric layer (45), the N+ type ohmic contact region (43) and the P+ type ohmic contact region (44) are all set to 0.2-0.8 μm, wherein the depths of the ohmic contact dielectric layer (45) and the N+ type ohmic contact region (43) are similar or the same, and the depth of the P+ type ohmic contact region (44) is greater than the depth of the ohmic contact dielectric layer (45).

2. The trench gate IGBT device according to claim 1, characterized in that: The width of the N+ type ohmic contact region (43) in a direction parallel to the trench gate (41) satisfies the following condition: the ratio of the width of the N+ type ohmic contact region (43) to the spacing between adjacent trench gates (41) is less than 5.

3. The trench gate IGBT device according to claim 1, characterized in that: The ohmic contact dielectric layer (45) is made of insulating materials including SiO2.

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