A Ka-band broadband small-step frequency synthesizer

Abstract

The present invention discloses a Ka-band broadband small-step frequency synthesizer, and relates to the field of satellite communications. The present invention is composed of a control circuit, a programmable reference circuit, a phase-locked circuit, an amplifier, a frequency multiplier, a filter and other components. The present invention adopts a single-loop phase-locked architecture with multiple references and high phase discrimination to achieve ultra-wideband local oscillator signal output, and has the advantages of small output step, fast frequency hopping, low phase noise, low spurious, low harmonics, wide frequency range, high degree of integration, low power consumption, simple structure, stable and reliable performance, etc. The present invention adopts a modular design, has a simple structure, stable and reliable performance, can work normally in a relatively harsh environment, and is particularly suitable for the frequency synthesizer implementation of ultra-wideband radio frequency channels in satellite communication systems in the Q band and V band.

Description

Technical Field

[0001] The present invention relates to a frequency synthesizer in the field of satellite communications, in particular to a Ka-band broadband small-step frequency synthesizer which can be used as a local oscillator source for ultra-wideband frequency conversion channel equipment. Background Art

[0002] With the advancement of Q-band and V-band satellite communication technologies, RF channel bandwidths are increasing. Ultra-wideband RF channels place increasing demands on frequency synthesizers with miniaturization, low power consumption, small step sizes, and ultra-wideband performance. Existing wideband frequency synthesis solutions rely on multi-loop synthesis using large-step phase-locked loops and small-step phase-locked loops. These circuits are complex, power-hungry, and bulky, and therefore cannot meet the requirements of RF channel terminals. Summary of the Invention

[0003] The object of the present invention is to avoid the deficiencies in the above-mentioned background technology and provide a Ka-band broadband small-step frequency synthesizer. The present invention adopts a multi-reference, high phase-detection scheme and has the characteristics of small output step, fast frequency hopping, low phase noise, low spurious, low harmonics, wide frequency range, high degree of integration, low power consumption, simple structure, stable and reliable performance, etc.

[0004] The object of the present invention is achieved like this:

[0005] A Ka-band broadband small-step frequency synthesizer, comprising a control circuit 1, a programmable reference circuit 2, a phase-locked circuit 3, a first amplifier 4, a first frequency multiplier 5, a first filter 6, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a third capacitor C3;

[0006] The input port of the control circuit 1 is connected to the external digital interface, and the output port is connected to the programmable reference circuit 2 and the phase-locked circuit 3;

[0007] The programmable reference circuit 2 generates four reference signals of different frequencies and outputs them to the phase-locked circuit 3;

[0008] The phase-locked circuit 3 performs frequency synthesis based on the input reference signal and the control signal, locks the local oscillator signal well through the external loop filter, and outputs the locked local oscillator signal to the first amplifier 4;

[0009] The first amplifier 4 amplifies the local oscillator signal and outputs it to the first frequency multiplier 5;

[0010] The first frequency multiplier 5 doubles the frequency of the local oscillator signal and outputs it to the first filter 6;

[0011] The first filter 6 suppresses harmonics of the input signal and connects the filtered signal to the outside;

[0012] The first resistor R1, the second resistor R2, the first capacitor C1, the second capacitor C2, and the third capacitor C3 form a phase-locked loop filter to filter out high-frequency components and noise in the error voltage.

[0013] Furthermore, one end of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are all connected to the ground, and the other end of the first capacitor C1 is connected to the phase-locked circuit 3; the first resistor R1 is connected in series between the first capacitor C1 and the second capacitor C2, and the second resistor R2 is connected in series between the first capacitor C1 and the third capacitor C3.

[0014] Furthermore, the programmable reference circuit 2 is composed of a power divider 7, a frequency divider 8, a second filter 9, a second frequency multiplier 10, a third filter 11, a second amplifier 12, a mixer 13, a first switch 14, a fourth filter 15, a fifth filter 16, a second switch 17, and a third amplifier 18;

[0015] The power divider 7 is connected to the external 100MHz signal, and after being split into two, it is output to the input port of the frequency divider 8 and the second frequency multiplier 10;

[0016] The frequency divider 8 divides the 100 MHz signal into four or five, and the divided signal is output to the second filter 9;

[0017] The second filter 9 suppresses the harmonics of the input signal and outputs it as an intermediate frequency signal to the mixer 13;

[0018] The second frequency multiplier 10 doubles the frequency of the input 100 MHz signal and outputs the doubled signal to the third filter 11;

[0019] The third filter 11 suppresses the harmonics of the input signal and outputs a low-spurious 200 MHz signal to the second amplifier 12;

[0020] The second amplifier 12 amplifies the input 200 MHz signal and outputs it as a local oscillator signal to the mixer 13;

[0021] The mixer 13 linearly superposes the input intermediate frequency signal and the local oscillator signal and outputs the result to the first switch 14;

[0022] The first switch 14 outputs the mixed signal to the fourth filter 15 or the fifth filter 16 for spurious suppression;

[0023] The fourth filter 15 outputs the filtered signal to the second switch 17; the fifth filter 16 outputs the filtered signal to the second switch 17; the second switch 17 selects the input signal and outputs the selected signal to the third amplifier 18;

[0024] The third amplifier 18 amplifies the input signal and outputs the amplified signal to the phase-locked circuit 3 .

[0025] Furthermore, the control circuit 1 analyzes the input frequency and, through FPGA simulation calculation, selects four different phase-locked frequencies of 175 MHz, 180 MHz, 220 MHz, and 225 MHz, and deviates the fractional spurious signals of all frequencies within 15 GHz to 30 GHz beyond the main frequency of 23 MHz, thereby filtering out the fractional spurious signals through the narrowband loop filtering characteristics of the phase-locked circuit 3.

[0026] Compared with the background technology, the present invention has the following advantages:

[0027] 1. This invention breaks through the traditional multi-loop synthesis mode of thinking and uses a single-loop, high phase-detection frequency, multi-reference fractional frequency division architecture to achieve low spurious, low phase noise, small-step Ka-band broadband local oscillator signal output.

[0028] 2. The present invention uses analog direct frequency synthesis to achieve the switching of the phase-lock frequency, which not only improves the switching time of the phase-lock frequency to the nanosecond level, but also reduces the noise floor and spurious degradation of the phase-lock frequency to the theoretical minimum.

[0029] 3. The present invention has a high degree of integration, low power consumption, small debugging workload, and can work normally in a relatively harsh ambient temperature of -40°C to +85°C.

[0030] 4. The present invention adopts optimized single-loop architecture phase-locked technology to achieve ultra-wideband local oscillator signal output of 22GHz to 30GHz with a step of 0.1Hz.

[0031] 5. The circuit structure of the present invention is simple, small in size, low in cost, and has the value of popularization and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a block diagram of the electrical principle of the present invention.

[0033] Figure 2 yes Figure 1 The electrical principle block diagram of the programmable reference circuit. DETAILED DESCRIPTION

[0034] like Figure 1As shown, a Ka-band broadband small-step frequency synthesizer includes a control circuit 1, a programmable reference circuit 2, a phase-locked circuit 3, an amplifier 4, a frequency multiplier 5, a filter 6, resistors R1, R2, and capacitors C1, C2, and C3; the input port of the control circuit 1 is connected to an external digital interface, and the output port is connected to the programmable reference circuit 2 and the phase-locked circuit 3; the programmable reference circuit 2 generates four reference signals of different frequencies and outputs them to the phase-locked circuit 3; the phase-locked circuit 3 performs frequency synthesis based on the input reference signal and the control signal, and The external loop filter locks the local oscillator signal effectively and outputs the locked local oscillator signal to amplifier 4; amplifier 4 amplifies the local oscillator signal and outputs it to frequency multiplier 5; frequency multiplier 5 doubles the local oscillator signal and outputs it to filter 6; filter 6 suppresses harmonics of the input signal and connects the filtered signal to the outside; resistors R1 and R2 and capacitors C1, C2, and C3 form a phase-locked loop filter, which filters out high-frequency components and noise in the error voltage to ensure the required loop performance and improve system stability.

[0035] like Figure 2 As shown, the programmable reference circuit 2 includes a power divider 7, a frequency divider 8, a filter 9, a frequency multiplier 10, a filter 11, an amplifier 12, a mixer 13, a switch 14, a filter 15, a filter 16, a switch 17, and an amplifier 18. The power divider 7 is connected to an external 100MHz signal, and after being divided into two, it is output to the input ports of the frequency divider 8 and the frequency multiplier 10; the frequency divider 8 divides the 100MHz signal into four or five, and the divided signal is output to the filter 9; the filter 9 suppresses the harmonics of the input signal and outputs it as an intermediate frequency signal to the mixer 13; the frequency multiplier 10 doubles the input 100MHz signal and outputs the multiplied signal to the filter 11; the filter 11 suppresses the harmonics of the input signal and outputs a low-spurious 200MHz signal to the second amplifier 12; the amplifier The mixer 12 amplifies the input 200 MHz signal and outputs it as a local oscillator signal to the mixer 13; the mixer 13 linearly superimposes the input intermediate frequency signal and the local oscillator signal and outputs it to the switch 14; the switch 14 outputs the mixed signal to the filter 15 or the filter 16 for spurious suppression; the filter 15 outputs the filtered signal to the switch 17; the filter 16 outputs the filtered signal to the switch 17; the switch 17 selects the output signal and outputs the selected signal to the amplifier 18; the amplifier amplifies the input signal and outputs it to the phase-locked circuit 3.

[0036] The control circuit 1 analyzes the input frequency and performs FPGA simulation calculations. When four different phase-locked frequencies of 175MHz, 180MHz, 220MHz, and 225MHz are selected, the fractional spurious signals of all frequencies between 15GHz and 30GHz can be deviated from the main frequency by 23MHz. In this way, the fractional spurious signals can be filtered out by the narrowband loop filtering characteristics of the phase-locked loop, thereby achieving the characteristics of small step size, low spurious signals, and low phase noise.

[0037] Reference Figure 1 and Figure 2 A Ka-band broadband small-step frequency synthesizer is composed of a control circuit 1, a programmable reference circuit 2, a phase-locked circuit 3, an amplifier 4, a frequency multiplier 5, a filter 6, resistors R1 and R2, and capacitors C1, C2, and C3. Figure 1 This is a block diagram of the electrical principle of the embodiment. Figure 1 Connection circuit. Among them, the control circuit 1 is connected to the external digital interface signal to realize external protocol recognition and internal timing configuration. The embodiment is made of the commercially available dedicated EP3C10F256I7N; the programmable circuit 2 generates four reference signals of different frequencies through analog direct frequency synthesis and outputs them to the phase-locked circuit 3; the phase-locked circuit 3 realizes small step frequency synthesis based on the input reference signal and control signal. The embodiment is made of the commercially available dedicated LMX2594RHAT. The LMX2594RHAT has a 32-bit fractional frequency division mode, and the frequency error can be reduced to 0.05Hz, which can achieve very small frequency steps; resistors R1, R2 capacitors C1, C2 Together with C3, a fast frequency hopping loop filter is formed for the phase-locked loop chip LMX2594RHAT to achieve fast locking. In the embodiment, commercially available general-purpose 0603 resistors and capacitors are used to make it. The amplifier 4 amplifies the fundamental frequency local oscillator signal to provide a certain gain. In the embodiment, the commercially available dedicated HMC516LC5 is used to make it. The frequency multiplier 5 doubles the frequency of the input fundamental frequency local oscillator signal. In the embodiment, the commercially available dedicated HMC578LC3B is used to make it. The filter 6 suppresses harmonics of the input signal and connects the filtered signal to the external interface B. In the embodiment, the BPF22-30GK-2624 of Chengdu Senaside Technology Co., Ltd. is used to make it.

[0038] Specifically, the control circuit 1 is connected to the external digital interface signal, analyzes the input control protocol, calculates the optimal phase-locked frequency through FPGA simulation, makes the fractional frequency spurious deviate from the main frequency beyond 23MHz, and outputs the control signal to the programmable reference circuit 2 and the phase-locked circuit 3 respectively; the programmable circuit 2 generates one of the four reference signals of 175MHz, 180MHz, 220MHz, and 225MHz through analog direct frequency synthesis, and outputs it to the phase-locked circuit 3; the phase-locked circuit 3 performs frequency synthesis based on the input reference signal and control signal, and outputs the reference signal through the external loop filter. The local oscillator signal is locked well and the locked local oscillator signal (11 GHz to 15 GHz) is output to amplifier 4. Resistors R1 and R2, capacitors C1, C2, and C3 form a fast frequency hopping loop filter for the phase-locked loop chip LMX2594RHAT to achieve fast locking. Amplifier 4 amplifies the fundamental frequency local oscillator signal, provides a certain gain, and outputs it to multiplier 5. Multiplier 5 doubles the input fundamental frequency local oscillator signal and outputs it at 22 GHz to 30 GHz. Filter 6 suppresses harmonics of the 22 GHz to 30 GHz signal and connects the filtered signal to external interface B.

[0039] Reference Figure 2 The programmable reference circuit 2 is composed of a power divider 7, a frequency divider 8, a filter 9, a frequency multiplier 10, a filter 11, an amplifier 12, a mixer 13, a switch 14, a filter 15, a filter 16, a switch 17, and an amplifier 18. Figure 2 This is the electrical schematic diagram of the programmable reference circuit 2. Figure 2Connecting lines. The power divider 7 divides the input 100MHz reference signal. In the embodiment, the commercially available dedicated SD-2 is used. The frequency divider 8 divides the 100MHz signal into four or five frequencies. In the embodiment, the commercially available dedicated HMC394LP4 is used. The filter 9 filters the output signal of the frequency divider 8. The filter is a self-made elliptical LC filter. In the embodiment, the commercially available general-purpose 0603 inductor and capacitor are used to make it. The frequency multiplier 10 doubles the frequency of the 100MHz reference signal. In the embodiment, the commercially available dedicated AMK-2-13+ is used. The filter 11 suppresses the harmonics of the multiplied signal. In the embodiment, the NDF2319 surface acoustic wave filter of Nanjing Jicheng Electronic Technology Co., Ltd. is used. The amplifier 12 amplifies the 200MHz signal after the multiplication. The embodiment uses the commercially available dedicated SPF5043Z; the mixer 13 linearly superimposes the multiplied signal and the divided signal, and the embodiment uses the commercially available dedicated ADEX-10L; the switch 14 and the switch 17 perform switch selection on the mixed signal, and the embodiment uses the commercially available dedicated HMC349MS8G; the filter 15 suppresses the mixing spurious of the high-band reference signal, and the embodiment uses the NDF2321 surface acoustic wave filter of Nanjing Jicheng Electronic Technology Co., Ltd.; the filter 16 suppresses the mixing spurious of the low-band reference signal, and the embodiment uses the NDF2320 surface acoustic wave filter of Nanjing Jicheng Electronic Technology Co., Ltd.; the amplifier 18 amplifies the final reference signal, and the embodiment uses the commercially available dedicated SPF5043Z.

[0040] Specifically, the power divider 7 is connected to the external 100MHz signal, and after the two-way split, it is output to the input port of the frequency divider 8 and the frequency multiplier 10; the frequency divider 8 divides the 100MHz signal into four or five, and outputs 20MHz or 25MHz to the filter 9 after the frequency division; the filter 9 suppresses the harmonics of 20MHz or 25MHz and outputs it as an intermediate frequency signal to the mixer 13; the frequency multiplier 10 doubles the input 100MHz signal and outputs a 200MHz signal to the filter 11 after the frequency multiplication; the filter 11 suppresses the harmonics of the 200MHz signal and outputs it to the mixer amplifier 12; the amplifier 12 suppresses the input 200MHz signal After amplification, the signal is output as a local oscillator signal to mixer 13; mixer 13 linearly superimposes the input 20 MHz or 25 MHz intermediate frequency signal and the 200 MHz local oscillator signal, and outputs 175 MHz, 180 MHz, 220 MHz, and 225 MHz signals to switch 14; switch 14 outputs the 175 MHz and 180 MHz signals to filter 15 for spurious suppression or outputs the 220 MHz and 225 MHz signals to filter 16 for spurious suppression; switch 17 selects the filtered signal and outputs the selected signal to amplifier 18; amplifier 18 amplifies the final reference signal and outputs it to phase-locked circuit 3.

[0041] The present invention briefly works as follows:

[0042] The input port of control circuit 1 is connected to an external digital interface at the input port, identifies the external interface protocol, and configures phase-locked circuit 3 and programmable reference circuit 2 according to the fractional frequency spurious optimization algorithm. The input port of power divider 7 is connected to an external reference source at input port C. The reference source signal can output four reference signals of different frequencies through programmable reference circuit 2. Phase-locked circuit 3 performs frequency synthesis based on the input reference signal and control signal, and effectively locks the local oscillator signal through an external loop filter. The locked local oscillator signal passes through amplifier 4, frequency multiplier 5, and filter 6, extending the frequency to a Ka-band broadband output. First, power is turned on. Control circuit 1 communicates with the external interface and configures data for programmable reference circuit 2 and phase-locked circuit 3. Phase-locked circuit 3 outputs the local oscillator's baseband signal, which is input to output port B through amplifier 4, frequency multiplier 5, and filter 6.

[0043] The installation structure of the present invention is as follows:

[0044] Bundle Figure 1 and Figure 2 All components of the control circuit 1, programmable reference circuit 2, phase-locked circuit 3, amplifier 4, and frequency multiplier 5 are double-sided mounted on a four-layer printed circuit board (PCB) measuring 72 mm (L x W x W) by 72 mm. The PCB is then mounted within a shielded enclosure, sealed by upper and lower covers. The filter 6 is secured to the enclosure's sidewalls with M2 screws and connected to the frequency multiplier 5 via an RF cable. The input port utilizes a 15-core J30J-15ZKWP socket, while input port C utilizes an SMA-KFK socket. Output port B utilizes a 2.92-KFK socket, completing the assembly of the present invention.

[0045] In summary, the present invention utilizes a multi-reference, high-phase-detection, single-loop phase-locked architecture to achieve ultra-wideband local oscillator signal output. This architecture offers advantages such as small output steps, fast frequency hopping, low phase noise, low spurious signals, low harmonics, a wide frequency range, high integration, low power consumption, a simple structure, and stable and reliable performance. The present invention utilizes a modular design, resulting in a simple structure and stable and reliable performance, capable of operating normally in harsh environments. It is particularly suitable for implementing frequency synthesizers for ultra-wideband RF channels in Q- and V-band satellite communication systems.

Claims

1. A Ka-band broadband small-step frequency synthesizer, characterized in that: The invention comprises a control circuit (1), a programmable reference circuit (2), a phase-locked circuit (3), a first amplifier (4), a first frequency multiplier (5), a first filter (6), a first resistor (R1), a second resistor (R2), a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3); The input port of the control circuit (1) is connected to an external digital interface, and the output port is connected to a programmable reference circuit (2) and a phase-locked circuit (3); The programmable reference circuit (2) generates four reference signals with different frequencies and outputs them to the phase-locked circuit (3); The phase-locked circuit (3) performs frequency synthesis according to the input reference signal and the control signal, locks the local oscillator signal well through an external loop filter, and outputs the locked local oscillator signal to the first amplifier (4); The first amplifier (4) amplifies the local oscillator signal and outputs the amplified signal to the first frequency multiplier (5); The first frequency multiplier (5) doubles the frequency of the local oscillator signal and outputs the signal to the first filter (6); The first filter (6) performs harmonic suppression on the input signal and connects the filtered signal to the outside; The first resistor (R1), the second resistor (R2), the first capacitor (C1), the second capacitor (C2), and the third capacitor (C3) form a phase-locked loop filter to filter out high-frequency components and noise in the error voltage; The programmable reference circuit (2) is composed of a power divider (7), a frequency divider (8), a second filter (9), a second frequency multiplier (10), a third filter (11), a second amplifier (12), a mixer (13), a first switch (14), a fourth filter (15), a fifth filter (16), a second switch (17), and a third amplifier (18); The power divider (7) is connected to an external 100 MHz signal and outputs to the input ports of the frequency divider (8) and the second frequency multiplier (10) after being divided into two paths; The frequency divider (8) divides the 100 MHz signal into four or five frequencies, and outputs the divided signal to the second filter (9); The second filter (9) suppresses the harmonics of the input signal and outputs the signal as an intermediate frequency signal to the mixer (13); The second frequency multiplier (10) doubles the frequency of the input 100 MHz signal, and outputs the frequency-multiplied signal to the third filter (11); The third filter (11) suppresses the harmonics of the input signal and outputs a low-spurious 200 MHz signal to the second amplifier (12); The second amplifier (12) amplifies the input 200 MHz signal and outputs it as a local oscillator signal to the mixer (13); The mixer (13) linearly superimposes the input intermediate frequency signal and the local oscillator signal and outputs the result to the first switch (14); The first switch (14) outputs the mixed signal to the fourth filter (15) or the fifth filter (16) for spurious suppression; The fourth filter (15) outputs the filtered signal to the second switch (17); the fifth filter (16) outputs the filtered signal to the second switch (17); the second switch (17) selects the input signal and outputs the selected signal to the third amplifier (18); The third amplifier (18) amplifies the input signal and outputs it to the phase-locked circuit (3).

2. A Ka-band broadband small-step frequency synthesizer according to claim 1, characterized in that: One end of the first capacitor (C1), the second capacitor (C2) and the third capacitor (C3) are all connected to the ground, and the other end of the first capacitor (C1) is connected to the phase-locked circuit (3); the first resistor (R1) is connected in series between the first capacitor (C1) and the second capacitor (C2), and the second resistor (R2) is connected in series between the first capacitor (C1) and the third capacitor (C3).

3. A Ka-band broadband small-step frequency synthesizer according to claim 1, characterized in that: The control circuit (1) analyzes the input frequency and, through FPGA simulation calculation, when selecting four different phase-locked frequencies of 175 MHz, 180 MHz, 220 MHz and 225 MHz, decimal spurs at all frequency points within 15 GHz to 30 GHz are deviated outside the main frequency of 23 MHz, thereby filtering out the decimal spurs through the narrowband loop filtering characteristics of the phase-locked circuit (3).

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