Multiply Accumulator

Abstract

An analog multiplier accumulator array comprises: analog multipliers arranged to form a matrix with rows and columns, wherein each analog multiplier comprises one or more analog input signal lines connected to the analog multipliers with rows of the array; an analog level sensing circuit; a group of bit lines, each bit line being electrically connected to the analog multiplier with columns of the row; and an analog accumulator arranged to connect the group of bit lines to the analog level sensing circuit to generate a digital output signal, wherein an access transistor and a variable resistor connected to the analog input signal lines form the analog multiplier.

Description

[0001] Related Applications

[0002] This application claims priority to the following prior application: U.S. Provisional Patent Application No. 62 / 901,270, filed on September 17, 2019, entitled “Multiply-Accumulate Unit,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to an accumulator circuit, and more particularly to an improved multiplier circuit using an analog circuit. Background Art

[0004] Multiply-Accumulator (MAC) circuits, which are used to perform multiplication operations on digital signals, are usually quite complex and large. Moreover, real-time MACs usually require fast ("on the fly") programming to efficiently generate operation outputs based on real-time input data. On the other hand, flash memory can be an effective way to store non-volatile data on an integrated circuit. However, flash memory must be programmed before running the circuit, and flash memory cannot be updated before running MAC operations due to its slow programming speed and limited availability of reprogramming. Therefore, data stored in flash memory should be static during MAC operations.

[0005] Figure 11 is a simplified functional block diagram of a conventional MAC array. The MAC array 100 is widely used in digital signal processing, communication, network and neural network. Such a conventional all-digital MAC includes a digital multiplier, a digital adder and a digital accumulator. Each subunit includes a plurality of digital logic gates combined with a plurality of transistors. Digital input data is fed from the data input bus D_IN_BUS for the MAC array 100 to receive. The MAC array data output is connected to the data output bus D_OUT_BUS. For the operation involved in a single MAC, each digit of a single operand (from the data input bus D_IN_BUS) is multiplied with each digit of the other operand (from the data input bus D_IN_BUS) to form a partial product; then these results are added. Then, those added products are sent to the digital accumulator in sequence and executed by the data output bus D_OUT_BUS. Such a conventional MAC array 100 generally requires a relatively large number of transistors, thereby occupying a relatively large chip area during fabrication of a large number of transistors on an integrated circuit, and such areal density is not efficient. When processing the operation of a single MAC, each digital logic signal requires a full VDD-GND swing, and each single wire in the MAC array carries only a single bit. Therefore, the conventional MAC array consumes a relatively large amount of power inefficiently. Due to this technical limitation, the goal of integrated circuit developers is to find a way to implement a multiplier with simple and efficient circuit components.

[0006] Figure 2 The MAC array 200 includes a plurality of non-volatile synapse (NV Synapse) cells arranged in a matrix of rows and columns. A plurality of word lines WL2, WL1 and WL0 are electrically connected to each non-volatile synapse cell in each row. A plurality of reference lines SL2, SL1 and SL0 are electrically connected to each non-volatile synapse cell in each row. Two pairs of complementary bit lines BL0 / BLB0 and BL1 / BLB1 are each connected to each non-volatile synapse cell in each row. A sensing circuit provides a pair of differential currents in a plurality of bit lines to each non-volatile synapse cell in each row. Four transistors (two pairs of CSO / CS1) connect the sensing circuit to the plurality of synapse cells and enable or disable the current (I BL ,I BLB ).

[0007] Although not shown, as a multiplier / accumulator circuit, each non-volatile synaptic cell is configured to receive an input as a first operand X and use a stored value (parameter) as a second operand Y. The non-volatile synaptic cell can be implemented to store the second operand Y using the aforementioned flash memory. After this storage, the second operand Y can be represented as a filter coefficient or weight parameter associated with a particular non-volatile synaptic cell. Each non-volatile synaptic cell generates a partial product from the first operand X and the second operand Y, and then the resulting partial products are summed in the corresponding bit line. The sensing circuit located at the end of the two complementary bit lines amplifies the small voltage difference between the analog input terminals of the complementary bit lines BL0 / BLB0 to a normal logic level. Assuming that the stored second operand Y is static, this architecture cannot support real-time MAC operations where the values ​​of its operands need to be updated in real time. Therefore, the MAC operation can only be obtained from the specific non-volatile synaptic cells in the array that have those pre-programmed parameter values.

[0008] This limits the available computing power to the size of a given non-volatile synaptic unit array. For example, if the MAC array has 1 million non-volatile synaptic units, the total number of available parameters is limited to no more than 1 million because each non-volatile synaptic unit can only store 1 parameter value at the moment. Therefore, in neural network applications, this traditional architecture is not efficient for deep and large models and training purposes because the total number of available operands is limited by the long programming time of non-volatile synaptic units. Summary of the invention

[0009] The present invention provides an accumulator circuit, in particular to an improved multiplication accumulator circuit realized by using an analog circuit.

[0010] According to the present invention, an analog multiplier accumulator array includes: a plurality of analog multipliers arranged to form a matrix with rows and columns, wherein each of the analog multipliers includes: one or more analog input signal lines coupled to a plurality of analog multipliers on one row of the array; an analog level sensing circuit; a group of bit lines having at least one bit line, each bit line being electrically connected to each column of the analog multipliers on one row; and an analog accumulator configured to connect the bit line to the analog level sensing circuit to generate a digital output signal, wherein an access transistor and a variable resistor connected to the analog input signal line form an analog multiplier.

[0011] In one embodiment, the variable resistor includes: one or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and the access transistor has a gate terminal connected to a second analog input line.

[0012] In another embodiment, the variable resistor includes: a read transistor; and a pair of coupling transistors configured to have a shared floating gate with the read transistor, wherein the coupling transistors are coupled to an input line, and the input line is separated from an analog input signal line connected to the access transistor.

[0013] In another embodiment, the analog multiplier further includes a switching transistor connected in series with the access transistor, the switching transistor having a gate terminal connected to the digital input line.

[0014] In another embodiment, a switching transistor is connected in series with the variable resistor so that the access transistor enables or disables current in the bit line to direct the variable resistor.

[0015] In another embodiment, the variable resistor includes: one or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and an access transistor has a gate terminal connected to a second analog input line.

[0016] Also, as another embodiment, the variable resistor includes: a read transistor; and a pair of coupling transistors configured to have a shared floating gate with the read transistor, wherein one of the coupling transistors is connected to a programming word line, and the other coupling transistor of the coupling transistors is connected to a write word line.

[0017] In another embodiment, the program word line connection is coupled to a control gate of one of the transistors, and the write word line connection is coupled to another of the transistors.

[0018] In another embodiment, the analog accumulator includes: an array of MOS transistors arranged in rows, each MOS transistor connected to a bit line in the group of bit lines; and a control line connected to the gate of the MOS transistor to enable switching of the MOS transistor, so that during the activation of the MOS transistor, currents flowing in the connected multiple bit lines are converged into one of the connected multiple bit lines.

[0019] In addition, in another embodiment, the analog accumulator includes: an array of CMOS transistors arranged in rows, each CMOS transistor being connected to a bit line in a bit line set; and a pair of control lines, connecting the gates of NMOS transistors forming the CMOS transistors, and the second source nodes being connected to the gates of PMOS transistors forming the CMOS transistors, so that during the start-up of the NMOS transistors, the PMOS transistors, or the NMOS transistors and the PMOS transistors, currents flowing through the connected plurality of bit lines are merged into one of the connected plurality of bit lines.

[0020] In addition, as another embodiment, the analog accumulator includes: an array of paired PMOS transistors in rows forming a current mirror, each pair of PMOS transistors forming a current mirror and including: a pair of first transistors and a second transistor having a shared node to connect the gates of a pair of transistors, wherein the first transistor has a drain terminal connected to the shared node, and the second transistor has a drain terminal that outputs an amplified current according to a current flowing in a bit line connected to the shared node.

[0021] According to the present invention, an analog multiplier accumulator array includes: analog multipliers arranged in a matrix of rows and columns, each multiplier including: pairs of analog input signal lines coupled to the analog multipliers in a row of the array; an analog level detection circuit; a group of bit lines, each bit line electrically connected to the analog multipliers in each column of the row; the analog accumulator is configured to connect the group of bit lines to the analog level sensing circuit for generating a digital output signal, wherein a pair of differential transistors, a variable resistor and a switch transistor form the analog multiplier.

[0022] In another embodiment, a first differential transistor in the differential transistors has a first signal line with a gate coupled to a pair of analog input signal lines, and the first differential transistor is associated with a first bit line of a group of bit lines; a second differential transistor in the pair of differential transistors has a second signal line with a gate coupled to a pair of analog input signal lines, and the second differential transistor is associated with a second bit line of the group of bit lines.

[0023] In another embodiment, the switching transistor includes a pair of MOS transistors connected in series with a pair of differential transistors.

[0024] In another embodiment, the variable resistor includes: a read transistor that forms an analog multiplier; and a pair of coupled transistors connected to the read transistor, the coupled transistors having a shared floating gate connected to the gate terminal of the read transistor, wherein the shared source terminal of the differential transistor is connected to the drain terminal of the read transistor.

[0025] In another embodiment, the analog multiplier accumulator array further includes: a sign selection unit having four transistors, configured such that gate terminals of the first and second transistors are connected to one of a plurality of complementary digital input signal lines, and gate terminals of the third and fourth transistors are connected to receive the other of the plurality of complementary digital input signal lines, wherein pairs of analog input signal lines are allowed to be associated with pairs of first and second transistors in the sign selection unit or pairs of third and fourth transistors in the sign selection unit.

[0026] In another embodiment, the analog accumulator includes: an array of MOS transistors arranged in rows, each MOS transistor connected to a bit line in a group of bit lines; and a control line connected to the gate of the MOS transistor to enable switching of the MOS transistor, so that during the activation of the MOS transistor, currents flowing in the connected multiple bit lines are combined on one of the connected multiple bit lines.

[0027] In another embodiment, the analog accumulator includes: an array of CMOS transistors arranged in rows, each CMOS transistor connected to a bit line in a group of bit lines; and a pair of control lines connecting the gates of NMOS transistors forming the CMOS transistors, and the second source nodes connected to the gates of PMOS transistors forming the CMOS transistors, so that during the activation of the NMOS transistors, the PMOS transistors, or the NMOS transistors and the PMOS transistors, the currents flowing in the connected multiple bit lines are combined on one of the connected multiple bit lines.

[0028] In addition, as another embodiment, the analog accumulator includes a PMOS transistor array arranged in rows, each pair of PMOS transistors forms a current mirror and includes: a pair of first transistors and a second transistor having a shared node to connect the gates of the paired transistors, wherein the first transistor has a drain terminal connected to the shared node, and the second transistor has a drain terminal that outputs an amplified current according to a current flowing in a bit line connected to the shared node. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The features of the present invention will be apparent to those skilled in the art through the description with reference to the accompanying drawings. It should be understood that the accompanying drawings are only used to describe representative embodiments of the present invention and are not intended to limit the scope of the present invention. The present invention is specifically described by the accompanying drawings, in which:

[0030] Figure 1 A simplified functional block diagram of an existing multiply-accumulate (MAC) array is provided;

[0031] Figure 2 A simplified functional block diagram of an electronic synapse circuit array;

[0032] Figure 3 A simplified functional block diagram of one embodiment of the present invention;

[0033] Figure 4 A functional block diagram of an embodiment of the present invention;

[0034] Figure 5 For Figure 4 Another multiplier accumulator array (MAC array) obtained by the MAC array shown;

[0035] Figure 6 and Figure 7 For respectively Figure 4 and Figure 5 Another multiplier-accumulator array (MACarray) obtained by the MAC array shown;

[0036] Figure 8 For Figure 4 Another multiplier accumulator array (MAC array) obtained by the MAC array shown;

[0037] Fig. 9 For Figure 8 Another multiplier accumulator array (MAC array) obtained by the MAC array shown;

[0038] Fig.10 and Fig.11 Respectively from Figure 8 and Fig. 9 Other proposed MAC arrays obtained;

[0039] Fig.12 Describing an exemplary analog multiplier circuit according to the present invention;

[0040] Fig.13 Describe for Fig.12 An exemplary voltage-controlled variable resistor of the multiplier circuit involved in;

[0041] Fig.14 Describe for Fig.12 An exemplary voltage controlled variable resistor in an analog multiplier circuit;

[0042] Fig.15 is a representative schematic diagram illustrating an analog multiplier circuit array according to one embodiment;

[0043] Fig.16 is a representative schematic diagram illustrating an analog multiplier circuit array according to one embodiment;

[0044] Fig.17 Some schematic circuit diagrams of an analog multiplier circuit with a differential voltage-shaped variable resistor according to an embodiment of the present invention;

[0045] Fig.18 is a representative schematic diagram illustrating an analog multiplier circuit array according to one embodiment;

[0046] Fig.19 is a representative schematic diagram illustrating an analog multiplier circuit array according to one embodiment;

[0047] Fig. 20 A schematic circuit diagram of a differential analog multiplier with logic-compatible flash memory according to one embodiment of the present invention;

[0048] Fig.21 is a representative schematic diagram of a differential analog multiplier array according to one embodiment of the present invention;

[0049] Fig. 22 is a representative schematic diagram of a differential analog multiplier array according to one embodiment of the present invention;

[0050] Fig.23 To describe an exemplary analog accumulator circuit in accordance with the present invention;

[0051] Fig.24 To describe other exemplary resistors R according to the present invention, the divided voltage may be carefully selected to set the transistor operation mode; and

[0052] FIG. 25 depicts an exemplary calculation involving a differential scale factor in accordance with the present invention. DETAILED DESCRIPTION

[0053] Hereinafter, some embodiments of the present invention will be described. For the purpose of explanation, specific configurations and details are set forth to provide an understanding of the embodiments. However, it will be appreciated by those skilled in the art that the present invention may be implemented without the specific details. In addition, in order not to confuse the description of the embodiments, a part of the present invention that is inherent and is basic to those skilled in the art is usually omitted or simplified. Further details of the present invention are described below in conjunction with the accompanying drawings.

[0054] Figure 3 A simplified functional block diagram of one embodiment of the present invention is described. The MAC array 300 is configured with an input / output (I / O) bus to input or output digital values ​​from a digital interface. In this array, analog multipliers, analog adders, and analog accumulators are configured to process data from a data input bus D_IN_BUS and output processed values ​​to a data output bus D_OUT_BUS. That is, the digital-analog interface receives digital data and converts the received digital data into analog signals. Unit cells (e.g., analog multipliers, analog adders, and analog accumulators) in the MAC array 300 process analog signals. The analog multiplier provides a converted analog input as a first operand X and a second digital input or a converted analog input as a second operand Y. The second operand Y can be represented as a filter coefficient or weight parameter associated with a specific analog multiplier. The analog multipliers generate a plurality of partial products from the first operand X and the second operand Y. The corresponding analog adders then sum those partial products.

[0055] At the end of the analog adder, the analog accumulator accumulates the totaled partial products to generate analog outputs. Then, the digital-to-analog interface converts the accumulated analog outputs into digital outputs. These converted digital outputs are then output or fed back through the data output bus D_OUT_BUS as one of the inputs of the next layer of the artificial neural network system. For a single MAC operation, each digit of one operand (from the data input bus D_IN_BUS) is multiplied with each digit of the other operand (also from the data input bus D_IN_BUS) to form partial products, the analog adder adds these results (which are the aforementioned partial products), and then the analog accumulator accumulates these results and converts them into digital outputs through the data output bus D_OUT_BUS. Those analog circuits do not necessarily require full voltage swings for critical operations. They are able to carry multiple bits of information on a single wire and are suitable for approximately computable applications such as analog front ends for vision, language processing, and channel coding support to correct data path errors.

[0056] Figure 4 A functional block diagram describing one embodiment of the present invention. However, the present invention is not limited to this specific configuration. Here, the multiplier accumulator array 400 includes a plurality of MAC circuit groups 410, 420, and 430 each formed in a single row, and each MAC circuit group 410, 420, and 430 includes a plurality of MAC units in a matrix of rows and columns. Each MAC circuit group 410, 420, and 430 includes an analog accumulator and an analog level sensing circuit interconnected therewith. Although the MAC units are shown to be formed in three rows and three columns in the MAC array 400, it should be understood that the number of rows and columns that can form a variety of combinations of MAC units may only be limited by a specific chip architecture.

[0057] The three MAC circuit groups 410, 420 and 430 are connected together through a data input bus D_IN_BUS and a data output bus D_OUT_BUS, so that each MAC circuit group 410, 420 and 430 has the same digital input from the input bus D_IN_BUS and adds each partial digital product on the data output bus D_OUT_BUS. In each MAC circuit group 410, 420 and 430, three MAC units are arranged in three rows and one column, and can be interconnected by one or more bit lines (BL[0], BL[1], BL[2], etc.) electrically connected to the analog accumulator. Each MAC unit includes (1) a local memory, (2) a digital-to-analog converter (DAC), and (3) an analog multiplier. The local memory is configured to store the digital value of the local multiplier digital input vector, which is the digital input voltage D_INA and D_INB. The local memory may be a static random access memory (SRAM), a read-only memory (ROM), a one-time programmable memory (OTP), a single-poly based EFLASH, a magnetoresistive random access memory (MRAM), etc. In the system startup procedure, the default value of the digital input voltage D_INB may be programmed in the local memory so that it can be executed in real time as soon as possible when the digital input voltage D_INA is available.

[0058] The digital / analog converter generates an analog voltage level corresponding to its digital value. For example, the digital / analog converter converts the digital input voltage D_INA into an analog voltage input A_INA. Each analog multiplier in the MAC unit receives two voltage inputs of the analog voltage input A_INA in the analog domain (level: from ground voltage (GND) to operating voltage (VDD)) and the digital input voltage D_INB in ​​the digital domain (level: GND or VDD), and generates an output in the corresponding bit lines BL[n-1]~BL[0] of the product result input in the analog domain (i.e., current or charge). Then, the partial product results are summed up by the corresponding bit lines to act as an analog adder.

[0059] like Figure 4As shown, in a two-dimensional multiplier accumulator array 400, the first bit line BL0[0] of the first column is electrically connected to a plurality of analog multipliers in the first line of three rows and the first column. The second bit line BL0[1] of the first column can be electrically connected to a plurality of analog multipliers in the second line of three rows and the first column. Similarly, the (n-1)th bit line BL0[n-1] of the first column can be electrically connected to a plurality of analog multipliers in the Nth line of three rows and the first column. Those bit line groups in each MAC group are connected to the corresponding analog accumulators coupled to the analog sensing circuits at the edge of the array, so that the accumulated analog output is converted into corresponding binary bits, which are then output through the data output bus D_OUT_BUS.

[0060] Each analog output (O00, O10, O20, etc.) is labeled as a partial product from a corresponding multiplier. Analog output O00[0] is labeled as a partial product reaching BL0[0] in the first group of MACs from the analog multiplier in the first row and first column. Similarly, analog output O20[n-1] is labeled as a partial product reaching BL0[n-1] in the first group of MACs from the analog multiplier in the third column and first row. Multiple analog outputs (O2X-O0X) of the analog multipliers may be accumulated on bit lines BLX[n-1]-BLX[0]. For example, partial products O00[0], O10[0], and O20[0] are summed in the first bit line BL0[0] of the first group of MACs. Partial products O00[n-1], O10[n-1], and O20[n-1] are summed in the nth bit line BL0[n-1] of the first group of MACs.

[0061] When the analog accumulator is enabled by the enable signal EN, the analog accumulator performs an accumulation operation on the output lines (OUT0-OUT2). Then, the result is fed to the analog level sensing circuit connected to the data output bus D_OUT_BUS to generate digital outputs D_OUT0-D_OUT2. By quickly providing new vectors to the analog voltage input A_INA and the digital input voltage D_INB, any combination of the two vectors can be operated in real time without reprogramming the analog multiplier. As an example, according to the MAC array proposed in the present invention, when the analog voltage input A_INA20, the digital input voltage D_INB20, the analog voltage input A_INA10, the digital input voltage D_INB10, the analog voltage input A_INA00, the digital input voltage D_INB00 have input vectors with corresponding values ​​of 7, 3, 2, 9, 4, 3, then the output vectors O20[n-1:0], O10[n-1:0], O00[n-1:0] of the multiplier have result values ​​of 21=7×3, 18=2×9, 12=4×3, and then O20+O10+O00=21+18+12=51 are accumulated on the output line OUT0. Upon receiving the accumulated value, the analog level sensing circuit converts the accumulated value into a corresponding binary bit, which is then carried by the data output bus D_OUT_BUS.

[0062] Figure 5 Describe from Figure 4 The functional block diagram of another multiplier-accumulator array (MAC array) obtained by the MAC array is shown. That is, each MAC unit of the three MAC circuit groups 510, 520 and 530 in the MAC array 500 is further configured with a digital-to-analog converter (DAC) to connect the local memory and the analog multiplier. Therefore, the analog multiplier can receive a pair of analog voltage inputs A_INA from the first digital-to-analog converter DAC and an analog voltage input A_INB from the second digital-to-analog converter DAC, and multiply the inputs of the two analog domains to generate a product on the corresponding bit line BL.

[0063] Figure 6 Describe from Figure 4The functional block diagram of another multiplier-accumulator array (MAC array) obtained by the MAC array is shown. That is, the MAC array 600 shows that the separated analog input sources (digital-to-analog converters) in the MAC units 420 and 430 are replaced with a common analog input source. That is, in the first row of MAC units 620 and 630, multiple analog multipliers receive analog voltage input A_INA from the digital-to-analog converter (DAC) in the MAC unit 610. In the second row of MAC units 620 and 630, multiple analog multipliers receive analog voltage input A_INA from the DAC in the same row in the MAC unit 610. In the third row of MAC units 620 and 630, multiple analog multipliers receive analog voltage input A_INA from the digital-to-analog converter in the same row in the MAC unit 610. Therefore, the MAC array can be configured with a smaller number of DACs, thereby reducing the overall space of the DACs.

[0064] Figure 7 Describe from Figure 5 1 is a functional block diagram of another multiplier-accumulator array (MAC array) obtained by the MAC array shown. That is, the MAC array 700 shows that the separate analog input sources (digital-to-analog converters) in the MAC units 520 and 530 are replaced with a common analog input source. That is, in the first row of MAC units 720 and 730, multiple analog multipliers (AnalogMultipliers) receive analog voltage input A_INA from the digital-to-analog converter (DAC) in the MAC unit 710. In the second row of MAC units 720 and 730, multiple analog multipliers receive analog voltage input A_INA from the DAC in the same row in the MAC unit 710. In the third row of MAC units 720 and 730, multiple analog multipliers receive analog voltage input A_INA from the DAC in the same row in the MAC unit 710. Therefore, the MAC array can be configured with a smaller number of DACs, thereby reducing the overall space of the DACs.

[0065] Figure 8 Describe from Figure 4The functional block diagram of another multiplier-accumulator array (MAC array) obtained by the MAC array is shown. In the MAC array 800, each digital-to-analog converter (DAC) is configured to generate a pair of differential analog input voltages (A_INA_N and A_INA_P). Each analog multiplier (Analog Multiplier) connected to the digital-to-analog converter is configured to generate a differential output pair (O_P[n-1] and O_N[n-1]) to (O_P[0] and O_N[0]) in the analog domain (i.e., current or charge) according to the differential analog input voltage (A_INA_P and A_INA_N) in the analog domain to correspond to the digital input voltage (D_INB) in the digital domain.

[0066] The multiple outputs of the analog multiplier can be accumulated on the bit lines BL[n-1]~BL[0] and BLB[n-1]~[BLB[0] respectively. When the differential analog level sensing circuit (Analog Level Sensing Circuit) is activated, the accumulated differential output current pairs (O_P0, O_N0), (O_P1, O_N1) and (O_P2, O_N2) are respectively input to the corresponding differential analog level sensing circuit. Then, this result is fed to the analog level sensing circuit to generate digital outputs D_OUT0~D_OUT2. By providing new vectors to the differential analog input voltages A_INA_N, A_INA_P and the digital input voltage D_INB, any combination of two vectors can be calculated in real time without being limited by the available neural network with a given analog multiplier capability. As an example of the MAC array according to the present invention, when the differential analog input voltages A_INA_P20 and A_INA_N20, the digital input voltage D_INB20, the differential analog input voltages A_INA_P10 and A_INA_N10, the digital input voltage D_INB10, the differential analog input voltages A_INA_P00 and A_INA_N00, and the digital input voltage D_INB00 have corresponding values ​​of 7, 3, 2, 9, 4, and 3, then the existing differential The differential vector of the output current pair (i.e., O_P20-O_N20, O_P10-O_N10, O_P00-O_N00) has result values ​​6=(5-3)×3, -4=(3-5)×2, 4=(6-2)×1, and then the existing result value (O_P20-O_N20)+(O_P10-O_N10)+(O_P00-O_N00)=6+(-4)+4=6 is accumulated on the output line O_P0-O_N0 (==D_OUT0).

[0067] Fig. 9 To describe from Figure 8FIG. 1 is a functional block diagram of another multiplier-accumulator array (MAC array) obtained from the MAC array in FIG. The analog multiplier receives two analog voltage inputs A_INA and A_INB from the local digital-to-analog converter (DAC) connected to the local memory. The multiple outputs output from the analog multiplier can be added on the bit lines BL[n-1]~BL[0] and BLB[n-1]~BLB[0] respectively. Then, when the analog accumulator (Analog Accumulator) is enabled, the analog accumulator differentially accumulates the differential vectors (O_P0~2 and O_N0~2) of the output lines. Therefore, the result is fed to the analog level sensing circuit (Analog Level Sensing Circuit) to generate digital outputs D_OUT0~D_OUT2.

[0068] Fig.10 and Fig.11 Display from Figure 8 and Fig. 9 Get the other MAC arrays. Fig.10 and Fig.11 In the example, three analog multipliers (Analog Multipliers) located in the same row receive common analog differential input voltages A_INA_P and A_INA_N. More precisely, in the first row, the analog multipliers receive common analog differential input voltages A_INA_N0 and A_INA_P0 of analog operands. In the second row, the analog multipliers receive common analog differential input voltages A_INA_N1 and A_INA_P1 of analog operands. In the third row, the analog multipliers receive common analog differential input voltages A_INA_N2 and A_INA_P2 of analog operands. Here, Figure 8 and Fig. 9 The separate in-line digital / analog converters (analog input sources) are replaced with a common analog input source. Therefore, the MAC array can be equipped with a smaller number of digital / analog converters (DACs), thereby reducing the overall DAC space. The analog differential input voltages A_INA_N0~2 and A_INA_P0~2 with the same analog voltage level can be shared and driven through multiple rows. Because the same DAC is shared, the DAC area required for the entire regional memory specification is reduced. Fig.11 In the embodiment, three analog multipliers located in the same row receive common analog differential input voltages A_INA_NX and A_INA_PX.

[0069] Fig.12Exemplary analog multiplier circuits are described in accordance with the present invention. The analog multiplier circuits are configured to generate digital output signals by processing analog input signals in combination with received digital input signals. Specifically, the circuits are configured to generate an output current (OUT) at a bit line (BL) node in response to receiving an analog voltage input A_INA and a 1-bit digital input voltage D_INB. Each analog multiplier circuit includes (1) an access transistor for receiving the analog voltage input A_INA from a supply node, (2) a variable resistor for storing data based on its conductance state, and (3) a switching transistor having a gate terminal for receiving the digital input voltage D_INB to control the output current level.

[0070] The variable resistor R is also non-volatile, so it does not require continuous power to retain stored data. As an embodiment, because the value of the variable resistor R cannot be set or modified during active operation of the circuit, the variable resistor R is configured to be programmed with a specific value before operating the analog multiplier circuit. Further details of the variable resistor R will be as follows Fig.13 and Fig.14 As described in.

[0071] The switching transistor is configured to be activated according to the digital input voltage (D_INB) to turn on or off the product of the analog voltage input A_INA and the programmed conductance value of the variable resistor R. During the operation of the circuit, the value of the digital input voltage (D_INB) dynamically changes (quickly selects) the state of the switching transistor. More precisely, when the digital input voltage D_INB is high, the switching transistor is turned on, and the current output (OUT) in the bit line BL node may be proportional to the product of the analog voltage input A_INA and the inverse of the resistance value of the default variable resistor R or its conductance value. On the other hand, when the digital input voltage D_INB becomes low, the switching transistor is turned off, and the current output (OUT) may be reduced to a trivial level. That is, when the low potential of the digital input voltage D_INB is reduced to a trivial level, it is determined to keep the switching transistor in a non-conducting state.

[0072] exist Fig.12 In (a), the analog multiplier circuit 1210 is provided with a voltage-controlled variable resistor, which includes a variable resistor R and a switching transistor 1214 to control the output current on the bit line BL according to the digital input voltage D_INB applied to its gate terminal. The source region of the access transistor 1212 connected to the analog voltage input A_INA is coupled to one end of the variable resistor R, and the other end of the variable resistor R is coupled to the drain region of the switching transistor 1214. Fig.12In (b), the analog multiplier circuit 1220 is configured to include a variable resistor R and a switching transistor 1224, such that the source region of the access transistor 1222 is connected to the drain region of the switching transistor 1224 and the source region of the switching transistor 1224 is connected to one end of the variable resistor R. Fig.12 In (c), the analog multiplier circuit 1230 is configured to present an analog multiplier circuit 1230 with a voltage-controlled variable resistor, which includes (1) a switching transistor 1232 that controls an output current on a bit line BL according to a digital input voltage (D_INB) applied to a gate terminal of the switching transistor 1232, (2) an access transistor 1234 operable to respond to an analog voltage input A_INA, and (3) a variable resistor R. The variable resistor R is configured to store a state of its resistance value.

[0073] Fig.13 An exemplary memory resistor for an analog multiplier circuit is depicted according to one embodiment. Fig.13 As shown in (Voltage Controlled Variable Resistor by Multi-GateFlash), Fig.12 The medium voltage controlled variable resistor may be configured by a group of flash memory cells. Those flash memory cells are arranged in series to store states through their cell threshold voltages. Each flash memory cell may be a floating gate memory transistor having a control gate coupled to one of a plurality of word lines (WL1, WL2, WL3, etc.).

[0074] Fig.13 (a) Display Fig.12 As an implementation of a Type I voltage controlled variable resistor (Type IVoltage Controlled Variable Resistor), the analog multiplier circuit 1310 includes a voltage controlled variable resistor, wherein the source terminal of a flash memory cell (not shown) is connected to the drain terminal of a switching transistor S1. Furthermore, the drain terminal of a flash memory cell 1312 is connected to the source terminal of an access transistor A1 and the source terminal of the flash memory cell 1312 is connected to the drain terminal of another flash memory cell (not shown). The number of flash memory cells including the flash memory cell 1312 is not explicitly described, but it should be understood that one or more flash memory cells (floating gate transistors) can be arranged in series in this manner.

[0075] As another implementation of a Type I Voltage Controlled Variable Resistor, the analog multiplier circuit 1320 includes a voltage controlled variable resistor, wherein the source terminal of the switching transistor S2 is connected to the drain terminal of the flash memory cell 1322. Furthermore, the source terminal of the access transistor A2 is connected to the drain terminal of the switching transistor S2 and the source terminal of the flash memory cell (not shown) through a conductive line or another series-connected transistor to connect to a common source line CSL.

[0076] As an implementation of a Type II Voltage Controlled Variable Resistor, the analog multiplier circuit 1330 has a voltage controlled variable resistor, which includes (1) a switching transistor S3, (2) an access transistor A3, and (3) at least one flash memory unit 1332. That is, the source terminal of the switching transistor S3 is connected to the drain terminal of the access transistor A3, and the source terminal of the access transistor A3 is connected to the drain terminal of the flash memory unit 1332.

[0077] Given the above circuit designs, when the digital input voltage D_INB is high and turns on the switching transistor, the current output (OUT) at the bit line BL node may be proportional to the product of the analog voltage input A_INA and the inverse of the resistance value of the default variable resistor R. On the other hand, when the digital input voltage D_INB becomes low and turns off the switching transistor, the current output (OUT) may decrease to a normal level. In other words, when the low value of the digital input voltage D_INB received by the switching transistor decreases to a normal level, it is determined to keep the switching transistor in a non-conducting state.

[0078] exist Fig.13 In (b), as another implementation of a Type I voltage-controlled variable resistor, the analog multiplier circuit 1340 includes a voltage-controlled variable resistor composed of a flash memory unit 1342. That is, the flash memory unit 1342 has a gate terminal to receive an analog voltage input A_INB (that is, the analog voltage input level is between the ground voltage (GND) and the operating voltage (VDD)). In this state, the level of the analog voltage input A_INB can be changed from Figure 5 , Figure 7 , Fig. 9 and Fig.11 The current in the bit line (BL) represents the product of (1) the carefully selected analog voltage input (A_INA or A_INB) and (2) the programmed resistance value of the variable resistor R.

[0079] Fig.14Describe for Fig.12 An exemplary memory resistor (Voltage Controlled Variable Resistor by Logic Flash) of an analog multiplier circuit is shown in FIG. Here, the variable resistor R includes one or more read (standard logic) transistors, each of which is connected to a pair of coupling transistors via a floating gate (FG) node that serves as a charge storage node. Fig.14 In (a), as one embodiment, an analog multiplier circuit 1410 includes a voltage controlled variable resistor, which includes a read (standard logic) transistor 1414 configured to form a floating gate FG as a charge storage node of a pair of coupled transistors 1416 and 1417. That is, the first transistor 1416 is connected to the programming word line PWL to provide a programming voltage to the floating gate FG. The second transistor 1417 is connected to the write word line WWL to operate data writing. Although only one read transistor 1414 is described, it should be understood that more than one read transistor can be arranged in series to form a variable resistor R. When more than one read transistor forms the variable resistor R, the first read transistor maintains a first pair of word lines (programming word line PWL and write word line WWL) separated from a second pair of word lines (not shown) connected to the second read transistor (not shown).

[0080] The node voltage of the floating gate (FG) is programmable to a target specific value. Therefore, when the digital input voltage D_INB is high to "turn on" the selected transistor, the current output (OUT) in the bit line BL node may be proportional to the product of the default analog voltage input A_INA and the default conductance of the variable resistor R (which is equivalent to the inverse of the resistance value of the variable resistor R). On the other hand, when the digital input voltage D_INB becomes low to turn off the selected transistor, the current output (OUT) may be reduced to a general level. Although a specific number of read transistors or selected transistors are shown, it should be understood that any number of read transistors and / or selected transistors may be connected in series.

[0081] The read transistor 1414 has (1) a drain terminal connected to the source terminal of the access transistor 1412 to receive the analog voltage input A_INA and (2) a source terminal connected to the drain terminal of the switching transistor 1418 through a wire or multiple read transistors (not shown) to receive the digital input voltage D_INB (binary digital input 0 and 1). The switching transistor 1418 is configured to enable or disable the current in the bit line according to the digital input voltage (D_INB) applied to the gate terminal of the switching transistor 1418.

[0082] As another implementation of a Type I Voltage Controlled Variable Resistor, the analog multiplier circuit 1420 shows a voltage controlled variable resistor, wherein the source terminal (not shown) of the switching transistor 1424 is connected to the drain terminal of the read transistor 1426. Furthermore, the source terminal of the access transistor 1422 is connected to the drain terminal of the switching transistor 1424 and the source terminal of the last read transistor (not shown) is connected to the common source line CSL through a conductive line or another series-connected transistor (not shown).

[0083] As an implementation of a Type II Voltage Controlled Variable Resistor, the analog multiplier circuit 1430 has a voltage controlled variable resistor, which includes (1) a switching transistor 1432, (2) an access transistor 1434, and (3) at least one voltage controlled variable resistor. That is, the source terminal of the switching transistor 1432 is connected to the drain terminal of the access transistor 1434, and the source terminal of the access transistor 1434 is connected to the drain terminal of the read transistor 1436.

[0084] Given the aforementioned circuit design, when the digital input voltage D_INB is high and turns on the switching transistor, the current output (OUT) at the bit line BL node may be proportional to the product of the analog voltage input A_INA and the inverse of the resistance value of the default variable resistor R. In addition, when the digital input voltage D_INB becomes low and turns off the switching transistor, the current output (OUT) may be reduced to a normal level. In other words, when the low value of the digital input voltage D_INB received by the switching transistor is reduced to a normal level, the switching transistor is ensured to be in a non-conducting state.

[0085] exist Fig.14 In (b), as another embodiment of the I-type voltage-controlled variable resistor, the analog multiplier circuit 1440 has a voltage-controlled variable resistor composed of one or more read (standard logic) transistors 1444. That is, the first transistor 1446 and the second transistor 1447 have a shared base to receive the analog voltage input A_INB (that is, the analog voltage input level is between the ground voltage (GND) and the operating voltage (VDD)). The level of the analog voltage input A_INB can be changed from Figure 5 , Figure 7 , Fig. 9 and Fig.11 The current in the bit line (BL) represents the product of (1) the carefully selected analog voltage input (A_INA or A_INB) and (2) the inverse of the programmed resistance value of the variable resistor R (the square in the dashed line).

[0086] Fig.15 A representative schematic diagram of an analog multiplier circuit array (Voltage Controlled Variable Resistor by “dashed squares”) is depicted according to one embodiment. Fig.15 Three (Types I-III) exemplary arrays 1510, 1520, and 1530 are described in which a group of four analog multiplier circuits are connected along a single voltage supply node. Each multiplier in the group is described in Fig.12 The four analog multipliers in each array are configured to generate four output currents (O3 to O0) in four bit lines (BL[3] to BL[0]) according to the analog voltage input A_INA and the four digital input voltages D_INB[3] to D_INB[0]. The four bit lines BL[3], BL[2], BL[1] and BL[0] in the array are designed so that the digital input voltage D_INB[3] is the most significant bit (MSB) and the digital input voltage D_INB[0] is the least significant bit (LSB).

[0087] In each array, the switching transistors S3, S2, S1 and S0 are configured to activate or deactivate the output current, which flows in four bit lines (BL[3] to BL[0]) according to four digital input voltages D_INB[3] to D_INB[0] received by the gate regions of the switching transistors S3, S2, S1 and S0, respectively. The variable resistors R3, R2, R1 and R0 can be programmed before operating the circuit. Furthermore, when the scale factor K (i.e., K=1, 2, 3, etc. integer) is specified, the programmed resistance value can have its value to identify the source (bit line) of the output current.

[0088] The output current in the bit line BL can be determined by the product of the carefully selected analog voltage input A_INA (operand X) and the inverse of the resistance value of the variable resistor R (operand Y). Therefore, a group of variable resistors (R3, R2, R1 and R0) can be deliberately set to identify the output current in the bit line (digital position). In other words, the magnitudes of the output currents O1, O2 and O3 can be scaled with reference to the magnitude of the output current O0. When the scale factor K is set to 2 with reference to the magnitude of 1 of the output current O0, the magnitudes of the output currents O0, O1, O2 and O3 will reach 1, 2, 4 and 8. The scale factor K is set in order to accurately distinguish other output currents on the bit line. When the corresponding digital input voltage D_INB is high, the output currents O0~O3 are proportional to the product of the carefully selected analog voltage input (A_INA or A_INB) and (2) the inverse of the programmed resistance value of the variable resistor R. In addition, when the “low” digital signal (digital input voltage D_INB) disables the switching transistors S3 , S2 , S1 and S0 , the amount of the output currents O0 ˜ O3 flowing out of the bit line (BL) is reduced to a normal level.

[0089] The output currents O0, O1, O2 and O3 in a pair of bit lines BL[3], BL[2], BL[1] and BL[0] are determined by a specific combination of the analog voltage input A_INA and the digital input voltages D_INB[3], D_INB[2], D_INB[1] and D_INB[0], respectively. Therefore, the output (data) can be continuously changed according to the product of the analog voltage input and the programmed static resistance of the variable resistor R. Furthermore, by providing a new vector to the analog voltage input A_INA and the digital input voltage D_INB, any combination of the two vectors can be calculated in real time without limiting the available product combinations of the neural network model for the total number of variable resistors in a given array.

[0090] Fig.16A representative schematic diagram of an analog multiplier circuit array (Type I Voltage Controlled Variable Resistor by LogicFlash) is described according to one embodiment. In the analog multiplier circuit array 1600, a programming word line PWL electrically connects a first transistor of a pair of coupled transistors to apply a programming voltage to a plurality of floating gates FG3, FG2, FG1, and FG0. A write word line WWL electrically connects a second transistor of a pair of coupled transistors to operate data writing. The circuit receives an analog voltage input A_INA and four digital input voltages D_INB[3], D_INB[2], D_INB[1], and D_INB[0], wherein the digital input voltage D_INB[3] is the most significant bit and the digital input voltage D_INB[0] is the least significant bit, and generates output currents O3, O2, O1, and O0 flowing in the bit lines BL[3], BL[2], BL[1], and BL[0], respectively.

[0091] This is Fig.14 The implementation of the multi-bit digital input voltage D_INB is shown. The node voltages of the floating gates FG3, FG2, FG1 and FG0 are programmed with specific values ​​before operation, so that the output currents O3-O0 have the relationship of O3=k×O2, O2=k×O1 and O1=k×O0 (i.e. k=1, 2, 3, etc. integers), and when the corresponding digital input voltage D_INB is high, they (output currents O0-O3) are proportional to the product of the carefully selected analog voltage input A_INA and the inverse of the effective resistance value of the NMOS device connected to the floating gate node. In addition, when the digital input voltages D_INB[3], D_INB[2], D_INB[1] and D_INB[0] are "low", the switching transistors S3, S2, S1 and S0 are disabled respectively, so that the amount of output current flowing into the bit lines BL[3], BL[2], BL[1] and BL[0] is reduced to a normal level.

[0092] Fig.17 According to one embodiment of the present invention, some schematic circuit diagrams of an analog multiplier circuit with a differential voltage-shaped variable resistor are described. Fig.17 In the embodiment, each analog multiplier circuit 1720, 1740 and 1760 includes a differential pair of n-channel MOS transistors connected to a variable resistor R and one or more switching transistors. The analog multiplier is configured to receive an analog differential input voltage (A_INA_P and A_INA_N) and a digital input voltage D_INB, and generate a pair of differential output currents (O_P and O_N) in a pair of bit lines (BL and BLB), respectively.

[0093] The first MOS transistor of the differential pair of n-channel MOS transistors has a gate terminal to receive a first analog differential input voltage A_INA_P. The first MOS transistor is configured to generate an output current flowing in the bit line BL according to a combination of the first analog differential input voltage A_INA_P and the digital input voltage D_INB. The second MOS transistor of the differential pair of n-channel MOS transistors has a gate terminal to receive a second analog differential input voltage A_INA_N. The second MOS transistor is configured to generate an output current flowing in the bit line BL according to a combination of the second analog differential input voltage A_INA_N and the digital input voltage D_INB.

[0094] The variable resistor R is programmed to a specific value before operating the multiplier. Therefore, when the digital input voltage D_INB is high and the switching transistor is turned on, the differential output current as the difference between the two currents in a pair of bit lines (BL and BLB) may be proportional to the product of the analog voltage input A_INA and the inverse of the resistance value of the default variable resistor R or its conductance value. On the other hand, when the digital input voltage D_INB becomes low and the switching transistor is turned off, the differential output currents O_P and O_N may decrease to a general level. That is, when the low level of the digital input voltage D_INB received by the switching transistor decreases to a general level, it is determined to keep the switching transistor in a non-conducting state.

[0095] Fig.17 (a) Description A pair of MOS transistors D1 and D2 have a shared source terminal connected to a first end of a variable resistor R. The first transistor D1 is connected to a bit line BL and a first end of the variable resistor R. The second transistor D2 is connected to a bit line BLB and a first end of the variable resistor R. The second end of the variable resistor R is connected to a drain terminal of a switching transistor S1. The switching transistor S1 has a gate terminal to receive a digital input voltage D_INB and a source terminal connected to a shared source line CSL. The switching transistor S1 is configured to enable or disable an output current (O_P, O_N) in a pair of bit lines (BL and BLB) according to a digital input voltage D_INB.

[0096] Fig.17 (b) A differential analog multiplier circuit 1740 is described having a pair of MOS transistors D3 and D4 having a shared source terminal connected to the drain terminal of a switching transistor S2. The switching transistor S2 is connected to the first transistor D3 and the second transistor D4 and a variable resistor R, so that the switching transistor S2 enables or disables the output current in a pair of bit lines according to the digital input voltage D_INB received by the gate region of the switching transistor S2. The variable resistor R connects the switching transistor S2 and the shared source line CSL.

[0097] Fig.17 (c) describes the differential analog multiplier circuit 1760 configured in a cascade configuration. Fig.17 In (c), the differential analog multiplier circuit 1760 includes a pair of MOS transistors D5 and D6 connected to corresponding switching transistors S3 and S4, respectively. That is, the drain terminals of the first transistor D5 and the second transistor D6 are connected to the source terminals of the switching transistors S3 and S4, respectively. The gate terminals of the switching transistors S3 and S4 are tied together and configured to receive the digital input voltage D_INB. The shared source terminal of the pair of MOS transistors D5 and D6 is connected to one end of the variable resistor R. The gate terminal of the first transistor D5 is configured to receive the analog differential input voltage A_INA_P from the first analog voltage source node. The gate terminal of the second transistor D6 is configured to receive the analog differential input voltage A_INA_N from the second analog voltage source node. The bit line BL connects the switching transistor S3 and the first transistor D5 in series, and the bit line BLB connects the switching transistor S4 and the second transistor D6 in series. The source terminals of the switching transistors S3 and S4 and the drain terminals of the first transistor D5 and the second transistor D6 are combined together to form a common source / drain region. The switching transistors S3 and S4 have gate terminals for receiving the digital input voltage D_INB, and enable or disable output currents in a pair of bit lines BL and BLB according to the digital input voltage D_INB applied to the gate regions of the switching transistors S3 and S4.

[0098] Fig.18 is a representative schematic diagram of an analog multiplier circuit array according to one embodiment. Fig.18 (a) Description The analog multiplier circuit array 1820 includes 4 pairs of analog multiplier circuits C0, C1, C2 and C3, each pair of analog multiplier circuits C0, C1, C2 and C3 is connected to a pair of voltage source nodes to receive analog differential input voltages A_INA_P and A_INA_N. Each pair of analog multiplier circuits C0, C1, C2 and C3 includes a pair of differential pair MOS transistors. The first transistors D1, D3, D5 and D7 in a group of differential pair MOS transistors are configured to receive the analog differential input voltage A_INA_P at their gate terminals, respectively. The second transistors D2, D4, D6 and D8 in a group of differential pair MOS transistors are configured to receive the analog differential input voltage A_INA_N at their gate terminals, respectively.

[0099] The paired MOS transistors of each circuit C0, C1, C2 and C3 have a shared source terminal to connect the variable resistor R connected to the switching transistor. The four variable resistors R3, R2, R1 and R0 connect the paired MOS transistors D1 / D2, D3 / D4, D5 / D6 and D7 / D8 to the four switching transistors S3, S2, S1 and S0, respectively. Each variable resistor R3, R2, R1 and R0 has been programmed to a target specific value. Switching transistors S3, S2, S1, and S0, which are respectively coupled to variable resistors R3, R2, R1, and R0, enable or disable output currents flowing into four pairs of bit lines BL[3] / BLB[3], BL[2] / BLB[2], BL[1] / BLB[1], and BL[0] / BLB[0] according to unsigned digital input voltages D_INB[3], D_INB[2], D_INB[1], and D_INB[0] received at gate terminals of the switching transistors S3, S2, S1, and S0, respectively. The analog multiplier circuits C0, C1, C2, and C3 may use the digital input voltage D_INB[3] to represent the most significant bit and the digital input voltage D_INB[0] to represent the least significant bit.

[0100] Once activated, each pair of analog multiplier circuits C0, C1, C2 and C3 allows paired currents (O_P3-O_N3), (O_P2-O_N2), (O_P1-O_N1) and (O_P0-O_N0) to flow in the nodes of bit lines BL and BLB. A differential output current is calculated based on the difference between the current in bit line BL and the current in bit line BLB. When switching transistors S3, S2, S1 and S0 are turned on, the amount of current in the node of each bit line BL is the product of the analog voltage input (operand X) and the reciprocal of the resistance value of the corresponding pre-programmed variable resistor R (operand Y). The four switching transistors S3, S2, S1 and S0 are configured to enable or disable output currents (O3~O0) flowing into the four pairs of bit lines BL[3] / BLB[3], BL[2] / BLB[2], BL[1] / BLB[1] and BL[0] / BLB[0] according to the unsigned digital input voltages D_INB[3], D_INB[2], D_INB[1] and D_INB[0] respectively received at the gate terminals of the switching transistors S3, S2, S1 and S0.

[0101] The four differential output currents (O_P3-O_N3), (O_P2-O_N2), (O_P1-O_N1), and (O_P0-O_N0) can be scaled with reference to the first differential output current (O_P0-O_N0). When the scale factor K is set to 2 as an integer with reference to the value 1 of the first differential output current (O_P0-O_N0), the values ​​of the remaining differential output currents (O_P3-O_N3), (O_P2-O_N2), (O_P1-O_N1), and (O_P0-O_N0) will reach 8, 4, 2, and 1. The scale factor K is set to accurately identify one output current from the other output currents of the bit line. Therefore, when the four digital input voltages D_INB[3], D_INB[2], D_INB[1], and D_INB[0] are high to turn on the selected transistors, the differential output currents (O_P-O_N) in each pair of analog multiplier circuits C0, C1, C2, and C3 of the analog multiplier circuit array 1820 are proportional to the product of the target default differential input voltages (A_INA_P and A_INA_N) and the resistance derivative values ​​of the variable resistors R3-R0. On the other hand, when the "low" digital input voltages (D_INB[3], D_INB[2], D_INB[1], D_INB[0]) disable the switching transistors (C3, C2, C1, and C0), the differential output currents O_P3-0 and O_N3-0 may be reduced to a normal level.

[0102] Fig.18 (b) Description of the analog multiplier circuit array 1840 includes four pairs of analog multiplier circuits E3, E2, E1 and E0, each pair of analog multiplier circuits E3, E2, E1 and E0 is connected to a pair of voltage source nodes to receive analog differential input voltages A_INA_P and A_INA_N, wherein each pair of analog multiplier circuits E3, E2, E1 and E0 is as shown in FIG. Fig.17 (b) shows. The switching transistors S3, S2, S1 and S0 are connected to the differential amplifier circuit and the four variable resistors R3, R2, R1 and R0, so that the switching transistors S3, S2, S1 and S0 enable or disable the output current flowing into the four pairs of bit lines BL[3] / BLB[3], BL[2] / BLB[2], BL[1] / BLB[1] and BL[0] / BLB[0] according to the unsigned digital input voltages D_INB[3], D_INB[2], D_INB[1] and D_INB[0] respectively received at the gate terminals of the switching transistors S3, S2, S1 and S0.

[0103] Fig.18(c) Description of the analog multiplier circuit array 1860 includes four pairs of analog multiplier circuits F3, F2, F1 and F0, each pair of analog multiplier circuits F3, F2, F1 and F0 is connected to a pair of voltage source nodes to receive analog differential input voltages (A_INA_P and A_INA_N), wherein each pair of analog multiplier circuits F3, F2, F1 and F0 is as shown in Fig.17 (c) Fig.17 (c) as described above, each pair of analog multiplier circuits F3, F2, F1 and F0 is configured in a cascade configuration. That is, the analog multiplier circuit F3 includes MOS transistors D1 and D2 connected to corresponding switching transistors S1 and S2. The switching transistors S1 and S2 are also MOS transistors to connect the corresponding MOS transistors D1 and D2. Specifically, the drain terminals of the MOS transistors D1 and D2 are connected to the source terminals of the corresponding switching transistors S1 and S2. The gate terminals of the switching transistors S1 and S2 are tied together and configured to receive the digital input voltage D_INB[3].

[0104] Fig.18 (c) Description of the analog multiplier circuit array 1860 includes four pairs of analog multiplier circuits F3, F2, F1 and F0, each pair of which is connected to a pair of voltage source nodes to receive analog differential input voltages (A_INA_P and A_INA_N), wherein each pair of analog multiplier circuits F3, F2, F1 and F0 is as shown in FIG. Fig.17 (c) Fig.17 As shown in (c), each pair of analog multiplier circuits F3, F2, F1 and F0 is configured in cascade. That is, the analog multiplier circuit F3 includes MOS transistors D1 and D2 connected to corresponding switching transistors S1 and S2.

[0105] The switching transistors S1 and S2 are also MOS transistors to connect the corresponding MOS transistors D1 and D2. That is, the drain terminals of the MOS transistors D1 and D2 are connected to the source terminals of the corresponding switching transistors S1 and S2. The gate terminals of the switching transistors S1 and S2 are tied together and configured to receive the digital input voltage D_INB[3]. The shared source terminal of a pair of MOS transistors D1 and D2 is connected to one end of the variable resistor R. The gate terminal of the first transistor D1 is configured to receive the analog differential input voltage A_INA_P from the first analog voltage source node. The gate terminal of the second transistor D2 is configured to receive the analog differential input voltage A_INA_N from the second analog voltage source node. The bit line BL[3] connects the switching transistor S1 and the first transistor D1 in series, and the bit line BLB[3] connects the switching transistor S2 and the second transistor D2 in series. The source terminals of the switching transistors S1 and S2 and the drain terminals of the first MOS transistor D1 and the second MOS transistor D2 are combined together to form a common source / drain region. Each of the switching transistors S1 and S2 has a gate terminal to receive the digital input voltage D_INB[3], so that the switching transistors S1 and S2 enable or disable the output current of the bit lines BL[3] and BLB[3] according to the digital input voltage D_INB[3] received by the gate regions of the switching transistors S1 and S2, respectively. The other analog multiplier circuits F2, F1 and F0 have the same architecture as the analog multiplier circuit F3, and they receive different digital input voltages D_INB[2], D_INB[1] and D_INB[0].

[0106] Fig.19 A representative schematic diagram of an analog multiplier circuit array according to one embodiment. Here, the analog multiplier circuit array is configured with a plurality of MOS transistors. Each of the analog multiplier circuit arrays 1920, 1940, and 1960 includes a symbol selection unit and three analog multiplier units. In each of the analog multiplier circuit arrays 1920, 1940, and 1960, the analog multiplier unit generates a plurality of pairs of currents O_P2 / O_N2, O_P1 / O_N1, and O_P0 / O_N0 to flow into a plurality of pairs of bit lines BL2 / BLB2, BL1 / BLB1, and BL0 / BLB0, respectively. The symbol selection unit SU includes a first pair of MOS transistors S1 and S2 and a second pair of MOS transistors S3 and S4.

[0107] exist Fig.19In (a), the sign selection unit (Sign Selection Unit or Sign Selection Block, SU) includes four MOS transistors S1, S2, S3 and S4, wherein the gate of each MOS transistor S1 and S2 is configured to receive a digital control signal S and the gate of each MOS transistor S3 and S4 is configured to receive a digital control signal SB complementary to the digital control signal S. In the symbol selection unit SU, two pairs of MOS transistors S1 / S2 and S3 / S4 are configured to operate so that (1) after being enabled, the first pair of transistors S1 / S2 can supply a first analog differential input voltage A_INA_P to the first transistors M1, M3 and M5 of each set of two transistors of the differential pair and a second analog differential input voltage A_INA_N is supplied to the second transistors M2, M4 and M6 of each set of two transistors of the differential pair, or (2) after being enabled, the second pair of transistors S3 / S4 can supply a first analog differential input voltage A_INA_P to the second transistors M2, M4 and M6 of each set of two transistors of the differential pair and a second analog differential input voltage A_INA_N is supplied to the first transistors M1, M3 and M5 of each set of two transistors of the differential pair, depending on the state of the complementary signal of the digital control signal S and the digital control signal SB. The difference in the magnitude of the current flowing in the bit lines BL / BLB is proportional to the differential input voltage applied to each transistor (M1-M6).

[0108] A first pair of MOS transistors S1 and S2 in the symbol selection unit SU is configured to be activated by receiving a digital control signal S at its gate terminals. A second pair of MOS transistors S3 and S4 in the symbol selection unit SU is configured to be activated by receiving a digital control signal SB at its gate terminals. The digital control signal S and the digital control signal SB are related to each other such that (1) when the digital control signal S is a high digital potential, the digital control signal SB is a low digital potential and (2) when the digital control signal SB is a high digital potential, the digital control signal S is a low digital potential. Therefore, a pair of MOS transistors in each analog multiplier circuit drives the analog differential input voltage A_INA_P or A_INA_N input through two pairs of MOS transistors in the symbol selection unit SU.

[0109] When the digital control signal S is a high digital potential and the digital control signal SB is a low digital potential, the digital control signal S(1) turns on the MOS transistor S1 so that the analog differential input voltage A_INA_P activates the first transistors M1, M3 and M5, so that the differential output currents O_P2, O_P1 and O_P0 flow into the bit lines BL[2], BL[1] and BL[0] respectively, and the digital control signal S(2) turns on the MOS transistor S2 so that the analog differential input voltage A_INA_N activates the second transistors M2, M4 and M6, so that the differential output currents O_N2, O_N1 and O_N0 flow into the bit lines BLB[2], BLB[1] and BLB[0] respectively. Similarly, when the digital control signal SB is a high digital potential and the digital control signal S is a low digital potential, the digital control signal SB(1) turns on the MOS transistor S3 so that the analog differential input voltage A_INA_P activates the second transistors M2, M4 and M6, so that the differential output currents O_N2, O_N1 and O_N0 flow into the bit lines BLB[2], BLB[1] and BLB[0] respectively, and the digital control signal S(2) turns on the MOS transistor S4 so that the analog differential input voltage A_INA_N activates the first transistors M1, M3 and M5, so that the differential output currents O_P2, O_P1 and O_P0 flow into the bit lines BL[2], BL[1] and BL[0] respectively. The differential output currents generated by transistor pairs M1 / M2, M3 / M4 and M5 / M6 in each analog multiplier are determined by subtracting the currents in bit lines BLB[2], BLB[1] and BLB[0] from the currents in bit lines BL[2], BL[1] and BL[0], respectively.

[0110] On the other hand, when the “low” digital input voltages D_INB[2], D_INB[1], and D_INB[0] do not activate the switching transistors SW2, SW1, and SW0, the differential output currents (O_P2-O_P0 and O_N2-O_N0) in the corresponding bit lines (BL[2]-BL[0] and BLB[2]-BL[0]) may be reduced to a normal level.

[0111] The variable resistors R2, R1 and R0 are programmed to specific values ​​before operating the circuit. The three differential output currents (O_P2-O_N2), (O_P1-O_N1), (O_P0-O_N0) can be scaled with reference to the first differential output current (O_P0-O_N0). When the scale factor K is set to 2 as an integer and with reference to the value 1 of the first differential output current (O_P0-O_N0), the values ​​of the remaining differential output currents (O_P2-O_N2), (O_P1-O_N1) and (O_P0-O_N0) will reach 4, 2 and 1. The scale factor K is set to accurately identify one output current from the other output currents of the bit line. Therefore, when the digital control signal S becomes high to turn on the selected transistors, the differential output current (O_P-O_N) in each analog multiplier circuit in the array is proportional to the product of the target default differential input voltage (A_INA_P and A_INA_N) and the resistance derivative value of the variable resistors R2-R0. On the other hand, when the "low" digital input voltage (D_INB[2], D_INB[1], D_INB[0]) disables each switching transistor SW2, SW1, and SW0, the differential output current (O_P2-0 and O_N2-0) may be reduced to a normal level.

[0112] Fig.19 (b) describes the analog multiplier circuit array 1940 including: Fig.19 (a) shows a symbol selection unit SU and three pairs of analog multiplier circuits E2, E1 and E0, each pair of which is connected to a pair of voltage source nodes to provide analog differential input voltages A_INA_P and A_INA_N, wherein the analog multiplier circuits are as shown in FIG. Fig.17 (b) shows. The switching transistors SW2, SW1 and SW0 are connected to the differential amplifier circuit and the three variable resistors R2, R1 and R0, so that the switching transistors SW2, SW1 and SW0 enable or disable the output current flowing into the three pairs of bit lines BL[2] / BLB[2], BL[1] / BLB[1] and BL[0] / BLB[0] according to the unsigned digital input voltages D_INB[2], D_INB[1] and D_INB[0] respectively received at the gate terminals of the switching transistors SW2, SW1 and SW0. Fig.19 (c) describes analog multiplier circuit array 1960 including: Fig.19 (a) shows a symbol selection unit SU and three pairs of analog multiplier circuits F2, F1 and F0, each pair of analog multiplier circuits F2, F1 and F0 is connected to a pair of voltage source nodes to provide analog differential input voltages A_INA_P and A_INA_N, wherein the analog multipliers are as shown in FIG. Fig.17 (c) as shown.

[0113] Fig. 20According to one embodiment of the present invention, a schematic circuit diagram of a differential analog multiplier with logic compatible flash memory is provided. Fig. 20 In FIG. 1 , the analog multiplier circuit 2000 is configured to receive a pair of analog differential input voltages A_INA_P and A_INA_N and a 1-bit digital input voltage D_INB, and to generate a resultant differential output current pair O_P and O_N to a pair of bit lines BL and BLB. The multiplier is Fig.17 The combination of a pair of differential MOS transistors and the variable resistor R is Fig.14 As shown in . The differential pair of MOS transistors includes a pair of MOS transistors M10 and M12 having a common source terminal connected to the drain terminal of a read transistor 2020. The read transistor 2020 has a control gate terminal connected to a pair of coupling transistors C1 and C2 and a floating gate (FG) as a charge storage node. The pair of MOS transistors M10 and M12 receive a pair of analog differential input voltages A_INA_P and A_INA_N respectively.

[0114] The read transistor 2020 has a control gate terminal connected to a pair of coupling transistors C1 and C2 and serves as a charge storage node through a floating gate FG. The coupling transistor C1 is connected to a programming word line PWL to provide a programming voltage to the floating gate FG. The coupling transistor C2 is connected to a write word line WWL to operate data writing. The drain terminal of the switching transistor 2040 is connected to the source terminal of the read transistor 2020, and the source terminal of the switching transistor 2040 is connected to a shared source line CSL. The switching transistor 2040 is configured to enable or disable the current in the bit line according to the digital input voltage D_INB received by the gate region of the switching transistor 2040.

[0115] The floating gate FG node voltage may be programmed to a target specific value, and when the digital input voltage D_INB is high to "turn on" the selected transistor, the current amount (O_P and O_N) of the differential output current pair may be proportional to the product of the default differential input voltage (A_INA_P and A_INA_N) and the conductance of the read transistor 2020 of the logic-compatible flash memory. On the other hand, when the digital input voltage D_INB becomes low to turn off the selected transistor, the current output amount (O_P and O_N) may be reduced to a general level. Although a specific number of read transistors or selected transistors is shown, it should be understood that any number of read transistors and / or selected transistors may be connected in series.

[0116] Fig.21 FIG. 1 is a representative schematic diagram of a differential analog multiplier array according to one embodiment of the present invention. Fig.21 In the embodiment, a pair of differential input signal source lines providing differential input voltages A_INA_P and A_INA_N are connected to four differential analog multipliers. Each differential analog multiplier having a logic-compatible flash memory in the array is as described above. Fig. 20 Described. Floating gates FG3, FG2, FG1 and FG0 that provide programming voltage to programming word line PWL are connected to first coupling transistors in each logic compatible flash memory. Write word line WWL for operation data writing is connected to second coupling transistors in each logic compatible flash memory. Switching transistors S3, S2, S1 and S0 are configured to enable or disable four pairs of differential output currents flowing in bit lines BL[3] / BLB[3], BL[2] / BLB[2], BL[1] / BLB[1] and BL[0] / BLB[0] according to digital input voltages D_INB[3], D_INB[2], D_INB[1] and D_INB[0]. Floating gates FG3, FG2, FG1 and FG0 have been programmed to specific values. In other words, the magnitudes of the differential output currents (O_P3 - O_N3), (O_P2 - O_N2), (O_P1 - O_N1), and (O_P0 - O_N0) may be scaled with reference to the magnitude of the differential output current (O_P0 - O_N0).

[0117] The scale factor K is an integer. When the scale factor K is set to 2 with reference to the differential output current (O_P0-O_N0) having a value of 1, the magnitudes of the differential output currents (O_P3-O_N3), (O_P2-O_N2), (O_P1-O_N1), and (O_P0-O_N0) will reach 8, 4, 2, and 1. The scale factor K is set in order to accurately identify one output current from other output currents on the bit line. The current of the bit line is the product of the default input voltage signal (operand X) and the conductance of the read transistor (operand Y). Therefore, when the four digital input voltages D_INB[3], D_INB[2], D_INB[1] and D_INB[0] are at a high level to turn on the selected transistors, the differential output currents (O_P3-O_N3), (O_P2-O_N2), (O_P1-O_N1) and (O_P0-O_N0) in each pair of analog multiplier circuits E0, E1, E2 and E3 of the analog multiplier circuit array 2100 are proportional to the product of the target default differential input voltages (A_INA_P and A_INA_N) and the conductances of the NMOS devices connected to the floating gates FG3, FG2, FG1 and FG0. On the other hand, when any of the digital input voltages (D_INB[3], D_INB[2], D_INB[1], D_INB[0]) becomes low to turn off the corresponding switching transistor (S3-S0), the differential output current (O_P3-0 and O_N3-0) may be reduced to a normal level. That is, when the digital input voltage D_INB[3], D_INB[2], D_INB[1] or D_INB[0] is low, it is determined to keep the switching transistor in a non-conducting state, and the current in the corresponding bit line can be reduced to a normal level.

[0118] Fig. 22 FIG. 2 is a representative schematic diagram of a differential analog multiplier array according to an embodiment of the present invention. The analog multiplier circuit array 2200 includes one symbol selection unit and three analog multiplier units. The symbol selection unit is as shown in FIG. Fig.19 As described, the analog multiplier circuit is Fig. 20 The three pairs of analog multiplier circuits F2, F1 and F0 in the analog multiplier circuit array 2200 respectively generate a plurality of pairs of differential output currents (O_P2 / O_N2-O_P0 / O_N0) in a plurality of pairs of bit lines (BL2 / BLB2-BL0 / BLB0). The symbol selection unit SU includes a first pair of MOS transistors S1 and S2 and a second pair of MOS transistors S3 and S4.

[0119] The magnitude of the differential output current (O_P2 / O_N2~O_P0 / O_N0) flowing in the bit line (BL2 / BLB2~BL0 / BLB0) is proportional to the differential input voltages A_INA_P and A_INA_N applied to the first pair of MOS transistors S1 and S2 and the second pair of MOS transistors S3 and S4. When the digital control signal S is at a high level, the differential output current (O_P2~0) generated in response to the differential input voltage A_INA_P flows in the bit line (BL2~0), and the differential output current (O_N2~0) generated in response to the differential input voltage A_INA_N flows in the bit line (BLB2~0). When the digital control signal S is at a low level, the differential output current (O_P2-0) generated in response to the differential input voltage A_INA_N flows in the bit line (BL2-0), and the differential output current (O_N2-0) generated in response to the differential input voltage A_INA_P flows in the bit line (BLB2-0). The differential output current (O_P2 / O_N2-O_P0 / O_N0) generated by the transistor pairs (M10 / M20, M30 / M40, M50 / M60) in each analog multiplier F2, F1 and F0 is determined by subtracting the current in the bit line BLB2-0 from the current in the bit line BL2-0.

[0120] The first pair of MOS transistors S1 and S2 in the symbol selection unit SU is configured to be activated by receiving a digital control signal S at its gates. The second pair of MOS transistors S3 and S4 in the symbol selection unit SU is configured to be activated by receiving a digital control signal SB at its gates. The digital control signal S and the digital control signal SB are related to each other so that (1) when the digital control signal S is a high digital potential, the digital control signal SB is a low digital potential and (2) when the digital control signal SB is a high digital potential, the digital control signal S is a low digital potential. Therefore, a pair of MOS transistors in each analog multiplier circuit F3-F0 drives the analog differential input voltage A_INA_P or A_INA_N input through two pairs of MOS transistors in the symbol selection unit SU.

[0121] When the first pair of MOS transistors S1 and S2 are activated in response to the digital control signal S of a high digital potential, the analog differential input voltage (A_INA_P) is connected to the upper input lines of the three analog multiplier circuits F3 to F0, and the other analog differential input voltage (A_INA_N) is connected to the lower input lines of the three analog multiplier circuits F3 to F0. Similarly, when the second pair of MOS transistors (S3 and S4) are activated in response to the digital control signal SB of a high digital potential, the analog differential input voltage (A_INA_P) is connected to the lower input lines of the three analog multiplier circuits F3 to F0, and the other analog differential input voltage (A_INA_N) is connected to the upper input lines of the three analog multiplier circuits F3 to F0.

[0122] Therefore, when the digital control signal S is high and the digital control signal SB is low, the NMOS transistor is then enabled to supply the analog differential input voltages A_INA_P and A_INA_N to the gates of the corresponding NMOS transistors through the upper input line and the lower input line. Therefore, the paired transistors enable the differential output currents O_P2~0 and O_N2~0, respectively. When the digital control signal S is low and the digital control signal SB is high, the NMOS transistor is then enabled to supply the analog differential input voltages A_INA_P and A_INA_N to the gates of the corresponding NMOS transistors through the upper input line and the lower input line. On the other hand, when any of the digital input voltages D_INB[2], D_INB[1], and D_INB[0] becomes low to turn off the corresponding switching transistor, the differential output currents O_P2~0 and O_N2~0 may be reduced to a normal level. That is, when the digital input voltage D_INB[2], D_INB[1] or D_INB[0] is at a low level, the switching transistor is maintained in a non-conducting state, and the current in the corresponding bit line may be reduced to a normal level.

[0123] Fig.23 An exemplary analog accumulator circuit is described in accordance with the present invention. Fig.23 (a) Description An exemplary current accumulator circuit 2320 includes a plurality of NMOS transistors. Each NMOS transistor (2322, 2324, etc.) is connected to an internal enable node EN via its control terminal and is connected to bit lines BL[n-1], BL[n-2], BL[n-3] ... BL[0] via its source terminal and drain terminal. Therefore, the NMOS transistors (2322, 2324, etc.) can accumulate the current of each bit line BL[n-1], BL[n-2], BL[n-3] ... BL[0] at the output line OUT node according to a high potential signal received from the internal enable node EN. Similarly, the NMOS transistors (2322, 2324, etc.) can shut down the current of each bit line BL[n-1], BL[n-2], BL[n-3] ... BL[0] at the output line OUT node according to a low potential signal received from the internal enable node EN.

[0124] Fig.23 (b) Description An exemplary current accumulator circuit 2340 includes a plurality of PMOS transistors. Each PMOS transistor (2342, 2344, etc.) is connected to the internal enable node ENB via its control terminal and is connected to the bit lines BL[n-1], BL[n-2], BL[n-3]...BL[0] via its source terminal and drain terminal. Therefore, the PMOS transistors (2342, 2344, etc.) can accumulate the current of each bit line BL[n-2], BL[n-3]...BL[0] at the output line OUT node according to a low potential signal received from the internal enable node ENB. Similarly, the PMOS transistors (2342, 2344, etc.) can shut down the current of each bit line BL[n-2], BL[n-3]...BL[0] at the output line OUT node according to a high potential signal received from the internal enable node ENB.

[0125] Fig.23(c) An exemplary current accumulator circuit 2360 is described, which includes multiple CMOS transistors. The first control gates of the multiple CMOS transistors (2362, 2364, etc.) are connected to the internal enable node EN. The second control gates of the multiple CMOS transistors (2362, 2364, etc.) are connected to the internal enable node ENB. The gate terminals and drain terminals of the multiple CMOS transistors (2362, 2364, etc.) are connected to multiple bit lines BL[n-1], BL[n-2], BL[n-3]...BL[0]. Therefore, the multiple CMOS transistors (2362, 2364, etc.) activated by the high potential signal of the internal enable node EN and the low potential signal of the internal enable node ENB accumulate the currents of the bit lines BL[n-2], BL[n-3]...BL[0] at the output line OUT node. Similarly, multiple CMOS transistors (2362, 2364, etc.) enabled by the low potential signal of the internal enable node EN and the high potential signal of the internal enable node ENB shut down the current of the bit lines BL[n-2], BL[n-3]...BL[0] in the output line OUT node.

[0126] Fig.23 (d) An exemplary current accumulator circuit is described having a plurality of current mirror circuits 2382, 2384, 2386, and 2388, each of which has a plurality of pairs of PMOS transistors. Each of the current mirror circuits 2382, 2384, 2386, and 2388 is configured to receive a mirror current 1 of the bit lines BL[n-1], BL[n-2], BL[n-3], and BL[0], and provide an amplified mirror current m n-1 、m n-2 、m n-3 and mirror current 1 to other branches and accumulate these mirror currents at the output line OUT node. In the configuration shown in the figure, each current mirror circuit 2382, 2384, 2386 and 2388 includes a pair of PMOS transistors. The gate terminals of the paired transistors in each current mirror circuit 2382, 2384, 2386 and 2388 are connected through the shared gate contact of the transistors. In each current mirror circuit 2382, 2384, 2386 and 2388, the shared gate contact connects the drain of the transistor and one of the bit lines BL[n-1], BL[n-2], BL[n-3]...BL[0].

[0127] The current in each bit line BL[n-1], BL[n-2], BL[n-3]...BL[0] is mirrored to the channel between the source terminal and the drain terminal of the transistor with a specific accumulator scaling factor m (i.e., m=1, 2, 3, etc. integer). Then, once the current mirror circuits 2382, 2384, 2386, and 2388 are enabled, the amplified mirrored current is accumulated at the output line node. For example, when the resistance scaling factor k is set to 1, the accumulator scaling factor m can be 2 to scale the current of the bit lines BL[n-1], BL[n-2], BL[n-3]...BL[0] for the most significant bit to the least significant bit position of the analog accumulator. In this state, the voltage-controlled variable resistor R can be used to simulate the most significant bit to the least significant bit position of the accumulator. Flash memory or other multi-level memory cell technologies are superior to other single-level memories, such as static random access memory (SRAM), read-only memory (ROM), one-time programmable memory (OTP), or magnetoresistive random access memory (MRAM), because the resistance value of flash memory can be adjusted after manufacturing.

[0128] Fig.24 Other exemplary resistors R according to the present invention are described. The voltage divider can be carefully selected to set the transistor operation mode. The voltage divider can be removed using a diode-connected NMOS or PMOS device. Multiple diode-connected NMOS or PMOS devices can also be connected in series. The transistor sizing is carefully set so that the target resistance value can be represented by the transistor. The ratio of transistor W / L can be scaled accordingly for different bit positions. Similarly, long wires and polysilicon gates can be used alternately to appropriately scale the resistant device for different bit positions from the most significant bit to the least significant bit.

[0129] FIG. 25 describes an exemplary operational calculation of the present invention including scale factors k and m. Here, the operational steps for generating the output are summarized as follows:

[0130] (1) Receive analog input and digital input data;

[0131] (2) Calculate partial output according to the equation:

[0132] O n =Xk (n-1) , where X is the analog input, k is the first programmed scale factor, and n is a number having a unit or multiple digits;

[0133] (3) generating a combined product by multiplying the partial products in binary form with the two-bit input data;

[0134] (4) Apply a second magnification factor (Pn) to the combined product, where Pn = mO n , where P is the partial product and m is the second scaling factor;

[0135] (5) adding a plurality of partial product values ​​to form a partial sum in a defined row;

[0136] (6) Repeat steps (2) to (5) for other definition rows; and

[0137] (7) Generate a total value from all sub-values ​​to provide the AnalogAccumulator.

[0138] In FIG. 25(a), the steps for generating the output of (7x3)+(2x6)+(4x1) are shown. Here, in step 1, as operand X, the numbers 7, 2, and 4 are analog inputs (A1, A2, and A3). As operand Y, the numbers 3, 6, and 1 (D1, D2, and D3) are converted to a set of binary numbers (011, 110, 001) to be multiplied. The calculations of operand X and operand Y are performed in a single row, so the three calculations of the components of operand X and operand Y are performed through three rows (Row 1, Row 2, and Row 3).

[0139] As operand X, numbers 7, 2, and 4 are analog inputs (A1, A2, and A3). As operand Y, numbers 3, 6, and 1 (D1, D2, and D3) are converted to a set of binary numbers (011, 110, 001) to be multiplied. The calculations for operand X and operand Y are done in a single row, so the three calculations for the components of operand X and operand Y are done through three rows (Row 1, Row 2, and Row 3).

[0140] In step 2, a set of first amplified outputs {28, 14, 7} is generated by applying a magnification factor (4, 2, 1) to the first input 7. The magnification factor is determined based on a scale factor 2 of the position of the reference unit or multiple bits. Therefore, the first bit is 1, the second bit is 2, and the third bit is 4 as the magnification factor. In step 3, a set of combined products {0, 14, 7} is generated by multiplying the first set of binary numbers {0, 1, 1} and the first set of amplified products {28, 14, 7}. In step 4, a second set of amplified products {0, 14, 7} is generated by multiplying the second factor (m=1) and the first amplified products {0, 14, 7}, which remain the same. In step 5, a first partial product 21 is obtained by adding each element of the first combined product {0, 14, 7}.

[0141] According to step 6, in step 2, a first set of amplified outputs {8,4,2} is generated by applying the amplification factor (4,2,1) to the second input 2. In step 3, a set of combined products {8,4,0} is generated by multiplying the second set of binary numbers {1,1,0} and the first set of amplified products {8,4,2}. In step 4, a second set of amplified products {8,4,0} is generated by multiplying the second factor (m=1) and the set of combined products {8,4,0}, which remain the same. In step 5, a second partial product 12 is obtained by adding each element of the second combined product {8,4,0}.

[0142] According to step 6, in step 3, a first set of amplified outputs {16, 8, 4} is generated by applying the amplification factor (4, 2, 1) to the third input 4. In step 3, a set of first combined products {0, 0, 4} is generated by multiplying the third set of binary numbers {0, 0, 1} and the third set of amplified products {16, 8, 4}. In step 4, a second set of amplified products {0, 0, 4} is generated by multiplying the second factor (m=1) and a set of combined products {0, 0, 4}. In step 5, a third partial product 4 is generated by adding each element of the third combined product {0, 0, 4}. In step 6, once proceeding to step 7, the calculation of the entire three rows (Row1, Row2, Row3) is performed. In step 7, the total value 37 is output as (7x3)+(2x6)+(4x1) by summing the first partial product 21, the second partial product 12 and the third partial product 4.

[0143] FIG. 25( b ) depicts the same steps as are actually performed to produce Fig.24 (a) describes the output of (7x 3) + (2x6) + (4x1). In step 1, as operand X, the numbers 7, 2, and 4 are analog inputs (A1, A2, and A3). As operand Y, the numbers 3, 6, and 1 (D1, D2, and D3) are converted to a set of binary numbers (011, 110, 001) to be multiplied. The calculations of operand X and operand Y are completed in a single row, so the three calculations of the components of operand X and operand Y are completed through three rows (Row1, Row2, and Row3).

[0144] In step 2, a set of first amplified outputs {7,7,7} is generated by applying an amplification factor (1,1,1) to the first input 7. The amplification factor is determined based on a scale factor 1 of the position of the reference unit or multiple bits. Therefore, the first bit is 1, the second bit is 1, and the third bit is 1 as the amplification factor. In step 3, a set of combined products {0,7,7} is generated by multiplying the first set of binary numbers {0,1,1} and the first set of amplified products {7,7,7}. In step 4, a second set of amplified products {0,14,7} is generated by multiplying the second amplification factor (4,2,1) and the first amplified output {0,7,7}, which remain the same. In step 5, a first partial product 21 is obtained by adding each element of the first combined product {0,14,7}.

[0145] According to step 6, in step 2, a first set of amplified outputs {2,2,2} is generated by applying the amplification factor (1,1,1) to the second input 2. In step 3, a set of combined products {2,2,0} is generated by multiplying the second set of binary numbers {1,1,0} and the first set of amplified products {2,2,2}. In step 4, a second set of amplified products {8,4,0} is generated by multiplying the second factor (4,2,1) and the set of combined products {2,2,0}, which remain the same. In step 5, a second partial product 12 is obtained by adding each element of the second combined product {8,4,0}.

[0146] According to step 6, in step 3, a first set of amplified outputs {4,4,4} is generated by applying the amplification factor (1,1,1) to the third input 4. In step 3, a set of first combined products {0,0,4} is generated by multiplying the third set of binary numbers {0,0,1} and the third set of amplified products {4,4,4}. In step 4, a second set of amplified products {0,0,4} is generated by multiplying the second factor (4,2,1) and a set of combined products {0,0,4}. In step 5, a third partial product 4 is generated by adding each element of the third combined product {0,0,4}. In step 7, a total value 37 is output as (7x3)+(2x6)+(4x1) by summing the first partial product 21, the second partial product 12 and the third partial product 4.

[0147] FIG. 25( c ) depicts the same operation steps actually performed to produce Fig.24(a) The output of (7 x 3) + (2 x 6) + (4 x 1) is described above, except that the accumulators are integrated into each row with an implicit scaling factor m = 1 (not shown) instead of a separate accumulator at the end. As operand X, the numbers 7, 2, and 4 are analog inputs (A1, A2, and A3). As operand Y, the numbers 3, 6, and 1 (D1, D2, and D3) are converted to a set of binary numbers (011, 110, 001) to be multiplied. The calculations for operand X and operand Y are done in a single row, therefore, the three calculations for the components of operand X and operand Y are done over three rows (Row1, Row2, and Row3).

[0148] In step 2, a first amplified output {28, 14, 7} is generated by applying the amplification factor (4, 2, 1) to the first input 7. The amplification factor is determined based on the scale factor 2 of the position of the reference unit or multiple bits. Therefore, the first bit is 1, the second bit is 2, and the third bit is 4 as the amplification factor. In step 3, a set of combined products {0, 14, 7} is generated by multiplying the first set of binary numbers {0, 1, 1} and the first set of amplified products {28, 14, 7}. In step 4, the first partial product 21 is obtained by adding each element of the first combined product {0, 14, 7}.

[0149] According to step 6, in step 2, a first set of amplified outputs {8,4,2} is generated by applying the amplification factor (4,2,1) to the second input 2. In step 3, a set of combined products {8,4,0} is generated by multiplying the second set of binary numbers {1,1,0} and the first set of amplified products {8,4,2}. In step 4, a second partial product 12 is obtained by adding the elements of the second combined product {8,4,0}.

[0150] According to step 6, in step 3, a first set of amplified outputs {16, 8, 4} is generated by applying amplification factors (4, 2, 1) to the third input 4. In step 3, a set of first combined products {0, 0, 4} is generated by multiplying the third set of binary numbers {0, 0, 1} and the third set of amplified products {16, 8, 4}. In step 4, a third partial product 4 is generated by adding each element of the third combined product {0, 0, 4}.

[0151] In step 6, once proceeding to step 7, the calculation of the entire three rows (Row1, Row2, Row3) is performed. In step 7, the total value 37 is output as (7x3)+(2x6)+(4x1) by summing the first partial product 21, the second partial product 12 and the third partial product 4.

Claims

1. An analog multiplier accumulator array, comprising: Analog multipliers, set up to form a matrix with rows and columns, one or more analog input signal lines coupled to the analog multipliers on a row of the array; Analog level sensing circuit; A set of one or more bit lines, each bit line being electrically connected to the analog multipliers in each column of a row; as well as an analog accumulator configured to connect the bit line to the analog level sensing circuit to generate a digital output signal, wherein each of the analog multipliers comprises an access transistor and a variable resistor connected to an analog input signal line; Each of the analog accumulators comprises: an array of MOS transistors arranged in rows, each of the MOS transistors being connected to a bit line in the set of bit lines; as well as A control line is connected to the respective gates of the MOS transistors to enable switching of the MOS transistors, so that during the activation of the MOS transistors, currents flowing in the connected bit lines are combined on one of the connected bit lines.

2. The analog multiplier accumulator array according to claim 1, wherein the variable resistor comprises: One or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and the access transistor has a gate terminal connected to a second analog input line.

3. The analog multiplier accumulator array according to claim 1 , wherein the variable resistor comprises: a read transistor; as well as A pair of coupling transistors are configured to have a shared floating gate with the read transistor, wherein the coupling transistors are coupled to an input line that is separate from the analog input signal line connected to the access transistor.

4. The analog multiplier accumulator array according to claim 1 , further comprising: A switching transistor is connected in series with the access transistor, the switching transistor having a gate terminal connected to a digital input line. 5 . The analog multiplier accumulator array of claim 4 , wherein the switching transistor is connected in series with the variable resistor such that the switching transistor enables or disables a current in the bit line toward the variable resistor.

6. The analog multiplier accumulator array according to claim 5, wherein the variable resistor comprises: One or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and the access transistor has a gate terminal connected to a second analog input line.

7. The analog multiplier accumulator array according to claim 5, wherein the variable resistor comprises: Read transistor; as well as A pair of coupling transistors are configured to have a shared floating gate with the read transistor, wherein one of the coupling transistors is connected to a program word line and the other of the coupling transistors is connected to a write word line.

8. The analog multiplier accumulator array of claim 7, wherein the program word line is connected to a control gate of one of the pair of coupled transistors, and the write word line is connected to the other of the coupled transistors.

9. An analog multiplier accumulator array, comprising: Analog multipliers, set up to form a matrix with rows and columns, pairs of analog input signal lines coupled to the analog multipliers on rows of the array; Analog level sensing circuit; a set of bit lines, each bit line being electrically connected to the analog multipliers in each column of the row; as well as an analog accumulator configured to connect the set of bit lines to the analog level sensing circuit to generate a digital output signal, wherein a pair of differential transistors, a variable resistor and a switching transistor form the analog multiplier, Each of the analog accumulators comprises: an array of MOS transistors arranged in rows, each of the MOS transistors being connected to a bit line in the set of bit lines; as well as A control line is connected to the respective gates of the MOS transistors to enable switching of the MOS transistors, so that during the activation of the MOS transistors, currents flowing in the connected bit lines are combined on one of the connected bit lines.

10. The analog multiplier accumulator array of claim 9, wherein: A first differential transistor of the differential transistors has a gate coupled to a first signal line of the pair of analog input signal lines, the first differential transistor being associated with a first bit line of the set of bit lines; as well as A second differential transistor of the differential transistors has a gate coupled to a second signal line of the pair of analog input signal lines, the second differential transistor being associated with a second bit line of the set of bit lines.

11. The analog multiplier accumulator array of claim 10, wherein the switching transistors include pairs of MOS transistors to connect the pairs of differential transistors in series.

12. The analog multiplier accumulator array of claim 10 , wherein the variable resistor comprises: a read transistor forming the analog multiplier; as well as A pair of coupled transistors is connected to the read transistor, wherein the coupled transistors have a shared floating gate connected to the gate terminal of the read transistor, wherein the shared source terminal of the differential transistor is connected to the drain terminal of the read transistor.

13. The analog multiplier accumulator array of claim 10 , further comprising: A symbol selection unit having four transistors configured such that gate terminals of a first and a second transistor are connected to one of the complementary digital input signal lines, and gate terminals of a third and a fourth transistor are connected to receive the other of the complementary digital input signal lines, wherein the paired analog input signal lines can be associated with the paired first and second transistors or the paired third and fourth transistors.

14. An analog multiplier accumulator array, comprising: Analog multipliers, set up to form a matrix with rows and columns, one or more analog input signal lines coupled to the analog multipliers on a row of the array; Analog level sensing circuit; A set of one or more bit lines, each bit line being electrically connected to the analog multipliers in each column of a row; as well as an analog accumulator configured to connect the bit line to the analog level sensing circuit to generate a digital output signal, wherein each of the analog multipliers comprises an access transistor and a variable resistor connected to an analog input signal line; Each of the analog accumulators comprises: an array of CMOS transistors arranged in rows, each of the CMOS transistors being connected to a bit line in the set of bit lines; as well as A pair of control lines are connected to the gates of the respective NMOS transistors of the CMOS transistors, and the second source nodes are connected to the gates of the respective PMOS transistors of the CMOS transistors, so that during the start-up of the NMOS transistor, the PMOS transistor, or the NMOS transistor and the PMOS transistor, the currents flowing in the connected bit lines are combined on one of the connected bit lines.

15. The analog multiplier accumulator array of claim 14, wherein the variable resistor comprises: One or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and the access transistor has a gate terminal connected to a second analog input line.

16. The analog multiplier accumulator array of claim 14, wherein the variable resistor comprises: a read transistor; as well as A pair of coupling transistors are configured to have a shared floating gate with the read transistor, wherein the coupling transistors are coupled to an input line that is separate from the analog input signal line connected to the access transistor.

17. The analog multiplier accumulator array of claim 14, further comprising: A switching transistor is connected in series with the access transistor, the switching transistor having a gate terminal connected to a digital input line.

18. The analog multiplier accumulator array of claim 17, wherein the switching transistor is connected in series with the variable resistor such that the switching transistor enables or disables a current in the bit line toward the variable resistor.

19. The analog multiplier accumulator array of claim 18, wherein the variable resistor comprises: One or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and the access transistor has a gate terminal connected to a second analog input line.

20. The analog multiplier accumulator array of claim 18, wherein the variable resistor comprises: Read transistor; as well as A pair of coupling transistors are configured to have a shared floating gate with the read transistor, wherein one of the coupling transistors is connected to a program word line and the other of the coupling transistors is connected to a write word line.

21. The analog multiplier accumulator array of claim 20, wherein the program word line is connected to a control gate of one of the pair of coupled transistors and the write word line is connected to the other of the coupled transistors.

22. An analog multiplier accumulator array, comprising: Analog multipliers, set up to form a matrix with rows and columns, pairs of analog input signal lines coupled to the analog multipliers on rows of the array; Analog level sensing circuit; a set of bit lines, each bit line being electrically connected to the analog multipliers in each column of the row; as well as an analog accumulator configured to connect the set of bit lines to the analog level sensing circuit to generate a digital output signal, The analog multipliers each include a pair of differential transistors, a variable resistor, and a switching transistor. The analog accumulator comprises: an array of CMOS transistors arranged in rows, each of the CMOS transistors being connected to a bit line in the set of bit lines; as well as A pair of control lines are connected to the gates of the respective NMOS of the CMOS transistors, and the second source nodes are connected to the gates of the respective PMOS of the CMOS transistors, so that during the start-up of the NMOS, PMOS or NMOS and PMOS, the currents flowing in the connected bit lines are combined on one of the connected bit lines.

23. The analog multiplier-accumulator array of claim 22, wherein: A first differential transistor of the differential transistors has a gate coupled to a first signal line of the pair of analog input signal lines, the first differential transistor being associated with a first bit line of the set of bit lines; as well as A second differential transistor of the differential transistors has a gate coupled to a second signal line of the pair of analog input signal lines, the second differential transistor being associated with a second bit line of the set of bit lines.

24. The analog multiplier accumulator array of claim 23, wherein the switching transistors include pairs of MOS transistors to connect the pairs of differential transistors in series.

25. The analog multiplier accumulator array of claim 23, wherein the variable resistor comprises: a read transistor forming the analog multiplier; as well as A pair of coupled transistors is connected to the read transistor, wherein the coupled transistors have a shared floating gate connected to the gate terminal of the read transistor, wherein the shared source terminal of the differential transistor is connected to the drain terminal of the read transistor.

26. The analog multiplier accumulator array of claim 23, further comprising: A symbol selection unit having four transistors configured such that gate terminals of a first and a second transistor are connected to one of the complementary digital input signal lines, and gate terminals of a third and a fourth transistor are connected to receive the other of the complementary digital input signal lines, wherein the paired analog input signal lines can be associated with the paired first and second transistors or the paired third and fourth transistors.

27. An analog multiplier accumulator array, comprising: Analog multipliers, set up to form a matrix with rows and columns, one or more analog input signal lines coupled to the analog multipliers on a row of the array; Analog level sensing circuit; A set of one or more bit lines, each bit line being electrically connected to the analog multipliers in each column of a row; as well as an analog accumulator configured to connect the bit line to the analog level sensing circuit to generate a digital output signal, wherein each of the analog multipliers comprises an access transistor and a variable resistor connected to an analog input signal line; The analog accumulators each include an array of pairs of PMOS transistors arranged in rows to form a row of current mirrors, each of the pairs of PMOS transistors including: A pair of first and second transistors have a shared node connected to gates of the paired transistors, wherein the first transistor has a drain terminal connected to the shared node, and the second transistor has a drain terminal to output an amplified current according to a current flowing in a bit line connected to the shared node.

28. The analog multiplier accumulator array of claim 27, wherein the variable resistor comprises: One or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and the access transistor has a gate terminal connected to a second analog input line.

29. The analog multiplier accumulator array of claim 27, wherein the variable resistor comprises: a read transistor; as well as A pair of coupling transistors are configured to have a shared floating gate with the read transistor, wherein the coupling transistors are coupled to an input line that is separate from the analog input signal line connected to the access transistor.

30. The analog multiplier accumulator array of claim 27, further comprising: A switching transistor is connected in series with the access transistor, the switching transistor having a gate terminal connected to a digital input line.

31. The analog multiplier accumulator array of claim 30, wherein the switching transistor is connected in series with the variable resistor such that the switching transistor enables or disables current in the bit line toward the variable resistor.

32. The analog multiplier accumulator array according to claim 31, wherein the variable resistor comprises: One or more flash memories, wherein at least one flash memory is configured to be connected to a first analog input line and the access transistor has a gate terminal connected to a second analog input line.

33. The analog multiplier accumulator array of claim 31 , wherein the variable resistor comprises: Read transistor; as well as A pair of coupling transistors are configured to have a shared floating gate with the read transistor, wherein one of the coupling transistors is connected to a program word line and the other of the coupling transistors is connected to a write word line.

34. The analog multiplier accumulator array of claim 33, wherein the program word line is connected to a control gate of one of the pair of coupled transistors and the write word line is connected to the other of the coupled transistors.

35. An analog multiplier accumulator array, comprising: Analog multipliers, set up to form a matrix with rows and columns, pairs of analog input signal lines coupled to the analog multipliers on rows of the array; Analog level sensing circuit; a set of bit lines, each bit line being electrically connected to the analog multipliers in each column of the row; as well as an analog accumulator configured to connect the set of bit lines to the analog level sensing circuit to generate a digital output signal, The analog multipliers each include a pair of differential transistors, a variable resistor, and a switching transistor. The analog accumulator comprises an array of pairs of PMOS transistors arranged in rows to form a current mirror in rows, each pair of PMOS transistors comprising: A pair of first and second transistors have a shared node connected to gates of the paired transistors, wherein the first transistor has a drain terminal connected to the shared node, and the second transistor has a drain terminal to output an amplified current according to a current flowing in a bit line connected to the shared node.

36. The analog multiplier accumulator array of claim 35, wherein: A first differential transistor of the differential transistors has a gate coupled to a first signal line of the pair of analog input signal lines, the first differential transistor being associated with a first bit line of the set of bit lines; as well as A second differential transistor of the differential transistors has a gate coupled to a second signal line of the pair of analog input signal lines, the second differential transistor being associated with a second bit line of the set of bit lines.

37. The analog multiplier accumulator array of claim 36, wherein the switching transistors include pairs of MOS transistors connecting the pairs of differential transistors in series.

38. The analog multiplier accumulator array of claim 36, wherein the variable resistor comprises: a read transistor forming the analog multiplier; as well as A pair of coupled transistors is connected to the read transistor, wherein the coupled transistors have a shared floating gate connected to the gate terminal of the read transistor, wherein the shared source terminal of the differential transistor is connected to the drain terminal of the read transistor.

39. The analog multiplier accumulator array of claim 36, further comprising: A symbol selection unit having four transistors configured such that gate terminals of a first and a second transistor are connected to one of the complementary digital input signal lines, and gate terminals of a third and a fourth transistor are connected to receive the other of the complementary digital input signal lines, wherein the paired analog input signal lines can be associated with the paired first and second transistors or the paired third and fourth transistors.

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