Modified stack for 3D NAND

Abstract

An exemplary method of forming a semiconductor structure can include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The method can include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer can be characterized by an oxygen concentration greater than or about 5 atomic %. The method can also include repeating the forming a silicon oxide layer and forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 884,034, filed August 7, 2019, the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This technology relates to semiconductor processes and materials. More specifically, this technology relates to the formation of alternating layer stacks. Background Technology

[0004] Integrated circuits are made possible by creating complex patterned material layers on a substrate surface. Creating patterned material on a substrate requires controlled methods for forming and removing exposed material. Stacked memory, such as vertical or 3D NAND, can contain alternating layers of dielectric material, through which multiple memory holes or apertures can be etched. The material properties of the layers, as well as the etching conditions and the material itself, can affect the uniformity of the resulting structure. Material defects can lead to inconsistencies in patterning, which can further affect the uniformity of the resulting structure.

[0005] Therefore, there is a need for improved systems and methods to produce high-quality devices and structures. This technology addresses these and other needs. Summary of the Invention

[0006] An exemplary method for forming a semiconductor structure may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The method may also include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized in that the oxygen concentration is greater than or about 5 atomic percent. The method may further include repeatedly forming silicon oxide layers and forming silicon nitride layers to produce a stack of alternating layers of silicon oxide and silicon nitride.

[0007] In some embodiments, the oxygen-containing precursor forming the silicon oxide layer and the oxygen-containing precursor forming the silicon nitride layer may be the same or similar precursors. The stack of alternating layers may include a first portion of the stack and a second portion of the stack covering the first portion, the first portion of the stack comprising a silicon oxide layer and a silicon nitride layer. The second portion of the stack may comprise a silicon nitride layer formed from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized in that its oxygen concentration differs from that of the silicon nitride layer in the first portion of the stack. The oxygen concentration of the silicon nitride layer may be between about 10 atomic percent and about 30 atomic percent, and the nitrogen atomic percentage may be greater than or about 30 atomic percent.

[0008] Forming the silicon nitride layer can include flowing a silicon-containing precursor and a nitrogen-containing precursor into the substrate processing region. Forming the silicon nitride layer can include forming an amount of silicon nitride. Forming the silicon nitride layer can include adding an oxygen-containing precursor while continuing to form the silicon nitride. The oxygen-containing precursor can flow at a constant flow rate, and the formed silicon nitride layer can be or can include a bilayer of substantially oxygen-free silicon nitride and silicon nitride characterized by an oxygen concentration greater than or about 5 atomic percent. The oxygen-containing precursor can flow at a varying flow rate, and the formed silicon nitride layer can include a gradient in oxygen concentration throughout the silicon nitride layer. During the addition of the oxygen-containing precursor, the flow rate of the oxygen-containing precursor can be increased. The method can include forming one or more features through the stack of alternating layers of silicon oxide and silicon nitride. Lateral removal of the silicon nitride layer at the interface of the silicon nitride layer and the overlying silicon oxide layer can extend a distance less than or about 50% of a distance corresponding to the thickness of the silicon nitride layer.

[0009] Some embodiments of the present technology can encompass a semiconductor structure. The structure can include a stack of layers overlying a semiconductor substrate. The stack of layers can include a first portion of layers including alternating layers of silicon oxide material and silicon nitride material. The stack of layers can include a second portion of layers overlying the first portion of layers, and the second portion of layers can include alternating layers of silicon oxide material and silicon nitride material. The stack of layers can include a third portion of layers overlying the second portion of layers, and the third portion of layers can include alternating layers of silicon oxide material and silicon nitride material. The structure can include one or more apertures formed through the stack of layers to the substrate. A lateral notch in each individual layer of silicon nitride material at the interface of the individual layer of silicon nitride material and the overlying layer of silicon oxide material can extend a distance less than or about 100% of a distance corresponding to the thickness of the individual layer of silicon nitride material.

[0010] In some embodiments, the silicon nitride material of at least one of the layers of the first portion, the layers of the second portion, or the layers of the third portion can include an oxygen concentration of at least about 5 atomic %. The oxygen concentration of the silicon nitride material throughout at least one of the layers of the first portion, the layers of the second portion, or the layers of the third portion can increase in a direction toward an interface of a single layer of the silicon nitride material and a capping layer of the silicon oxide material, throughout a thickness of each of the layers of the silicon nitride material. The refractive index of the silicon nitride material of at least one of the layers of the first portion, the layers of the second portion, or the layers of the third portion can be higher than the refractive index of the layers of the other two portions. The refractive index of the silicon nitride of the layers of the second portion can be higher than the refractive index of the silicon nitride of the layers of the first portion and the silicon nitride of the layers of the third portion. The silicon nitride of the layers of the first portion can be characterized by a dopant concentration higher than the silicon nitride of the layers of the second portion and the layers of the third portion. The silicon nitride of the layers of the second portion or the silicon nitride of the layers of the third portion can be characterized by a carbon concentration higher than the silicon nitride of the layers of the first portion. The silicon nitride of the layers of the first portion or the silicon nitride of the layers of the second portion can be characterized by a ratio of nitrogen to silicon greater than the silicon nitride of the layers of the third portion.

[0011] Some embodiments of the present technology can encompass a method of forming a semiconductor structure. The method can include forming a first stack of alternating layers of a silicon oxide material and a silicon nitride material. The method can include annealing the first stack of alternating layers of the silicon oxide material and the silicon nitride material. The annealing can reduce a hydrogen concentration of the silicon nitride material. The method can include forming a second stack of alternating layers of the silicon oxide material and the silicon nitride material. The silicon nitride material can be characterized by an oxygen concentration greater than or about 5 atomic %.

[0012] The above-described techniques can provide numerous benefits over conventional systems and techniques. For example, the processing and structures can prevent defects from being formed during etching operations. In addition, the operations of embodiments of the present technology can improve memory hole formation through a stack. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the following description and attached figures. BRIEF DESCRIPTION OF DRAWINGS

[0013] A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remaining portions of the specification and the attached drawings.

[0014] Figure 1 A schematic cross-sectional view of an example processing chamber is illustrated in accordance with some embodiments of the present technology.

[0015] Figures 2A to 2D A schematic cross-sectional view of a substrate material is depicted in accordance with some embodiments of the present technology.

[0016] Figure 3 Selected operations in a formation method are illustrated in accordance with some embodiments of the present technology.

[0017] Figures 4A to 4BSchematic cross-sectional views of substrate materials on which selected operations are performed in accordance with some embodiments of the present technology are illustrated.

[0018] Some of the drawings contained in the attached Drawing Figures are included as schematic illustrations. It should be understood that the drawings are for illustrative purposes only and are not meant to be drawn to scale unless specifically stated to be to scale. Additionally, as schematic illustrations, the drawings are provided to aid in the understanding and can not contain all aspects or information as compared to a realistic representation, and can contain extraneous or exaggerated material for purposes of illustration.

[0019] In the drawings, like reference numerals can be used to denote similar components and / or features. Additionally, various components of the same type can be distinguished from each other by adding a letter suffix, e.g., 102a and 102b can each be an electromechanical component of the same type. If the first reference numeral is used only once in the specification, it is intended to be a generic reference to all like components of that type regardless of the letter suffix. DETAILED DESCRIPTION

[0020] As the number of formation units of 3D NAND structures grows, the aspect ratio of memory holes and other structures sometimes increases dramatically. During 3D NAND processing, stacks of placeholder layers and dielectric materials can form inter-electrode dielectric layers or inter-poly dielectric (“IPD”) layers. These placeholder layers can be performed for various operations that place structures before the material is completely removed and replaced with metal. IPD layers are often formed over conductor layers, such as polysilicon. When forming memory holes, the hole diameter can extend through all of the alternating layers of material before entering the polysilicon or other material substrate. Subsequent processing can form stepped structures for contacts and can also exhume the placeholder material laterally.

[0021] A reactive ion etch (“RIE”) operation can be performed to produce high aspect ratio memory holes. RIE processing often involves a combination of chemical and physical removal of alternating layers, which can form a carbon polymer layer on the sidewalls during etching and can protect the layer from further etching. As one non-limiting example, where the alternating layers can include silicon oxide and silicon nitride, the silicon oxide can be removed to a greater extent by physical bombardment of the layers during RIE, and the silicon nitride can be removed to a greater extent by chemical reaction of the RIE precursor with the nitride material.

[0022] Conventional techniques can struggle with uniformity and control during memory hole formation due to material differences between the two layer types and the RIE process and materials. The present technology overcomes these issues by adjusting material properties prior to the RIE process, which can accommodate or limit one or more challenges that might otherwise occur. While the remaining disclosure will routinely identify specific materials and semiconductor structures with which the disclosed technology is utilized, it will be readily understood that the systems, methods, and materials are equally applicable to many other structures that can benefit from aspects of the present technology. Thus, the technology should not be considered as limited to use only with 3D NAND processing or materials. Further, while an exemplary chamber is described to provide a basis for the present technology, it should be understood that the present technology can be applied to nearly any semiconductor processing chamber that can allow for the described operations.

[0023] Figure 1 A cross-sectional view of an exemplary processing chamber system 100 according to some embodiments of the present technology is illustrated. According to some embodiments of the present technology, the chamber 100 can be used to form a film layer, although it should be understood that the methods can similarly be performed within any chamber in which film formation can occur. The processing chamber 100 can include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled with the chamber body 102 and enclosing the substrate support 104 in a processing volume 120. A substrate 103 can be provided to the processing volume 120 via an opening 126, which can conventionally be sealed for processing by using a slit valve or door. The substrate 103 can rest on a surface 105 of the substrate support during processing. The substrate support 104 can be rotated along an axis 147 as indicated by arrow 145, with a stem 144 of the substrate support 104 being located on the axis 147. Alternatively, the substrate support 104 can be lifted for rotation as desired during deposition processing.

[0024] A plasma profile modifier 111 can be disposed in the processing chamber 100 to control the plasma distribution across a substrate 103 disposed on the substrate support 104. The plasma profile modifier 111 can include a first electrode 108, which can be disposed adjacent to the chamber body 102 and can be separate from other components of the lid assembly 106. The first electrode 108 can be part of the lid assembly 106, or can be a separate sidewall electrode. The first electrode 108 can be a ring or ring-like member, and can be a ring electrode. The first electrode 108 can be a continuous ring around the circumference of the processing chamber 100 that encircles the processing volume 120, or can be discontinuous at selected locations if desired. The first electrode 108 can also be a perforated electrode, such as a perforated ring or mesh electrode, or can be a plate electrode, such as a second gas distributor.

[0025] One or more isolators 110a, 110b can be a dielectric material, such as a ceramic or a metal oxide, such as aluminum oxide and / or aluminum nitride, which can contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and from the chamber body 102. The gas distributor 112 can define an aperture 118 for distributing process precursors into the processing volume 120. The gas distributor 112 can be coupled with a first electrical power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that can be coupled with a process chamber. In some embodiments, the first electrical power source 142 can be an RF power source.

[0026] The gas distributor 112 can be an electrically conductive gas distributor or a non- conductive gas distributor. The gas distributor 112 can also be formed of electrically conductive and non-conductive components. For example, the body of the gas distributor 112 can be electrically conductive, while the faceplate of the gas distributor 112 can be non-conductive. The gas distributor 112 can be electrically powered, for example, by the first electrical power source 142 shown, or in some embodiments, the gas distributor 112 can be grounded. Figure 1

[0027] The first electrode 108 can be coupled with a first tuning circuit 128, which can control a ground path of the process chamber 100. The first tuning circuit 128 can include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 can be or can include a variable capacitor or other circuit component. The first tuning circuit 128 can be or can include one or more inductors 132. The first tuning circuit 128 can be any circuit that achieves a variable or controllable impedance under plasma conditions present in the processing volume 120 during processing. In some embodiments shown, the first tuning circuit 128 can include a first circuit branch and a second circuit branch coupled in parallel between a ground and the first electronic sensor 130. The first circuit branch can include a first inductor 132A. The second circuit branch can include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and a node connecting both the first circuit branch and the second circuit branch to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor, and can be coupled with the first electronic controller 134, which can provide a degree of closed loop control over plasma conditions within the processing volume 120.

[0028] ​The second electrode 122 can be coupled with the substrate support 104. The second electrode 122 can be embedded within the substrate support 104 or coupled with a surface of the substrate support 104. The second electrode 122 can be a plate, a perforated plate, a mesh, a wire mesh, or any other distributed arrangement of conductive elements. The second electrode 122 can be a tuning electrode and can be coupled with a second tuning circuit 136 through a conduit 146, such as a cable having a selected resistance, for example 50 ohms, disposed in a stem 144 of the substrate support 104. The second tuning circuit 136 can have a second electronic sensor 138 and a second electronic controller 140, which can be a second variable capacitor. The second electronic sensor 138 can be a voltage or current sensor and can be coupled with the second electronic controller 140 to provide further control over plasma conditions in the processing volume 120.

[0029] The third electrode 124 can be a bias electrode and / or an electrostatic chucking electrode, which can be coupled with the substrate support 104. The third electrode can be coupled with a second electrical power source 150 via a filter 148, which can be an impedance matching circuit. The second electrical power source 150 can be DC power, pulsed DC power, RF bias power, pulsed RF source, or a bias power, or a combination of these or other power sources. In some embodiments, the second electrical power source 150 can be RF bias power.

[0030] Figure 1 The lid assembly 106 and substrate support 104 can be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 can provide real-time control over plasma conditions in the processing volume 120. A substrate 103 can be disposed on the substrate support 104 and processing gas can be flowed through the lid assembly 106 by using the inlet 114 according to any desired flow plan. The gas can exit the processing chamber 100 via the outlet 152. Electrical power can be coupled with the gas distributor 112 to establish a plasma in the processing volume 120. In some embodiments, the substrate can be subjected to an electrical bias by using the third electrode 124.

[0031] When a plasma is ignited in the processing volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. The flow properties of the ground paths represented by the two tuning circuits 128 and 136 can then be adjusted using the electronic controllers 134, 140. Set points can be communicated to the first and second tuning circuits 128, 136 to provide independent control of deposition rate and plasma density uniformity from center to edge. In embodiments where the electronic controllers can each be variable capacitors, the electronic sensors can adjust the variable capacitors to independently maximize deposition rate and minimize thickness non-uniformity.

[0032] Each of the tuning circuits 128, 136 can have a variable impedance that can be adjusted using the respective electronic controllers 134, 140. In the case where the electronic controllers 134, 140 are variable capacitors, the range of capacitance of each variable capacitor can be selected as well as the inductance of the first and second inductors 132A, 132B to provide a range of impedances. This range can depend on the frequency and voltage characteristics of the plasma, which can have a minimum value within the range of capacitance of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 can be high, resulting in a plasma shape with a minimum over-the-air or lateral coverage over the substrate support. When the capacitance of the first electronic controller 134 is near the value that minimizes the impedance of the first tuning circuit 128, the over-the-air coverage of the plasma can grow to a maximum, effectively covering the entire working area of the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape can shrink from the chamber walls and the over-the-air coverage of the substrate support can decrease. The second electronic controller 140 can have a similar effect, with the capacitance of the second electronic controller 140 can be varied to increase and decrease the over-the-air coverage of the plasma over the substrate support.

[0033] The electronic sensors 130, 138 can be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point of current or voltage can be installed in each sensor, and the sensor can be provided with control software that determines adjustments to each respective electronic controller 134, 140 to minimize deviation from the set point. Thus, the plasma shape can be selected and dynamically controlled during processing. It should be understood that although the foregoing discussion is based on electronic controllers 134, 140 that can be variable capacitors, any electronic component with an adjustable characteristic can be used to provide an adjustable impedance for the tuning circuits 128 and 136.

[0034] As previously described, a reactive ion etch ("RIE") process can create a number of structural effects through a stack of semiconductor materials that, if not controlled, can result in a defective device. Figures 2A to 2D Some of the structural problems that can occur during via formation are illustrated. For example, Figure 2AAn etching effect, which can be referred to as notching, can be illustrated that can create a sloped defect in the silicon nitride layer. The figure includes a structure 200 having a stack 205 that can include alternating layers of material of multiple portions 210 formed over a substrate 215. Although three portions 210a, 210b, 210c are illustrated, it should be understood that the stack 205 can include any number of portions encompassed by embodiments of the technology. Each portion 210 can illustrate four alternating layers of silicon oxide material 212 and silicon nitride material 214. Although four layers are illustrated, it should be understood that any number of layers can be included in each portion and throughout the stack. Additionally, although illustrated in a particular orientation with silicon nitride as the bottom layer, it should be understood that the layers can be reversed and can begin with a layer of silicon oxide.

[0035] As described above, during the RIE process, etching of the silicon oxide material can occur to a greater degree due to ion bombardment, while etching of the silicon nitride material can occur to a greater degree due to chemical reactions between the RIE precursor and the nitride material. Thus, the silicon oxide etching can be controlled by controlling the RIE beam, and oxides disposed laterally outward (which in embodiments can include radially) from the RIE beam can not be etched. However, the nitride material can be etched based on contact and chemical reactions with precursors or effluents of the RIE beam. In some embodiments, silicon nitride can also etch slower than silicon oxide. Because of the hydrogen or other materials associated with the silicon nitride, interaction with effluents of the RIE (which can include carbon) can create an amount of polymerized material that can passivate or protect the sidewalls of the memory hole to limit lateral etching.

[0036] However, at the interface between the oxide material and the underlying silicon nitride material layer, the amount of polymerization can be minimized. Additionally, the etch rate of the silicon nitride can be different than the etch rate of the silicon oxide, which can create an increased exposure or effluent residence time at the nitride layer. Prior to the formation of the protective polymerized material, the effluents can react with the exposed nitride, as at the transition between the oxide layer and the nitride layer, increasing the lateral etching of the material. This lateral etching can taper as the polymer buildup occurs, and can form a notch 220 around the leading edge in the direction of etching of the silicon nitride material. In some embodiments, this notch can hinder or affect the formation of subsequent layers or materials, and can increase the diameter or critical dimension of the memory hole.

[0037] Figure 2BExamples of striations that can affect control of memory hole formation can be illustrated in both vertical cross-section 230 and horizontal cross-section 240. Striations can occur when a certain amount of lateral etching occurs through the structure layers in succession. For example, in a sense, each layer can act as a kind of mask for the layer below. If a lateral defect is formed in the overburden, this can expose a portion of the layer below that would otherwise be preserved, which can be removed. These defects can continue to form, which can continue to increase the critical dimension and cause the memory hole to flare at one or more locations through the stack.

[0038] Figure 2C Examples of stress effects can be illustrated that can create misregistration of the memory hole through the stack. For example, Figure 2C A detailed view of a single portion 250 of the stack can be drawn prior to formation of a subsequent stack of overburden covering the illustrated alternating layers. The number of alternating layers illustrated is for illustrative purposes only and is not intended to limit the number of layers in any particular portion of the stack. A memory hole can be created through each portion of the stack prior to formation of the overburden covering portion of the stack. This process can affect the properties of the pillars, which can be more susceptible to stress effects. For example, if a subsequent process exposes the pillars to high temperatures, a certain amount of outgassing can occur. Continuing this example, which is not intended to limit the present technology, silicon nitride can contain a certain amount of hydrogen depending on the precursors utilized, such as silane in one non-limiting example. When exposed to temperatures above a few hundred degrees Celsius, outgassing can occur, which can create stress within each pillar and can cause the structure as illustrated to deform. When an additional stack is formed over the etched stack, the formation process can occur at a temperature that causes outgassing, which can create a shift in the underlying memory hole, which can create misregistration when the overburden memory hole is formed to connect with the underlying memory hole.

[0039] Figure 2DAn example of bowing 260 or critical dimension expansion that can be illustrated within a structure through which RIE can be performed to create a memory hole. Bowing can occur anywhere throughout the structure, and can be caused by a number of issues. For example, bowing can be caused by limited passivation or polymerization on the sidewalls, which can cause a certain amount of lateral etching to occur. Bowing can also occur due to changes in the hardmask material or other structural features. For example, if the edge of the hardmask 265 can be eroded during the RIE process, ions can be projected into the feature or memory hole at a different direction or angle than perpendicular to the substrate, which can create additional lateral etching within certain areas of the structure until the hardmask taper is removed or etched away. Thus, a number of issues can occur during the RIE process, which can affect the memory hole structure in a number of ways. The present technology can include one or more adjustments to the material properties of the stacked layers, which can accommodate, offset, or prevent one or more of the challenges described.

[0040] The present technology can adjust the material properties of one or more layers or materials within an example stack, which can target one or more of the challenges described above. Following a general description of a method of forming one or more portions of a stack of semiconductor material layers, adjustments will be discussed that can be combined or performed in any variation or combination to improve memory hole formation. The chamber 100 previously discussed can be used to perform example methods including the formation methods. Turning to Figure 3 , Figure 3 Example operations in a method 300 for forming a semiconductor structure according to embodiments of the present technology are illustrated. Prior to the first operations of the method, the substrate can be treated in one or more ways prior to being placed within a processing region of a chamber in which the method 300 can be performed. Some or all of the operations can be performed in a chamber or system tool as previously described, or can be performed in a different chamber on the same system tool that can include a chamber in which the operations of the method 300 can be performed.

[0041] The method 300 can include a number of optional operations as illustrated, which can or can not be specifically relevant to some embodiments of the method according to the present technology. For example, a number of operations are described in order to provide a greater range of structural formation, but are not critical to the technology, or can be performed by alternative methods as will be further discussed below. The method 300 describes Figures 4A to 4B The operations schematically illustrated in FIG. 4 will be described in connection with the illustration of the operations of the method 300. It should be understood that FIG. 4 illustrates only a partial schematic, and that the substrate can include any number of structural portions having aspects as illustrated, as well as alternative structural aspects that can still benefit from the operations of the present technology.

[0042] Structure 400 can illustrate a partial view of a stack of alternating layers of materials that can be used in 3D NAND memory formation in some embodiments. The alternating layers of materials can be produced by a number of methods, including plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal enhanced chemical vapor deposition, or any other formation technique. In some embodiments, plasma enhanced chemical vapor deposition can be performed in a processing chamber, such as processing chamber 100 previously described. Although the remainder of the disclosure will discuss a stack of alternating layers of silicon oxide and silicon nitride, embodiments of the present technology can use a combination of different materials, such as silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials. Although method 300 will discuss forming silicon oxide and then forming silicon nitride, the order of formation can be reversed in embodiments similarly encompassed by the present technology. Additionally, according to embodiments of the present technology, any number of layers of materials can be produced in the stack or any portion of any stack, and different portions of the stack can include more, fewer, or a similar number of layers of any other portion of the stack.

[0043] Method 300 can include forming a layer of silicon oxide on a substrate at operation 305. The formation can be performed with a silicon-containing precursor and an oxygen-containing precursor. The method can also include forming a layer of silicon nitride over the layer of silicon oxide at operation 310. The formation can be performed with a silicon-containing precursor and a nitrogen-containing precursor. These operations can be repeated any number of times until a predetermined number of pairs of layers that can make up a stack of layers can be formed. Figure 4A Structure 400 is illustrated, which includes a substrate 405 having a stack 410 of alternating layers of silicon oxide and silicon nitride. The illustrated stack 410 can include a plurality of portions 415, each portion 415 can include at least one layer of silicon oxide material 417 and at least one layer of silicon nitride material 419. Each portion can also include a plurality of pairs of layers, including greater than or about 2 pairs, greater than or about 10 pairs, greater than or about 50 pairs, greater than or about 100 pairs, or more pairs of layers. Any particular number of pairs encompassed by any of these recited ranges is understood as specifically described herein. Although three portions 415a, 415b, and 415c are illustrated, more or fewer portions can be included according to some embodiments of the present technology.

[0044] In some embodiments, the plurality of portions (including all portions) can be formed during operations 305 and 310, but in some embodiments, the portions can be produced in multiple operations. For example, and as will be further described below, one or more optional operations can be performed between forming the stacked overcoat portions, or adjustments as will be described below can occur between any of the portions, which can be represented as different portions. For example, at optional operation 315, a high temperature anneal can be performed prior to forming the stacked second portion. Optional operation 315 can also include forming the first portion of the memory hole, as well as adjustments to the precursors as will be described below. The second portion of the stack can be formed by forming at least one layer of silicon oxide material at optional operation 320 and at least one layer of silicon nitride material at optional operation 325, and can be repeated to produce any number of pairs of layers similar to the first portion described above.

[0045] Additional optional operation 330 can include additional high temperature annealing or forming the second portion of the memory hole, as well as further adjustments to the precursors. The third portion of the stack can be formed by forming at least one layer of silicon oxide material at optional operation 335 and at least one layer of silicon nitride material at optional operation 340, and can be repeated to produce any number of pairs of layers that can be more or less than the number of pairs of the first portion or the second portion. In some embodiments of the present technology, any of the silicon oxide materials or silicon nitride materials described below can include or be any of the layers of any of the portions of the stack.

[0046] A mask material 420 can be formed over any of the portions of the stack prior to forming a portion of the memory hole or other features through the structure. Features of structures according to the present technology can be characterized by any aspect ratio or height to width ratio of the structure, but in some embodiments, the features of the material can be characterized by a greater aspect ratio, which can increase the impact on aspects of the resulting structure as described previously. For example, in some embodiments, the aspect ratio of exemplary structures, such as the depth of the aperture or memory hole relative to the cross-sectional diameter, can be greater than or about 10: 1, greater than or about 20: 1, greater than or about 30: 1, greater than or about 40: 1, greater than or about 50: 1, or greater. These high aspect ratios can preclude many conventional etching operations, or produce or exacerbate any of the problems described previously.

[0047] In embodiments, the substrate 405 can have a substantially planar surface or an uneven surface. The substrate can be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or non-patterned wafers, silicon on insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 405 can have various dimensions, such as a 200 mm or 300 mm wafer diameter, as well as rectangular or square panels. Silicon-containing precursors that can be used during silicon oxide formation or silicon nitride formation can include, but are not limited to, silane (SiH4), disilane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethoxysilane (TEOS), and any other silicon-containing precursors that can be used in silicon-containing film formation. Oxygen-containing precursors used in any of the operations described throughout the present technology can include O2, N2O, NO2, O3, H2O, and any other oxygen-containing precursors that can be used in silicon oxide film formation, silicon oxynitride film formation, or other film formation. Nitrogen-containing precursors used in any of the operations can include N2, N2O, NO2, NH3, N2H2, and any other nitrogen-containing precursors that can be used in silicon nitride film formation. In any of the formation operations, one or more additional precursors can be included, such as inert precursors, which can include Ar, He, Xe, Kr, nitrogen, hydrogen, or other precursors.

[0048] As previously described, notches can occur in the silicon nitride layer during via formation due to the lateral diffusion of the reactive species through the structure before sufficient polymerization reactions have occurred. However, in some embodiments, the formation of the silicon nitride layer can include incorporating an amount of oxygen. As described above, in some embodiments, the RIE process can occur to a greater extent with oxygen due to bombardment, and by incorporating oxygen into the nitride layer to a controlled amount, notches can be reduced or removed. For example, during the formation of one or more silicon nitride layers in any portion of the stack, an oxygen-containing precursor can be flowed with a nitrogen-containing precursor and / or a silicon-containing precursor to produce a film incorporating an amount of oxygen. The oxygen-containing precursor can be any of the oxygen-containing precursors described above, and in some embodiments can be the same oxygen-containing precursor used in forming the silicon oxide material. By using the same precursors in some embodiments, fewer modifications can be made during the formation of the stack, which can reduce wait times.

[0049] In some embodiments, one or more of the layers of silicon nitride material can include greater than or about 5 atomic % oxygen, and can include greater than or about 10 atomic % oxygen, greater than or about 15 atomic % oxygen, greater than or about 20 atomic % oxygen, greater than or about 25 atomic % oxygen, greater than or about 30 atomic % oxygen, or more. Additional incorporation of oxygen can affect downstream processing, such as digging of the silicon nitride layer, and thus in some embodiments, the amount of oxygen can be maintained below or about 30 atomic % oxygen, below or about 25 atomic % oxygen, below or about 20 atomic % oxygen, or lower, which can help to selectively remove the nitride material during subsequent operations without damaging the silicon oxide material. In some embodiments, the layers of silicon nitride material can maintain an amount of nitrogen above a threshold, such as greater than or about 20 atomic %, and can result in a silicon nitride material characterized by an amount of nitrogen greater than or about 25 atomic %, greater than or about 30 atomic %, greater than or about 35 atomic %, greater than or about 40 atomic %, greater than or about 45 atomic %, or more.

[0050] As noted above, a notch can occur at the leading edge of the silicon nitride material in the direction of etching toward the substrate. In some embodiments, the incorporation of oxygen can be tailored to accommodate this effect. For example, in some embodiments, the formation of the silicon nitride material can include forming a bilayer of silicon nitride and silicon oxynitride for each layer of silicon nitride. For example, a silicon-containing precursor and a nitrogen-containing precursor can be flowed to produce an amount of silicon nitride, and then an oxygen-containing precursor can be added to the flow, which can include maintaining or adjusting the flow rate of the silicon-containing precursor and / or the nitrogen-containing precursor. Each layer of the bilayer can constitute any percentage of the bilayer between about 10% and about 90% of the thickness of the bilayer.

[0051] Regardless of whether the oxygen-containing precursor can be added initially during the formation of the silicon nitride material, or at some time after the initial formation, the flow rate of the oxygen-containing precursor can remain constant, can decrease, or can increase during the formation of the layer. For example, a gradient of oxygen concentration from an incorporation of about 0 atomic % oxygen up to any of the previously mentioned incorporation amounts can be produced within the silicon nitride material. By starting and then adjusting the flow rate of the oxygen-containing precursor, the silicon nitride material can include a gradient of incorporation. For example, the flow rate of the oxygen-containing precursor can increase during the formation of a layer or bilayer of silicon nitride material, so that a portion of the silicon nitride material at the interface overlying the silicon oxide material can be characterized by an increased amount of oxygen over an underlying portion of the silicon nitride material. Thus, in some embodiments, the notch effect can be reduced where it is most likely to occur, while maintaining more nitride incorporation throughout the film.

[0052] In some embodiments, the amount of oxygen incorporation into one or more layers of silicon nitride material can also be adjusted between different portions of the stack, and any layer in any portion can be characterized by any of the amounts of oxygen incorporation described above, or can maintain substantially no oxygen incorporation. For example, some striation effects and / or contour variations can occur in a second portion of the stack, such as in portion 415b between first portion 415a and third portion 415c. By adjusting the amount of oxygen incorporation in the silicon nitride in this portion of the stack, these problems can be limited or resolved. For example, some bowing and striations can occur due to the radical effluents of the RIE process etching the silicon nitride laterally, which can expose additional silicon oxide and increase the amount of etching of those materials, increasing the impact. By limiting the impact on the nitride material, the impact on the oxide material can also be reduced, improving these problems as well as the uniformity of memory hole formation. By increasing the oxygen incorporation in the nitride layer in the area where striations and / or bowing can occur, the resistance to lateral etching can be increased, which can limit the impact of these problems.

[0053] Similarly, memory hole alignment problems can be improved, such as by increasing the oxygen concentration in the nitride material in lower portions of the stack. Silicon oxide can provide improved control over stress effects by reducing the amount of hydrogen in the film, or otherwise provide more control over stress effects, which can limit the distortions described previously. Thus, in some embodiments, a first portion of the stack can include an increased oxygen concentration in the nitride layer, which can reduce stress effects due to outgassing. An optional anneal can also be performed as previously described, which can increase the temperature of the formed film with or without an increased oxygen concentration in the nitride material, and which can increase outgassing prior to forming additional portions of the stack. The anneal can include a process that increases the temperature of the first portion of the stack to greater than or about 500°C, and the temperature of the first portion of the stack can be increased to greater than or about 550°C, greater than or about 600°C, greater than or about 650°C, greater than or about 700°C, greater than or about 750°C, greater than or about 800°C, greater than or about 850°C, greater than or about 900°C, or higher. For example, when the temperature exceeds about 650°C, a significant amount of outgassing can occur to limit distortion of the structure, providing improved alignment between portions of the memory holes.

[0054] By including an amount of oxygen within the nitride material, notches can be reduced or removed in some embodiments of the present technology. Figure 4BA close-up view of the underlying layers of silicon nitride material 425 and the overlying portions of silicon oxide material 427, in which notches 430 can be formed. The notches can be characterized by a distance of intrusion A laterally at the interface between the silicon nitride layer and the overlying silicon oxide material. The silicon nitride material layer can also be characterized by a thickness B. In some embodiments, any particular layer of silicon nitride material can include notches with an intrusion distance A that is less than or about 100% of the distance corresponding to the thickness B. In some embodiments, the distance A can be less than or about 75% of the distance B, the distance A can be less than or about 50% of the distance B, the distance A can be less than or about 40% of the distance B, the distance A can be less than or about 30% of the distance B, the distance A can be less than or about 20% of the distance B, the distance A can be less than or about 10% of the distance B, the distance A can be less than or about 5% of the distance B, the distance A can be less than or about 1% of the distance B, or the distance A can be zero, where no notches can be formed in the layer.

[0055] Additional adjustments can be performed to accommodate or adjust the effects described previously, and any of these adjustments can be combined together or with any other operations or incorporations discussed elsewhere. For example, the silicon nitride material can be characterized by a refractive index, which can be adjusted by adjusting the film formation material or conditions. For example, in some embodiments, increasing the refractive index of the silicon nitride material can decrease the lateral etch rate or the overall dry etch rate. Thus, in some embodiments, the areas where bending or striations can occur can be modified by forming a silicon nitride layer characterized by a refractive index that is increased over other material layers. For example, any silicon nitride material can be characterized by a refractive index between about 1.7 and about 2.3. In some embodiments, the silicon nitride material in the lower portions of the structure, such as portion 415a, can be characterized by a refractive index that is less than the silicon nitride material in portions of the structure that are further from the substrate. Additionally, the silicon nitride material in the middle portions of the structure, such as portion 415b, can be characterized by a refractive index that is higher than the silicon nitride material both above and below. Thus, in one non-limiting example, a stack, such as stack 410, can include a portion in which the silicon nitride material in the third portion 415c can be characterized by a refractive index that is higher than the material in the first portion 415a and the silicon nitride material in the second portion 415b can be characterized by a refractive index that is higher than the material in the third portion 415c or the first portion 415a. Any number of other modifications to adjust the refractive index can be similarly performed to adjust the etching characteristics in various areas of the stack.

[0056] In some embodiments of the technology, the dopant concentration can also be adjusted in one or more layers of silicon nitride material. For example, the silicon nitride can be doped with a material including phosphorous, boron, oxygen, or other materials that can increase the etch rate of the silicon nitride material, which can improve etching at locations where tapering or narrowing can occur, such as in a first portion of the stack. These dopants can have an affinity for certain materials in the RIE chemistry, which can increase etching through the portion. Thus, incorporating from about 0.01% to about 5% or more of these dopants can increase etching of the material. Similarly, silicon nitride with increased carbon incorporation can be formed, which can decrease etching in certain portions. Many RIE etchants can include halocarbon compounds, such as chlorocarbon compounds, fluorocarbon compounds, or fluorochlorocarbon compounds, which can decrease etching of films with increased carbon incorporation relative to films with lower carbon content. Thus, as one non-limiting example, one or more layers or one or more portions of the stack can include an increased carbon concentration, such as between about 1% and about 10%, to control etching. For example, in some embodiments, the layer of silicon nitride material in the second portion 415b can have an increased carbon concentration relative to the first portion 415a.

[0057] In some embodiments, the ratio of nitrogen to silicon within a layer of silicon nitride material can also be adjusted to affect the etch rate. For example, by increasing the ratio of nitrogen to silicon, the etch rate of the material can be increased, and by decreasing the ratio of nitrogen to silicon, the etch rate of the material can be decreased. Thus, in some embodiments, one or more layers of silicon nitride material can be characterized by an increased ratio of nitrogen to silicon relative to one or more other layers (such as, for example, in a first portion), and / or one or more layers of silicon nitride material can be characterized by a decreased ratio of nitrogen to silicon relative to one or more other layers (such as, for example, in a second portion). An increased ratio of nitrogen to silicon can be greater than or about 1.3, and can be greater than or about 1.4, greater than or about 1.5, greater than or about 1.6, or higher. A decreased ratio of nitrogen to silicon can be less than or about 1.3, and can be less than or about 1.2, less than or about 1.1, less than or about 1.0, or less.

[0058] In some embodiments, the layers of silicon oxide material can also be adjusted, which can also affect the etch rate and profile through the stack. For example, in portions that can promote increased etching relative to other layers or portions, such as in the first portion, the silicon containing precursor can be adjusted to have increased hydrogen bonding to silicon. As one non-limiting example, while TEOS can be used to form the layers of silicon oxide material of the second portion and / or the layers of the third portion, silane or disilane can be used to form the layers of silicon oxide material of the first portion, among other precursors with higher amounts of silicon hydrogen bonding. For portions that can promote decreased etching, the opposite can be performed with the precursors, and precursors with less silicon hydrogen bonding can be used, such as in the second portion of the stack. Additionally, due to reasons described previously with respect to the etchant used in the RIE process, precursors containing additional carbon can be used, or carbon incorporation within the silicon oxide film can be increased.

[0059] By utilizing one or more of the described processes, improved formation of memory holes can be provided, which can limit effects such as notching, and improve uniformity of the profile through the memory hole. For example, in some embodiments, a feature through the layers or portions of the stack can be characterized by a variation in diameter of the memory hole through the stack of less than or about 200%, and a feature can be characterized by a variation in diameter of the memory hole through the stack of less than or about 150%, less than or about 100%, less than or about 90%, less than or about 80%, less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, less than or about 20%, less than or about 10%, or less. Thus, the present technology can provide improved manufacturing, which can result in more uniform stack structures as compared to conventional techniques.

[0060] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments can be practiced without some or all of these details.

[0061] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Additionally, many known processes and components are not described in detail herein because they are commonly known to those skilled in the art. Accordingly, the above description should not be taken as limiting the scope of the present technology. Additionally, methods or processes can be described as sequential or in steps, but it is to be understood that operations can be performed concurrently, or in different orders than listed.

[0062] When a range of values is provided, it is understood that each intervening value, to the minimum resolution of the measurement unit, between the upper and lower limits of that range is also specifically disclosed. Any narrower ranges given of either the specified ranges also are specifically disclosed. These smaller ranges are obtained by dividing the total range by dividing the number of units between the upper and lower limits of that range. All ranges and sub-ranges are equally disclosed herein as specifically set forth. The ranges and sub-ranges are equally applied to each listed endpoint. The endpoints of the ranges and sub-ranges are included in the ranges and sub-ranges. Unless expressly indicated, the use of "between" in the context of a range should not be interpreted as requiring an end point to end in the middle of a unit (e.g., between 1 and 3 should not be interpreted as including 1.5).

[0063] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural reference unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents of such layer as known to those skilled in the art, and so forth.

[0064] Further, as used herein and in the appended claims, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including" are intended to be open-ended and non-limiting. That is, use of such terms indicates that the named element can be present, but not to the exclusion of one or more other elements that are not specifically recited.

Claims

1. A method of forming a semiconductor structure, the method comprising: forming a silicon oxide layer from a silicon-containing precursor and an oxygen- containing precursor; forming a silicon nitride layer from a silicon-containing precursor, a nitrogen- containing precursor, and an oxygen-containing precursor, wherein the silicon nitride layer is characterized by an oxygen concentration greater than or equal to 5 atomic percent; repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride; and forming one or more features through the stack of alternating layers of silicon oxide and silicon nitride, wherein lateral removal of the silicon nitride layer at an interface of the silicon nitride layer and an overlying silicon oxide layer extends a distance less than or equal to 20 percent of a distance corresponding to a thickness of the silicon nitride layer.

2. The method of forming a semiconductor structure of claim 1, wherein the oxygen- containing precursor of the forming a silicon oxide layer is the same precursor as the oxygen- containing precursor of the forming a silicon nitride layer.

3. The method of forming a semiconductor structure of claim 1, wherein the stack of alternating layers includes a first portion of the stack and a second portion of the stack overlying the first portion of the stack, the first portion of the stack including the silicon oxide layers and the silicon nitride layers, and wherein producing the second portion of the stack comprises: forming a silicon nitride layer from the silicon-containing precursor and the nitrogen- containing precursor and an oxygen-containing precursor, wherein the silicon nitride layer is characterized by an oxygen concentration different than the oxygen concentration of the silicon nitride layers in the first portion of the stack.

4. The method of forming a semiconductor structure of claim 1, wherein the oxygen concentration of the silicon nitride layer is between 10 atomic percent and 30 atomic percent, and wherein a nitrogen atomic percentage is greater than or equal to 30 atomic percent.

5. The method of forming a semiconductor structure of claim 1, wherein forming the silicon nitride layer comprises: flowing the silicon-containing precursor and the nitrogen-containing precursor into a substrate processing region, forming an amount of silicon nitride, and adding the oxygen-containing precursor while continuing to form silicon nitride.

6. The method of forming a semiconductor structure of claim 5, wherein the oxygen- containing precursor is flowed at a constant flow rate, and wherein the formed silicon nitride layer includes a bilayer of substantially oxygen-free silicon nitride and silicon nitride characterized by an oxygen concentration greater than or equal to 5 atomic percent.

7. The method of forming a semiconductor structure of claim 5, wherein during the adding of the oxygen-containing precursor, the oxygen-containing precursor is flowed at an increasing flow rate, and wherein the formed silicon nitride layer includes a gradient in oxygen concentration throughout the silicon nitride layer.

8. The method of forming a semiconductor structure of claim 1, wherein the lateral removal of the silicon nitride layer at the interface of the silicon nitride layer and the overlying silicon oxide layer extends a distance less than or equal to 10 percent of the distance corresponding to the thickness of the silicon nitride layer.

9. A semiconductor structure comprising: a stack of layers overlying a semiconductor substrate, the stack of layers including: a first portion of layers including alternating layers of silicon oxide material and silicon nitride material, a second portion of layers overlying the first portion of layers, the second portion of layers including a first layer of silicon oxide material and a second layer of silicon nitride material, wherein the first layer of silicon oxide material is characterized by an oxygen concentration greater than or equal to 5 atomic percent, and wherein the second layer of silicon nitride material is characterized by an oxygen concentration less than the oxygen concentration of the first layer of silicon oxide material. a second portion of layers overlying the first portion of layers, the second portion of layers comprising alternating layers of silicon oxide material and silicon nitride material, a third portion of layers overlying the second portion of layers, the third portion of layers comprising alternating layers of silicon oxide material and silicon nitride material, and one or more apertures formed through the stack of layers to the substrate, wherein a lateral notch in each of the individual layers of silicon nitride material at an interface of an individual layer of silicon nitride material and an overlying layer of silicon oxide material extends a distance that is less than or equal to 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material, wherein the silicon nitride material of at least one of the first portion of layers, the second portion of layers, or the third portion of layers comprises an oxygen concentration of at least 5 atomic percent, and wherein the oxygen concentration of the silicon nitride material throughout at least one of the first portion of layers, the second portion of layers, or the third portion of layers increases through a thickness of each of the layers of silicon nitride material in a direction toward the interface of the individual layer of silicon nitride material and the overlying layer of silicon oxide material.

10. The semiconductor structure of claim 9, wherein a refractive index of the silicon nitride material of the second portion of layers is higher than the refractive index of the silicon nitride material of the first portion of layers and the silicon nitride material of the third portion of layers.

11. The semiconductor structure of claim 9, wherein the silicon nitride material of the first portion of layers is characterized by a dopant concentration that is higher than the silicon nitride material of the second portion of layers and the third portion of layers.

12. The semiconductor structure of claim 9, wherein the silicon nitride material of the second portion of layers or the silicon nitride material of the third portion of layers is characterized by a carbon concentration that is higher than the silicon nitride material of the first portion of layers.

13. The semiconductor structure of claim 9, wherein the silicon nitride material of the first portion of layers or the silicon nitride material of the second portion of layers is characterized by a ratio of nitrogen to silicon that is greater than the silicon nitride material of the third portion of layers.

14. A method of forming a semiconductor structure, the method comprising: forming a first stack of alternating layers of silicon oxide material and silicon nitride material; annealing the first stack of alternating layers of silicon oxide material and silicon nitride material, wherein the annealing reduces a hydrogen concentration of the silicon nitride material; and forming a second stack of alternating layers of silicon oxide material and silicon nitride material on the annealed first stack of alternating layers of silicon oxide material and silicon nitride material, wherein the silicon nitride material in the second stack of alternating layers is characterized by an oxygen concentration that is greater than or equal to 5 atomic percent, wherein the silicon nitride material in the second stack of alternating layers is characterized by an oxygen concentration that is different than an oxygen concentration of the silicon nitride material in the first stack of alternating layers.

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