Semiconductor structure including buried porous layer for radio frequency applications

Abstract

The present invention relates to a semiconductor structure (10) for radio frequency applications, comprising: a carrier substrate (2) made of silicon and comprising a mesoporous layer (3); a dielectric layer (4) arranged on the mesoporous layer (3); and a surface layer (5) arranged on the dielectric layer (4). The structure (10) is characterized in that: the mesoporous layer (3) comprises hollow pores, the inner walls of which are mostly coated with an oxide, and the mesoporous layer has a thickness between 3 μm and 40 μm and a resistivity of more than 20 kilo-ohm-cm over its entire thickness; the carrier substrate (2) has a resistivity between 0.5 ohm-cm and 4 ohm-cm. The present invention also relates to a method for manufacturing the semiconductor structure (10).

Description

Field of the Invention

[0001] The present invention relates to the field of semiconductor materials for microelectronic components and in particular to an SOI substrate structure comprising a buried mesoporous silicon layer, which is particularly suitable for high-performance radio frequency devices in terms of thermal stability and linearity. Background Art

[0002] Radio frequency (RF) devices are widely used in telecommunications (cellular phones, Wi-Fi, Bluetooth, etc.). These devices are manufactured on substrates in the form of wafers, which primarily serve as a support for device fabrication. However, the increasing integration density and expected performance of these RF devices has led to an increasingly close connection between their performance and the properties of the substrates on which they are formed.

[0003] As an example of device / substrate coupling, the electromagnetic field generated by a high-frequency signal propagating through an RF device penetrates into the bulk of the substrate and interacts with any charge carriers found there. This leads to nonlinear distortion (harmonics) in the signal, wasteful consumption of some of the signal's power through insertion loss, and possible crosstalk between devices.

[0004] Therefore, in most applications involving the transmission or reception of radio frequency signals (10 MHz to 100 GHz), RF device manufacturing requires substrates that meet an increasingly demanding set of specifications, particularly those resulting from the evolution of mobile phone standards (2G, 3G, LTE, LTE Advanced, LTE Advanced PRO, etc.). In particular, the properties of the materials used for the substrate must provide:

[0005] - low insertion loss (low attenuation of the signal) and good linearity (low distortion of the signal, the cause of harmonics), typically achieved by an effective resistivity exceeding 1000 ohm·cm over the entire frequency range;

[0006] - The stability of the aforementioned properties over temperature, especially within the operating range of RF devices [-40°C; 150°C];

[0007] - Low capacitive coupling between the active layer and the carrier substrate, typically through a dielectric constant equal to or lower than silicon (ε silicium =11.7) to achieve the dielectric constant;

[0008] - Of course, good mechanical strength, compatible with the production of microelectronic devices.

[0009] Furthermore, to meet the high-volume demands, the substrate must be compatible with the semiconductor industry, particularly with silicon CMOS manufacturing lines. Furthermore, it must be cost-competitive in order to be adopted in high-volume market applications, particularly in telecommunications (cellular phones, Wi-Fi connectivity, Bluetooth, etc.).

[0010] Radio frequency (RF) devices such as antenna adapters and switches, power amplifiers, low noise amplifiers or even passive (R, L, C) components can be manufactured on various types of substrates.

[0011] High-resistivity silicon-based substrates are known, comprising a carrier substrate, a trapping layer disposed on the carrier substrate, a dielectric layer disposed on the trapping layer, and an active semiconductor layer disposed on the dielectric layer. The carrier substrate typically has a resistivity exceeding 1 kiloohm·cm. The trapping layer may comprise undoped polysilicon. Combining a high-resistivity carrier substrate with a trapping layer according to the prior art allows for reducing the aforementioned device / substrate coupling, thereby ensuring good performance of the RF device. In this regard, those skilled in the art will find an overview of the performance of RF devices fabricated on known prior art high-resistivity semiconductor substrates in "Silicon-on-insulator (SOI) Technology, manufacture and applications," sections 10.7 and 10.8, by Oleg Kononchuk and Bich-Yen Nguyen, published by Woodhead Publishing.

[0012] However, the polysilicon trapping layer has the disadvantage of undergoing partial recrystallization during the high-temperature heat treatment step, which results in a decrease in the trap density in this layer. Because the evolving standards requirements in mobile phones place increasingly stringent specifications on RF components, the negative impact on device performance caused by this decrease in trap density is unacceptable for some applications.

[0013] An alternative to the polysilicon capture layer is a porous silicon layer. Document US2017062284 proposes an SOI structure comprising a porous layer under a buried oxide (BOX), but does not specify the thickness range and porosity characteristics that make it possible to achieve the desired level of mechanical strength and RF performance. Application WO2016 / 016532 proposes an SOI structure comprising a very thin mesoporous layer with a thickness of less than 1 μm: this structure provides the required mechanical strength and good RF performance, unlike the porous layers of larger thickness (between 10 μm and 80 μm) conventionally proposed in the prior art, on which subject document WO2016 / 016532 indicates a mechanical strength that is incompatible with some steps in device fabrication and the prerequisites for the carrier of the final working device.

[0014] In order to solve this mechanical strength problem, document WO 2016 / 149113 proposes filling the pores of the porous layer with amorphous or polycrystalline silicon or with silicon oxide.

[0015] Purpose of the Invention

[0016] The present invention provides an alternative to the prior art. In particular, the present invention relates to a SOI structure including a mesoporous silicon layer suitable for high performance radio frequency devices.

[0017] Summary of the Invention

[0018] The present invention relates to a semiconductor structure for radio frequency applications, comprising: a carrier substrate made of silicon and comprising a mesoporous layer; a dielectric layer disposed on the mesoporous layer; and a surface layer disposed on the dielectric layer. The semiconductor structure is notable in that: the mesoporous layer comprises hollow pores, the inner walls of which are coated with an oxide, the thickness of the mesoporous layer being between 3 μm and 40 μm, and the resistivity of the layer exceeding 20 kiloohm·cm throughout its thickness; and the resistivity of the carrier substrate being between 0.5 ohm·cm and 4 ohm·cm.

[0019] According to other advantageous and non-limiting features of the invention, considered alone or in any technically feasible combination:

[0020] The thickness of the mesoporous layer is less than 20 μm;

[0021] The resistivity of the carrier substrate is between 1 ohm·cm and 2 ohm·cm;

[0022] The surface layer is formed of at least one material selected from silicon, germanium, silicon carbide, IV-IV, III-V, or II-VI semiconductor compounds, and piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.);

[0023] The porosity of the mesoporous layer is between 40% and 60%, preferably about 50%;

[0024] The semiconductor structure comprises radio frequency devices produced in and / or on the surface layer.

[0025] The present invention also relates to a method for manufacturing a semiconductor structure for radio frequency applications, comprising the following steps:

[0026] - step a) of providing a donor substrate comprising a buried weakened plane defining a surface layer relative to the front side of the donor substrate;

[0027] - step b) of providing a carrier substrate made of silicon exhibiting a resistivity between 0.5 ohm·cm and 4 ohm·cm;

[0028] - step c) of making the carrier substrate porous so as to form a mesoporous layer on the front of the carrier substrate, said mesoporous layer exhibiting a resistivity exceeding 20 kilo-ohm·cm and having a thickness between 3 μm and 40 μm;

[0029] - step d) of annealing the carrier substrate at a temperature between 300° C. and 400° C. in an oxidizing atmosphere in order to stabilize the mesoporous layer (3) having hollow pores whose inner walls are coated with an oxide;

[0030] - step e), depositing a dielectric layer on the mesoporous layer;

[0031] - step f) of attaching the donor substrate to the dielectric layer via the front side of the donor substrate;

[0032] - Step g), separating along the buried weakened plane to transfer the surface layer to the carrier substrate.

[0033] According to other advantageous and non-limiting features of the invention, considered alone or in any technically feasible combination:

[0034] The resistivity of the silicon carrier substrate is between 1 ohm·cm and 2 ohm·cm;

[0035] The porosification in step c) is performed electrochemically;

[0036] The duration of the annealing in the oxidizing atmosphere in step d) is between 5 minutes and 200 minutes;

[0037] Step d) comprises, after the annealing in an oxidizing atmosphere, an annealing in a neutral atmosphere at a temperature between 400° C. and 450° C., advantageously at 420° C.;

[0038] The duration of the annealing under a neutral atmosphere in step d) is between 2 hours and 16 hours, preferably 10 hours;

[0039] Wherein step g) comprises: performing a separation heat treatment at a temperature between 200°C and 500°C, advantageously at 400°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Other features and advantages of the present invention will become apparent from the following detailed description of the invention given with reference to the accompanying drawings, in which:

[0041] [ Figure 1 ] Figure 1 shows a semiconductor structure according to the present invention;

[0042] [ Figure 2 ] Figure 2 A method for manufacturing a semiconductor structure according to the present invention is shown;

[0043] [ Figure 3 ] Figure 3 Several options for carrying out the porosification step in the manufacturing method according to the invention are shown;

[0044] [ Figure 4 ] Figure 4 shows the measurement results of the resistivity of the mesoporous layer as a function of its thickness;

[0045] [ Figure 5 ] Figure 5 shows the characterization of the second harmonic distortion (HD2) on a carrier substrate provided with a mesoporous layer as a function of the operating temperature;

[0046] [ Figure 6 ] Figure 6 shows the characterization of the second harmonic distortion (HD2) on a carrier substrate provided with a mesoporous layer according to the thickness of the mesoporous layer;

[0047] [ Figure 7 ] Figure 7 The changes in the chemical bonds in the mesoporous layer after stabilization annealing in step d) are shown. DETAILED DESCRIPTION

[0048] In the description, the same reference numerals may be used for elements of the same type in the drawings. The drawings are schematic representations and, for the sake of clarity, are not drawn to scale. In particular, the thickness of the layers along the z-axis is not proportional to the lateral dimensions along the x-axis and y-axis; the relative thicknesses of these layers relative to each other are not necessarily relative in the drawings. It should be noted that Figure 1 The coordinate system (x, y, z) applies to Figure 2 .

[0049] The present invention relates to a semiconductor structure 10 for radio frequency applications.

[0050] The semiconductor structure 10 first includes a carrier substrate 2 made of silicon, whose resistivity is between 0.5 ohm·cm and 4 ohm·cm, preferably between 1 ohm·cm and 2 ohm·cm ( Figure 1 The carrier substrate 2 includes a mesoporous silicon layer 3. Recall that porous silicon comes in three forms: macroporous silicon (pore size greater than 50 nm); mesoporous silicon (pore size between 2 nm and 50 nm); and nanoporous silicon, also known as microporous silicon (pore size less than 2 nm).

[0051] The mesoporous layer 3 according to the present invention comprises hollow pores, the inner walls of which are largely coated with an oxide. The thickness of the oxide layer on the inner walls of the pores is typically about one nanometer. The term "hollow pores" should be understood to refer to pores that are not filled with a solid material (e.g., silicon oxide). The oxide coating on the inner walls of the pores imparts a stable state to the mesoporous layer 3, wherein the Si-Hx dangling bonds are largely replaced by more stable Si-O-Si bonds. This improves the mechanical strength of the mesoporous layer 3.

[0052] Advantageously, the porosity of the mesoporous layer 3 is between 40% and 60%, preferably 50%. This porosity provides the mesoporous layer 3 with a good balance between mechanical and electrical properties.

[0053] The resistivity of the mesoporous layer 3 exceeds 20 kilohm·cm throughout its thickness; this high resistivity is in particular related to the specific resistivity range chosen for the carrier substrate 2 , as will be described further below in conjunction with the method for manufacturing the semiconductor structure 10 .

[0054] Furthermore, the thickness of the mesoporous layer 3 is between 3 μm and 40 μm, advantageously less than 20 μm. The thickness of the mesoporous layer 3 and its morphology (pore stability, porosity) will determine the mechanical strength of said layer 3. Therefore, the applicant has selected a series of properties that provide the mesoporous layer 3 with a mechanical strength suitable for supporting the manufacture of the semiconductor structure 10 and suitable for being retained in the final working device.

[0055] Furthermore, the thickness of the mesoporous layer 3, combined with its very high resistivity that is stable to temperatures between -40°C and 225°C, provides the semiconductor structure 10 with the resistivity and insulation properties required for high performance radio frequency applications.

[0056] The semiconductor structure 10 further comprises a dielectric layer 4 disposed on the mesoporous layer 3. Advantageously, but not restrictively, the dielectric layer 4 will comprise at least one of the following materials: silicon dioxide, silicon nitride, aluminum oxide, etc. Its thickness will vary between 10 nm and 3 μm.

[0057] The semiconductor structure 10 further includes a surface layer 5 ( Figure 1 (i)). The surface layer 5 is formed of at least one material selected from silicon, germanium, silicon carbide, IV-IV, III-V or II-VI semiconductor compounds and piezoelectric materials (such as LiNbO3, LiTaO3, etc.). The thickness of this layer is generally between a few nanometers and a few micrometers, advantageously between 200 nm and 1500 nm.

[0058] Radiofrequency microelectronic devices 6 can then be produced in and / or on the surface layer 5 of the semiconductor structure 10 ( Figure 1(ii)). The RF device 6 may comprise, for example, a switching circuit ("switch"), an antenna matching or tuning circuit ("tuner"), or a power amplifier circuit ("PA") produced using microelectronics technology. The manufacture of microelectronic components may require multiple steps, including high-temperature heat treatment, typically at temperatures between 950°C and 1100°C, or even higher. The mesoporous layer 3 retains its physical (mechanical strength) and electrical (resistivity, charge carrier trapping) properties after this heat treatment.

[0059] According to a variant, the semiconductor structure 10 comprises a layer of RF device layer 6 on a dielectric layer 4, and a surface layer 5 is located on said device 6 ( Figure 1 (iii)). This configuration can be obtained, for example, when a layer of RF device 6 is produced in or on the surface layer 5 while the surface layer is still attached to the donor substrate. The assembly formed by the layer of device 6 and the surface layer 5 can then be transferred to the dielectric layer 4 using a layer transfer technique that can be obtained from Smart Cut TM The method is selected from a method that combines bonding of the donor substrate and chemical-mechanical thinning.

[0060] Whatever the variant of the semiconductor structure 10 , due to the high resistivity of the mesoporous layer 3 and its stability over temperature (typically up to about 225° C.), the electromagnetic field generated by the high-frequency signal intended to propagate through the RF device 6 and to penetrate into the mesoporous layer 3 and the carrier substrate 2 suffers only small losses (insertion losses) and is hardly disturbed (crosstalk, harmonics).

[0061] The low dielectric constant of the mesoporous layer 3 (about half that of silicon, considering a porosity of about 50%) also promotes low capacitive coupling with the RF device 6 .

[0062] The stability of the RF performance of the semiconductor structure 10 is also promoted by the shallower penetration of the electromagnetic field for a given thickness of the mesoporous layer 3 (low dielectric constant) and by the fact that the electrical properties of the carrier substrate 2 do not change over the operating temperature range (resistivity of 0.5-4 ohm·cm compared to high-resistivity substrates of the prior art).

[0063] The present invention also relates to the manufacture of Figure 1 The method of the semiconductor structure 10 is shown in (i).

[0064] The method comprises a first step a) of providing a donor substrate 50 comprising a buried weakened plane 51 ( Figure 2 (a)).

[0065] The donor substrate 50 may be formed of at least one material selected from silicon, germanium, silicon carbide, IV-IV, III-V or II-VI semiconductor compounds and piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.). It may also include one or more additional layers disposed on its front and / or back surfaces, the additional layers being of any nature, such as dielectric (in the case of Figure 2 (not shown in (a)).

[0066] The buried weakened plane 51 is advantageously formed by ion implanting a light species into the donor substrate 50 at a defined depth. The light species is preferably selected from hydrogen and helium, or a combination of hydrogen and helium, since these species promote the formation of microcavities around the defined implantation depth, resulting in the buried weakened plane 51, as in the well-known Smart Cut TM as described in Methods.

[0067] For example, in the case of a donor substrate 50 made of silicon comprising an additional silicon oxide layer on the surface with a thickness between 10 nm and 400 nm, the implantation energy may be between 76 keV and 160 keV and 1 e 17 / cm 2 to 1.5 e 17 / cm 2 Hydrogen ions are implanted with a dose between 100 nm and 200 nm to form a buried weakened plane 51 and to define a surface layer with a thickness between 400 nm and 1500 nm.

[0068] The method further comprises step b) providing a carrier substrate 2 ( Figure 2 (b)). The carrier substrate 2 is made of silicon and has a resistivity between 0.5 ohm·cm and 4 ohm·cm. The applicant has defined this very narrow resistivity range in order to produce a mesoporous layer 3 with high resistivity and suitable porosity in the next step c). The resistivity range of the carrier substrate 2 is preferably even limited to between 1 ohm·cm and 2 ohm·cm.

[0069] It should also be noted that silicon substrates with resistivities between 0.5 ohm·cm and 4 ohm·cm (or between 1 ohm·cm and 2 ohm·cm) are widely available, compared to substrates with very high resistivities (>1 kiloohm·cm) that are typically used in RF applications.

[0070] The method then comprises a step c) of making the carrier substrate 2 porous to form a mesoporous layer 3 ( Figure 2 (c)).

[0071] The porosification step is performed electrochemically or photoelectrochemically. It is based on the anodic dissolution of silicon in an acidic medium using a carrier substrate 2 ( Figure 3). In practice, the carrier substrate 2 is immersed in a hydrofluoric acid-based solution 21. The carrier substrate 2 is in contact with the anode A, and the cathode C is positioned facing the face of the carrier substrate 2 to be made porous.

[0072] Various configurations of the experimental apparatus 20 are referred to as single cell configurations ( Figure 3 (a)) or dual pool configuration ( Figure 3 (b), (c)) are available. In the first case, only the front side of the carrier substrate 2 is immersed in the solution 21. In the second case, the front and back sides of the carrier substrate 2 are in contact with the same HF solution 21 or different solutions 23. In the case of a double cell, the back side can be illuminated 22 to replace the doped layer in contact with the anode.

[0073] When it is placed in the experimental device 20, the carrier substrate 2 undergoes electrolysis: the current density is advantageously 1 mA / cm 2 Up to 50mA / cm 2 The HF concentration of the solution 21 exceeds 30%, and advantageously contains an additive (such as isopropyl alcohol (IPA) or ethanol). Thus, a mesoporous silicon layer 3 ( Figure 2 (c)). The porosification time defines the thickness of the layer 3.

[0074] Surprisingly, the Applicant has observed that, for the carrier substrate 2, only a narrow resistivity range of between 0.5 ohm·cm and 4 ohm·cm, advantageously between 1 ohm·cm and 2 ohm·cm, is able to give the mesoporous layer 3 a high resistivity (over 20 kiloohm·cm) throughout its thickness. This observation was first made using SRP (Spreading Resistance Profile) measurements, which allow the resistivity of the mesoporous layer 3 to be measured throughout its thickness. Exemplary SRP measurement results for mesoporous layers with thicknesses of 12 μm, 12 μm and 15 μm produced on carrier substrates 2 of 6 ohm·cm, 2 ohm·cm and 0.2 ohm·cm are shown in FIG. Figure 4 . A carrier substrate 2 with a resistivity of 2 ohm·cm allows the mesoporous layer 3 to achieve a very high resistivity throughout its thickness, which is different from the other resistivities tested. The applicant has thus determined a very narrow resistivity range for the substrate 2, namely between 0.5 ohm·cm and 4 ohm·cm, which allows a resistivity of more than 20 kiloohm·cm to be achieved throughout the thickness of the mesoporous layer 3 according to the present invention. It should be noted that a resistivity range of between 1 ohm·cm and 2 ohm·cm for the carrier substrate 2 is more preferred for achieving a high resistivity (>20 kiloohm·cm) of the mesoporous layer 3 throughout its thickness.

[0075] This observation has been confirmed by measuring the so-called second harmonic distortion (HD2) characterization on the same carrier substrate 2 provided with the mesoporous layer as measured by SRP. This measurement was performed at 900 MHz for an output power of 15 dBm on a coplanar line with a length of 2 mm. A detailed description of the second harmonic distortion (HD2) characterization can be found in document US 2015 / 0168326 and is straightforward to implement because it does not require the full fabrication of the RF device 6 on the structure 10. Moreover, it is particularly suitable because it is highly representative of the performance of the RF device 6 that can be formed on the carrier substrate 2 being characterized, in particular in or on the surface layer 5 of the semiconductor structure 10.

[0076] Figure 5 The second harmonic distortion (called HD2) measurements in dBm are shown for operating temperatures ranging from 20° C. to 225° C. It should be noted that the RF performance of the carrier substrate 2 provided with the mesoporous layer 3 does not degrade or hardly degrades towards the lowest operating temperature (down to −70° C.).

[0077] In order to ensure very high performance of the RF devices 6 to be produced in and / or on the surface layer 5 of the structure 10 (e.g., required for 5G mobile applications), the HD2 value must be below -95 dBm, and advantageously below -100 dBm. It can be observed that the carrier substrate 2 having a resistivity of 2 ohm·cm and provided with the mesoporous layer 3 is the only carrier substrate that exhibits the desired behavior over the entire operating temperature range. The mesoporous layer 3 provided on a carrier substrate 2 having a resistivity between 0.5 ohm·cm and 4 ohm·cm, preferably between 1 ohm·cm and 2 ohm·cm, exhibits the desired properties of high resistivity throughout its thickness and stability over the operating temperature range.

[0078] Furthermore, the mesoporous layer 3 must be at least 10 μm thick to achieve the target RF performance. This minimum thickness has been determined by performing second harmonic distortion characterization measurements on carrier substrates 2 with mesoporous layers 3 of various thicknesses. The measurements were performed under the same conditions as described above.

[0079] Figure 6 The x-axis of the graph shows the thickness of the mesoporous layer 3 in micrometers. The y-axis shows the HD2 measurement in dBm. To be below the target HD2 value of -95 dBm, the thickness of the mesoporous layer 3 must be greater than 10 μm + / - 0.5 μm.

[0080] It should be noted that for applications with lower requirements in terms of RF performance, an HD2 value of approximately -90 dBm or even -80 dBm may be targeted. The thickness of the mesoporous layer 3 may then be reduced, as Figure 6As shown: For example, to provide an HD2 value of -80 dBm, a thickness of 6 μm + / - 0.5 μm would be sufficient. The mesoporous layer 3 then guarantees the performance over the entire operating temperature range.

[0081] Since increasing the thickness of the mesoporous layer 3 would adversely affect its mechanical strength, the applicant has defined a thickness range compatible with subsequent steps in the manufacture of the semiconductor structure 10 and with steps in the manufacture of the RF microelectronic device 6, namely between 3 μm and 40 μm, advantageously less than 20 μm.

[0082] The mesoporous layer 3 produced on a carrier substrate 2 made of silicon with a resistivity within the above narrow range also exhibits a porosity between 40% and 60%, preferably of about 50%.

[0083] After the porosification step c), the manufacturing method comprises a step d) of annealing the carrier substrate 2 at a temperature between 300° C. and 400° C. in an oxidizing atmosphere to stabilize the mesoporous layer 3 ( Figure 2 (d)). Preferably, the duration of annealing in an oxidizing atmosphere is between 5 minutes and 200 minutes.

[0084] This annealing allows most of the Si-Hx dangling bonds, especially those present on the inner wall of the pore, to be replaced by more stable Si-O-Si bonds, such as Figure 7 shown. Figure 7 The absorption spectra of Si-Hx and Si-O species present in the mesoporous layer 3 before and after stabilization annealing in an oxidizing atmosphere, obtained using Fourier transform infrared spectroscopy, are shown. It should be noted that after annealing at 300°C for 10 minutes in an oxidizing atmosphere, the peak associated with the Si-Hx bond disappears in favor of the more stable Si-O bond.

[0085] As described above, the pores of the mesoporous layer 3 according to the present invention remain hollow, and their inner walls are coated with a thin oxide layer having a thickness of about one nanometer, resulting in a stable state of the mesoporous layer 3 .

[0086] Advantageously, step d) comprises, after the annealing in an oxidizing atmosphere, annealing in a neutral atmosphere at a temperature between 400° C. and 500° C., advantageously at 420° C. The duration of the annealing in a neutral atmosphere is generally between 2 and 16 hours, ideally 10 hours.

[0087] Carrying out step d) prevents, in particular, any outgassing during the thermal treatment later applied to the semiconductor structure 10, which adversely affects the quality of said structure 10; moreover, the curvature (“bend”) of the carrier substrate 2 provided with the mesoporous layer 3 is stable and the curvature of the semiconductor structure 10 hardly changes after the thermal treatment.

[0088] The manufacturing method then includes step e) depositing a dielectric layer 4 on the mesoporous layer 3 ( Figure 2 (e)). Advantageously, but not limitingly, dielectric layer 4 comprises at least one of the following materials: silicon dioxide, silicon nitride, aluminum oxide, etc. Dielectric layer 4 is deposited, for example, by thermal oxidation or LPCVD, PECVD, or HDP deposition. Its thickness may vary from 10 nm to 3 μm.

[0089] It should be noted that the dielectric layer 4 can be produced completely on the mesoporous layer 3 or partly on the mesoporous layer 3 and partly on the donor substrate 50 ; in this second case, the dielectric layer 4 assumes its total thickness after the subsequent attachment step f).

[0090] The method comprises a step f) of attaching the donor substrate 50 to the dielectric layer 4 via the front side of the donor substrate 50 ( Figure 2 (f)). The attachment operation can be performed using any known method, preferably direct bonding by molecular adhesion. This known prior art will not be described in detail here. However, it should be remembered that before attachment, the donor substrate 50 and the carrier substrate 2 will undergo conventional surface activation and / or cleaning procedures to ensure the quality of the bonding interface in terms of defects and bonding energy.

[0091] The next step g) of the method consists in separating along the buried weakened plane 51 to transfer the surface layer 5 to the carrier substrate 2, thereby obtaining the semiconductor structure 10 and the remaining part of the donor substrate 50 ( Figure 2 (g)). Preferably, step g) comprises a separate heat treatment at a temperature between 200°C and 500°C. This heat treatment can increase the degree of weakening of the embedded weakened plane 51, which is an effect known to those skilled in the art as Smart Cut TM The method is important.

[0092] A temperature of approximately 400° C. is advantageous because the assembly is subjected to less stress associated with the different expansion coefficients of the materials in the donor substrate 50, the dielectric layer 4, the mesoporous layer 3, and the carrier substrate 2. In particular, excessive stresses could affect the integrity of the mesoporous layer 3. Thus, the mechanical strength of the semiconductor structure 10 is maintained even during the separation step g), so that a low degree of stress is applied to the donor substrate 50 / carrier substrate 2 assembly.

[0093] After separation, step g) may comprise a heat treatment for finishing the surface layer 5 in order to improve its crystallinity and its surface quality (roughness, defects). The semiconductor structure 10 withstands heat treatments well even at high temperatures (from 900° C. to 1100° C. or even 1200° C.), in particular since the mesoporous layer 3 has already been stabilized in step d).

[0094] The semiconductor structure 10 is also compatible with the thermal and chemical treatments typically applied in the manufacture of radio frequency microelectronic devices. The mesoporous layer 3 provides sufficient mechanical strength and is not affected by changes that may affect its physical and electrical properties, thereby providing:

[0095] - Low insertion loss (low attenuation of the signal) and good linearity (low distortion of the signal, the cause of harmonics);

[0096] - the stability of this performance over temperature, in particular within the operating range of RF devices [-40°C; 150°C] and even up to about 225°C;

[0097] - Low capacitive coupling between the RF devices 6 in / on the surface layer 5 and the carrier substrate 2, typically achieved by a dielectric constant lower than that of silicon.

[0098] Because the physical and electrical properties of the mesoporous layer 3 arranged on the carrier substrate 2 provide good RF and mechanical properties for the component, the semiconductor structure 10 for radio frequency applications according to the present invention is therefore suitable for any application in which high-frequency signals are propagated, which may be subject to losses or undesirable interference in the carrier substrate 2.

[0099] Of course, the invention is not limited to the embodiments and examples described, and variant embodiments thereof may be envisaged without departing from the scope of the invention as defined in the claims.

Claims

1. A semiconductor structure (10) for radio frequency applications, comprising: - a carrier substrate (2) made of silicon and comprising a mesoporous layer (3); - a dielectric layer (4) disposed on the mesoporous layer (3); - a surface layer (5) provided on the dielectric layer (4); The semiconductor structure (10) is characterized in that: - the mesoporous layer (3) comprises hollow pores, the inner walls of the hollow pores are coated with an oxide, the hollow pores are not filled with solid material and the thickness of the mesoporous layer (3) is between 3 μm and 40 μm, and the resistivity of the mesoporous layer (3) exceeds 20 kilohm·cm throughout the thickness of the mesoporous layer; - The resistivity of the carrier substrate (2) is between 0.5 ohm·cm and 4 ohm·cm.

2. The semiconductor structure (10) according to claim 1, wherein The thickness of the mesoporous layer (3) is less than 20 μm.

3. The semiconductor structure (10) according to any one of claims 1 and 2, wherein The resistivity of the carrier substrate (2) is between 1 ohm·cm and 2 ohm·cm.

4. The semiconductor structure (10) according to claim 1, wherein The surface layer (5) is formed of at least one material selected from silicon, germanium, silicon carbide, IV-IV, III-V, or II-VI semiconductor compounds and piezoelectric materials.

5. The semiconductor structure (10) of claim 1, wherein: The porosity of the mesoporous layer (3) is between 40% and 60%.

6. The semiconductor structure (10) according to claim 1, comprising radio frequency devices (6) produced in and / or on the surface layer (5).

7. A method for manufacturing a semiconductor structure (10) for radio frequency applications, the method comprising the steps of: - step a) of providing a donor substrate (50) comprising a buried weakened plane (51) delimiting a surface layer (5) relative to the front side of said donor substrate (50); - step b) of providing a carrier substrate (2) made of silicon exhibiting a resistivity between 0.5 ohm·cm and 4 ohm·cm; - step c) of making the carrier substrate (2) porous so as to form a mesoporous layer (3) on the front of the carrier substrate (2), said mesoporous layer (3) exhibiting a resistivity exceeding 20 kilo-ohm-cm over the entire thickness of said mesoporous layer, said thickness being between 3 μm and 40 μm; - step d) of annealing the carrier substrate (2) at a temperature between 300° C. and 400° C. in an oxidizing atmosphere to stabilize the mesoporous layer (3) having hollow pores whose inner walls are coated with an oxide and which are not filled with solid material; - step e), depositing a dielectric layer (4) on the mesoporous layer (3); - step f) of attaching the donor substrate (50) to the dielectric layer (4) via the front side of the donor substrate (50); - Step g), separation along the buried weakened plane (51) to transfer the surface layer (5) to the carrier substrate (2).

8. The method for producing a semiconductor structure (10) for radio frequency applications according to claim 7, wherein: The resistivity of the carrier substrate (2) provided in step b) is between 1 ohm·cm and 2 ohm·cm.

9. Method for producing a semiconductor structure (10) for radio frequency applications according to any one of claims 7 and 8, wherein The porosification in step c) is performed electrochemically.

10. The method for producing a semiconductor structure (10) for radio frequency applications according to claim 7, wherein: The duration of the annealing in the oxidizing atmosphere in step d) is between 5 minutes and 200 minutes.

11. The method for producing a semiconductor structure (10) for radio frequency applications according to claim 10, wherein: Step d) comprises: after the annealing in an oxidizing atmosphere, annealing in a neutral atmosphere at a temperature between 400° C. and 450° C.

12. The method for producing a semiconductor structure (10) for radio frequency applications according to claim 11, wherein: The annealing was performed at a temperature of 420° C. under a neutral atmosphere.

13. The method for producing a semiconductor structure (10) for radio frequency applications according to claim 11, wherein: The duration of the annealing in the neutral atmosphere in step d) is between 2 hours and 16 hours.

14. The method for producing a semiconductor structure (10) for radio frequency applications according to claim 7, wherein: Step g) comprises: performing a separation heat treatment at a temperature between 200°C and 500°C.

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