Integrated circuit, power supply circuit

Abstract

An integrated circuit of the present invention switches a transistor of a power supply circuit including a first capacitor and an inductor to which a voltage corresponding to an alternating voltage is applied, and the transistor that controls an inductor current flowing through the inductor, generates an output voltage of a target level from the alternating voltage, the integrated circuit including: an identification circuit that identifies whether a voltage level of a root mean square value of the alternating voltage is a first level or a second level higher than the first level; and a signal output circuit that outputs a drive signal that drives the transistor when the voltage level of the root mean square value is the first level, and corrects and outputs the drive signal to correct an input current to the power supply circuit when the voltage level of the root mean square value is the second level.

Description

Technical Field

[0001] This invention relates to integrated circuits and power supply circuits. Background Technology

[0002] Typically, there are integrated circuits that improve the power factor by making the waveform of the AC voltage similar to the waveform of the input current (e.g., Patent Documents 1-3).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 6599024

[0006] Patent Document 2: Japanese Patent No. 4580849

[0007] Patent Document 3: Japanese Patent Application Publication No. 2015-039261 Summary of the Invention

[0008] The technical problem to be solved by the present invention

[0009] However, when an AC voltage is applied to the input capacitor of an AC-DC converter, the input current sometimes becomes distorted, thus degrading the power factor.

[0010] The present invention was made in view of the above-mentioned problems, and its object is to provide an integrated circuit that appropriately changes the input current, suppresses total harmonic distortion, and improves the power factor.

[0011] Technical solutions for solving technical problems

[0012] The first embodiment of the integrated circuit of the present invention that solves the above problems is an integrated circuit that switches a transistor in a power supply circuit. The power supply circuit includes a first capacitor and an inductor to which a voltage corresponding to an AC voltage is applied, and the transistor controls the inductor current flowing through the inductor. It generates an output voltage of a target level based on the AC voltage. The integrated circuit includes: an identification circuit that identifies whether the effective value of the AC voltage is a first level or a second level higher than the first level; and a signal output circuit that outputs a drive signal to drive the transistor when the effective value of the voltage level is the first level, and corrects and outputs the drive signal to correct the input current to the power supply circuit when the effective value of the voltage level is the second level.

[0013] Furthermore, a first embodiment of the power supply circuit of the present invention is a power supply circuit that generates an output voltage of a target level based on an AC voltage. The power supply circuit includes: a first capacitor and an inductor to which a voltage corresponding to the AC voltage is applied; a transistor that controls the inductor current flowing through the inductor; an identification circuit that identifies whether the effective value of the AC voltage is a first level or a second level higher than the first level; and a signal output circuit that outputs a drive signal to drive the transistor when the effective value of the voltage level is the first level, and corrects and outputs the drive signal to correct the input current to the power supply circuit when the effective value of the voltage level is the second level.

[0014] Furthermore, a second embodiment of the integrated circuit of the present invention is an integrated circuit that switches a transistor in a power supply circuit, the power supply circuit including a first capacitor and an inductor to which a voltage corresponding to an AC voltage is applied, and the transistor controlling the inductor current flowing through the inductor, and generating an output voltage of a target level according to the AC voltage, wherein the integrated circuit includes: a signal output circuit that outputs a drive signal when the phase angle of a first rectified voltage obtained after full-wave rectification of the AC voltage is between a first phase angle and a second phase angle, such that the period during which the transistor is turned on is longer than when the phase angle is less than the first phase angle; and a drive circuit that drives the transistor based on the drive signal.

[0015] Furthermore, a second embodiment of the power supply circuit of the present invention is a power supply circuit that generates a target level output voltage based on an AC voltage, wherein the power supply circuit includes: a first capacitor and an inductor having a voltage corresponding to the AC voltage applied thereto; a transistor for controlling the inductor current flowing through the inductor; a signal output circuit that outputs a drive signal when the phase angle of a first rectified voltage obtained after full-wave rectification of the AC voltage is between a first phase angle and a second phase angle, such that the period during which the transistor is turned on is longer than when the phase angle is less than the first phase angle; and a drive circuit that drives the transistor based on the drive signal.

[0016] Furthermore, a third embodiment of the integrated circuit of the present invention is an integrated circuit that switches a transistor in a power supply circuit. This power supply circuit includes a first capacitor and an inductor to which a voltage corresponding to an AC voltage is applied, and the transistor controls the inductor current flowing through the inductor. It generates an output voltage of a target level based on the AC voltage. The integrated circuit includes: a signal output circuit that stops outputting a drive signal until the phase angle of a first rectified voltage obtained after full-wave rectification of the AC voltage changes from a third phase angle to a fourth phase angle, and outputs the drive signal after the phase angle changes to the fourth phase angle; and a drive circuit that drives the transistor based on the drive signal.

[0017] Furthermore, a third embodiment of the power supply circuit of the present invention is a power supply circuit that generates an output voltage of a target level based on an AC voltage. The power supply circuit includes: a first capacitor and an inductor to which a voltage corresponding to the AC voltage is applied; a transistor that controls the inductor current flowing through the inductor; a signal output circuit that stops outputting a drive signal until the phase angle of the first rectified voltage obtained after full-wave rectification of the AC voltage changes from a third phase angle to a fourth phase angle, and outputs the drive signal after the phase angle changes to the fourth phase angle; and a drive circuit that drives the transistor based on the drive signal.

[0018] Furthermore, a fourth embodiment of the integrated circuit of the present invention is an integrated circuit that switches a transistor in a power supply circuit, the power supply circuit including a first capacitor and an inductor to which a voltage corresponding to an AC voltage is applied, and the transistor controlling the inductor current flowing through the inductor, and generating an output voltage of a target level according to the AC voltage, wherein the integrated circuit includes: a signal output circuit that outputs a drive signal such that the input current increases as the load state of the power supply circuit becomes light load; and a drive circuit that drives the transistor based on the drive signal.

[0019] Furthermore, a fourth embodiment of the power supply circuit of the present invention is a power supply circuit that generates a target level output voltage based on an AC voltage, wherein the power supply circuit includes: a first capacitor and an inductor having a voltage corresponding to the AC voltage applied; a transistor controlling the inductor current flowing through the inductor; a signal output circuit that outputs a drive signal such that the input current increases as the load state of the power supply circuit becomes light load; and a drive circuit that drives the transistor based on the drive signal.

[0020] Furthermore, a fifth embodiment of the integrated circuit of the present invention is an integrated circuit that switches a transistor in a power supply circuit, the power supply circuit including a first capacitor and an inductor to which a voltage corresponding to an AC voltage is applied, and the transistor controlling the inductor current flowing through the inductor, and generating an output voltage of a target level according to the AC voltage, wherein the integrated circuit includes: an adjustment circuit that changes at least one of a feedback voltage corresponding to the output voltage and a reference voltage corresponding to the target level, so that the target level of the output voltage becomes lower; a signal output circuit that outputs a drive signal based on the feedback voltage and the reference voltage; and a drive circuit that drives the transistor based on the drive signal.

[0021] Furthermore, a fifth embodiment of the power supply circuit of the present invention is a power supply circuit that generates an output voltage of a target level based on an AC voltage, wherein the power supply circuit includes: a first capacitor and an inductor having a voltage corresponding to the AC voltage applied; a transistor for controlling the inductor current flowing through the inductor; an adjustment circuit that changes at least one of a feedback voltage corresponding to the output voltage and a reference voltage corresponding to the target level, so that the target level of the output voltage becomes lower; a signal output circuit that outputs a drive signal based on the feedback voltage and the reference voltage; and a drive circuit that drives the transistor based on the drive signal.

[0022] Invention Effects

[0023] According to the present invention, an integrated circuit can be provided that can appropriately change the input current, suppress total harmonic distortion, and improve the power factor. Attached Figure Description

[0024] Figure 1 This is a diagram illustrating an example of an AC-DC converter 10.

[0025] Figure 2 This is a diagram showing an example of an input line filter 20.

[0026] Figure 3 This is a diagram illustrating an example of the power factor improvement IC26.

[0027] Figure 4 It is a graph showing the relationship between AC voltage Vac, voltage Vh, and voltage divider Vhdiv.

[0028] Figure 5 This is a diagram illustrating an example of the identification circuit 51.

[0029] Figure 6This is a graph showing the relationship between the effective value of AC voltage Vac and the reference voltages VREF0 and VREF1.

[0030] Figure 7 This is a diagram illustrating an example of a frequency identification circuit 52.

[0031] Figure 8 This is a diagram illustrating an example of the adjustment circuit 54.

[0032] Figure 9 This is a diagram illustrating an example of the cut-off detection circuit 55 and the discharge circuit 56.

[0033] Figure 10 This is a graph showing the relationship between the reference voltages VREF3 and VREF4 and the voltage divider voltage Vhdiv.

[0034] Figure 11 This is a diagram illustrating an example of a conduction signal output circuit 80.

[0035] Figure 12 This is a diagram illustrating an example of a turn-off signal output circuit 82.

[0036] Figure 13 This is a diagram showing an example of the correction circuit 71a.

[0037] Figure 14 This is a diagram illustrating an example of a turn-off signal output circuit 82a.

[0038] Figure 15 This diagram illustrates the operation of the power factor improvement IC26, which includes the correction circuit 71a and the shutdown signal output circuit 82a.

[0039] Figure 16 This is a graph showing the variation of the input current Iin when using the power factor improvement IC26, which includes the correction circuit 71a and the shutdown signal output circuit 82a.

[0040] Figure 17 This is a diagram illustrating an example of the correction circuit 71b.

[0041] Figure 18 This is a diagram illustrating an example of a turn-off signal output circuit 82b.

[0042] Figure 19 This is a diagram illustrating an example of the correction circuit 71c.

[0043] Figure 20 This is a diagram illustrating an example of a conduction signal output circuit 81.

[0044] Figure 21 This is a diagram illustrating an example of a turn-off signal output circuit 82c.

[0045] Figure 22 It is a diagram showing an example of the oscillation circuit 141 and the conduction width expansion circuit 193c.

[0046] Figure 23 It is a diagram showing the changes in Icap, IL, and Iin accompanying the mode transition.

[0047] Figure 24 It is a diagram showing the change in the drive signal Vdr accompanying the mode transition.

[0048] Figure 25 It is a diagram showing an example of the correction circuit 71d.

[0049] Figure 26 It is a diagram showing an example of the oscillation circuit 141 and the conduction width expansion circuit 193d.

[0050] Figure 27 It is a diagram showing an example of the correction circuit 71e.

[0051] Figure 28 It is a diagram showing an example of the turn-off signal output circuit 82e. Detailed Embodiments

[0052] Cross-reference to Related Applications

[0053] This application claims priority based on Japanese Patent Application No. 2020-072678 filed on April 15, 2020, and incorporates its content by reference.

[0054] Based on the description of this specification and the drawings, at least the following matters become clear.

[0055] =====This Embodiment=====

[0056] Figure 1 It is a diagram showing an example of the structure of the AC-DC converter 10 according to an embodiment of the present invention. The AC-DC converter 10 is a boost chopper type power supply circuit that generates an output voltage Vout of a target level from the AC voltage Vac of a commercial power supply.

[0057] The load 11 is, for example, a DC-DC converter or an electronic device that operates at a DC voltage.

[0058] <<<Overview of the AC-DC Converter 10>>>

[0059] The AC-DC converter 10 is configured to include an input line filter 20, a full-wave rectifier circuit 21, capacitors 22, 25, 33, 34, a transformer 23, diodes 24, 28, 29, a power factor improvement IC 26, an NMOS transistor 27, and resistors 30 to 32.

[0060] An input line filter 20 is disposed between nodes N1 and N2 where the AC voltage Vac is applied and the full-wave rectifier circuit 21 (described later), and is a circuit used to remove noise from the commercial power supply to the AC-DC converter 10. Furthermore, in this embodiment, the current in nodes N1 and N2 where the AC voltage Vac is applied is defined as the input current Iin. Here, the AC voltage Vac is, for example, a voltage of 100–277V with a frequency of 50–60Hz.

[0061] Reference Figure 2 The input line filter 20 is described below. The input line filter 20 is configured to include capacitors 41, 43, 44, and 45 and a choke coil 42. Capacitors 41 and 43 are X capacitors for removing normal-mode noise, and choke coil 42 and capacitors 44 and 45 are filters for removing common-mode noise.

[0062] return Figure 1 The full-wave rectifier circuit 21 performs full-wave rectification on the specified AC voltage Vac after noise removal, and applies it as the rectified voltage Vrec to the main coil L1 of capacitor 22 and transformer 23.

[0063] Alternatively, the rectified voltage Vrec is applied directly to the main coil L1, but it can also be applied to the main coil L1 through components such as a resistor (not shown). Furthermore, in this embodiment, "applying" includes not only providing voltage directly to a designated node, but also providing voltage indirectly via components such as a resistor (not shown), and providing a voltage after voltage division.

[0064] Capacitor 22 is a component used to smooth the rectified voltage Vrec, and is charged by the charging current Icap. Transformer 23 has a main coil L1 and an auxiliary coil L2 magnetically coupled to the main coil L1. Here, in this embodiment, the auxiliary coil L2 is wound such that the polarity of the voltage generated in the auxiliary coil L2 is opposite to the voltage generated in the main coil L1. The voltage Vzcd generated in the auxiliary coil L2 is applied to the terminal ZCD of the power factor improvement IC 26 (described later).

[0065] Furthermore, the main coil L1, together with diode 24, capacitor 25, and NMOS transistor 27, constitutes a boost chopper circuit. Therefore, the charging voltage of capacitor 25 becomes the DC output voltage Vout. Additionally, the output voltage Vout is, for example, 400V.

[0066] The power factor improvement IC26 is an integrated circuit that controls the switching of the NMOS transistor 27 to improve the power factor of the AC-DC converter 10 and make the output voltage Vout level a target level (e.g., 400V). Specifically, the power factor improvement IC26 drives the NMOS transistor 27 based on the inductor current IL flowing through the main coil L1 and the output voltage Vout.

[0067] Details of the power factor correction IC26 will be described later. The power factor correction IC26 has terminals FB, ZCD, COMP, OUT, and VH. In addition, the power factor correction IC26 also has terminals other than the five terminals mentioned above (FB, ZCD, COMP, OUT, and VH), but these are omitted here for convenience.

[0068] NMOS transistor 27 is a transistor used to control the power supplied by AC-DC converter 10 to load 11. In this embodiment, NMOS transistor 27 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. NMOS transistor 27 can also be a bipolar transistor, for example, as long as it is a transistor capable of controlling power. Furthermore, the gate electrode of NMOS transistor 27 is connected to be driven by a signal from terminal OUT.

[0069] Resistors 30 and 31 form a voltage divider circuit that divides the output voltage Vout and generates a feedback voltage Vfb used when switching the NMOS transistor 27. Additionally, the feedback voltage Vfb generated at the node connecting resistors 30 and 31 is applied to terminal FB.

[0070] Resistor 32 and capacitors 33 and 34 are components used for phase compensation in the feedback-controlled power factor improvement IC26. Resistor 32 and capacitor 33 are connected in series between terminal COMP and ground, and capacitor 34 is connected in parallel between them.

[0071] Diodes 28 and 29 form a full-wave rectifier circuit connected to the front stage of the full-wave rectifier circuit 21. This circuit applies a voltage Vh corresponding to the AC voltage Vac to the terminal VH of the power factor improvement IC 26. Voltage Vh is obtained by rectifying the AC voltage Vac obtained from the node of the front stage of the full-wave rectifier circuit 21. Therefore, the phase angle of voltage Vh can be detected more accurately without being affected by capacitor 22. Specifically, the anode of diode 28 is connected to the non-grounded line of the front stage of the full-wave rectifier circuit 21. On the other hand, the anode of diode 29 is connected to the grounded line of the front stage of the full-wave rectifier circuit 21. The cathodes of diodes 28 and 29 are connected together and connected to the terminal VH of the power factor improvement IC 26. Alternatively, a voltage divider obtained by dividing the voltage across the cathodes of diodes 28 and 29 can be applied to the terminal VH of the power factor improvement IC 26.

[0072] Here, diodes 28 and 29 correspond to the "first rectifier circuit," and the voltage corresponding to the AC voltage Vac corresponds to the "first rectified voltage." Full-wave rectifier circuit 21 corresponds to the "second rectifier circuit," and the rectified voltage Vrec corresponds to the "second rectified voltage." Furthermore, the main coil L1 corresponds to an "inductor," and the current flowing through the main coil L1 is the "inductor current IL." Additionally, capacitor 22 corresponds to the "first capacitor," and capacitors 33 and 34 correspond to the "second capacitors."

[0073] <<<Structure of Power Factor Improvement IC26>>>

[0074] Figure 3 This diagram illustrates an example of a power factor correction IC 26. The power factor correction IC 26 is configured to include a voltage divider circuit 50, an identification circuit 51, a frequency identification circuit 52, a switching circuit 53, an adjustment circuit 54, a cutoff detection circuit 55, a discharge circuit 56, a signal output circuit 57, and a drive circuit 58. Furthermore, in... Figure 3 For convenience, in conjunction with Figure 1 Terminals are depicted in different locations, but the wiring, components, etc. connected to each terminal are... Figure 1 and Figure 3 Same as above.

[0075] <<<<Voltage Divider Circuit 50>>>>

[0076] Figure 4This diagram illustrates the relationship between the AC voltage Vac, the voltage Vh obtained by full-wave rectification of the AC voltage Vac, and the voltage divider voltage Vhdiv generated by the voltage divider circuit 50. The voltage divider circuit 50 generates the voltage divider voltage Vhdiv by dividing the voltage Vh, and includes resistors 60 and 61. Specifically, one end of resistor 60 is connected to terminal VH, and the other end is connected in series with one end of resistor 61. The other end of resistor 61 is grounded. The voltage Vhdiv is generated at the node connecting resistors 60 and 61. Furthermore, the voltage level of the AC voltage Vac changes periodically according to the phase angle, and the voltage levels of voltage Vh and the voltage divider voltage Vhdiv also change periodically according to the phase angle. Specifically, the voltage level of the AC voltage Vac increases when the phase angle changes from 0 degrees to 90 degrees, and decreases when the phase angle changes from 90 degrees to 270 degrees. The voltage level of the AC voltage Vac increases when the phase angle changes from 270 degrees to 360 degrees. On the other hand, the voltage level Vh rises when the phase angle changes from 0 degrees to 90 degrees and falls when the phase angle changes from 90 degrees to 180 degrees. The voltage level Vh changes in the same way when the phase angle changes from 180 degrees to 360 degrees as it does when the phase angle changes from 0 degrees to 180 degrees. Since the voltage divider Vhdiv is obtained by dividing the voltage Vh, it changes periodically with respect to the phase angle, just like the voltage Vh.

[0077] Furthermore, although an example of providing a voltage divider circuit 50 within the power factor improvement IC 26 has been described, a voltage divider circuit can also exist externally to the power factor improvement IC 26. This circuit rectifies the AC voltage Vac using diodes 28 and 29, and applies the voltage obtained by the voltage divider circuit to terminal VH. While resistors 60 and 61 have been described as being used in the voltage divider circuit 50, it is not limited to these and can be any combination of resistors. Additionally, terminal VH is equivalent to "terminal".

[0078] <<<<Identification Circuit 51>>>>

[0079] Figure 5 This diagram illustrates an example of the identification circuit 51. The identification circuit 51 compares the divided voltage Vhdiv with reference voltages VREF0 and VREF1, and identifies the voltage level of the effective value of the AC voltage Vac. Specifically, the effective values ​​of the AC voltage Vac include 100V, 200V, and 277V, and as shown... Figure 6 As shown, by setting reference voltages VREF0 and VREF1, the identification circuit 51 identifies the voltage level of the effective value of AC voltage Vac.

[0080] The identification circuit 51 is configured to include comparators 91 and 93 and timers 92 and 94. When the voltage divider voltage Vhdiv becomes higher than the reference voltage VREF0, comparator 91 outputs a high-level (hereinafter referred to as "H") signal Vhdet. On the other hand, when the voltage divider voltage Vhdiv is lower than the reference voltage VREF0, comparator 91 outputs a low-level (hereinafter referred to as "L") signal Vhdet. When the "L" level signal Vhdet is input, timer 92 starts counting based on the clock signal CLKa. As a result, when the voltage divider voltage Vhdiv is lower than the reference voltage VREF0, timer 92 counts a predetermined number of times and outputs an "H" level signal Venb0 after counting a predetermined number of times. On the other hand, when the voltage divider voltage Vhdiv becomes higher than the reference voltage VREF0 and the "H" level signal Vhdet is input, timer 92 resets, stops counting, and does not count a predetermined number of times. Thus, it outputs an "L" level signal Venb0. Therefore, when the voltage divider voltage Vhdiv is lower than the reference voltage VREF0, the timer 92 outputs a "H" level signal Venb0 indicating that the effective value of the AC voltage Vac is 100V. On the other hand, when the voltage divider voltage Vhdiv becomes higher than the reference voltage VREF0, the timer 92 outputs a "L" level signal Venb0 indicating that the effective value of the AC voltage Vac is 200V.

[0081] Similar to timer 92, timer 94 outputs a signal Venb1 indicating an effective value of AC voltage Vac of 200V or 100V, or a signal Venb1 indicating an effective value of AC voltage Vac of 277V, based on the output of comparator 93 and whether the output of comparator 93 is at the L level during the counting of a predetermined number of times.

[0082] Furthermore, 100V corresponds to the "first level", 200V corresponds to the "second level", and 277V corresponds to the "third level". Also, for ease of explanation, the effective values ​​of the AC voltage Vac are described as 100V, 200V, and 277V, but the effective value of the AC voltage Vac recognized by the identification circuit 51 is not limited to these.

[0083] <<<<Frequency Identification Circuit 52>>>>

[0084] Figure 7 This is a diagram illustrating an example of a frequency identification circuit 52. The frequency identification circuit 52 includes a toggle (T) flip-flop 101 and a timer 102, and identifies the frequency (e.g., 50 Hz or 60 Hz) of the AC voltage Vac based on the signal Vhdet from the identification circuit 51.

[0085] Specifically, the T flip-flop 101 outputs a signal that inverts for each rising edge of the signal Vhdet. The timer 102 is reset by the signal from the T flip-flop. When the frequency of the AC voltage Vac is, for example, 50Hz, both the reset period and the de-reset period are longer than in the case of a frequency of 60Hz. Therefore, the timer 102 counts a predetermined number of times and outputs a signal Vacf at the "H" level. On the other hand, when the frequency of the AC voltage Vac is, for example, 60Hz, the de-reset period is shorter compared to when the frequency of the AC voltage Vac is, for example, 50Hz. Therefore, the timer 102 does not count a predetermined number of times and outputs a signal Vacf at the "L" level. Furthermore, the period during which the signal Vhdet is high remains almost unchanged when the effective value of the AC voltage Vac is 200V and when the effective value of the AC voltage Vac is 277V. Therefore, identification can be performed without any problems in this structure.

[0086] In addition, 50Hz corresponds to the "first frequency" and 60Hz corresponds to the "second frequency".

[0087] <<<<Switching Circuit 53>>>>

[0088] Return to Figure 3 The switching circuit 53 selects either the clock signal CLKa or a clock signal CLKb with a higher frequency than CLKa based on the signal Vacf from the frequency identification circuit 52, and outputs it as the clock signal CLK. Specifically, when the signal Vacf is at the "H" level, the switching circuit 53 outputs the clock signal CLKa as the clock signal CLK; when the signal Vacf is at the "L" level, the switching circuit 53 outputs the clock signal CLKb as the clock signal CLK. Furthermore, the clock signal CLKa is equivalent to the "first clock signal," and the clock signal CLKb is equivalent to the "second clock signal."

[0089] <<<<Adjusting Circuit 54>>>>

[0090] Figure 8 This diagram illustrates an example of the adjustment circuit 54. The adjustment circuit 54 selects either a reference voltage VREFA or VREFB based on the signal Venb0 and outputs it as the reference voltage VREF2. Specifically, the adjustment circuit 54 includes inverters 111 and 112 and transmission gates 113 and 114. When the signal Venb0 is at a "H" level, it outputs the reference voltage VREFA as the reference voltage VREF2; when the signal Venb0 is at a "L" level, it outputs the reference voltage VREFB as the reference voltage VREF2.

[0091] Here, the reference voltage VREFA is the reference voltage when the AC-DC converter 10 generates the target level output voltage Vout based on the AC voltage Vac, and the reference voltage VREFB is the reference voltage when the AC-DC converter 10 generates a specified level output voltage Vout lower than the target level based on the AC voltage Vac. Furthermore, the reference voltage VREFA is equivalent to the "first voltage," and the reference voltage VREFB is equivalent to the "second voltage."

[0092] <<<<Disconnection detection circuit 55 and discharge circuit 56>>>>

[0093] Reference Figure 9 This illustrates an example of cutting off the detection circuit 55 and the discharge circuit 56.

[0094] The cut-off detection circuit 55 is a circuit that detects whether the AC voltage Vac is provided, i.e., whether the AC voltage Vac is cut off, based on the voltage divider voltage Vhdiv. It includes a comparator 121 and a timer 122. The comparator 121 detects whether the voltage divider voltage Vhdiv is higher than the reference voltage VREF3.

[0095] Figure 10 This is a graph showing the relationship between the reference voltages VREF3 and VREF4 (described later) and the voltage divider voltage Vhdiv. For example... Figure 10 As shown, the reference voltage VREF3 used by the cut-off detection circuit 55 to determine that the AC voltage Vac is not provided is set to a level lower than the maximum level of the voltage divider voltage Vhdiv when the phase angle is around 90 degrees. On the other hand, the reference voltage VREF3 is set to the lower level of the voltage divider voltage Vhdiv when the level of the voltage divider voltage Vhdiv becomes lower (almost 0V), and the phase angle is around 0 degrees, 180 degrees, and 360 degrees (for example, 170 degrees to 190 degrees in the case of a phase angle of 180 degrees). That is, the reference voltage VREF3 is set to a level between the maximum level and the lower level that should be determined when the AC voltage Vac is continuously lower than the reference voltage VREF3 for a "predetermined time T1".

[0096] Specifically, comparator 121 compares the voltage divider Vhdiv corresponding to the voltage at terminal VH with the reference voltage VREF3 and outputs a signal Scmp to detect whether AC voltage Vac is provided.

[0097] Timer 122 detects whether comparator 121 continuously outputs a signal Scmp indicating that the voltage divider voltage Vhdiv is lower than the reference voltage VREF3 within "time T1". Specifically, timer 122 counts "time T1" when comparator 121 outputs the "H" level signal Scmp, and outputs an "H" level pulse signal Stim to timer 123 after "time T1" has elapsed while the signal Scmp remains at the "H" level. On the other hand, timer 122 resets during the period when AC voltage Vac is provided. Here, "time T1" is a time set for determining whether AC voltage Vac is provided based on the voltage divider voltage Vhdiv. That is, when AC voltage Vac is not provided for "time T1", the cut-off detection circuit 55 determines that AC voltage Vac is cut off. For example, when the frequency of AC voltage Vac is 50Hz, "time T1" is, for example, 20ms or more.

[0098] The discharge circuit 56 is a circuit that discharges capacitors 41, 43, 44, and 45 of the input line filter 20 when the cut-off detection circuit 55 detects that the AC voltage Vac is not provided. It includes a timer 123, an NMOS transistor 124, and a resistor 125.

[0099] Timer 123 is a circuit that turns on NMOS transistor 124 during "discharge time D1". When the cutoff detection circuit 55 detects the cutoff of AC voltage Vac, it continuously outputs a "H" level signal Sdis during "discharge time D1". On the other hand, when the cutoff detection circuit 55 does not detect the cutoff of AC voltage Vac, timer 123 outputs a "L" level signal Sdis. Here, "discharge time D1" is the time sufficient to discharge capacitors 41, 43, 44, and 45.

[0100] NMOS transistor 124 is a component used to discharge capacitors 41, 43, 44, and 45 of the input line filter 20, and is turned on during the period when timer 123 outputs a "H" level signal Sdis. Thus, NMOS transistor 124 discharges capacitors 41, 43, 44, and 45 of the input line filter 20 through resistor 125 disposed between NMOS transistor 124 and capacitors 41, 43, 44, and 45.

[0101] Therefore, when the cut-off detection circuit 55 and discharge circuit 56 detect that the AC voltage Vac is not provided based on the voltage divider voltage Vhdiv corresponding to the voltage at terminal VH, they discharge capacitors 41, 43, 44, and 45 of the input line filter 20. Additionally, capacitors 41, 43, 44, and 45 correspond to the "third capacitor," and NMOS transistor 124 corresponds to the "switch." Resistor 125 corresponds to the "discharge resistor." Furthermore, the resistance value of the voltage divider circuit 50 (i.e., the resistance value between terminal VH and ground) is greater than the resistance value of resistor 125.

[0102] <<<<Signal Output Circuit 57>>>>

[0103] Return to Figure 3 The signal output circuit 57 is described below. The signal output circuit 57 generates a drive signal Vp1 based on voltages Vzcd, Vfb, Vhdiv, and the signal Venb0 / 1 from the identification circuit 51. Specifically, when the effective value of the AC voltage Vac is 100V, and both the signal Venb0 and Venb1 are at an "H" level, the signal output circuit 57 outputs the drive signal Vp1 to drive the NMOS transistor 27. When the effective value is 200V, the signal Venb0 is at an "L" level, and the signal Venb1 is at an "H" level, the signal output circuit 57 corrects and outputs the drive signal Vp1 to correct the input current Iin. When the effective value is 277V, the signal Venb0 is at an "L" level, and the signal Venb1 is at an "L" level, the signal output circuit 57 corrects and outputs the drive signal Vp1 to correct the input current Iin.

[0104] The signal output circuit 57 is configured to include a correction circuit 71 and a drive signal output circuit 72. The correction circuit 71 has circuitry corresponding to the embodiment described later, and is activated based on the signal Venb0 / 1 from the identification circuit 51. The drive signal output circuit 72 operates according to the signal from the correction circuit 71, and has circuitry corresponding to the correction circuit 71.

[0105] <<<<Driver Circuit 58>>>>

[0106] The driving circuit 58 is a buffer circuit that drives the NMOS transistor 27 based on the driving signal Vp1. Specifically, the driving circuit 58 uses a signal Vdr with the same logic level as the input signal to drive the NMOS transistor 27, which has a relatively large gate capacitance. Furthermore, the driving circuit 58 turns on the NMOS transistor 27 based on the "H" level driving signal Vp1 and turns off the NMOS transistor 27 based on the "L" level driving signal Vp1.

[0107] <<<<<Correction Circuit 71>>>>>

[0108] The correction circuit 71 outputs various signals to the drive signal output circuit 72 (described later) based on the voltage divider voltage Vhdiv and the signal Venb0 / 1. When it is necessary to correct the input current Iin, that is, when at least the signal Venb0 is at the "L" level, the drive signal output circuit 72 corrects the drive signal Vp1. On the other hand, when it is not necessary to correct the input current Iin, that is, when the signal Venb0 is at the "H" level, the correction circuit 71 stops the drive signal output circuit 72 from correcting the drive signal Vp1.

[0109] <<<<<Drive signal output circuit 72>>>>>

[0110] The drive signal output circuit 72 outputs a drive signal Vp1 based on the feedback voltage Vfb corresponding to the output voltage Vout and the reference voltage VREF2 corresponding to the target level. Specifically, when it is necessary to correct the input current Iin, the drive signal output circuit 72 corrects the drive signal Vp1 based on the signal from the correction circuit 71, etc.

[0111] The drive signal output circuit 72 is configured to include an on signal output circuit 80, an off signal output circuit 82, and an SR flip-flop 83 that operates in a reset-priority manner. The on signal output circuit 80 generates an on signal Ss, and the off signal output circuit 82 generates an off signal Sr.

[0112] <<<<<<Conduction Signal Output Circuit 80>>>>>>

[0113] Figure 11 This diagram illustrates an example of the structure of the turn-on signal output circuit 80. When the inductor current IL becomes almost zero, the turn-on signal output circuit 80 outputs a turn-on signal Ss to turn on the NMOS transistor 27. The turn-on signal output circuit 80 is configured to include a zero-current detection circuit 131, a delay circuit 132, a turn-on timer 133, and an OR circuit 134. Furthermore, in this embodiment, the "prescribed condition" is the condition described later, where the inductor current IL is almost zero.

[0114] The zero-current detection circuit 131 detects whether the current value of the inductor current IL is a "current value Ia" (hereinafter, for convenience, "nearly zero" will be simply referred to as zero) based on the voltage Vzcd at terminal ZCD. Furthermore, when the zero-current detection circuit 131 detects that the current value of the inductor current IL is a "zero" "current value Ia", it outputs a "H" level signal Vz. The zero-current detection circuit 131 is configured to include a comparator (not shown) that compares a predetermined voltage of the auxiliary coil L2 when the inductor current IL becomes "current value Ia" with the voltage Vzcd.

[0115] When the zero current detection circuit 131 outputs a signal Vz at the "H" level, the delay circuit 132 outputs a pulse signal Vp2 after a specified delay.

[0116] When the power factor improvement IC26 is activated, or when the AC voltage Vac is not provided and there is no output pulse signal Vp2, the turn-on timer 133 outputs a pulse signal Vp3 to turn on the NMOS transistor 27. Specifically, when there is no output pulse signal Vp2 within a specified period, a "H" level pulse signal Vp3 is output in each specified cycle.

[0117] OR circuit 134 calculates and outputs the logical OR of pulse signals Vp2 and Vp3. Therefore, in Figure 11 In the case of the conduction signal output circuit 80 shown, pulse signal Vp2 or pulse signal Vp3 is output from OR circuit 134 as signal Ss.

[0118] <<<<<<Shutdown signal output circuit 82>>>>>>

[0119] Figure 12 This diagram illustrates an example of the structure of the shutdown signal output circuit 82. The shutdown signal output circuit 82 outputs a shutdown signal Sr based on the feedback voltage Vfb. The shutdown signal output circuit 82 is configured to include an oscillation circuit 141, an error output circuit 142, and a comparator 143.

[0120] When an "H" level signal Vp1 is input, the oscillation circuit 141 outputs a ramp wave Vr. Specifically, when an "H" level signal Vp1 is input, the oscillation circuit 141 outputs a ramp wave Vr with gradually increasing amplitude.

[0121] Error output circuit 142 is a transconductance amplifier that generates an error current Ie based on the error between the feedback voltage Vfb and the reference voltage VREF2, and charges capacitors 33 and 34 via terminal COMP. Here, the reference voltage VREF2 is a voltage determined based on the target level output voltage Vout, and is either a reference voltage VREFA or VREFB selected by adjustment circuit 54. Furthermore, the voltage at terminal COMP, which is connected to the output of error output circuit 142, is defined as voltage Vcomp.

[0122] Comparator 143 is a circuit that compares voltage Vcomp with ramp wave Vr and outputs a turn-off signal Sr of "H" level when ramp wave Vr becomes higher than voltage Vcomp. Specifically, comparator 143 compares the magnitudes of voltage Vcomp and ramp wave Vr and outputs turn-off signal Sr as the comparison result. Here, voltage Vcomp is applied to the inverting input terminal of comparator 143, and ramp wave Vr is applied to the non-inverting input terminal of comparator 143. Therefore, when the level of ramp wave Vr is lower than the level of voltage Vcomp, turn-off signal Sr becomes "L" level, and when the level of ramp wave Vr is higher than the level of voltage Vcomp, turn-off signal Sr becomes "H" level. Additionally, ramp wave Vr corresponds to a "triangular-wave-like oscillating voltage".

[0123] <<<<SR flip-flop 83>>>>>

[0124] In addition, return Figure 3 , SR flip-flop 83 outputs drive signal Vp1 based on conduction signal Ss and turn-off signal Sr. Conduction signal Ss is input to the S input of SR flip-flop 83, and turn-off signal Sr is input to the R input. Therefore, drive signal Vp1, which is the Q output of SR flip-flop 83, becomes "H" level when signal Ss becomes "H" level. On the other hand, when signal Sr becomes "H" level, drive signal Vp1 becomes "L" level. Additionally, the SR flip-flop operates in a reset-priority manner, and when signal Sr is "H" level, it outputs drive signal Vp1 of "L" level regardless of the logic level of signal Ss. Also, SR flip-flop 83 corresponds to an "output circuit".

[0125] <<<<Correction circuit 71a>>>>

[0126] Figure 13 is a diagram showing an example of correction circuit 71a. When the phase angle of voltage Vh is greater than a specified phase angle θ1 (e.g., 80 degrees), correction circuit 71a causes drive signal output circuit 72 to correct drive signal Vp1 such that the period during which NMOS transistor 27 is turned on is longer than when the phase angle is less than specified phase angle θ1.

[0127] Specifically, when the phase angle of voltage Vh is less than specified phase angle θ1, correction circuit 71a causes drive signal output circuit 72 to output drive signal Vp1 for which the period during which NMOS transistor 27 is turned on according to feedback voltage Vfb is "period P1". On the other hand, when the phase angle of voltage Vh is greater than phase angle θ1, correction circuit 71a causes drive signal output circuit 72 to output drive signal Vp1 for which the period during which NMOS transistor 27 is turned on includes "period P2" that is longer than "period P1".

[0128] Furthermore, the phase angle θ1 is defined as equivalent to the "first phase angle". Also, although it is recorded as the "phase angle of voltage Vh", it is the same as the "phase angle of voltage Vhdiv".

[0129] <<<Details of the correction circuit 71a>>>

[0130] When the phase angle of voltage Vh is less than the phase angle θ1, the correction circuit 71a causes the drive signal output circuit 72 to output a drive signal Vp1 for a period "period P1" during which the NMOS transistor 27 is turned on. On the other hand, when the phase angle is greater than the phase angle θ1 and less than the phase angle θ2, the correction circuit 71a causes the drive signal output circuit 72 to generate a drive signal Vp1 for a period "period P2" longer than "period P1" during a "predetermined period P0" (i.e., a period when the phase angle is greater than the phase angle θ1 and less than the phase angle θ2). The correction circuit 71a is configured to include a comparator 151 and a timer 152.

[0131] Comparator 151 compares the voltage Vhdiv corresponding to the voltage at terminal VH with the reference voltage VREF4 and outputs a detection signal Sd indicating whether the phase angle of voltage Vh is greater than the phase angle θ1. Figure 10 As shown, the reference voltage VREF4 used by comparator 151 to detect whether the phase angle of voltage Vh is greater than the phase angle θ1 is set such that the phase angle of voltage Vh is the maximum level of the voltage divider voltage Vhdiv, which is about 90 degrees.

[0132] Timer 152 counts the "period P0" based on the detection signal Sd indicating that the phase angle of voltage Vh is greater than the phase angle θ1, and outputs a signal Sq indicating that the counting is in progress. Here, "period P0" is the period from when the phase angle of voltage Vh becomes the phase angle θ1 determined according to the capacitance value of capacitor 22 until it becomes the phase angle θ2, where the phase angle θ2 is greater than the phase angle θ1 and less than 180 degrees.

[0133] Specifically, when the voltage divider voltage Vhdiv is higher than the reference voltage VREF4, comparator 151 detects that the phase angle of voltage Vh is greater than the phase angle θ1 and outputs a detection signal Sd at the "H" level. On the other hand, when the voltage divider voltage Vhdiv is lower than the reference voltage VREF4, comparator 151 detects that the phase angle of voltage Vh is less than the phase angle θ1 and outputs a detection signal Sd at the "L" level.

[0134] Timer 152 is configured to include an SR flip-flop 161 and a counter 162. Timer 152 counts the "period P0" and outputs a "H" level signal Sq indicating that the "period P0" is being counted. Specifically, when the phase angle of voltage Vh is less than the phase angle θ1, that is, when the signal Sd from comparator 151 is at the "L" level, the Q output of SR flip-flop 161, i.e., the signal Sq, is at the "L" level. When the phase angle of voltage Vh is greater than the phase angle θ1, that is, when the detection signal Sd from the input of comparator 151 to the S input becomes at the "H" level, SR flip-flop 161 outputs the "H" level signal Sq. When the signal Sq becomes at the "H" level, counter 162 counts the "period P0". When the "period P0" has elapsed, counter 162 outputs the "H" level signal Scnt to the R input of SR flip-flop 161. In SR flip-flop 161, when signal Scant changes to "H" level, the Q output of SR flip-flop 161 changes to "L" level, and signal Sq also changes to "L" level. On the other hand, when signal Sq is at "L" level, counter 162 is reset. Therefore, when the phase angle of voltage Vh changes to phase angle θ1, timer 152 outputs signal Sq at "P0" and "H" levels.

[0135] Here, "period P0" is timed using a clock signal CLK from switching circuit 53. The clock signal CLK is selected from CLKa or CLKb based on a signal Vacf from frequency identification circuit 52 that identifies whether the frequency of AC voltage Vac is 50Hz or 60Hz. When the frequency of AC voltage Vac is 50Hz, timer 152 counts "period P0" a predetermined number of times using CLKa, and when the frequency of AC voltage Vac is 60Hz, timer 152 counts "period P0" a predetermined number of times using CLKb. Thus, timer 152 can time the period from when the phase angle changes to phase angle θ1 until it changes to phase angle θ2, regardless of the frequency of AC voltage Vac. Furthermore, regardless of whether the frequency of AC voltage is 50Hz or 60Hz, the count of timer 152 can be changed according to the frequency of AC voltage Vac to time the period from when the phase angle changes to phase angle θ1 until it changes to phase angle θ2. Additionally, phase angle θ2 corresponds to a "second phase angle".

[0136] <<<Shutdown signal output circuit 82a>>>

[0137] Figure 14 This is a diagram illustrating an example of a turn-off signal output circuit 82a. In Figure 14The diagram shows the correction circuit 71a to illustrate the structure of the turn-off signal output circuit 82a. The turn-off signal output circuit 82a generates a turn-off signal Sr to turn off the NMOS transistor 27. Here, the reference voltage VREF4 is the voltage value of the voltage divider voltage Vhdiv when the phase angle of the voltage Vh changes to the phase angle θ1.

[0138] When the phase angle of voltage Vh is less than the phase angle θ1, the turn-off signal output circuit 82a outputs a turn-off signal Sr that makes NMOS transistor 27 turn on during the period of "period P1" based on the feedback voltage Vfb. When "period P0" is timed, the turn-off signal output circuit 82a outputs a turn-off signal Sr that makes NMOS transistor 27 turn on during the period of "period P2" based on the feedback voltage Vfb and the signal Sq of timer 152.

[0139] In addition to the shutdown signal output circuit 82, the shutdown signal output circuit 82a also includes a current source 144a, which charges capacitors 33 and 34 with a specified current I1 via terminal COMP.

[0140] Current source 144a charges capacitors 33 and 34 using a predetermined current I1 based on the signal Sq from timer 152 and the signal Venb0 / 1 from identification circuit 51. Specifically, current source 144a includes inverter 171, OR circuits 172, 173, 174, PMOS transistors 176, 178, and current sources 175a and 177a connected to the power supply voltage Vdd generated internally in power factor improvement IC 26. When signal Sq is at the "H" level, i.e., when counter 162 counts "period P0", current source 144a charges capacitors 33 and 34 using the predetermined current I1. Specifically, during the period when signal Sq is at the "H" level, the output of inverter 171 becomes at the "L" level, and when signal Venb0 is at the "L" level, PMOS transistor 176 is turned on. Furthermore, when the output of inverter 171 is at the "L" level and signals Venb0 and Venb1 are at the "L" level, PMOS transistor 178 is turned on. When PMOS transistor 176 or PMOS transistors 176 and 178 are turned on, the current I1 from current source 144a is output to terminal COMP. On the other hand, when signal Sq is at the "L" level, that is, during the period when counter 162 does not count "period P0", the output of inverter 171 becomes the "H" level, PMOS transistors 176 and 178 are turned off, and the current I1 from current source 144a is not output to terminal COMP.

[0141] That is, when the signal Sq indicates that timing of "period P0" is in progress, the current source 144a charges capacitors 33 and 34 using a constant current I1. Furthermore, the phase compensation resistor 32 and capacitors 33 and 34 are connected via terminal COMP between the output of the error output circuit 142 and the output of the current source 144a and ground. Here, the voltage at terminal COMP connecting the output of the error output circuit 142 and the output of the current source 144a is defined as voltage Vcomp.

[0142] Based on the above, when the phase angle of voltage Vh is less than the phase angle θ1, the turn-off signal output circuit 82a outputs a turn-off signal Sr based on the feedback voltage Vfb, wherein the period during which the NMOS transistor 27 is turned on is "period P1". On the other hand, when the phase angle of voltage Vh is greater than the phase angle θ1 and "period P0" is timed, i.e., the phase angle of voltage Vh is less than the phase angle θ2, the turn-off signal output circuit 82a outputs a turn-off signal Sr based on the feedback voltage Vfb and the signal Sq, wherein the period during which the NMOS transistor 27 is turned on includes "period P2". Here, "period P2" is longer than "period P1".

[0143] Furthermore, comparator 151 corresponds to the "first detection circuit". Additionally, timer 152 corresponds to the "first timing circuit". Error output circuit 142 corresponds to the "first charging circuit". Furthermore, current source 144a corresponds to the "second charging circuit", and current I1 corresponds to the "first current". Comparator 143 corresponds to the "comparison circuit". "Period P0" corresponds to the "correction time". Furthermore, "Period P0" when the frequency of AC voltage Vac is 50Hz corresponds to the "first time", and "Period P0" when the frequency of AC voltage Vac is 60Hz corresponds to the "second time".

[0144] <<<Power factor correction IC26 operation utilizes correction circuit 71a>>>

[0145] Figure 15 This diagram illustrates the operation of the power factor improvement IC26 using the correction circuit 71a.

[0146] exist Figure 15 At time t0, the phase angle of voltage Vh is 0 degrees, and at time t6, the phase angle of voltage Vh is 180 degrees. Furthermore, the driving signal Vp1 is actually a signal of, for example, a few kHz, and the same applies to the ramp wave Vr. However, to make the switching action easier to understand, at... Figure 15 The amplified driving signal Vp1 and the ramp wave Vr are illustrated in the diagram.

[0147] Before time t2 (described later), the phase angle of voltage Vh is less than the phase angle θ1, and comparator 151 outputs a detection signal Sd at the "L" level. Therefore, timer 152 outputs a signal Sq at the "L" level.

[0148] Since signal Sq is at "L" level before time t0 to time t1, current source 144a does not output current I1. On the other hand, error output circuit 142 outputs error current Ie and generates voltage Vcomp. Furthermore, voltage Vcomp, charged by current I1 in the half-wave preceding voltage Vh, gradually discharges and decreases, becoming voltage V1. Voltage V1 represents the voltage value of Vcomp when load 11 remains unchanged and output voltage Vout reaches the target level.

[0149] At time t0, the inductor current IL becomes zero, the conduction signal output circuit 80 outputs a "H" level conduction signal Ss, and the SR flip-flop 83 outputs a "H" level signal Vp1. Consequently, the drive circuit 58 outputs a "H" level signal OUT, and the NMOS transistor 27 turns on. The oscillation circuit 141 outputs a ramp wave Vr.

[0150] At time t1, if the ramp wave Vr becomes higher than the voltage Vcomp generated by the error current Ie of the error output circuit 142, the comparator 143 outputs a "H" level turn-off signal Sr. When the turn-off signal Sr becomes "H", the SR flip-flop 83 outputs a "L" level signal Vp1. Consequently, the drive circuit 58 outputs a "L" level signal OUT, and the NMOS transistor 27 is turned off. Furthermore, the period from time t0 to time t1 is "period P1". The same operation is repeated from time t1 to time t2.

[0151] At time t2, if the phase angle of voltage Vh becomes greater than the phase angle θ1, then voltage Vhdiv becomes greater than the reference voltage VREF4, therefore comparator 151 outputs a "H" level signal Sd. When comparator 151 outputs a "H" level signal Sd, SR flip-flop 161 outputs a "H" level signal Sq, and counter 162 begins timing for "period P0". When SR flip-flop 161 outputs a "H" level signal Sq, current source 144a outputs current I1. Voltage Vcomp gradually increases due to the current I1 from current source 144a.

[0152] At time t3, the inductor current IL becomes zero, the turn-on signal output circuit 80 outputs a "H" level turn-on signal Ss, and the SR flip-flop 83 outputs a "H" level signal Vp1. Consequently, the drive circuit 58 outputs a "H" level signal OUT, and the NMOS transistor 27 turns on. The oscillation circuit 141 outputs a ramp wave Vr. When the voltage Vhdiv is lower than the reference voltage VREF4, the comparator 151 outputs a "L" level signal Sd. However, since the "H" level signal Scnt has not yet been input to the R input of the SR flip-flop 161, the SR flip-flop 161 continues to output a "H" level signal Sq. Therefore, the current source 144a continues to output current I1.

[0153] At time t4, if the ramp wave Vr becomes higher than the voltage Vcomp generated by the error current Ie of the error output circuit 142, the comparator 143 outputs a "H" level turn-off signal Sr. When the turn-off signal Sr becomes "H", the SR flip-flop 83 outputs a "L" level signal Vp1. Consequently, the drive circuit 58 outputs a "L" level signal OUT, and the NMOS transistor 27 turns off. Furthermore, the period from time t3 to time t4 is "period P2". During this period, a drive signal Vp1 is generated within "period P0" to turn on the NMOS transistor 27 during the "period P2", which is longer than "period P1". The same operation is repeated from time t4 to time t5.

[0154] At time t5, if the inductor current IL becomes zero, the conduction signal output circuit 81 outputs a "H" level conduction signal Ss, and the SR flip-flop 83 outputs a "H" level signal Vp1. Consequently, the drive circuit 58 outputs a "H" level signal OUT, and the NMOS transistor 27 is turned on. The oscillation circuit 141 outputs a ramp wave Vr. At time t5, after the "period P0" from time t2, the counter 162 outputs a "H" level signal Scnt, and the SR flip-flop 161 is reset. As a result, the signal Sq becomes "L" level, and the current source 144a stops outputting current I1. Then, the cycle repeats from time t0 to time t6.

[0155] Furthermore, "period P0" is the period from when the phase angle of voltage Vh becomes phase angle θ1, which is determined according to the capacitance value of capacitor 22, until it becomes phase angle θ2, where phase angle θ2 is greater than phase angle θ1 and less than 180 degrees.

[0156] Based on the above, since the voltage Vcomp gradually increases during the "period P0", the off-state signal Sr output when the ramp wave Vr becomes higher than the voltage Vcomp is slower than the on-state signal Ss output when the NMOS transistor 27 is turned on. As a result, the period during which the signal Vp1 is at the "H" level gradually lengthens, and the period during which the NMOS transistor 27 is turned on also gradually lengthens.

[0157] <<<Effect of power factor correction using IC26 with correction circuit 71a>>>

[0158] Figure 16 This is a graph showing the relationship between AC voltage Vac and input currents Iin and Iin_a when the power factor improvement IC26 using correction circuit 71a is employed. The solid line represents the waveform of AC voltage Vac, the dashed line represents the waveform of input current Iin without correction circuit 71a, and the dotted-dash line represents the waveform of input current Iin_a with correction circuit 71a.

[0159] When the phase angle of voltage Vh changes to a specified range X (e.g., 0 degrees to 30 degrees), the current used to charge the discharged capacitor 22 flows as the input current Iin. Therefore, a large input current Iin flows within the range X, but as it deviates from X, the input current Iin decreases, resulting in waveform distortion of the input current Iin. Furthermore, this phenomenon contributes to the deterioration of the power factor.

[0160] On the other hand, during the period when "period P0" is timed, that is, during the period within the phase angle range from phase angle θ1 to phase angle θ2, as the period during which NMOS transistor 27 is turned on increases, the input current Iin_a flows more than the input current Iin. Therefore, by using the correction circuit 71a, the waveform distortion of the input current Iin_a is reduced compared to the input current Iin, and the power factor is improved. Furthermore, the phase angle θ1 can be any angle as long as it is within the range of 30 degrees to 180 degrees.

[0161] <<<<<Correction Circuit 71b>>>>>

[0162] Figure 17 This is a diagram illustrating an example of the correction circuit 71b. The correction circuit 71b is obtained by adding a load detection circuit 180 to the correction circuit 71a. The load detection circuit 180 includes a single-trigger timer 181, an NMOS transistor 182, and a capacitor 183. It samples and holds the voltage Vcomp using pulses based on the signal Vhdet from the identification circuit 51, and detects the load based on the voltage Vcomp.

[0163] Specifically, when a pulse from the single-trigger timer 181 is input to the gate electrode of the NMOS transistor 182, the load detection circuit 180 charges the capacitor 183 using the current corresponding to the voltage Vcomp. The correction circuit 71c outputs the voltage of the capacitor 183 as the voltage Vload. Here, the single-trigger timer 181 generates a pulse for each rising edge of the signal Vhdet.

[0164] <<<Shutdown signal output circuit 82b>>>

[0165] Figure 18 This diagram illustrates an example of a shutdown signal output circuit 82b. The shutdown signal output circuit 82b is configured to also include a current source 144b, replacing the current source 144a of the shutdown signal output circuit 82a. The current source 144b includes current sources 175b and 177b, which cause current to flow to change the current I1 according to the voltage Vload. Specifically, the current source 144b increases the current I1 so that the input current Iin increases as the load 11 of the AC-DC converter 10 becomes lightly loaded. As a result, the voltage Vcomp rises further, and the timing delay of the output shutdown signal Sr is increased. The period during which the drive signal Vp1 is at the "H" level becomes longer, and the input current Iin increases.

[0166] Therefore, the lighter the load 11 becomes, the higher the output voltage Vout will rise. This can suppress the decrease in input current Iin caused by the decrease in the difference between the load and AC voltage Vac, and can appropriately change the input current Iin and improve the power factor.

[0167] <<<<<Correction Circuit 71c>>>>>

[0168] Figure 19 This diagram illustrates an example of the correction circuit 71c. The correction circuit 71c causes the drive signal output circuit 72 to correct the drive signal Vp1 based on the phase angle of the AC voltage Vac. Specifically, the correction circuit 71c causes the drive signal output circuit 72 to output the drive signal Vp1 that turns off the NMOS transistor 27 until the phase angle of the AC voltage Vac changes from a predetermined phase angle θa to θb; after the phase angle changes to θb, the drive signal output circuit 72 outputs the drive signal Vp1 again.

[0169] After the phase angle changes to phase angle θb, until it changes to phase angle θc, if a specified condition is met, the correction circuit 71c causes the period during which the NMOS transistor 27 is turned on and off to become a specified drive signal Vp1. Then, after the phase angle changes to phase angle θc, until it changes to phase angle θd, the correction circuit 71c causes the drive signal output circuit 72 to correct the drive signal Vp1, so that the period during which the NMOS transistor 27 is turned on is longer than the period from phase angle θb to phase angle θc.

[0170] <<<Details of the 71c calibration circuit>>>

[0171] The identification circuit 71c is configured to include a comparator 191, a timer 192, and a conduction width expansion circuit 193c. The comparator 191 compares the voltage Vhdiv with the reference voltage VREF5 to detect when the phase angle of the AC voltage Vac changes to phase angle θa. Based on the detection result of the comparator 191, the timer 192 uses the clock signal CLK from the switching circuit 53 to count and time the timing of phase angle changes to phase angles θa, θb, θc, and θd. Therefore, regardless of whether the frequency of the AC voltage Vac is 50Hz or 60Hz, the timing of phase angle changes to phase angles θa, θb, θc, and θd can be timed using the clock signal CLK. The timer 192 outputs an "H" level signal Sstop when the phase angle changes from θa to θb, an "H" level signal Srst when the phase angle changes from θb to θc, and an "H" level signal Son_expd when the phase angle changes from θc to θd.

[0172] Details of the conduction width expansion circuit 193c will be described later. When the signal Son_expd is output, the oscillation circuit 141 is controlled so that the conduction period of the NMOS transistor 27 becomes longer than at least the period from phase angle θb to phase angle θc.

[0173] On the other hand, details of the correction circuit 71c will be described later. When the signal Sstop becomes "H" level, the shutdown signal output circuit 82c outputs a shutdown signal Sr of "H" level. Furthermore, when the signal Srst becomes "H" level, the correction circuit 71c activates the turn-on signal output circuit 81 (described later) and the turn-off signal output circuit 82c (described later) to generate a drive signal Vp1 during the period when the NMOS transistor 27 is turned off, which is a predetermined period.

[0174] In addition, comparator 191 is equivalent to the "second detection circuit", and timer 192 is equivalent to the "second timing circuit". Furthermore, phase angles θa, θb, θc, and θd are equivalent to the "third phase angle", "fourth phase angle", "fifth phase angle", and "sixth phase angle", respectively, and the timing of the phase angles changing to phase angles θa, θb, θc, and θd are equivalent to the "first timing", "second timing", "third timing", and "fourth timing", respectively.

[0175] <<<Conduction Signal Output Circuit 81>>>

[0176] Figure 20 This diagram illustrates an example of a turn-on signal output circuit 81. The turn-on signal output circuit 81 is obtained by adding a circuit to the turn-on signal output circuit 80 that disables the output signal Vp4 of the OR circuit 134 of the turn-on signal output circuit 80 when an input signal Srst of "H" level is received. Specifically, the turn-on signal output circuit 81 is configured to include the turn-on signal output circuit 80, the AND circuit 201, the OR circuits 202 and 204, and the timer 203.

[0177] In the turn-on signal output circuit 81, signal Vp4 is generated in the same manner as in the turn-on signal output circuit 80. However, when signal Srst is at an "H" level, signal Vp4 is invalidated by the AND circuit 201. On the other hand, when signal Srst is at an "H" level, if signal Vp1 changes to an "L" level, timer 203 starts timing to make the off period of NMOS transistor 27 specified and outputs a "H" level signal. As a result, signal Ss becomes "H" level, and NMOS transistor 27 turns on. Furthermore, when signal Srst is at an "H" level, if signal Vp1 changes to an "H" level, timer 203 is reset.

[0178] Furthermore, when the signal Srst is at the "L" level, the timer 203 is reset and outputs a "L" level signal. Therefore, when the signal Srst is at the "L" level, the turn-on signal output circuit 81 operates in the same way as the turn-on signal output circuit 80.

[0179] In addition, the AND circuit 201, OR circuits 202 and 204, and timer 203 are equivalent to part of the "control circuit".

[0180] <<<Shutdown Signal Output Circuit 82c>>>

[0181] Figure 21 This diagram illustrates an example of a turn-off signal output circuit 82c. Figure 21The figure shows the correction circuit 71c to illustrate the structure of the shutdown signal output circuit 82c. The shutdown signal output circuit 82c is configured to control the oscillation circuit 141 of the shutdown signal output circuit 82c by the current Ico from the correction circuit 71c, and is also configured to include an OR circuit 145, which sets the shutdown signal Sr to the "H" level when the signal Sstop is at the "H" level.

[0182] When the signal Sstop changes to the "H" level, the OR circuit 145 outputs the "H" level turn-off signal Sr. At this time, the SR flip-flop 83 becomes a priority reset, thus outputting the "L" level drive signal Vp1 and turning off the NMOS transistor 27.

[0183] When the signal Sstop is at the "L" level and the signal Son_expd is at the "H" level, the oscillation circuit 141 is controlled by the current Ico, as detailed later. Therefore, the slope of the ramp wave Vr is smaller than when the signal Srst is at the "H" level, and after the specified conditions are met, the timing delay of the output signal Sr and the conduction period of the NMOS transistor 27 become longer.

[0184] Since both the signal Sstop and the signal Son_expd are at "L" level, the off-state signal Sr is output based on the feedback voltage Vfb when the oscillation circuit 141 is not controlled by the current Ico. Furthermore, the OR circuit 145 is equivalent to part of the "control circuit".

[0185] <<<<Control of Oscillator Circuit 141 Based on On-Width Extension Circuit 193c>>>>

[0186] Figure 22 This diagram illustrates an example of the oscillation circuit 141 and the on-width expansion circuit 193c. When the NMOS transistor 27 is turned on, i.e., when the signal Vp1 is at a "H" level, the oscillation circuit 141 outputs a ramp wave Vr. Then, when the signal Son_expd changes to a "H" level, the on-width expansion circuit 193c reduces the slope of the ramp wave Vr by shunting the current Iramp0 from the current source 221 within the oscillation circuit 141 to ground.

[0187] First, before detailing the conduction width expansion circuit 193c, the operation of the oscillation circuit 141 will be explained. The oscillation circuit 141 includes a current source 221, a capacitor 222, an inverter 223, and an NMOS transistor 224. When the signal Vp1 is at a "H" level, the capacitor 222 is charged using a current Iramp corresponding to the current Iramp0 from the current source 221. The oscillation circuit 141 outputs the voltage of the capacitor 222 as a ramp wave Vr. On the other hand, when the signal Vp1 is at a "L" level, the NMOS transistor 224 is turned on, the capacitor 222 discharges, and therefore no ramp wave Vr is output; the oscillation circuit 141 outputs a voltage at ground level.

[0188] Next, the conduction width expansion circuit 193c will be described. When the signal Son_expd is at the "H" level, the conduction width expansion circuit 193c shunts the current Iramp0 from the current source 221 in the oscillation circuit 141 and controls the current Iramp. The conduction width expansion circuit 193c is configured to include AND circuits 211 and 213, OR circuit 212, switches 214 and 216, and current sources 215c and 217c.

[0189] Specifically, when the signal Son_expd is at level "H" and the signal Venb0 is at level "L", the conduction width expansion circuit 193c turns on the switch 214 and reduces the current Iramp flowing through the current source 215c. As a result, the oscillation circuit 141 outputs a ramp wave with a longer period of conduction for the NMOS transistor 27.

[0190] Furthermore, when the signal Son_expd is at "H" level and signals Venb0 and Venb1 are at "L" level, the conduction width expansion circuit 193c turns on switch 216 and further reduces the current Iramp flowing through current source 217c. That is, based on the voltage level of the effective value of AC voltage Vac, the current Ico shunt Iramp decreases. As a result, the oscillation circuit 141 outputs a ramp wave Vr that further lengthens the period during which NMOS transistor 27 is turned on.

[0191] On the other hand, when the signal Son_expd is at the "L" level, or when the signals Venb0 and Venb1 are at the "H" level, switches 214 and 216 are turned off, and the current Iramp becomes the current Iramp0.

[0192] <<<Power factor correction IC26 operation using correction circuit 71c>>>

[0193] Figure 23 This diagram illustrates the operation of the power factor improvement IC26 using the correction circuit 71c.

[0194] When the phase angle of the AC voltage Vac is less than (greater than 0 degrees) the phase angle θa (e.g., 10 degrees), the correction circuit 71c causes the drive signal output circuit 72 to output a drive signal Vp1 with a "period P3", which is the period during which the NMOS transistor 27 is turned on, corresponding to the feedback voltage Vfb. The mode in this case is set to "NORM".

[0195] When the phase angle changes to phase angle θa, comparator 191 detects that the voltage Vhdiv becomes higher than the reference voltage VREF5. Timer 192 times the change of phase angle to phase angle θa and outputs an "H" level signal Sstop. When the signal Sstop becomes "H", the shutdown signal output circuit 82c outputs an "H" level shutdown signal Sr. When the "H" level signal Sr is received, the SR flip-flop 83 outputs an "L" level drive signal Vp1. As a result, the NMOS transistor 27 stops switching.

[0196] Furthermore, when the phase angle changes to phase angle θa, the charging current begins to flow in capacitor 22, and the current Icap flowing in capacitor 22 increases. However, since the NMOS transistor stops switching, the inductor current IL does not flow, and the input current Iin is corrected, becoming almost solely the charging current. The mode for changing the phase angle from phase angle θa to phase angle θb is set to "STOP".

[0197] When the phase angle changes to phase angle θb, timer 192 sets signal Sstop to "L" level and signal Sirst to "H" level. When signal Sirst becomes "H" level, the turn-on signal output circuit 81 invalidates the output signal Vp4 of OR circuit 134. Then, when drive signal Vp1 becomes "L" level, the timer 203 is released from reset. When the reset is released, timer 203 counts the period during which NMOS transistor 27 is off, and when this period reaches a predetermined value, it outputs a "H" level signal. Then, the turn-on signal output circuit 81 outputs a "H" level turn-on signal Ss. When the "H" level signal Ss is received, SR flip-flop 83 outputs a "H" level drive signal Vp1.

[0198] Subsequently, the turn-off signal output circuit 82c outputs a turn-off signal Sr at the "H" level, corresponding to the feedback voltage Vfb. When the "H" level signal Sr is received, the SR flip-flop 83 sets the drive signal Vp1 to the "L" level. The turn-on signal output circuit 81 repeats this operation until the phase angle changes from phase angle θb to phase angle θc. As a result, the drive circuit 58 starts switching the NMOS transistor 27.

[0199] Furthermore, when the phase angle changes to phase angle θb, the current Icap decreases. Although the current Icap decreases, the inductor current IL flows, therefore, the input current Iin is corrected and increases. The mode where the phase angle changes from phase angle θb to phase angle θc is set to "SS".

[0200] When the phase angle changes to phase angle θc, timer 192 sets signal Srst to "L" level and signal Son_expd to "H" level. When signal Son_expd becomes "H" level, conduction width expansion circuit 193c performs control to reduce the slope of ramp wave Vr output by oscillator circuit 141. Then, turn-off signal output circuit 82c outputs turn-off signal Sr with a delay longer than the timing of NMOS transistor 27 turning on. As a result, SR flip-flop 83 outputs drive signal Vp1, which has a "period P4" longer than the period during which NMOS transistor 27 is on compared to when the phase angle is between phase angles θb and θc.

[0201] Furthermore, when the phase angle changes to phase angle θc, the current Icap decreases further, and the conduction period of NMOS transistor 27 becomes longer, thus increasing the inductor current IL. Consequently, the input current Iin is corrected and further increased. The mode where the phase angle changes from phase angle θc to phase angle θd is set to "EXPD".

[0202] When the phase angle changes to phase angle θd, timer 192 sets the signal Son_expd to "L" level. When the signal Son_expd is at "L" level, the conduction width expansion circuit 193c stops controlling the reduction of the slope of the ramp wave Vr output by the oscillation circuit 141. Then, the turn-on signal output circuit 81 and the turn-off signal output circuit 82c are no longer controlled by the correction circuit 71c and switch to operation when the phase angle is less than the phase angle θa.

[0203] Furthermore, when the phase angle changes to phase angle θd, the charging current flowing through capacitor 22 becomes less than the "specified value Ib". The "specified value Ib" is defined as the charging current value when the proportion of the charging current in the current Icap becomes negligible. The mode when the phase angle is greater than phase angle θd is "NORM".

[0204] In addition, "period P3" is equivalent to "period one" and "period P4" is equivalent to "period two".

[0205] <<<Changes in the driving signal Vdr accompanying mode transition>>>

[0206] Figure 24This is a graph showing the change in the drive signal Vdr accompanying the mode transition. When the mode is "NORM", the correction circuit 71c does not operate, and the drive signal Vdr is generated to make the NMOS transistor 27 conduct during the "period P3" corresponding to the feedback voltage Vfb.

[0207] When the mode is "STOP", the timer 192 outputs the "H" level signal Sstop, thereby the drive signal output circuit 72 outputs the "L" level signal Vp1, and the drive circuit 58 outputs the drive signal Vdrv that stops the switching of the NMOS transistor 27.

[0208] When the mode is "SS", timer 192 outputs a "H" level signal Sirst. Additionally, the turn-on signal output circuit 81 outputs a turn-on signal Ss to ensure that the period during which NMOS transistor 27 is turned off is a predetermined period. Then, the turn-off signal output circuit 82c outputs a turn-off signal Sr to determine the period during which NMOS transistor 27 is turned on based on the feedback voltage Vfb. Consequently, drive signal output circuit 72 generates a signal Vp1 that ensures the period during which NMOS transistor 27 is turned off is a predetermined period, and drive circuit 58 outputs a drive signal Vdrv that ensures the period during which NMOS transistor 27 is turned off is a predetermined period.

[0209] When the mode is "EXPD", timer 192 outputs a "H" level signal Son_expd. Furthermore, the turn-on signal output circuit 81 outputs a "H" level turn-on signal Ss based on voltage Vzcd. Then, since the slope of the ramp wave Vr output by oscillation circuit 141 decreases due to the current Ico from the turn-on width expansion circuit 193c, the turn-off signal output circuit 82c outputs a turn-off signal Sr, making the "period P4" during the turn-on period of NMOS transistor 27 at least longer than in the "SS" mode. Consequently, drive signal output circuit 72 generates a signal Vp1, making "period P4" longer than "period P3", and drive circuit 58 outputs a drive signal Vdrv, making "period P4" longer than "period P3".

[0210] <<<<<Correction Circuit 71d>>>>>

[0211] Figure 25 This is a diagram illustrating an example of a correction circuit 71d. The correction circuit 71d is obtained by adding a load detection circuit 180 to the correction circuit 71c.

[0212] <<<<Control of Oscillator Circuit 141 Based on On-Width Extension Circuit 193d>>>>

[0213] Figure 26This diagram illustrates an example of the oscillation circuit 141 and the on-width expansion circuit 193d. The on-width expansion circuit 193d is obtained by adding current sources 215d and 217d to the on-width expansion circuit 193c, allowing current to flow according to the voltage Vload, instead of the current sources 215d and 217d. Except that the current Ico varies according to the voltage Vload, the on-width expansion circuits 193c and 193d operate similarly. In this embodiment, when the load 11 becomes lightly loaded and the output voltage Vout rises, the voltage Vload decreases as the voltage Vcomp decreases. As a result, the on-time of the NMOS transistor 27 is shortened, and the input current Iin decreases. To correct and increase the input current Iin and improve the power factor, the on-width expansion circuit 193d controls the current sources 215d and 217d according to the voltage Vload to increase the current Ico. As a result, the slope of the ramp wave Vr decreases, the period during which the drive signal Vp1 is at the "H" level becomes longer, and the input current Iin increases. However, the operation used to correct the input voltage Iin according to the load condition is not limited to this.

[0214] Therefore, the lighter the load 11 becomes, the higher the output voltage Vout will rise. This can suppress the decrease in input current Iin caused by the decrease in the difference between the effective value of AC voltage Vac and output voltage Vout, and can appropriately change the input current Iin and improve the power factor.

[0215] <<<<<Correction Circuit 71e>>>>>

[0216] Figure 27 This diagram illustrates an example of the correction circuit 71e. The correction circuit 71e is a circuit obtained by combining the correction circuits 71a and 71d. The individual circuits of the correction circuit 71e operate as described so far.

[0217] Furthermore, the power factor improvement IC26 uses correction circuit 71e for correction circuit 71, conduction signal output circuit 81 for conduction signal output circuit 80, and shutdown signal output circuit 82e for shutdown signal output circuit 82. The structure of shutdown signal output circuit 82e is as follows: Figure 28 As shown. The circuits of the shutdown signal output circuit 82e operate as described so far.

[0218] ===Transformation Examples===

[0219] In this embodiment, an example is described in which the power factor improvement IC 26, obtained by combining the correction circuit 71a and the turn-off signal output circuit 82a, charges the COMP terminal with current I1 according to the phase angle of the voltage Vh. However, the conduction period of the NMOS transistor 27 can also be changed by altering the slope of the ramp waveform Vr according to the phase angle of the voltage Vh.

[0220] Furthermore, in this embodiment, an example is described where, in the power factor improvement IC 26 obtained by combining the correction circuit 71a and the turn-off signal output circuit 82a, the terminal COMP is charged with current I1 according to the phase angle of the voltage Vh. However, the voltage of the terminal COMP can also be adjusted by adjusting the reference voltage VREF2 of the error output circuit 142 according to the phase angle of the voltage Vh, thereby changing the conduction period of the NMOS transistor 27.

[0221] Furthermore, in this embodiment, the conduction period of the NMOS transistor 27 is adjusted by PWM control. However, the conduction period of the NMOS transistor 27 can also be adjusted by PFM control.

[0222] Furthermore, in this embodiment, it has been described that the adjustment circuit 54 changes the reference signal VREF2 input to the error output circuit 142 based on the signal Venb0. However, the adjustment circuit 54 may also change the feedback voltage Vfb input to the error output circuit 142 based on the signal Venb0.

[0223] In addition, comparators 151 and 191 are used in this embodiment to detect the phase angle of the AC voltage Vac, but hysteresis comparators with a high reference voltage VREF4 and a low reference voltage VREF5 can also be used to detect the high and low voltage levels of the voltage Vhdiv.

[0224] ===Summary===

[0225] (1) The AC-DC converter 10 of this embodiment has been described above. The identification circuit 51 identifies whether the effective value of the AC voltage Vac is 100V or 200V. When the effective value of the AC voltage Vac is 200V, the input current decreases because the voltage difference between the input voltage and the output voltage of the AC-DC converter 10 becomes smaller. Compared to the decrease in input current, the proportion of the charging current to the capacitor 22 increases, and the distortion of the input current becomes significant. Therefore, the power factor improvement IC 26 corrects the input current based on the identification of the effective value of the AC voltage Vac by the identification circuit 51. That is, an integrated circuit can be provided that appropriately changes the input current, suppresses total harmonic distortion, and improves the power factor.

[0226] (2) Furthermore, by switching the effective / ineffective state of the correction circuit 71 based on the identification result of the identification circuit 51, control can be performed to correct the input current when power factor improvement is required. Over-correction of the input current can be avoided when power factor improvement is not required.

[0227] (3) Furthermore, when the phase angle of voltage Vh is greater than the phase angle θ1, the correction circuit 71a causes the drive signal output circuit 72 to output a drive signal Vp1, so that the period during which NMOS transistor 27 is turned on becomes a "period P2" that is longer than "period P1". As a result, the AC-DC converter 10 receives an increased input current Iin from the commercial power supply. Then, the distortion of the input current Iin of the AC-DC converter 10 is eliminated. Thus, the waveforms of the AC voltage Vac and the input current Iin can be made to have similar shapes.

[0228] (4) Furthermore, in the detection of the phase angle of voltage Vh based on the voltage of terminal VH, comparator 151 is used, and a timer is used to time the "specified period P0". Thus, the power factor can be improved without using an AD converter, and the power factor improvement IC26 can operate with low power consumption.

[0229] (5) Furthermore, the shutdown signal output circuit 82a changes the output timing of the shutdown signal Sr of the NMOS transistor according to the phase angle of the voltage Vh. As a result, the power factor improvement IC26 can improve the distortion of the input current Iin without changing the timing of the output of the turn-on signal Ss for turning on the NMOS transistor 27.

[0230] (6) In addition, by using current to charge capacitors 33 and 34 via terminal COMP, the timing of the output turn-off signal Sr can be prevented from changing drastically.

[0231] (7) In addition, the identification circuit 51 identifies whether the effective value of the AC voltage Vac is 100V, 200V or 277V. When the effective value of the AC voltage Vac is 277V, compared with the case of an effective value of 200V, by further strengthening the correction of the input current, the decrease in power factor that accompanies the decrease in the voltage difference between the input voltage and the output voltage can be suppressed.

[0232] (8) Furthermore, when the load condition is light, the required input current Iin decreases, and the ratio of current Icap (e.g., charging current) to input current Iin increases. Therefore, when the load condition indicates a light load, the load detection circuit 180 is corrected to further increase the input current Iin, thereby improving the power factor when the load condition is light.

[0233] (9) Furthermore, since the phase angle detection is more accurate by rectifying the AC voltage Vac from the front node of the full-wave rectifier circuit 21, it is not affected by the capacitor 22, and the level of voltage Vh is more accurately equivalent to the forward voltage of at least one diode than the rectified voltage Vrec via the full-wave rectifier circuit 21. Moreover, the conduction period of the NMOS transistor 27 can be controlled based on the accurate voltage Vh.

[0234] (10) The voltage at terminal VH can also be used in the cut-off detection circuit 55 for detecting the cut-off of AC voltage Vac. The discharge circuit 56 can discharge the capacitors 41, 43 to 45 of the input line filter.

[0235] (11) Furthermore, the power factor improvement IC26 has a voltage divider circuit 50, so that the comparator 151 can detect the phase angle of the voltage Vh based on the divided voltage Vhdiv. In addition, using the divided voltage Vhdiv prevents high voltage from being applied to the power factor improvement IC26, and eliminates the need for a high-voltage process in manufacturing the power factor improvement IC26. The resistance value of the voltage divider circuit 50 is relatively large to suppress current consumption during normal operation, but the resistance value of the resistor 125 in the discharge circuit 56 can be reduced as long as it protects the NMOS transistor 124.

[0236] (12) In addition, the frequency identification circuit 52 identifies the frequency of the AC voltage Vac and switches the clock signal CLK used in the counter 162 according to the frequency of the AC voltage Vac.

[0237] (13) In addition, the timer 152 can accurately time the timing of the phase angle of voltage Vh changing to phase angle θ2, regardless of the frequency of AC voltage Vac.

[0238] (14) In addition, the adjustment circuit 54 can suppress the rise of the output voltage Vout caused by the correction of the input current.

[0239] (15) Furthermore, the adjustment circuit 54 can suppress the rise of the output voltage Vout by switching the reference voltage corresponding to the target level to a reference voltage corresponding to a specified level lower than the target level. In particular, by using the correction circuit 71a to add current to the terminal COMP to make the voltage Vcomp higher, the switching control is changed, and the output voltage VOUT is controlled to be higher than necessary. This can be suppressed by switching the reference voltage.

[0240] (16) Furthermore, the phase angle θ1 is a phase angle determined based on the capacitance value of capacitor 22, and the phase angle θ2 is greater than the phase angle θ1 and less than 180 degrees. Thus, it is possible to correct the input current Iin after the charging current flowing in capacitor 22 becomes less than or equal to a specified value Ib.

[0241] (17) In addition, the AC-DC converter 10 can provide suppression of total harmonic distortion and improvement of power factor by including identification circuit 51 and signal output circuit 57.

[0242] (18) In addition, the power factor improvement IC26 can also provide suppression of total harmonic distortion and improvement of power factor by having a circuit structure corresponding to the correction circuit 71a.

[0243] (19) Furthermore, the AC-DC converter 10, by having a circuit structure corresponding to the correction circuit 71a, can provide suppression of total harmonic distortion and improvement of power factor.

[0244] (20) In addition, the correction circuit 71c stops the switching of the NMOS transistor 27 during the period when the phase angle of the AC voltage Vac changes from the phase angle θa to θb, so that the input current Iin is close to the current Icap, thereby correcting the input current Iin.

[0245] (21) Furthermore, during the period from phase angle θb to θc, the correction circuit 71c causes the drive signal output circuit 72 to output a drive signal Vp1 that turns off the NMOS transistor 27 for a specified period. As a result, the correction circuit 71c gradually increases the inductor current to suppress distortion of the input current Iin.

[0246] (22) Furthermore, during the period from phase angle θc to θd, the correction circuit 71c causes the drive signal output circuit 72 to output a drive signal Vp1 that prolongs the period during which the NMOS transistor 27 is turned on. Thus, the correction circuit 71c corrects the input current Iin.

[0247] (23) Furthermore, the oscillation circuit 141 adjusts the slope of the ramp wave Vr by adjusting the current Iramp flowing through the capacitor 222, thereby lengthening the period during which the NMOS transistor 27 is turned on. This allows the slope of the ramp wave Vr to be adjusted only when control of the conduction width expansion circuit 193c is required, and enables fine adjustments to the slope of the ramp wave Vr.

[0248] (24) In addition, the correction circuit 71d includes a load detection circuit 180, which can control the oscillation circuit 141 according to the state of the load.

[0249] (25) In addition, the identification circuit 51 identifies whether the effective value of the AC voltage Vac is 100V, 200V or 277V.

[0250] (26) Furthermore, in the detection of the phase angle of voltage Vh based on the voltage at terminal VH, comparator 191 is used, and timer 192 is used to output signals Sstop, Srst, and Son_expd. Thus, the power factor can be improved without using an AD converter, and the power factor improvement IC26 can operate with low power consumption.

[0251] (27) In addition, the frequency identification circuit 52 identifies the frequency of the AC voltage Vac and switches the clock signal CLK used in the timer 192 according to the frequency of the AC voltage Vac.

[0252] (28) Furthermore, since the effect of capacitor 22 does not exist, the phase angle detection becomes more accurate by using the voltage Vh obtained by rectifying the AC voltage Vac from the front node of the full-wave rectifier circuit 21.

[0253] (29) In addition, the voltage at terminal VH can also be used in the cut-off detection circuit 55 that detects the cut-off of AC voltage Vac. The discharge circuit 56 can discharge the capacitors 41, 43 to 45 of the input line filter.

[0254] (30) In addition, the power factor improvement IC26 has a voltage divider circuit 50.

[0255] (31) Furthermore, by correcting the input current Iin during the period when the charging current flows through the capacitor 22, total harmonic distortion suppression and power factor improvement can be provided.

[0256] (32) In addition, the adjustment circuit 54 can suppress the rise of the output voltage Vout caused by the correction of the input current.

[0257] (33) In addition, the adjustment circuit 54 can suppress the rise of the output voltage Vout by switching the reference voltage corresponding to the target level to a reference voltage corresponding to a specified level lower than the target level.

[0258] (34) In addition, the power factor improvement IC26 can also provide suppression of total harmonic distortion and improvement of power factor by having a circuit structure corresponding to the correction circuit 71c.

[0259] (35) Furthermore, the AC-DC converter 10, by having a circuit structure corresponding to the correction circuit 71c, can provide suppression of total harmonic distortion and improvement of power factor.

[0260] (36) In addition, the load detection circuit 180 can correct the input current Iin corresponding to the state of the load.

[0261] (37) In addition, the identification circuit 51 identifies whether the effective value of the AC voltage Vac is 100V, 200V or 277V.

[0262] (38) In addition, the identification circuit 51 can identify the effective value of the AC voltage Vac based on the voltage of the terminal VH.

[0263] (39) In addition, the voltage at terminal VH can also be used in the cut-off detection circuit 55 that detects the cut-off of AC voltage Vac. The discharge circuit 56 can discharge the capacitors 41, 43 to 45 of the input line filter.

[0264] (40) In addition, the power factor improvement IC26 has a voltage divider circuit 50.

[0265] (41) In addition, the power factor improvement IC26 can also provide suppression of total harmonic distortion and improvement of power factor by having a circuit structure corresponding to the load detection circuit 180.

[0266] (42) Furthermore, the AC-DC converter 10, by having a circuit structure corresponding to the load detection circuit 180, can provide suppression of total harmonic distortion and improvement of power factor.

[0267] (43) In addition, the adjustment circuit 54 can suppress the rise of the output voltage Vout caused by the correction of the input current.

[0268] (44) In addition, the adjustment circuit 54 can suppress the rise of the output voltage Vout by switching the reference voltage corresponding to the target level to a reference voltage corresponding to a specified level lower than the target level.

[0269] (45) In addition, the power factor improvement IC26 can also provide suppression of total harmonic distortion and improvement of power factor by having a circuit structure corresponding to the adjustment circuit 54.

[0270] (46) Furthermore, the AC-DC converter 10, by having a circuit structure corresponding to the adjustment circuit 54, can provide suppression of total harmonic distortion and improvement of power factor.

[0271] The above embodiments are provided to facilitate understanding of the present invention, but are not intended to limit or explain the present invention. Furthermore, modifications and improvements can be made to the present invention without departing from its spirit, and equivalent inventions are naturally included within the scope of the present invention.

[0272] Label Explanation

[0273] 10 AC-DC converter

[0274] 11 Load

[0275] 20 Input Line Filter

[0276] 21 Full-wave rectifier circuit

[0277] Capacitors 22, 25, 33, 34, 41, 43, 44, 45, 183, 222

[0278] 23 Transformers

[0279] Diodes 24, 28, and 29

[0280] 27, 124, 182, 224 NMOS transistors

[0281] 30, 31, 32, 60, 61, 125 resistors

[0282] 42 Choke coil

[0283] 50V divider circuit

[0284] 51 Identification Circuit

[0285] 52 Frequency Identification Circuit

[0286] 53 Switching circuit

[0287] 54 Adjustment Circuit

[0288] 55. Disconnect the detection circuit.

[0289] 56 Discharge Circuit

[0290] 57 Signal Output Circuit

[0291] 58 drive circuit

[0292] Correction circuits 71, 71a, 71b, 71c, 71d, 71e

[0293] 72 Drive signal output circuit

[0294] 80, 81 Conductor signal output circuit

[0295] 82, 82a, 82b, 82c, 82e Shutdown signal output circuits

[0296] 83, 161 SR triggers

[0297] Comparators 91, 93, 121, 143, 151, 191

[0298] 92, 94, 102, 122, 123, 152, 192, 203 Timers

[0299] 101 Toggle (T) Trigger

[0300] Inverters 111, 112, 171, and 223

[0301] 113, 114 Transmission Gates

[0302] 131 Zero Current Detection Circuit

[0303] 132 Delay Circuit

[0304] 133 On Timer

[0305] 134, 145, 172, 173, 174, 202, 204, 212 OR circuits

[0306] 141 Oscillating Circuit

[0307] 142 Error Output Circuit

[0308] Current sources 144a, 144b, 175a, 175b, 177a, 177b, 215c, 215d, 217c, 217d, 221

[0309] 162 counter

[0310] 176, 178 PMOS transistors

[0311] 180 Load Detection Circuit

[0312] 181 Single-trigger timer

[0313] 193c, 193d conduction width expansion circuit

[0314] 201, 211, 213 AND circuits

[0315] Switches 214 and 216.

Claims

1. An integrated circuit for switching transistors in a power supply circuit, the power supply circuit including a first capacitor and an inductor to which a voltage corresponding to an AC voltage is applied, and the transistor controlling the inductor current flowing through the inductor, and generating an output voltage of a target level according to the AC voltage, characterized in that, include: An identification circuit that identifies whether the effective value of the AC voltage is a first level or a second level higher than the first level; as well as A signal output circuit that outputs a drive signal to drive the transistor when the effective voltage level is the first level, and corrects and outputs the drive signal to correct the input current to the power supply circuit when the effective voltage level is the second level.

2. The integrated circuit as described in claim 1, characterized in that, The signal output circuit includes: A drive signal output circuit, which outputs the drive signal based at least on a feedback voltage corresponding to the output voltage and a reference voltage corresponding to the target level; and A correction circuit is provided that, when the effective voltage level is the first level, the drive signal output circuit stops correcting the drive signal, and when the effective voltage level is the second level, the drive signal output circuit corrects the drive signal.

3. The integrated circuit as described in claim 2, characterized in that, When the effective voltage level is the second level and the phase angle of the AC voltage is between the first phase angle and the second phase angle, the correction circuit causes the drive signal output circuit to correct the drive signal so that the period during which the transistor is turned on is longer than when the phase angle is less than the first phase angle.

4. The integrated circuit as described in claim 3, characterized in that, The correction circuit includes: A first detection circuit detects whether the phase angle is greater than the first phase angle; and A first timing circuit, based on the detection result of the first detection circuit, times the correction time from when the phase angle changes from the first phase angle to the second phase angle. During the period when the first timing circuit times the correction time, the correction circuit causes the drive signal output circuit to correct the drive signal so that the period during which the transistor is turned on is longer than when the phase angle is less than the first phase angle.

5. The integrated circuit as described in claim 4, characterized in that, The drive signal output circuit includes: A turn-on signal output circuit that outputs a turn-on signal for turning on the transistor based on specified conditions; A shutdown signal output circuit, which outputs a shutdown signal for turning off the transistor based on the feedback voltage; and An output circuit that outputs the drive signal based on the on signal and the off signal. When the phase angle is between the first phase angle and the second phase angle, the correction circuit causes the shutdown signal output circuit to output the shutdown signal, so that the period during which the transistor is turned on is longer than when the phase angle is less than the first phase angle.

6. The integrated circuit as described in claim 5, characterized in that, The shutdown signal output circuit includes: A first charging circuit charges a second capacitor using an error current based on the feedback voltage and a reference voltage corresponding to the target level of the output voltage. A second charging circuit charges the second capacitor using a first current when the phase angle is between the first phase angle and the second phase angle. An oscillating circuit that outputs a triangular wave-shaped oscillating voltage when the specified conditions are met; and A comparator circuit that outputs the turn-off signal when the oscillation voltage becomes higher than the voltage of the second capacitor.

7. The integrated circuit as described in claim 6, characterized in that, The identification circuit identifies whether the voltage level of the effective value of the AC voltage is a third level that is higher than the second level. When the effective voltage level is the third level, the second charging circuit increases the first current when the effective voltage level is the second level.

8. The integrated circuit as described in claim 6 or 7, characterized in that, The correction circuit also includes a load detection circuit for detecting the state of the load on the power supply circuit. The second charging circuit changes the first current based on the detection result of the load detection circuit, so that the input current increases as the load state becomes light load.

9. The integrated circuit according to any one of claims 4 to 7, characterized in that, This includes a terminal to which a first rectified voltage from a first rectifier circuit that rectifies the AC voltage is applied. The identification circuit identifies the voltage level of the effective value based on the voltage at the terminal. The first detection circuit detects whether the phase angle is greater than the first phase angle based on the voltage of the terminal.

10. The integrated circuit as claimed in claim 9, characterized in that, It also includes: a cut-off detection circuit that detects whether the AC voltage is provided based on the voltage at the terminals; and A discharge circuit that discharges a third capacitor in an input line filter located between the node where the AC voltage is applied and a second rectifier circuit when the cut-off detection circuit detects that the AC voltage is not provided. The second rectifier circuit rectifies the AC voltage and applies a second rectified voltage to the first capacitor and the inductor.

11. The integrated circuit as claimed in claim 10, characterized in that, This includes a voltage divider circuit that divides the voltage at the terminals to generate a divided voltage. The discharge circuit includes: A switch that is turned on when the cut-off detection circuit detects that the AC voltage is not being provided; and A discharge resistor is provided between the switch and the third capacitor. The resistance value of the voltage divider circuit is greater than the resistance value of the discharge resistor.

12. The integrated circuit according to any one of claims 4 to 7, characterized in that, It also includes a frequency identification circuit that identifies whether the frequency of the AC voltage is a first frequency or a second frequency higher than the first frequency. When the frequency is the first frequency, the first timing circuit uses the first time from when the phase angle changes from the first phase angle to the second phase angle as the correction time for timing, and when the frequency is the second frequency, it uses the second time from when the phase angle changes from the first phase angle to the second phase angle as the correction time for timing.

13. The integrated circuit as claimed in claim 12, characterized in that, In the first timing circuit, When the frequency is the first frequency, the first time is timed using a first clock signal corresponding to the first frequency. When the frequency is the second frequency, the second time is timed using a second clock signal corresponding to the second frequency.

14. The integrated circuit according to any one of claims 3 to 7, characterized in that, It also includes an adjustment circuit that, when the voltage level of the effective value is the second level, changes at least one of the feedback voltage and the reference voltage to make the target level of the output voltage lower.

15. The integrated circuit as claimed in claim 14, characterized in that, The adjustment circuit switches the reference voltage from a first voltage corresponding to the target level to a second voltage corresponding to a specified level lower than the target level.

16. The integrated circuit according to any one of claims 3 to 7, characterized in that, The first phase angle is determined based on the capacitance value of the first capacitor. The second phase angle is greater than the first phase angle but less than 180 degrees.

17. The integrated circuit as claimed in claim 2, characterized in that, When the effective voltage level is the second level, the correction circuit stops the drive signal output circuit from outputting the drive signal until the phase angle of the AC voltage changes from the third phase angle to the fourth phase angle. After the phase angle changes to the fourth phase angle, the drive signal output circuit outputs the drive signal.

18. The integrated circuit as claimed in claim 17, characterized in that, The correction circuit, from the time the phase angle becomes the fourth phase angle until the time the phase angle becomes the fifth phase angle, causes the drive signal output circuit to output the drive signal that turns off the transistor for a predetermined period.

19. The integrated circuit as claimed in claim 18, characterized in that, In the drive signal output circuit Based on the feedback voltage and the reference voltage, a drive signal is output that enables the transistor to conduct during a first period. The correction circuit, from the time the phase angle becomes the fifth phase angle until the time the phase angle becomes the sixth phase angle, causes the drive signal output circuit to output a drive signal for a second period that makes the transistor conduct for a longer period than the first period.

20. The integrated circuit as claimed in claim 19, characterized in that, The drive signal output circuit includes: A turn-on signal output circuit that outputs a turn-on signal for turning on the transistor based on specified conditions; A shutdown signal output circuit that outputs a shutdown signal for turning off the transistor based on the feedback voltage; An output circuit that outputs the drive signal based on the on signal and the off signal; and A control circuit, during the period from the third phase angle to the fourth phase angle, causes the output circuit to output a drive signal that turns off the transistor. The shutdown signal output circuit includes: A first charging circuit charges a second capacitor using an error current corresponding to the feedback voltage. An oscillating circuit that outputs a triangular wave-shaped oscillating voltage when the specified conditions are met; and A comparator circuit that outputs the turn-off signal when the oscillation voltage becomes higher than the voltage of the second capacitor. The oscillation circuit outputs the oscillation voltage during the period from the fifth phase angle to the sixth phase angle, such that the period during which the transistor is turned on is longer, at least compared to the period from the fourth phase angle to the fifth phase angle.

21. The integrated circuit as claimed in claim 20, characterized in that, The correction circuit also includes a load detection circuit for detecting the state of the load on the power supply circuit. Based on the detection results of the load detection circuit, the oscillation circuit outputs an oscillation voltage that increases the input current as the load state changes to a light load.

22. The integrated circuit as claimed in claim 20 or 21, characterized in that, The identification circuit identifies whether the voltage level of the effective value of the AC voltage is a third level that is higher than the second level. When the effective voltage level is the third level, the oscillation circuit outputs an oscillation voltage that further lengthens the period during which the transistor is turned on.

23. The integrated circuit as claimed in claim 20 or 21, characterized in that, The correction circuit includes: A second detection circuit detects whether the phase angle is greater than the third phase angle; and The second timing circuit, based on the detection result of the second detection circuit, times the first to fourth timings corresponding to the timing when the phase angle changes from the third phase angle to the sixth phase angle.

24. The integrated circuit as claimed in claim 23, characterized in that, It also includes a frequency identification circuit that identifies whether the frequency of the AC voltage is a first frequency or a second frequency higher than the first frequency. In the second timing circuit, When the frequency is the first frequency, the first timing to the fourth timing is performed using a first clock signal corresponding to the first frequency. When the frequency is the second frequency, the first timing to the fourth timing is timed using a second clock signal corresponding to the second frequency.

25. The integrated circuit as claimed in claim 23, characterized in that, This includes a terminal to which a first rectified voltage from a first rectifier circuit that rectifies the AC voltage is applied. The identification circuit identifies the voltage level of the effective value based on the voltage at the terminal. The second detection circuit detects whether the phase angle is greater than the third phase angle based on the voltage of the terminal.

26. The integrated circuit as claimed in claim 25, characterized in that, It also includes: a cut-off detection circuit that detects whether the AC voltage is provided based on the voltage at the terminals; and A discharge circuit that discharges a third capacitor in an input line filter located between the node where the AC voltage is applied and a second rectifier circuit when the cut-off detection circuit detects that the AC voltage is not provided. The second rectifier circuit rectifies the AC voltage and applies a second rectified voltage to the first capacitor and the inductor.

27. The integrated circuit as claimed in claim 26, characterized in that, This includes a voltage divider circuit that divides the voltage at the terminals to generate a divided voltage. The discharge circuit includes: A switch that is turned on when the cut-off detection circuit detects that the AC voltage is not being provided; and A discharge resistor is provided between the switch and the third capacitor. The resistance value of the voltage divider circuit is greater than the resistance value of the discharge resistor.

28. The integrated circuit according to any one of claims 19 to 21, characterized in that, The third phase angle is a phase angle greater than 0 degrees. The sixth phase angle is less than 90 degrees and is a phase angle that causes the charging current to the first capacitor to be less than a predetermined value.

29. The integrated circuit according to any one of claims 17 to 21, characterized in that, It also includes an adjustment circuit that, when the voltage level of the effective value is the second level, changes at least one of the feedback voltage and the reference voltage to make the target level of the output voltage lower.

30. The integrated circuit as claimed in claim 29, characterized in that, The adjustment circuit switches the reference voltage from a first voltage corresponding to the target level to a second voltage corresponding to a specified level lower than the target level.

31. The integrated circuit as described in claim 2, characterized in that, The correction circuit also includes a load detection circuit for detecting the state of the load on the power supply circuit. The drive signal output circuit corrects the drive signal based on the detection result of the load detection circuit, so that the input current increases as the load state becomes light load.

32. The integrated circuit as claimed in claim 31, characterized in that, The identification circuit identifies whether the voltage level of the effective value of the AC voltage is a third level that is higher than the second level. When the effective voltage level is the third level, the drive signal output circuit corrects the drive signal so that the input current increases further as the load state becomes light load.

33. The integrated circuit as described in claim 31 or 32, characterized in that, This includes a terminal to which a first rectified voltage from a first rectifier circuit that rectifies the AC voltage is applied. The identification circuit identifies the voltage level of the effective value based on the voltage of the terminal.

34. The integrated circuit as described in claim 33, characterized in that, It also includes: a cut-off detection circuit that detects whether the AC voltage is provided based on the voltage at the terminals; and A discharge circuit that discharges a third capacitor in an input line filter located between the node where the AC voltage is applied and a second rectifier circuit when the cut-off detection circuit detects that the AC voltage is not provided. The second rectifier circuit rectifies the AC voltage and applies a second rectified voltage to the first capacitor and the inductor.

35. The integrated circuit as described in claim 34, characterized in that, This includes a voltage divider circuit that divides the voltage at the terminals to generate a divided voltage. The discharge circuit includes: A switch that is turned on when the cut-off detection circuit detects that the AC voltage is not being provided; and A discharge resistor is provided between the switch and the third capacitor. The resistance value of the voltage divider circuit is greater than the resistance value of the discharge resistor.

36. The integrated circuit as claimed in claim 2, characterized in that, It also includes an adjustment circuit that, when the voltage level of the effective value is the second level, changes at least one of the feedback voltage and the reference voltage to make the target level of the output voltage lower.

37. The integrated circuit as claimed in claim 36, characterized in that, The adjustment circuit switches the reference voltage from a first voltage corresponding to the target level to a second voltage corresponding to a specified level lower than the target level.

38. A power supply circuit that generates a target level output voltage based on an AC voltage, characterized in that it comprises: A first capacitor and an inductor having a voltage corresponding to the AC voltage applied to them; A transistor that controls the inductor current flowing through the inductor; An identification circuit that identifies whether the effective value of the AC voltage is a first level or a second level higher than the first level; as well as A signal output circuit that outputs a drive signal to drive the transistor when the effective voltage level is the first level, and corrects and outputs the drive signal to correct the input current to the power supply circuit when the effective voltage level is the second level.

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