A debugging method, device, equipment and computer-readable storage medium

Abstract

The present invention discloses a debugging method. In this application, a hardware-accelerated simulation platform can be used to simulate and generate a SoC chip under test and an auxiliary controller in advance. Next, the auxiliary controller can be used to control the initialization configuration of the UART interface of the SoC chip under test. Furthermore, the auxiliary controller can be used to transmit test data to the UART interface of the SoC chip under test and receive the output data fed back by the SoC chip under test. Since the main body for UART debugging in this application only includes a hardware-accelerated simulation platform and a test terminal, the structure is relatively simple and the cost is relatively low. The present invention also discloses a debugging device, equipment and computer-readable storage medium, which have the same beneficial effects as the above debugging method.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and in particular to a debugging method. The present invention also relates to a debugging device, equipment and computer-readable storage medium. Background Art

[0002] With the improvement of chip complexity, verification testing has become increasingly important. The improvement and enhancement of chip performance, etc., not only occur in the design process, but also are continuously iterated in the chip debugging and verification processes; UART (Universal Asynchronous Receiver / Transmitter) debugging is of great significance in the design and verification of SoC (System on Chip) chips. Especially in the co- debugging of software and hardware of complex SoCs, it is usually used as the receiving and transmitting interface for debugging information. Its configuration is simple and the stability is high, which can well meet the transmission task of string information. However, there is a lack of a mature debugging method in the prior art, resulting in a relatively complex architecture and high cost of the debugging system.

[0003] Therefore, how to provide a solution to the above technical problems is what those skilled in the art need to solve currently. Summary of the Invention

[0004] The purpose of the present invention is to provide a debugging method. Since the main body for UART debugging in this application only includes a hardware acceleration simulation platform and a test terminal, the structure is relatively simple and the cost is low; another purpose of the present invention is to provide a debugging device, equipment and computer-readable storage medium. Since the main body for UART debugging in this application only includes a hardware acceleration simulation platform and a test terminal, the structure is relatively simple and the cost is low.

[0005] To solve the above technical problems, the present invention provides a debugging method, including:

[0006] Pre- simulate and generate a to- be- tested SoC chip and an auxiliary controller in a hardware acceleration simulation platform;

[0007] In response to a test start command, control the to- be- tested SoC chip in the hardware acceleration simulation platform to start;

[0008] Control the Universal Asynchronous Receiver / Transmitter (UART) interface of the to- be- tested SoC chip to perform initialization configuration through the auxiliary controller;

[0009] Transmit test data to the UART interface of the to- be- tested SoC chip through the auxiliary controller, and receive the output data fed back by the to- be- tested SoC chip through the UART interface, so as to complete the test.

[0010] Preferably, the specific steps of pre-simulating and generating the SoC chip under test and the auxiliary controller in the hardware acceleration simulation platform are as follows:

[0011] Load the simulation top-level file containing the auxiliary controller program and the design under test (DUT) of the SoC chip under test into the hardware acceleration simulation platform in advance;

[0012] Call the automated test tool UTF script of the hardware acceleration simulation platform in advance to convert the simulation top-level file into data adapted to the hardware acceleration simulation platform and form a database;

[0013] Load the startup file of the SoC chip under test into the SoC chip under test in the hardware acceleration simulation platform in advance so that the SoC chip under test can be started.

[0014] Preferably, the specific steps of initializing and configuring the UART interface of the SoC chip under test through the auxiliary controller are as follows:

[0015] Run the dynamic link library pre-built to include the parameter configuration program and the software test program, so as to control the UART interface of the SoC chip under test to perform initialization configuration through the auxiliary controller and transmit test data to the UART interface of the SoC chip under test through the auxiliary controller.

[0016] Preferably, the auxiliary controller is a transaction-level processor.

[0017] Preferably, after transmitting test data to the UART interface of the SoC chip under test through the auxiliary controller and receiving the output data fed back by the SoC chip through the UART interface, the debugging method further includes:

[0018] Control the prompt to prompt the output data.

[0019] Preferably, the specific step of controlling the prompt to prompt the output data is as follows:

[0020] Control the printer to print the output data.

[0021] Preferably, after transmitting test data to the UART interface of the SoC chip under test through the auxiliary controller and receiving the output data fed back by the SoC chip through the UART interface, the debugging method further includes:

[0022] Judge whether the output data is received within a preset time period;

[0023] If not, control the alarm to alarm.

[0024] To solve the above technical problems, the present invention also provides a debugging device, including:

[0025] A pre-generation module, configured to pre-simulate and generate a SoC chip under test and an auxiliary controller in a hardware-accelerated simulation platform;

[0026] A control module, configured to control the start of the SoC chip under test in the hardware-accelerated simulation platform in response to a test start command;

[0027] An initialization configuration module, configured to control the UART interface of the SoC chip under test to perform initialization configuration through the auxiliary controller;

[0028] A test module, configured to transmit test data to the UART interface of the SoC chip under test through the auxiliary controller, and receive output data fed back by the SoC chip under test through the UART interface, so as to complete the test.

[0029] To solve the above technical problems, the present invention also provides a debugging device, including:

[0030] A memory, configured to store a computer program;

[0031] A processor, configured to implement the steps of the above-mentioned debugging method when executing the computer program.

[0032] To solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned debugging method are implemented.

[0033] The present invention provides a debugging method. In the present application, a SoC chip under test and an auxiliary controller can be pre-simulated and generated in a hardware-accelerated simulation platform. Next, the UART interface of the SoC chip under test can be controlled through the auxiliary controller to perform initialization configuration. Furthermore, test data can be transmitted to the UART interface of the SoC chip under test through the auxiliary controller, and output data fed back by the SoC chip under test can be received. Since the main bodies for UART debugging in the present application only include a hardware-accelerated simulation platform and a test terminal, the structure is relatively simple and the cost is relatively low.

[0034] The present invention also provides a debugging device, equipment and computer-readable storage medium, which have the same beneficial effects as the above-mentioned debugging method. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A flowchart of a debugging method provided by the present invention;

[0037] Figure 2 A structural schematic diagram of a simulation device provided by the present invention;

[0038] Figure 3 A schematic diagram of the structure of a debugging system provided by the present invention;

[0039] Figure 4 A schematic diagram of the structure of a debugging device provided by the present invention;

[0040] Figure 5 A structural schematic diagram of a debugging device provided by the present invention. DETAILED DESCRIPTION

[0041] The core of the present invention is to provide a debugging method. Since the main body of the UART debugging in this application only includes a hardware acceleration simulation platform and a test terminal, the structure is relatively simple and the cost is low. Another core of the present invention is to provide a debugging device, equipment and computer-readable storage medium. Since the main body of the UART debugging in this application only includes a hardware acceleration simulation platform and a test terminal, the structure is relatively simple and the cost is low.

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Please refer to Figure 1 , Figure 1 A flowchart of a debugging method provided by the present invention, the debugging method comprising:

[0044] S101: Pre-simulating and generating a SoC chip to be tested and an auxiliary controller in a hardware acceleration simulation platform;

[0045] Specifically, considering the technical problems in the above background art and also considering that the simulation of the SoC chip can also be achieved by using a hardware-accelerated simulation platform, and the testing of the SoC chip can be carried out by combining a test terminal (host computer) with the hardware-accelerated simulation platform without other hardware parts, and the structure is relatively simple. Therefore, this application intends to implement the UART debugging of the SoC chip based on the hardware-accelerated simulation platform and the test terminal, and this application can be applied to the test terminal.

[0046] Specifically, if you want to conduct UART testing on the SoC chip based on the hardware-accelerated simulation platform, you need to simulate the SoC chip in the hardware-accelerated simulation platform. Since the SoC chip needs to be tested through UART debugging, but the hardware-accelerated simulation platform itself does not have a UART interface, it is also necessary to simulate an auxiliary controller in the hardware-accelerated simulation platform, and use the UART interface of the auxiliary controller to transmit data with the UART interface of the SoC chip to be tested to achieve UART debugging.

[0047] S102: In response to the test start command, control the SoC chip to be tested in the hardware-accelerated simulation platform to start;

[0048] Specifically, after the above steps, the test terminal can control the SoC chip to be tested in the hardware-accelerated simulation platform to start in response to the test start command, so as to carry out subsequent test work.

[0049] Specifically, in order for the SoC chip to be tested to start normally, it is also necessary to pre-load the bootloader startup loader and Image file into the ROM (Read-Only Memory) and RAM (Random Access Memory) of the SoC through commands in advance.

[0050] S103: Control the Universal Asynchronous Receiver / Transmitter (UART) interface of the SoC chip to be tested to perform initialization configuration through the auxiliary controller;

[0051] Specifically, after controlling the SoC chip to be tested to start, the UART test can be started next. Before the formal test, it is necessary to initialize the UART interface of the SoC chip to be tested so that normal communication can be carried out through the UART interface.

[0052] Specifically, the initialization configuration of the UART interface can include operations such as setting the word length, parity bit, stop bit, and setting the baud rate. The embodiments of the present invention do not limit this here.

[0053] S104: Transmit test data to the UART interface of the SoC chip under test through the auxiliary controller, and receive the output data fed back by the SoC chip under test through the UART interface to complete the test.

[0054] Specifically, after initializing and configuring the UART interface, the test can be carried out. The test terminal can transmit test data to the UART interface of the SoC chip under test through the auxiliary controller. Under normal circumstances, the SoC chip under test will feed back output data after receiving the test data. Then, the test terminal can receive the output data fed back by the SoC chip under test through the UART interface through the auxiliary controller. The output data can reflect the problems of the SoC chip under test, thereby completing the test.

[0055] The present invention provides a debugging method. In this application, the SoC chip under test and the auxiliary controller can be simulated and generated in the hardware acceleration simulation platform in advance. Next, the auxiliary controller can be used to control the initialization and configuration of the UART interface of the SoC chip under test. Furthermore, test data can be transmitted to the UART interface of the SoC chip under test through the auxiliary controller, and the output data fed back by the SoC chip can be received. Since the main bodies for UART debugging in this application only include the hardware acceleration simulation platform and the test terminal, the structure is relatively simple and the cost is relatively low.

[0056] To better illustrate the embodiments of the present invention, please refer to Figure 2 and Figure 3 , Figure 2 which is a schematic structural diagram of a simulation device provided by the present invention, Figure 3 which is a schematic structural diagram of a debugging system provided by the present invention. On the basis of the above embodiments:

[0057] As a preferred embodiment, the specific steps of simulating and generating the SoC chip under test and the auxiliary controller in the hardware acceleration simulation platform in advance are as follows:

[0058] Load the simulation top-level file including the auxiliary controller program and the DUT of the SoC chip under test into the hardware acceleration simulation platform in advance;

[0059] Call the automated test tool UTF script of the hardware acceleration simulation platform in advance to convert the simulation top-level file into data adapted to the hardware acceleration simulation platform and form a database;

[0060] Load the startup file of the SoC chip under test into the SoC chip under test in the hardware acceleration simulation platform in advance to start the SoC chip under test.

[0061] Specifically, the embodiments of the present invention introduce the content of building a hardware simulation environment. A simulation environment usually includes a BFM (Bus Function Model), a DUT (Design under test), clock and reset generation logic. These modules are uniformly encapsulated at the top level of the simulation. Generally, the top level of the simulation can be divided into two parts: the synthesizable part, which usually has a separate top level that is directly connected to the hardware simulation platform. The simulation model is generally non-synthesizable HVL (Hardware Verification Language) and runs on the simulator. All the top-level logics in this application are synthesizable. The encapsulated top-level simulation file is loaded into the hardware-accelerated simulation platform. By calling the UTF (Unicode Transformation Format) script file of the hardware-accelerated simulation platform, compilation parameters are added. After processes such as compilation, synthesis, partitioning, placement and routing, and bitstream generation, a database that can be linked and used during the runtime stage is finally generated.

[0062] Specifically, in Figure 2 , XTOR, that is, the transaction-level processor Transactor, and DUT, that is, the design under test of the SoC chip to be tested. Figure 3 The Sever / PC-side software test in

[0063] is also the test terminal. XTOR includes two parts: one part is the hardware part implemented in SystemVerilog (SV language), and the other part is the software part implemented in C / C++. The two parts use DPI (Direct Programming Interface) as the interaction interface to achieve mutual function calls and communications. The C / C++ testbench written by the test engineer controls the hardware part of XTOR by calling the API (Application Programming Interface) reserved on the software side of XTOR.

[0064] As a preferred embodiment, the specific operation of controlling the UART interface of the SoC chip to be tested by the auxiliary controller is as follows:

[0065] Specifically, the software test code can be compiled with the testbench (parameter configuration program) through the g++ compiler to generate a dynamic link library.so file. Then, during the establishment of the runtime environment, the test terminal can execute the dynamic link library.so file. First, initialize and configure the UART between the auxiliary processor and the SoC under test through the software API. After that, the auxiliary controller can be used to initialize and configure the UART interface of the SoC under test and transmit test data to the UART interface of the SoC under test through the auxiliary controller.

[0066] As a preferred embodiment, the auxiliary controller is a transaction-level processor.

[0067] Specifically, the transaction-level processor Transactor has advantages such as strong stability and strong processing ability.

[0068] Of course, in addition to the transaction-level processor, the auxiliary controller can also be of other types, which are not limited in the embodiments of the present invention.

[0069] As a preferred embodiment, after transmitting test data to the UART interface of the SoC under test through the auxiliary controller and receiving the output data fed back by the SoC under test through the UART interface, the debugging method further includes:

[0070] Controlling the prompter to prompt the output data.

[0071] Specifically, in order to facilitate the user to learn the output data in the first time, in the embodiments of the present invention, the prompter can be controlled to prompt the output data, which is beneficial to improving work efficiency.

[0072] As a preferred embodiment, controlling the prompter to prompt the output data specifically is:

[0073] Controlling the printer to print the output data.

[0074] Specifically, controlling the printer to print the output data is more convenient for the user to analyze the output data.

[0075] Of course, in addition to this specific method, controlling the prompter to prompt the output data can also be of other types, which are not limited in the embodiments of the present invention.

[0076] As a preferred embodiment, after transmitting test data to the UART interface of the SoC under test through the auxiliary controller and receiving the output data fed back by the SoC under test through the UART interface, the debugging method further includes:

[0077] Judging whether the output data is received within a preset time period;

[0078] If not, controlling the alarm to alarm.

[0079] Specifically, considering that the SoC chip under test will not feedback and output data in case of abnormality, in the embodiments of the present invention, an alarm can be controlled to alarm when no output data is received within a preset duration, so that users can respond more efficiently and further improve work efficiency.

[0080] Among them, the alarm can be of various types. For example, it can be a buzzer, etc., and the embodiments of the present invention do not limit this here.

[0081] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a debugging device provided by the present invention. The debugging device includes:

[0082] A pre-generation module 41, configured to pre-simulate and generate a SoC chip under test and an auxiliary controller in a hardware acceleration simulation platform;

[0083] A control module 42, configured to control the start of the SoC chip under test in the hardware acceleration simulation platform in response to a test start command;

[0084] An initialization configuration module 43, configured to control the UART interface of the SoC chip under test to perform initialization configuration through the auxiliary controller;

[0085] A test module 44, configured to transmit test data to the UART interface of the SoC chip under test through the auxiliary controller and receive the output data feedback by the SoC chip through the UART interface, so as to complete the test.

[0086] For the introduction of the debugging device provided by the embodiments of the present invention, please refer to the embodiments of the foregoing debugging method, and the embodiments of the present invention will not be elaborated here.

[0087] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of a debugging device provided by the present invention. The debugging device includes:

[0088] A memory 51, configured to store a computer program;

[0089] A processor 52, configured to implement the steps of the debugging method in the foregoing embodiments when executing the computer program.

[0090] For the introduction of the debugging device provided by the embodiments of the present invention, please refer to the embodiments of the foregoing debugging method, and the embodiments of the present invention will not be elaborated here.

[0091] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the debugging method in the foregoing embodiments are implemented.

[0092] For the introduction of the computer-readable storage medium provided by the embodiments of the present invention, please refer to the embodiments of the foregoing debugging method, which will not be elaborated herein.

[0093] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section. It should also be noted that in this specification, the terms "comprise", "include" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising that element.

[0094] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A debugging method, characterized in that, Including: Pre-simulate and generate a System-on-Chip (SoC) chip to be tested and an auxiliary controller in a hardware-accelerated simulation platform; In response to a test start command, control the SoC chip to be tested in the hardware-accelerated simulation platform to start; Control the Universal Asynchronous Receiver-Transmitter (UART) interface of the SoC chip to be tested for initialization configuration through the auxiliary controller; Transmit test data to the UART interface of the SoC chip to be tested through the auxiliary controller, and receive the output data fed back by the SoC chip through the UART interface to complete the test.

2. The debugging method according to claim 1, characterized in that, The pre-simulating and generating a System-on-Chip (SoC) chip to be tested and an auxiliary controller in a hardware-accelerated simulation platform specifically is: Pre-load a simulation top-level file including an auxiliary controller program and a Design Under Test (DUT) of the SoC chip to be tested into the hardware-accelerated simulation platform; Pre-call the automated test tool UTF script of the hardware-accelerated simulation platform to convert the simulation top-level file into data adapted to the hardware-accelerated simulation platform and form a database; Pre-load the startup file of the SoC chip to be tested into the SoC chip to be tested in the hardware-accelerated simulation platform so that the SoC chip to be tested can be started.

3. The debugging method according to claim 2, wherein The controlling the UART interface of the SoC chip to be tested for initialization configuration through the auxiliary controller specifically is: Run a dynamically linked library pre-built including a parameter configuration program and a software test program, so as to control the UART interface of the SoC chip to be tested for initialization configuration through the auxiliary controller and transmit test data to the UART interface of the SoC chip to be tested through the auxiliary controller.

4. The debugging method according to claim 1, characterized in that The auxiliary controller is a transaction-level processor.

5. The debugging method according to claim 1, wherein After transmitting test data to the UART interface of the SoC chip to be tested through the auxiliary controller and receiving the output data fed back by the SoC chip through the UART interface, the debugging method further includes: Control a prompter to prompt the output data.

6. The debugging method according to claim 5, wherein The controlling a prompter to prompt the output data specifically is: Control a printer to print the output data.

7. The debugging method according to any one of claims 1 to 6, characterized in that After transmitting test data to the UART interface of the SoC chip to be tested through the auxiliary controller and receiving the output data fed back by the SoC chip through the UART interface, the debugging method further includes: Judge whether the output data is received within a preset time period; If not, control an alarm to give an alarm.

8. A debugging device, characterized in that, Including: A pre-generation module, used for pre-simulating and generating a System-on-Chip (SoC) chip to be tested and an auxiliary controller in a hardware-accelerated simulation platform; A control module, used for controlling the SoC chip to be tested in the hardware-accelerated simulation platform to start in response to a test start command; An initialization configuration module, used for controlling the UART interface of the SoC chip to be tested for initialization configuration through the auxiliary controller; A test module, used for transmitting test data to the UART interface of the SoC chip to be tested through the auxiliary controller and receiving the output data fed back by the SoC chip through the UART interface to complete the test.

9. A debugging device, characterized in that, Including: A memory for storing a computer program; A processor for implementing the steps of the debugging method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the debugging method according to any one of claims 1 to 7 are implemented.

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