Method for manufacturing trench power device

Abstract

The present application discloses a method for manufacturing a trench-type power device. The manufacturing method includes: forming a drift region on a semiconductor substrate; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; using a first ion implantation to form a P-type well region and a doped region in the drift region; and using a second ion implantation to form an N-type source region in the well region, wherein the first ion implantation forms a well region in which the dopant concentration gradually decreases with depth, and the second ion implantation inverts the upper portion of the well region to form the source region. This manufacturing method forms the P-type well region and the doped region in a self-aligned manner during a common ion implantation step, which not only improves the performance of the power device but also reduces the number of ion implantation process steps and masks, thereby reducing the manufacturing cost of the power device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more particularly, to a method for manufacturing a trench-type power device. Background Art

[0002] Power semiconductor devices, also known as power electronic devices, include power diodes, power transistors, and thyristors. Examples of power transistors include VDMOS (vertical double-diffused metal oxide semiconductor) field-effect transistors, LDMOS (laterally diffused metal oxide semiconductor) field-effect transistors, and IGBTs (insulated gate bipolar transistors). Based on the VDMOS field-effect transistor, the trench MOSFET was developed. The gate conductor and gate dielectric are formed in the trench. In the on-state, current flows primarily along the trench sidewalls.

[0003] In circuit application scenarios, a diode is connected in parallel between the source and drain of a power transistor to improve the reverse recovery capability of the power transistor. Figure 1 A schematic circuit diagram of a drive circuit for a three-phase brushless DC motor is shown. The drive circuit includes power transistors S11 to S13 and S21 to S23, diodes D11 to D13 and D21 to D23, and an input capacitor. Power transistors S11 to S13 and S21 to S23 are connected to form a full-bridge inverter circuit. Diodes D11 to D13 and D21 to D23 are connected in anti-phase parallel with the corresponding power transistors. For example, the anode and cathode of diode D11 are connected to the source and drain of power transistor S11, respectively. When the power transistor is turned off, the diode provides a feedback path for the load current to the power supply, thereby reducing the reverse bias voltage of the power transistor and improving the reverse recovery capability.

[0004] It is expected that the manufacturing process of trench MOSFET will be further improved, and the reverse recovery capability can be improved by integrating a reverse diode and simplifying the process steps. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a method for manufacturing a trench-type power device, wherein a double-trench structure is adopted to form a P-type well region and a doped region in a self-aligned manner in a common ion implantation step to reduce the manufacturing cost of the power device.

[0006] According to one aspect of the present invention, a method for manufacturing a trench-type power device is provided, comprising: forming a drift region on a semiconductor substrate; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; using a first ion implantation to form a P-type well region and a doped region in the drift region; and using a second ion implantation to form an N-type source region in the well region, wherein the first ion implantation forms a well region in which the dopant concentration gradually decreases with depth, and the second ion implantation inverts the upper portion of the well region to form the source region.

[0007] Preferably, in the first ion implantation, the gate stack is used as a hard mask to form the well region between the first trench and the second trench, and a doped region is formed below the bottom of the second trench.

[0008] Preferably, in the second ion implantation, the gate stack is used as a hard mask, and a resist mask is used to shield the second trench, and dopants are implanted into an upper portion of the well region.

[0009] Preferably, the semiconductor substrate and the drift region are doped with N-type doping, and the semiconductor substrate serves as a drain region of a power transistor.

[0010] Preferably, the method further comprises: forming a Schottky metal on the sidewall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode.

[0011] Preferably, the step of forming a Schottky metal includes: forming a conformal first metal layer in the second trench; and removing the portion of the first metal layer located at the upper part and bottom of the side wall of the second trench by anisotropic etching, wherein the portion of the first metal layer remaining at the lower part of the side wall of the second trench forms a Schottky metal.

[0012] Preferably, in the step of forming the Schottky metal, the etching time of the anisotropic etching is controlled so that the top of the Schottky metal is located between the source region and the drift region.

[0013] Preferably, after the step of forming the Schottky metal, the method further includes: forming a conformal second metal layer in the second trench; using a silicidation process to react a portion of the second metal layer to form a silicide; and using a selective etching process to remove unreacted metal of the second metal layer relative to the Schottky metal and the silicide, wherein the portion of the silicide located at the upper portion of the sidewall of the second trench forms a first contact layer, and the portion of the silicide located at the bottom portion of the sidewall of the second trench forms a second contact layer.

[0014] Preferably, after the step of forming the Schottky metal, the method further comprises: filling the second trench with a conductive material to form a conductive channel for providing an electrical connection path between the source region and the Schottky metal.

[0015] According to the manufacturing method of a trench power device according to an embodiment of the present invention, a P-type well region and a doped region are formed in a self-aligned manner during a common ion implantation step. The gate conductor is located in the first trench and at least a portion is adjacent to the body region, applying an electric field to the channel in the body region. The channel of the trench MOSFET is adjacent to the sidewalls of the first trench and extends vertically, thereby forming a vertical channel, resulting in a smaller cell area, lower specific on-resistance Rsp, and improved voltage withstand capability. A heavily doped P-type doped region is formed below the bottom of the second trench. The P-type doped region helps alleviate the electric field concentration below the first trench, thereby improving the reliability of the electric field control of the gate stack. This manufacturing method not only improves the yield and performance of power devices through a self-aligned process, but also uses a single resist mask and two ion implantations to form three doped regions, thereby reducing the number of ion implantation process steps and masks, thereby reducing the manufacturing cost of the power device.

[0016] In a preferred embodiment, a Schottky metal is formed on the sidewall of the second trench, so that a Schottky diode can be integrated at a minimum unit area cost to enhance the reverse recovery capability of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic circuit diagram showing a drive circuit for a three-phase brushless DC motor.

[0019] Figure 2 A schematic cross-sectional view of a power device according to the prior art is shown.

[0020] Figure 3 A schematic cross-sectional view shows a trench power device according to a first embodiment of the present invention.

[0021] Figures 4a to 4h Schematic cross-sectional views showing different stages of a method for manufacturing a trench power device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by similar reference numerals throughout the various figures. For clarity, parts in the figures are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps may be depicted in a single figure.

[0023] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0024] If the purpose is to describe the situation of being directly on another layer or another area, this article will use the expression "directly on..." or "above and adjacent to...".

[0025] The specific implementation of the present invention is further described in detail below with reference to the accompanying drawings and examples.

[0026] Figure 2 A schematic cross-sectional view of a power device according to the prior art is shown. The power device integrates a power transistor and a diode, wherein the diode is a Schottky barrier diode (SBD).

[0027] The power device 100 includes a semiconductor substrate 101, a drift region 102 located on the semiconductor substrate 101, a well region 103 located in the drift region 102, and a source region 104 located in the well region 103. The semiconductor substrate 101 also serves as the drain region of the MOSFET. The doping type of the semiconductor substrate 101, the drift region 102, and the source region 104 is, for example, N-type, and the doping type of the well region is, for example, P-type. The semiconductor substrate 101 is, for example, a heavily doped N-type silicon carbide substrate, and the drift region 102 is, for example, a lightly doped N-type epitaxial layer epitaxially grown on the surface of the semiconductor substrate 101. The well region 103 and the source region 104 are, for example, doped regions formed by ion implantation.

[0028] An opening is formed in the well region 103, which exposes the surface of the drift region 102. For example, the well region 103 is split into two parts and an opening is formed between the two parts, or the well region 103 is in an integral shape and forms an opening surrounded by a closed part. The anode metal 112 of the Schottky barrier diode is located above the opening, thereby contacting the surface of the drift region 102 through the opening. The performance requirements of the Schottky barrier diode can be achieved by utilizing the contact area provided by the opening. The contact layer 113 is located on the surface of the source region 104 of the MOSFET and extends laterally to the anode metal 112 of the Schottky barrier diode, thereby connecting the source of the MOSFET to the anode of the Schottky barrier diode.

[0029] The gate stack includes a stacked gate dielectric 105 and a gate conductor 106. The gate stack extends laterally from the edge of the source region 103 to the edge of the body region 104, for example. Therefore, at least a portion of the gate conductor 106 is located above the body region 103 and is separated from the body region 103 by the gate dielectric 105, thereby applying an electric field to the channel in the body region 103.

[0030] Interlayer dielectric layer 114 covers the source region and gate stack of the power device, and includes a channel hole exposing the Schottky anode metal. A conductive material is filled in the channel hole to form a conductive channel 115. Furthermore, a source electrode 116 electrically connected to conductive channel 115 is formed on interlayer dielectric layer 114, and a drain electrode 118 is formed on the surface of semiconductor substrate 101 opposite the source region.

[0031] The power device according to the prior art includes a source electrode and a drain electrode formed on opposite surfaces of a substrate. However, a planar gate structure is still adopted in the power device.

[0032] The inventors noted that, compared to planar gate power devices, trench MOSFETs employing a trench gate structure can achieve a smaller cell area, lower specific on-resistance (Rsp), and improved withstand voltage. Therefore, the inventors further developed trench MOSFETs with integrated Schottky barrier diodes.

[0033] Figure 3 A schematic cross-sectional view of a trench power device according to a first embodiment of the present invention is shown, wherein the trench power device integrates a power transistor and a diode, wherein the diode is a Schottky barrier diode (SBD).

[0034] The power device 200 includes a semiconductor substrate 101, a drift region 102 located on the semiconductor substrate 101, a well region 103 located in the drift region 102, and a source region 104 located in the well region 103. The semiconductor substrate 101 also serves as the drain region of the MOSFET. The doping type of the semiconductor substrate 101, the drift region 102, and the source region 104 is, for example, N-type, and the doping type of the well region is, for example, P-type. The semiconductor substrate 101 is, for example, a heavily doped N-type silicon carbide substrate, and the drift region 102 is, for example, a lightly doped N-type epitaxial layer epitaxially grown on the surface of the semiconductor substrate 101. The well region 103 and the source region 104 are, for example, doped regions formed by ion implantation.

[0035] The first trench and the second trench extend from the surface of the source region 104 into the drift region 102 , respectively, and penetrate the source region 104 and the well region 103 in sequence.

[0036] A gate dielectric 105 is formed on the sidewalls and bottom of the first trench, and the interior of the first trench is filled with a gate conductor 106. At least a portion of the gate conductor 106 is adjacent to the body region 103 and is separated from the body region 103 by the gate dielectric 105, thereby applying an electric field to the channel in the body region 103.

[0037] A Schottky metal 112 and a contact layer 113 are formed on the sidewalls of the second trench, and the interior of the second trench is filled with a conductive channel 115. The contact layer 113 is located at the upper portion of the sidewall and contacts the end of the source region 104. The Schottky metal 112 is located at the lower portion of the sidewall and contacts the drift region 102. Preferably, the top of the Schottky metal 112 is located between the source region 104 and the drift region 102, that is, in the well region 103. The contact layer 113 extends along the sidewalls of the second trench, thereby connecting the source of the MOSFET to the anode of the Schottky barrier diode. The performance requirements of the Schottky barrier diode can be achieved by utilizing the contact area provided by the sidewalls of the second trench.

[0038] Furthermore, a drain electrode 118 is formed on the surface of the semiconductor substrate 101 opposite the source region. Although not shown, the trench MOSFET 200 may further include an interlayer dielectric layer and a source electrode located on the interlayer dielectric layer. The source electrode is connected to the conductive channel 115 via a conductive channel in the interlayer dielectric layer, thereby achieving electrical connection between the source region 104 of the MOSFET and the anode metal 112 of the Schottky barrier diode.

[0039] The trench power device according to this embodiment not only includes source and drain electrodes formed on opposing surfaces of the substrate, but also employs a dual-trench structure. The gate conductor is located in the first trench, at least a portion of which is adjacent to the body region, applying an electric field to the channel in the body region. The trench MOSFET's channel is adjacent to the sidewalls of the first trench and extends vertically, forming a vertical channel. This results in a smaller cell area, lower specific on-resistance (Rsp), and improved withstand voltage capability.

[0040] Furthermore, a heavily doped P-type doped region 121 is formed below the bottom of the second trench, and a contact layer 122 is formed at the bottom of the second trench. The conductive channel 115 filled in the second trench is connected to the doped region 121 via the contact layer 122, to the source region 103 via the contact layer 113, and directly to the anode metal 112. The doped region 121 helps alleviate the electric field concentration below the first trench, thereby improving the reliability of the electric field control of the gate stack.

[0041] In a preferred embodiment, a Schottky metal is formed on the sidewall of the second trench, so that a Schottky diode can be integrated at a minimum unit area cost to enhance the reverse recovery capability of the power device.

[0042] The inventors have noted that while forming a P-type doped region 121 and integrating a Schottky diode in a trench power device is beneficial for improving device performance, forming the P-type doped region 121 requires the use of an additional resist mask and ion implantation process, which increases the manufacturing cost of the power device. Therefore, the inventors have further proposed a method for manufacturing a trench MOSFET to simplify the process steps.

[0043] Figures 4a to 4h Schematic cross-sectional views showing different stages of a method for manufacturing a trench power device according to a second embodiment of the present invention.

[0044] The manufacturing method begins with a semiconductor substrate 101. Semiconductor substrate 101 used in power transistors can be, for example, a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate. In this embodiment, a heavily doped N-type silicon carbide substrate is preferred. The wide bandgap of silicon carbide helps reduce leakage current and power consumption, while its high breakdown field strength improves withstand voltage, increases current density, and reduces device size. Furthermore, the heavily doped N-type silicon carbide substrate can also serve as the drain region of the power device.

[0045] See also Figure 4a , a drift region 102 is formed on the semiconductor substrate 101.

[0046] In this step, an epitaxial layer is grown on the surface of the semiconductor substrate 101 using an epitaxial growth process. During the growth, the epitaxial layer is in-situ doped to form a lightly doped N-type epitaxial layer. In this embodiment, a silicon carbide epitaxial layer is formed on a silicon carbide substrate using chemical vapor deposition, thereby forming a lightly doped N-type drift region 102 composed of silicon carbide.

[0047] See also Figure 4b , forming a first trench 131 and a second trench 132 extending from the surface of the source region 104 into the drift region 102 .

[0048] In this step, a resist mask is formed on the surface of the source region 104, and a pattern is formed in the resist mask using a photolithography process. Anisotropic dry etching is then used to etch the drift region 102 through the openings in the pattern, thereby forming the first trench 131 and the second trench 132. By controlling the etching time, the first trench 131 and the second trench 132 can be controlled to reach a predetermined depth in the drift region 102.

[0049] After the etching process, the resist mask is removed by solvent dissolution or ashing.

[0050] See also Figure 4c A gate dielectric 105 is formed on the sidewalls and bottom of the first trench 131 , and a gate conductor 106 is filled in the first trench.

[0051] In this step, silicon carbide is converted into silicon oxide by thermal oxidation, for example, to form gate dielectric 105. Then, a conductive material is deposited to fill first trench 131, and the conductive material outside first trench 131 is removed by chemical mechanical planarization to form gate conductor 106.

[0052] See also Figure 4d , a first ion implantation is performed to form a P-type well region 103 and a doped region 111 in the drift region 102 .

[0053] In this step, the gate stack is used as a hard mask, and P-type dopants are injected into the portion of the drift region 102 located between the first trench 131 and the second trench 132 to form a well region 103, and P-type dopants are injected into the portion of the drift region 102 located below the bottom of the second trench 132 to form a doped region 111.

[0054] In the first ion implantation, the dopant used to form the P-type doping region is, for example, Al and / or B. By controlling the process parameters of the ion implantation, such as ion energy and implantation dose, a doping profile can be formed in which the dopant concentration gradually decreases with depth.

[0055] See also Figure 4e , a second ion implantation is performed to form an N-type source region 104 in the well region 103 .

[0056] In this step, a resist mask PR is formed by the above-mentioned photolithography process to block the second trench 132. Using the gate stack as a hard mask and the resist mask PR, N-type dopants are implanted into the well region 103 to form a source region 104.

[0057] In the second ion implantation, the dopant used to form the N-type doped region is, for example, N. By controlling the process parameters of the ion implantation, such as ion energy and implantation dose, the implantation depth and dopant concentration can be controlled so that the N-type dopant is located in the upper portion of the well region 103 and the concentration of the N-type dopant is higher than that of the P-type dopant, thereby inverting the upper portion of the well region 103 to form the source region 104.

[0058] Furthermore, since the well region 103 formed in the first ion implantation process has a dopant concentration profile that gradually decreases with depth, after the second ion implantation process, the remaining portion of the well region 103 is a lightly doped P-type well region. By utilizing the first and second ion implantations, three doped regions (i.e., the well region 103, the source region 104, and the doped region 111) can be formed using a single resist mask and two ion implantations, thereby reducing the number of ion implantation process steps and masks.

[0059] After the second ion implantation process, the resist mask PR is removed by solvent dissolution or ashing.

[0060] See also Figure 4f A Schottky metal 112 is formed at the lower portion of the sidewall of the second trench 132 .

[0061] In this step, chemical vapor deposition is used to form a conformal metal layer in the second trench 132. Furthermore, an anisotropic etching process is used to remove the portion of the metal layer located on the upper sidewalls of the second trench 132 and the portion located on the bottom surface of the second trench 132, thereby leaving only the metal layer at the lower sidewalls of the second trench 132 to form the Schottky metal 112. By controlling the etching time, the top position of the Schottky metal 112 can be controlled. In this embodiment, the top of the Schottky metal 112 is located between the source region 104 and the drift region 102. The metal layer used for the Schottky metal 112 is composed of titanium, for example.

[0062] See also Figure 4g A contact layer 113 is formed on the upper portion of the sidewall of the second trench 132 , and a contact layer 122 is formed on the bottom of the second trench 132 .

[0063] In this step, chemical vapor deposition or sputtering is used to form a conformal metal layer on the sidewalls and bottom of the second trench 132. At the upper portion of the sidewalls of the second trench 132, the metal layer covers the exposed surfaces of the source region 104 and the well region 103, and at the bottom of the second trench 132, the metal layer covers the exposed surface of the drift region 102. Furthermore, a silicidation process, such as heat treatment, is used to react the metal layer with silicon in the source region 104, the well region 103, and the drift region 102 to form silicide. Furthermore, a selective wet etch is used to selectively remove unreacted metal material relative to the Schottky metal and the silicide, so that the silicide remaining on the upper portion of the sidewalls of the second trench 132 forms the contact layer 113, and the silicide remaining at the bottom of the second trench 132 forms the contact layer 122. For example, the Schottky metal is composed of titanium, the contact layers 113 and 122 are composed of nickel silicide, and the metal layer used to form the contact layers 113 and 122 is composed of nickel. Therefore, in the etching process, the etching rates of different materials can be used for selective removal.

[0064] See also Figure 4h A conductive material is filled in the interior of the second trench 132 to form a conductive channel 115 .

[0065] The conductive channel 115 filled in the second trench is connected to the doped region 121 via the contact layer 122, to the source region 103 via the contact layer 113, and directly to the anode metal 112. The conductive channel 115 is made of aluminum, copper, or alloys thereof.

[0066] Furthermore, a drain electrode 118 is formed on the surface of the semiconductor substrate 101 opposite the source region. Although not shown, the trench MOSFET may further include an interlayer dielectric layer and a source electrode located on the interlayer dielectric layer. The source electrode is connected to the conductive channel 115 via a conductive channel in the interlayer dielectric layer, thereby achieving electrical connection between the source region 104 of the MOSFET and the anode metal 112 of the Schottky barrier diode.

[0067] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a trench power device, comprising: forming a drift region on a semiconductor substrate; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; Using a first ion implantation, a P-type well region and a doped region are formed in the drift region; as well as A second ion implantation is performed to form an N-type source region in the well region. The first ion implantation forms a well region in which the dopant concentration gradually decreases with depth, and the second ion implantation inverts the upper portion of the well region to form the source region. In the second ion implantation, the gate stack is used as a hard mask, and a resist mask is used to shield the second trench, and dopants are implanted into an upper portion of the well region.

2. The manufacturing method according to claim 1, wherein In the first ion implantation, the gate stack is used as a hard mask to form the well region between the first trench and the second trench, and a doped region is formed below the bottom of the second trench.

3. The manufacturing method according to claim 1, wherein: The doping type of the semiconductor substrate and the drift region is N-type, and the semiconductor substrate serves as a drain region of a power transistor.

4. The manufacturing method according to claim 1, further comprising: forming a Schottky metal on the sidewall of the second trench, Wherein, the Schottky metal and the drift region form a Schottky barrier diode.

5. The manufacturing method according to claim 4, wherein: The steps to form a Schottky metal include: forming a conformal first metal layer in the second trench; and Anisotropic etching is used to remove the portion of the first metal layer located on the upper portion and the bottom portion of the sidewall of the second trench, The portion of the first metal layer remaining at the lower portion of the sidewall of the second trench forms a Schottky metal.

6. The manufacturing method according to claim 5, wherein: In the step of forming the Schottky metal, the etching time of the anisotropic etching is controlled so that the top of the Schottky metal is located between the source region and the drift region.

7. The manufacturing method according to claim 6, further comprising, after the step of forming the Schottky metal: forming a conformal second metal layer in the second trench; Using a silicidation process to react a portion of the second metal layer to form silicide; as well as Using a selective etching process, removing unreacted metal of the second metal layer relative to the Schottky metal and the silicide, The portion of the silicide located at the upper portion of the sidewall of the second trench forms a first contact layer, and the portion of the silicide located at the bottom portion of the sidewall of the second trench forms a second contact layer.

8. The manufacturing method according to claim 6, further comprising, after the step of forming the Schottky metal: A conductive material is filled in the second trench to form a conductive channel for providing an electrical connection path between the source region and the Schottky metal.

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