Semiconductor device

Abstract

This disclosure provides a memory cell and a semiconductor device including the memory cell. According to this technology, a semiconductor device includes: a plurality of active layers vertically stacked on a substrate along a first direction and extending horizontally along a second direction intersecting the first direction; a plurality of bit lines coupled to a first side of a respective active layer and extending horizontally upward along a third direction intersecting the first and second directions; a plurality of capacitors coupled to a second side of a respective active layer; word lines extending vertically through the active layers along the first direction; upper-level interconnects coupled to the upper ends of the word lines; and lower-level interconnects coupled to the lower ends of the word lines.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0141820, filed on October 29, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a memory cell and a semiconductor device including the memory cell. Background Technology

[0004] In recent years, memory cells have been steadily shrinking in order to increase the net die size of memory devices.

[0005] Although shrinking memory cells are thought to lead to a decrease in parasitic capacitance (Cb) and an increase in capacitance, it is difficult to increase net die size due to the structural limitations of memory cells. Summary of the Invention

[0006] Embodiments of this disclosure provide a highly integrated memory cell and a semiconductor device including the memory cell.

[0007] According to one embodiment, a semiconductor device includes: a plurality of active layers stacked vertically on a substrate along a first direction and extending horizontally along a second direction intersecting the first direction; a plurality of bit lines coupled to a first side of a respective active layer and extending horizontally upward along a third direction intersecting the first and second directions; a plurality of capacitors coupled to a second side of a respective active layer; word lines extending vertically through the active layers along the first direction; upper-level interconnects coupled to the upper ends of the word lines; and lower-level interconnects coupled to the lower ends of the word lines.

[0008] According to one embodiment, a semiconductor device includes: a first word line and a first memory cell stack, the first word line being oriented along a first direction perpendicular to a substrate, the first memory cell stack sharing the first word line and being stacked perpendicularly along the first direction; a second word line and a second word line of a second memory cell stack being oriented perpendicularly along the first direction, the second memory cell stack sharing the second word line and being stacked perpendicularly along the first direction; an upper-level interconnect coupled to the upper ends of the first word line and the second word line, respectively; and a lower-level interconnect coupled to the lower ends of the first word line and the second word line, wherein the second memory cell stack and the second word line are horizontally spaced apart from the first memory cell stack and the first word line along a second direction intersecting the first direction.

[0009] According to one embodiment, a semiconductor device includes: a first memory cell array including a plurality of first vertical word lines extending vertically over a substrate; a second memory cell array including a plurality of second vertical word lines extending vertically over a substrate; a first horizontal interconnect coupled to the first vertical word lines of the first memory cell array; and a second horizontal interconnect coupled to the second vertical word lines of the second memory cell array.

[0010] According to one embodiment, a semiconductor device includes: a plurality of active layers vertically stacked on a substrate; a plurality of bit lines connected to a first side of a respective active layer and horizontally oriented; a plurality of capacitors connected to a second side of a respective active layer; word lines vertically oriented through the active layers; and interconnects that interconnect the upper and lower ends of the word lines in a zigzag manner.

[0011] According to one embodiment, a semiconductor device includes: a plurality of memory cell stacks, each memory cell stack including a plurality of memory cells vertically stacked on a substrate and vertical word lines coupled to the memory cells; and a plurality of interconnects that connect at least two vertical word lines in a zigzag manner to form chain word lines.

[0012] This technology can reduce the number of access lines for horizontally arranged vertical word lines (WL) by linking them together.

[0013] These and other features and advantages of the invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a perspective view schematically showing a semiconductor device according to one embodiment;

[0015] Figure 2 It is along Figure 1 The layout view intercepted by line A-A';

[0016] Figure 3 It is along Figure 2 A cross-sectional view taken by line B-B';

[0017] Figure 4 This is a layout view showing a semiconductor device according to another embodiment;

[0018] Figure 5 It is along Figure 4 A cross-sectional view taken from the C-C' line shows the chain structure of the word lines;

[0019] Figure 6 This is a schematic view illustrating the chain structure of word lines according to another embodiment; and

[0020] Figure 7 , Figure 8 and Figure 9 This is a schematic view illustrating the chain structure of word lines according to other embodiments. Detailed Implementation

[0021] Embodiments of this disclosure are described with reference to cross-sectional views, plan views, or block diagrams. Therefore, the shapes of the example views may be modified due to manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure are not limited to those shown, but encompass various changes and modifications due to manufacturing processes. Therefore, the areas shown in the drawings are schematic in nature, and the shapes of the areas shown in the drawings are intended to represent specific shapes of areas of the example device, and do not limit the scope of this disclosure.

[0022] According to the implementation described below, memory cells can be vertically stacked to increase memory cell density and reduce parasitic capacitance.

[0023] Figure 1 This is a perspective view schematically showing a semiconductor device according to an embodiment. Figure 2 It is along Figure 1 The layout view is captured by line A-A'. Figure 3 It is along Figure 2 The cross-sectional view taken by line B-B'.

[0024] Reference Figures 1 to 3Semiconductor device 100 may include a substrate LS and a plurality of memory cell stacks MCS1 / MCS2 formed on the substrate LS. The memory cell stacks MCS1 and MCS2 may be oriented perpendicular to the substrate LS. The substrate LS may define a plane. The memory cell stacks MCS1 and MCS2 may be oriented perpendicular to the plane of the substrate LS. The memory cell stacks MCS1 and MCS2 may be oriented vertically upward from the substrate LS along a first direction D1. Each of the memory cell stacks MCS1 and MCS2 may include a three-dimensional array of memory cells MC. Each of the memory cell stacks MCS1 and MCS2 may include a plurality of memory cells MC. In the memory cell stacks MCS1 and MCS2, the plurality of memory cells MC may be stacked vertically along the first direction D1. Each memory cell MC of the memory cell stacks MCS1 and MCS2 may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR and capacitor CAP may be horizontally oriented along a second direction D2. Each memory cell MC may further include a word line WL, and the word line WL may be oriented vertically along the first direction D1, which is perpendicular to the upper surface of the substrate LS. Bit lines BL can be horizontally oriented along a third direction D3 parallel to the upper surface of the substrate LS. In each memory cell MC, bit lines BL, transistors TR, capacitors CAP, and board lines PL can be horizontally arranged along a second direction D2. Memory cell stacks MCS1 and MCS2 can be referred to as memory cell arrays. Memory cell stacks MCS1 and MCS2 can include dynamic random access memory (DRAM) memory cell arrays. In another embodiment, memory cell stacks MCS1 and MCS2 can include phase-change random access memory (PCRAM), resistive random access memory (RERAM), or magnetoresistive random access memory (MRAM), and capacitors CAP can be replaced by other memory elements.

[0025] The substrate LS can be formed from any material suitable for semiconductor processing. For example, the substrate LS can be selected to include at least one of conductive, dielectric, and semiconductor materials. Various materials can be formed on the substrate LS. In one embodiment, the substrate LS may include a semiconductor substrate, such as, for example, a semiconductor substrate formed from a silicon-containing material. Examples of silicon-containing semiconductor substrates may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate LS may also include other semiconductor materials, such as germanium. The substrate LS may include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The substrate LS may include a silicon-on-insulator (SOI) substrate.

[0026] The substrate LS may include a peripheral circuitry region (not shown). For example, the peripheral circuitry region may include multiple control circuits for controlling the memory cell array MCA. At least one control circuit in the peripheral circuitry region may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuitry region may include address decoder circuitry, read circuitry, and write circuitry. At least one control circuit in the peripheral circuitry region may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, or a FinFET.

[0027] For example, at least one control circuit in the peripheral circuit region may be electrically connected to the bit line BL. The peripheral circuit region may include a sense amplifier SA, and the sense amplifier SA may be electrically connected to the bit line. Although not shown, a multi-level metal interconnect MLM may be located between the memory cell stacks MCS1 and MCS2 and the substrate LS, and the peripheral circuit region and the bit line BL may be coupled via the multi-level metal interconnect MLM.

[0028] Bit line BL may extend along a third direction D3, parallel to the upper surface of substrate LS and orthogonal to the first direction D1 and the second direction D2. Bit line BL may be spaced apart from substrate LS and oriented horizontally (or laterally). Bit line BL may also be referred to as a horizontally oriented bit line or a horizontally extending bit line. Bit line BL may be formed of any suitable material, including, for example, a conductive material. Suitable materials for bit line BL may include silicon-based materials, metal-based materials, or combinations thereof. For example, suitable materials for bit line BL may include polysilicon, metal, metal nitride, metal silicide, or combinations thereof. Memory cells MC arranged horizontally along the third direction D3 may share a single bit line BL. In some embodiments, bit line BL may be formed of polysilicon, titanium nitride, tungsten, or combinations thereof. For example, bit line BL may be formed of polysilicon or titanium nitride (TiN) doped with N-type impurities. In some embodiments, bit line BL may be formed of a stack of titanium nitride and tungsten (TiN / W). Bit line BL may also include an ohmic contact layer such as a metal silicide.

[0029] The transistor TR can be arranged horizontally along a second direction D2 parallel to the surface of the substrate LS. That is, the transistor TR can be horizontally located between the bit line BL and the capacitor CAP. The transistor TR can be located at a level higher than the substrate LS, and the transistor TR and the substrate LS can be spaced apart from each other.

[0030] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend vertically along a first direction D1, and the active layer ACT may extend horizontally along a second direction D2. The first direction D1 may be perpendicular to the second direction D2. The active layer ACT may be arranged horizontally from the bit line BL. The active layer ACT may be oriented parallel to the plane of the substrate LS.

[0031] The word line WL can be cylindrical, extending through the active layer ACT. The word line WL can be referred to as a cylindrical word line or a vertical word line. The gate dielectric layer GD can be formed on the sidewalls of the word line WL. The gate dielectric layer GD can surround the sidewalls of the word line WL.

[0032] The gate dielectric layer (GD) can be formed from any suitable material, including, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or combinations thereof. In some embodiments, the gate dielectric layer (GD) can be made of SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON.

[0033] Suitable materials for word lines (WL) may include metals, metal mixtures, metal alloys, or semiconductor materials. In some embodiments, suitable materials for word lines (WL) may include titanium nitride, tungsten, polycrystalline silicon, or combinations thereof. For example, in some embodiments, word lines (WL) may be made of a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. Word lines (WL) may be made of N-type work function materials or P-type work function materials. For example, N-type work function materials may have a low work function of 4.5 or lower, while P-type work function materials may have a high work function of 4.5 or higher.

[0034] Word lines (WL) and bit lines (BL) can extend in directions that intersect each other.

[0035] Suitable materials for the active layer ACT may include semiconductor materials such as polycrystalline silicon. The active layer ACT may include multiple impurity regions. The impurity regions may include a first source / drain region SD1 and a second source / drain region SD2. In some embodiments, the active layer ACT may include doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, or oxide semiconductor materials. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type or P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with impurities of the same conductivity type. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. Bit line BL can be electrically connected to a first edge portion of the active layer ACT, and capacitor CAP can be electrically connected to a second edge portion of the active layer ACT. The first edge portion of the active layer ACT can be provided by a first source / drain region SD1, and the second edge portion of the active layer ACT can be provided by a second source / drain region SD2.

[0036] The active layers ACT adjacent to each other along the third direction D3 can be separated and supported by a separation layer IL. The separation layer IL can be located between memory cells MC adjacent to each other along the third direction D3. The separation layer IL can be located between memory cells MC adjacent to each other along the second direction D2. The separation layer IL can be located between memory cells MC adjacent to each other along the first direction D1. The separation layer IL may include an insulating material (or dielectric material), such as an oxide.

[0037] The capacitor CAP can be positioned horizontally relative to the transistor TR. The capacitor CAP can extend horizontally from the active layer ACT along a second direction D2. The capacitor CAP can include a storage node SN, a dielectric layer DE, and a board node PN. The storage node SN, dielectric layer DE, and board node PN can be arranged horizontally along the second direction D2. The storage node SN can have a horizontally oriented cylindrical shape, and the board node PN can be shaped to extend to the inner and outer walls of the cylinder of the storage node SN. The dielectric layer DE can be located inside the storage node SN and surround the board node PN. The board node PN can be connected to the board line PL. The storage node SN can be electrically connected to the second source / drain region SD2.

[0038] The capacitor CAP can be, for example, a metal-insulator-metal (MIM) capacitor. In one embodiment, the storage node SN and the board node PN can be made of a metal-based material. In one embodiment, the dielectric layer DE can be made of silicon oxide, silicon nitride, high-k materials, or combinations thereof. High-k materials can have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) can have a dielectric constant of about 3.9, and the dielectric layer DE can include a high-k material having a dielectric constant of 4 or higher. High-k materials can have a dielectric constant of about 20 or higher. Suitable high-k materials can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer DE can be formed of a composite layer comprising two or more layers of the above-mentioned high-k materials.

[0039] The dielectric layer DE can be formed of zirconium-based oxide. The dielectric layer DE can have a stacked structure comprising zirconium oxide (ZrO2). The stacked structure comprising zirconium oxide (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. The ZA and ZAZ stacks can be referred to as a zirconium oxide substrate (ZrO2 substrate). In another embodiment, the dielectric layer DE can be formed of hafnium-based oxide. The dielectric layer DE can have a stacked structure comprising hafnium oxide (HfO2). Stacked structures including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a structure in which aluminum oxide (Al2O3) is stacked on top of hafnium oxide (HfO2). HAH stacks can have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are stacked sequentially. HA stacks and HAH stacks can be referred to as hafnium oxide substrates (HfO2 substrates). In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, the band gap of aluminum oxide (Al2O3) can be larger than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) can be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can comprise a stack of a high-k material and a high-bandgap material having a larger bandgap than the high-k material. The dielectric layer DE can comprise silicon oxide (SiO2) as the high-bandgap material, unlike aluminum oxide (Al2O3). Because the dielectric layer DE contains a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. For example, the high-bandgap material can be thinner than the high-k material. In another embodiment, the dielectric layer DE can comprise a laminated structure in which high-k materials and high-bandgap materials are alternately stacked. For example, it can comprise ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the layered structure described above, the aluminum oxide (Al2O3) can be very thin. For example, the thickness of the aluminum oxide (Al2O3) can be [missing information].

[0040] In another embodiment, the dielectric layer DE may include a stacked structure, a multilayer structure, or a mixture of zirconium oxide, hafnium oxide, and aluminum oxide.

[0041] In another embodiment, an interface control layer (not shown) for mitigating leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the board node PN and the dielectric layer DE.

[0042] Suitable materials for storage nodes (SN) and board nodes (PN) can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and board nodes (PN) can be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, or tungsten nitride / tungsten (WN / W) stacks. Board nodes (PN) can include combinations of metal-based and silicon-based materials. For example, board nodes (PN) can be stacks of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can serve as the gap filler material filling the interior of the storage node SN, while titanium nitride (TiN) can essentially function as the plate node for the capacitor CAP. Tungsten nitride can be a low-resistance material. Adjacent plate nodes PN can be jointly connected to the plate line PL. The bottom of the plate line PL can be insulated from the substrate LS.

[0043] A storage node (SN) can have a three-dimensional (3D) structure, and the 3D structure of the storage node (SN) can be a horizontal 3D structure oriented along a second direction D2. As an example of a 3D structure, the storage node (SN) can be cylindrical, columnar, or pylinder-shaped. A pylinder-shaped structure can refer to a structure that combines columnar and cylindrical shapes.

[0044] Return to reference Figure 3The separator layer IL and the active layer ACT can be stacked alternately along a first direction D1. Multiple word lines WL can be formed perpendicularly through the active layer ACT and the separator layer IL. Multiple bit lines BL oriented horizontally along a third direction D3 can be formed in a direction intersecting the word lines WL. Word lines WL adjacent to each other in the horizontal direction along a second direction D2 can be electrically connected to each other. For example, word lines WL can be coupled via multiple interconnects LHWL and UHWL. The multiple interconnects LHWL and UHWL can include, for example, lower-level interconnects LHWL and upper-level interconnects UHWL. Lower-level interconnects LHWL can interconnect the bottom of word lines WL. Upper-level interconnects UHWL can connect to the upper part of any word line WL. Lower-level interconnects LHWL can be located at a lower level than the word line WL, and upper-level interconnects UHWL can be located at a higher level than the word line WL. An electrical path can be provided between word lines WL via multiple interconnects LHWL and UHWL. The multiple interconnects LHWL and UHWL can be formed from a metal-based material such as tungsten. The multiple interconnects LHWL and UHWL can be horizontally oriented along a second direction D2.

[0045] As described above, the number of access lines for word lines WL can be reduced by connecting word lines WL horizontally along the second direction D2 via chain links. Word lines WL can be referred to as cylindrical word lines PWL, and interconnects LHWL and UHWL can be referred to as horizontal word lines HWL. In another embodiment, interconnects LHWL and UHWL can be referred to as horizontal access lines.

[0046] As described above, the semiconductor device 100 may include a word line WL vertically oriented from the substrate LS along a first direction D1, a memory cell stack MCS1 sharing the word line WL and stacked vertically along the first direction D1, a memory cell stack MCS2 sharing the word line WL and stacked vertically along the first direction D1, an upper-level interconnect UHWL connected to the upper ends of the word line WL of the memory cell stack MCS1 and the upper ends of the word line WL of the memory cell stack MCS2, and a lower-level interconnect LHWL interconnecting the lower ends of the word line WL of the memory cell stack MCS1 and the lower ends of the word line WL of the memory cell stack MCS2. The word line WL of the memory cell stack MCS2 may be horizontally spaced from the word line WL of the memory cell stack MCS1 along a second direction D2 intersecting the first direction D1.

[0047] Figure 4 This is a layout view showing a semiconductor device according to another embodiment. Figure 5 It is along Figure 4 A cross-sectional view taken from the C-C' line shows the chain structure of the word lines.

[0048] exist Figure 4 In, with Figures 1 to 3 The same reference numerals in the accompanying drawings denote the same elements. Semiconductor device 200 may be similar to... Figures 1 to 3 Semiconductor device 100. Repeated descriptions of the same or substantially the same elements may be omitted.

[0049] Reference Figure 4 and Figure 5 The semiconductor device 200 may include a mirrored memory cell array (MCA) sharing a board line PL. Each mirrored memory cell array (MCA) may include... Figures 1 to 3 The memory cell MC shown is illustrated. A mirrored memory cell array MCA can be referred to as a mirrored memory cell stack MCS. Each memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT, a word line WL passing through the active layer ACT, and a gate dielectric layer GD surrounding the sidewalls of the word line WL. The word line WL may be vertically oriented along a first direction D1. The word lines WL may be horizontally separated from each other along a second direction D2 and a third direction D3. The word lines WL horizontally arranged along the second direction D2 may be coupled through multiple interconnects UHWL and LHWL. The word lines WL horizontally arranged along the second direction D2 may have a chain shape, wherein they are coupled in a zigzag manner through multiple interconnects UHWL and LHWL. The word lines WL horizontally arranged along the third direction D3 may not be coupled. That is, multiple interconnects UHWL and LHWL may not be coupled to the word lines WL horizontally arranged along the third direction D3.

[0050] Figure 6 This is a schematic view illustrating the chain structure of word lines according to another embodiment.

[0051] Reference Figure 6 The semiconductor device 300 may include multiple memory cell arrays 301, 302, and 303. The memory cell array 301, arranged vertically along a first direction D1, may share word lines WL. The memory cell array 302 may include multiple word lines WL. The word lines WL of the memory cell array 302, arranged horizontally along a second direction D2, may be chained, and they are coupled in a zigzag manner through multiple interconnects UHWL and LHWL. The word lines WL of the memory cell array 303, arranged horizontally along a third direction D3, may not be coupled. The memory cell array 302 may include a horizontal array of memory cell stacks. Each memory cell stack may include vertically stacked memory cells. Each memory cell stack in the memory cell array 302 shares each word line WL.

[0052] Figure 7 , Figure 8 and Figure 9 This is a schematic view illustrating the chain structure of word lines according to other embodiments. Figures 7 to 9In, with Figures 1 to 6 The same reference numerals in the accompanying drawings denote the same elements. Semiconductor devices 401, 402, and 403 can be similar to... Figures 1 to 6 Semiconductor devices 100, 200, and 300. Repeated descriptions of the same or substantially the same elements may be omitted.

[0053] Reference Figure 7 Semiconductor device 401 may include multiple memory cell arrays 301, 302, and 303. Memory cell array 301, arranged vertically along a first direction D1, may share word lines WL. The word lines WL of memory cell array 302, arranged horizontally along a second direction D2, may have a chain-like structure coupled through upper-level interconnects UHWL. The word lines WL of memory cell array 303, arranged horizontally along a third direction D3, may not be coupled. Figure 6 The semiconductor devices are different from those in the 300 series. Figure 7 Semiconductor device 401 may not include lower-level interconnect LHWL.

[0054] Reference Figure 8 Semiconductor device 402 may include multiple memory cell arrays 301, 302, and 303. Memory cell array 301, arranged vertically along a first direction D1, may share word lines WL. The word lines WL of memory cell array 302, arranged horizontally along a second direction D2, may have a chain-like structure coupled via lower-level interconnects LHWL. The word lines WL of memory cell array 303, arranged horizontally along a third direction D3, may not be coupled. Figure 6 The semiconductor devices are different from those in the 300 series. Figure 8 Semiconductor device 402 may not include upper-level interconnect UHWL.

[0055] Reference Figure 9 The semiconductor device 403 may include multiple memory cell arrays 301, 302, and 303. The memory cell array 301, arranged vertically along a first direction D1, may share word lines WL. The word lines WL of the odd-numbered memory cell array 302, arranged horizontally along a second direction D2, may be chained, wherein the word lines WL of the odd-numbered memory cell array 302 are coupled through upper-level interconnects UHWL. The word lines WL of the even-numbered memory cell array 302, arranged horizontally along the second direction D2, may be chained, wherein the word lines WL of the even-numbered memory cell array 302 are coupled through lower-level interconnects LHWL. The word lines WL of the memory cell array 303, arranged horizontally along a third direction D3, may not be coupled.

[0056] Although this disclosure has been shown and described with reference to various embodiments thereof, it will be readily understood by those skilled in the art that various changes or modifications may be made thereto without departing from the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Multiple active layers are stacked vertically on a substrate along a first direction and extend horizontally along a second direction that intersects the first direction; Multiple bit lines, which are coupled to a first side of the corresponding active layer and extend horizontally upward on a third side intersecting the first direction and the second direction; Multiple capacitors are coupled to the second side of the respective active layer; The character line extends perpendicularly through the active layer along a first direction; Upper-level interconnects are coupled to the upper end of the word lines; as well as The lower-level interconnect is coupled to the lower end of the word line.

2. The semiconductor device according to claim 1, wherein, The upper-level interconnect and the lower-level interconnect are horizontally oriented along the second direction.

3. The semiconductor device according to claim 1, wherein, The active layer, the bit line, and the capacitor are located at the same level.

4. The semiconductor device according to claim 1, wherein, Each capacitor includes: A cylindrical storage node, which is connected to the corresponding second side of the active layer; The dielectric layer on the cylindrical storage node; and Board nodes on the dielectric layer, The cylindrical storage node is horizontally oriented along the second direction.

5. The semiconductor device of claim 4, further comprising a board line commonly coupled to a board node of the capacitor. in, The plate line extends perpendicularly along the first direction.

6. The semiconductor device of claim 1, further comprising a gate dielectric layer between the active layer and the word line.

7. A semiconductor device, comprising: A first word line and a first memory cell are stacked, the first word line is oriented along a first direction perpendicular to the substrate, and the first memory cell stack shares the first word line and is stacked perpendicularly along the first direction; The second word line and the second memory cell are stacked, the second word line is oriented perpendicularly to the first direction, and the second memory cell stack shares the second word line and is stacked perpendicularly to the first direction; Upper-level interconnects are respectively coupled to the upper ends of the first word line and the second word line; as well as The lower-level interconnect is coupled to the lower ends of the first word line and the second word line. The second memory cell stack and the second word line are horizontally spaced from the first memory cell stack and the first word line along a second direction that intersects the first direction.

8. The semiconductor device according to claim 7, wherein, The upper-level interconnect and the lower-level interconnect are horizontally oriented along the second direction.

9. The semiconductor device according to claim 7, wherein, Both the first storage cell stack and the second storage cell stack include: Multiple active layers are stacked vertically on the substrate along the first direction and oriented horizontally along the second direction; Multiple bit lines, coupled to a first side of the respective active layer and horizontally oriented in a direction intersecting the first and second directions; and Multiple capacitors are coupled to the second side of the respective active layer. Wherein, the first word line passes perpendicularly through the active layer of the first memory cell stack along the first direction, and the second word line passes perpendicularly through the active layer of the second memory cell stack along the first direction.

10. The semiconductor device according to claim 9, wherein, The active layer, the bit line, and the capacitor are located at the same level.

11. The semiconductor device according to claim 9, wherein, Each capacitor includes: A cylindrical storage node, which is connected to the second side of the corresponding active layer; The dielectric layer on the cylindrical storage node; and Board nodes on the dielectric layer, The cylindrical storage node is horizontally oriented along the second direction.

12. The semiconductor device of claim 11, further comprising a plate line commonly coupled to a plate node of the capacitor, wherein, The plate lines are oriented perpendicularly to the first direction.

13. The semiconductor device of claim 9, further comprising a gate dielectric layer between the active layer and the first word line and between the active layer and the second word line.

14. A semiconductor device, comprising: A first memory cell array includes a plurality of first vertical word lines extending vertically above a substrate; The second memory cell array includes a plurality of second vertical word lines extending vertically above the substrate; A first horizontal interconnect is coupled to a first vertical word line of the first memory cell array; as well as The second horizontal interconnect is coupled to the second vertical word line of the second memory cell array. Wherein, both the first horizontal interconnect and the second horizontal interconnect include upper-level interconnects and lower-level interconnects, the upper-level interconnects having a higher level than the first memory cell array and the second memory cell array, and the lower-level interconnects having a lower level than the first memory cell array and the second memory cell array. The upper-level interconnect and the lower-level interconnect are horizontally oriented relative to the substrate.

15. The semiconductor device according to claim 14, wherein, The first vertical character line is coupled in a Z-shape to form a first chain-like character line through the upper-level interconnect and the lower-level interconnect, and The second vertical word line is coupled in a Z-shape to form a second chain word line through the upper-level interconnect and the lower-level interconnect.

16. The semiconductor device of claim 14, wherein, The first storage cell array includes a horizontal array of first storage cell stacks, each of the first storage cell stacks including vertically stacked first storage cells, each of the first storage cell stacks sharing a first vertical word line. The second storage cell array includes a horizontal array of second storage cell stacks, the second storage cell stacks include vertically stacked second storage cells, and each second storage cell stack shares each second vertical word line.

17. The semiconductor device according to claim 14, wherein, Both the first memory cell array and the second memory cell array further include: Multiple active layers are vertically stacked on the substrate; Multiple horizontally oriented bit lines are coupled to the first side of the corresponding active layer; Multiple capacitors, coupled to the second side of the respective active layer; and The plate wires, which are collectively connected to the capacitor, The first vertical character line and the second vertical character line pass through the active layer.

18. The semiconductor device according to claim 17, wherein, The active layer, the bit line, and the capacitor are located at the same level.

19. The semiconductor device according to claim 17, wherein, Each capacitor includes: A horizontally oriented cylindrical storage node is coupled to the second side of the corresponding active layer; The dielectric layer on the horizontally oriented cylindrical storage node; and Board nodes on the dielectric layer.

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