Semiconductor device with test structure and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a first test region, a word line structure disposed in the first test region and arranged parallel to a first axis, a first column of capacitor plug structures disposed in the first test region and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor plug structures disposed adjacent to the first column of capacitor plug structures and arranged parallel to the first column of capacitor plug structures, and a first test structure including a first drain portion extending along the second axis and a first source portion extending along the second axis. The first drain portion is disposed on the first column of capacitor plug structures, and the first source portion is disposed on the second column of capacitor plug structures.

Description

[0001] Cross-referencing related applications

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 084,058, filed October 29, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device having a test structure and a method for fabricating the same. Background Technology

[0004] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. To meet the ever-increasing demand for computing power, the size of semiconductor devices continues to shrink. However, this shrinking has led to various problems in the manufacturing process, and these problems are constantly evolving into different scenarios. Therefore, challenges remain in improving the performance, quality, yield, and reliability of semiconductor devices, as well as reducing their complexity.

[0005] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device, comprising: a first test region; a word line structure disposed in the first test region and arranged parallel to a first axis; a first-pillar capacitor plug structure disposed in the first test region and arranged parallel to a second axis, the second axis being perpendicular to the first axis; a second-pillar capacitor plug structure disposed adjacent to the first-pillar capacitor plug structure and arranged parallel to the first-pillar capacitor plug structure; and a first test structure including a first drain portion and a first source portion, the first drain portion extending along the second axis, and the first source portion extending along the second axis. The first drain portion is disposed on the first-pillar capacitor plug structure, and the first source portion is disposed on the second-pillar capacitor plug structure.

[0007] In some embodiments, the first test area is located in a cutting channel.

[0008] In some embodiments, the semiconductor device further includes a second test region located in the dicing channel; a first row of capacitor plug structures disposed in the second test region and arranged parallel to the first axis; a second row of capacitor plug structures disposed adjacent to the first row of capacitor plug structures and arranged parallel to the first row of capacitor plug structures; and a second test structure including a second drain portion and a second source portion, the second drain portion extending along the first axis and the second source portion extending along the first axis; the second drain portion being disposed on the first row of capacitor plug structures and the second source portion being disposed on the second row of capacitor plug structures.

[0009] In some embodiments, the semiconductor device further includes a third test region located in the dicing channel; a first oblique column of capacitor plug structures disposed in the third test region and arranged parallel to a first direction, the first direction being inclined relative to the first axis and the second axis; a second oblique column of capacitor plug structures disposed adjacent to the first oblique column of capacitor plug structures and arranged parallel to the first oblique column of capacitor plug structures; and a third test structure including a third drain portion and a third source portion, the third drain portion extending along the first direction, and the third source portion extending along the first direction. The third drain portion is disposed on the first oblique column of capacitor plug structures, and the third source portion is disposed on the second oblique column of capacitor plug structures.

[0010] In some embodiments, the semiconductor device includes a substrate. The capacitor plug structure of the first pillar is disposed on the substrate, and the word line structure is disposed within the substrate.

[0011] In some embodiments, the semiconductor device includes a substrate. The capacitor plug structure of the first pillar extends from an upper portion of the substrate, and the character line structure is disposed within the substrate.

[0012] In some embodiments, the semiconductor device includes a bit line structure disposed between the capacitor plug structure of the first post and the capacitor plug structure of the second post.

[0013] In some embodiments, the semiconductor device includes an etch stop layer disposed between the bit line structure and the substrate.

[0014] In some embodiments, the semiconductor device includes a plurality of bit line spacers disposed on the sidewalls of the bit line structure.

[0015] In some embodiments, the bit line structure includes a bottom conductive layer, a middle conductive layer, a top conductive layer, and a cover layer. The bottom conductive layer is disposed on the substrate, the middle conductive layer is disposed on the bottom conductive layer, the top conductive layer is disposed on the middle conductive layer, and the cover layer is disposed on the top conductive layer.

[0016] In some embodiments, the semiconductor device includes a bit line plug disposed under the bottom conductive layer of the bit line.

[0017] In some embodiments, the character line structure includes a character line dielectric layer, a character line bottom conductive layer, a character line top conductive layer, and a character line cover layer. The character line dielectric layer is recessed within the substrate, the character line bottom conductive layer is disposed on the character line dielectric layer, the character line top conductive layer is disposed on the character line bottom conductive layer, and the character line cover layer is disposed on the character line top conductive layer.

[0018] In some embodiments, the semiconductor device includes a plurality of drain regions disposed under the capacitor plug structure of the first pillar.

[0019] In some embodiments, the capacitor plug structure of the first post includes polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, titanium nitride, tantalum nitride, cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or tantalum silicide.

[0020] Another aspect of this disclosure provides a semiconductor device, comprising: a second test region located in a dicing channel; a word line structure disposed in the second test region and arranged parallel to a first axis; a bit line structure disposed in the second test region and arranged parallel to a second axis, the second axis being perpendicular to the first axis; a first row of capacitor plug structures disposed in the second test region and arranged parallel to the first axis; a second row of capacitor plug structures adjacent to and arranged parallel to the first row of capacitor plug structures; and a second test structure including a second drain portion and a second source portion, the second drain portion extending along the first axis, and the second source portion extending along the first axis. The second drain portion is disposed on the first row of capacitor plug structures, and the second source portion is disposed on the second row of capacitor plug structures.

[0021] Another aspect of this disclosure provides a semiconductor device comprising: a third test region located in a dicing channel; a word line structure disposed in the third test region and arranged parallel to a first axis; a word line structure disposed in the third test region and arranged parallel to a second axis, the second axis being perpendicular to the first axis; a first oblique column of capacitor plug structures disposed in the third test region and arranged parallel to a first direction, the first direction being oblique relative to the first axis and the second axis; a second oblique column of capacitor plug structures disposed adjacent to the first oblique column of capacitor plug structures and arranged parallel to the first oblique column of capacitor plug structures; and a third test structure including a third drain portion and a third source portion, the third drain portion extending along the first direction, and the third source portion extending along the first direction. The third drain portion is disposed on the first oblique column of capacitor plug structures, and the third source portion is disposed on the second oblique column of capacitor plug structures.

[0022] In some embodiments, the semiconductor device includes a first test region located in the dicing channel; a first-pillar capacitor plug structure disposed in the first test region and arranged parallel to the second axis; a second-pillar capacitor plug structure disposed adjacent to the first-pillar capacitor plug structure and arranged parallel to the first-pillar capacitor plug structure; and a first test structure including a first drain portion and a first source portion, the first drain portion extending along the second axis, and the first source portion extending along the second axis. The first drain portion is disposed on the first-pillar capacitor plug structure, and the first source portion is disposed on the second-pillar capacitor plug structure.

[0023] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a word line structure within the substrate and arranged parallel to a first axis; forming a capacitor plug structure with a first pillar on the substrate and arranged parallel to a second axis, the second axis being perpendicular to the first axis; and a capacitor plug structure with a second pillar adjacent to and parallel to the first pillar; forming a first drain portion extending along the second axis and located on the capacitor plug structure with the first pillar; and forming a first source portion extending along the second axis and located on the capacitor plug structure with the second pillar. The first drain portion and the first source portion together form a first test structure.

[0024] In some embodiments, the first drain portion and the first source portion comprise copper, aluminum, or a combination thereof.

[0025] In some embodiments, the capacitor plug structure of the first post includes polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, titanium nitride, tantalum nitride, cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or tantalum silicide.

[0026] Because of the design of the semiconductor device disclosed herein, leakage current of adjacent capacitor plug structures can be detected, thereby improving the reliability and yield of the semiconductor device.

[0027] The technical features and advantages of this disclosure have been summarized quite extensively above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0028] A more complete understanding of this disclosure can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0029] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0030] Figure 2 For illustrative purposes, a top view is provided to illustrate a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0031] Figure 3 For illustrative purposes, an enlarged top view is used as an example. Figure 2 The first test area in the middle;

[0032] Figure 4 and Figure 5 For illustration purposes, the diagrams show the following directions: Figure 3 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0033] Figure 6 For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0034] Figure 7 For illustration purposes, along Figure 6 Cross-sectional view of line B-B' in the middle;

[0035] Figure 8 For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0036] Figure 9 For illustration purposes, along Figure 8 Cross-sectional view of line B-B' in the middle;

[0037] Figure 10 For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0038] Figure 11 and Figure 12 For illustration purposes, the diagrams show the following directions: Figure 10 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0039] Figure 13 and Figure 14 For illustration purposes, the diagrams show the following directions: Figure 10 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0040] Figure 15 For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0041] Figure 16 and Figure 17 For illustration purposes, the diagrams show the following directions: Figure 15 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0042] Figure 18 and Figure 19 For illustration purposes, the diagrams show the following directions: Figure 15 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0043] Figure 20 and Figure 21 For illustration purposes, the diagrams show the following directions: Figure 15 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0044] Figure 22 For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0045] Figure 23 and Figure 24 For illustration purposes, the diagrams show the following directions: Figure 22 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0046] Figure 25 For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0047] Figure 26 and Figure 27 For illustration purposes, the diagrams show the following directions: Figure 25 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0048] Figure 28For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​a semiconductor device semi-finished product according to an embodiment of the present disclosure;

[0049] Figure 29 For illustration purposes, along Figure 28 Cross-sectional view of line A-A' in the middle;

[0050] Figure 30 For illustrative purposes, a top view is provided to illustrate a semiconductor device disclosed in another embodiment;

[0051] Figure 31 For illustrative purposes, an enlarged top view is used as an example. Figure 30 The first test area in the middle;

[0052] Figure 32 For illustration purposes, along Figure 31 Cross-sectional view of line A-A' in the middle;

[0053] Figure 33 For illustrative purposes, an enlarged top view is used as an example. Figure 30 The second test area in the middle;

[0054] Figure 34 For illustration purposes, along Figure 33 Cross-sectional view of line C-C' in the middle.

[0055] Figure 35 For illustrative purposes, an enlarged top view is used as an example. Figure 30 The third test area in the middle;

[0056] Figure 36 and Figure 37 For illustration purposes, the diagrams show the following directions: Figure 35 Cross-sectional views of lines A-A' and B-B' in the middle section;

[0057] Figure 38 For illustrative purposes, an enlarged top view is used to illustrate the first test area of ​​the semiconductor device in another embodiment of this disclosure;

[0058] Figure 39 and Figure 40 For illustration purposes, the diagrams show the following directions: Figure 25 A cross-sectional view of line A-A' in the middle; and

[0059] Figure 41 For illustration purposes, along Figure 28 Cross-sectional view of line A-A' in the middle.

[0060] Symbol Explanation

[0061] 10: First Test Area

[0062] 20: Second Test Area

[0063] 30: Third Test Area

[0064] 40: Grain region

[0065] 100: Preparation Method

[0066] 101: Base

[0067] 103: Isolation layer

[0068] 107-3: Drain region

[0069] 105: Active Zone

[0070] 107-1: Source Region

[0071] 109: Etching Stop Layer

[0072] 111: First insulating layer

[0073] 113: Second insulating layer

[0074] 201: Character Line Structure

[0075] 203: Character line dielectric layer

[0076] 205: Conductive layer at the bottom of the character line

[0077] 207: Top conductive layer of character lines

[0078] 209: Character Line Overlay

[0079] 301: Bitline Structure

[0080] 301SW: Sidewall

[0081] 303: Conductive layer at the bottom of the bit line

[0082] 305: Conductive layer in the middle of the bit line

[0083] 307: Top conductive layer of bit line

[0084] 309: Bitline overlay

[0085] 309TS: Top surface

[0086] 311: Bitline plug

[0087] 311BS: Bottom surface

[0088] 313: Bit line gap wall

[0089] 313BS: Bottom surface

[0090] 313TS: Top surface

[0091] 401: Capacitor plug structure

[0092] 403: Conductive layer at the bottom of the plug

[0093] 405: Conductive layer in the middle of the plug

[0094] 407: Top conductive layer of the plug

[0095] 407SW: Sidewall

[0096] 407TS: Top surface

[0097] 501: First Test Structure

[0098] 503: First drain section

[0099] 505: Connection part

[0100] 507: First source section

[0101] 509: Connection Part

[0102] 601: Second Test Structure

[0103] 603: Second drain section

[0104] 605: Connection part

[0105] 607: Second source portion

[0106] 609: Connection part

[0107] 701: Third Test Structure

[0108] 703: Third drain section

[0109] 705: Connection Part

[0110] 707: Third source section

[0111] 709: Connection Part

[0112] 801: Character Line Ditch

[0113] 803: Plug opening

[0114] 805: First conductive material

[0115] 807: Second conductive material

[0116] 809: Third conductive material

[0117] 811: First insulating material

[0118] 813: First masking layer

[0119] 815: Spacer Wall Material

[0120] C1: First Pillar

[0121] C2: Second Column

[0122] D1: Inclination direction

[0123] R1: First line

[0124] R2: Second line

[0125] S1: First Direction

[0126] SL: Cutting Track

[0127] SR1: First diagonal column

[0128] SR2: Second diagonal column Detailed Implementation

[0129] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form a part of this specification, illustrates embodiments of this disclosure; however, this disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0130] Terms such as "an embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0131] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0132] In this disclosure, a semiconductor device generally refers to a component that can function by utilizing the properties of a semiconductor, and electro-optical components, light-emitting display components, semiconductor circuits, and electronic components are all included in the category of semiconductor devices.

[0133] In the description of this disclosure, the upper arrow corresponds to the direction of the Z-axis, and the lower arrow corresponds to the opposite direction of the Z-axis.

[0134] Figure 1 For illustrative purposes, a flowchart is used to illustrate a method 100 for fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2For illustrative purposes, a top view is provided to illustrate a semiconductor device according to an embodiment of the present disclosure. Figure 3 For illustrative purposes, an enlarged top view is used as an example. Figure 2 The first test area is 10. Figure 4 and Figure 5 For illustration purposes, the diagrams show the following directions: Figure 3 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0135] Reference Figures 1 to 5 In step S11, a substrate 101 is provided, an isolation layer 103 is formed in the substrate 101, and a plurality of active regions 105 are defined by the isolation layer 103.

[0136] Reference Figure 2 In the top view, the semiconductor device 1A includes multiple die regions 40 and multiple dicing tracks SL. The dicing tracks SL are located between the die regions 40. The dicing tracks SL will be cut during wafer dicing. A first test region 10 is located within the dicing tracks SL.

[0137] Reference Figures 3 to 5 The substrate 101 comprises an organic semiconductor or a single-layer stacked semiconductor such as silicon / silicon-germanium, silicon-on-insulator, or silicon-germanium-on-insulator. When the substrate 101 is formed of silicon-on-insulator, the substrate 101 comprises a top semiconductor layer and a bottom semiconductor layer made of silicon, and a buried insulating layer that separates the top semiconductor layer and the bottom semiconductor layer. The buried insulating layer includes, for example, crystalline oxides or amorphous oxides, nitrides, or any combination thereof.

[0138] Reference Figures 3 to 5 In the cross-sectional view, the isolation layer 103 is formed within the substrate 101. The top surface of the isolation layer 103 is substantially coplanar with the top surface of the substrate 101.

[0139] The insulating layer 103 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a fluorine-doped silicate. In this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0140] Reference Figures 3 to 5In the top view, the isolation layer 103 surrounds a portion of the base 101. The portion of the base 101 surrounded by this layer is considered the active region 105. The active region 105 is bar-shaped. Each active region 105 extends along an inclined direction D1. The active regions 105 are arranged along a first axis X and a second axis Y. The active regions 105 are separated from each other along the inclined direction D1. The first axis X and the second axis Y are perpendicular to each other. The inclined direction D1 is inclined relative to the first axis X and the second axis Y.

[0141] Figure 6 For illustrative purposes, an enlarged top view is provided to illustrate the first test area 10 of a semiconductor device semi-finished product according to an embodiment of the present disclosure. Figure 7 For illustration purposes, along Figure 6 A cross-sectional view along line B-B' is provided to illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure. Figure 8 For illustrative purposes, an enlarged top view is provided to illustrate the first test area 10 of a semiconductor device semi-finished product according to an embodiment of the present disclosure. Figure 9 For illustration purposes, along Figure 8 The cross-sectional view along line B-B' illustrates a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0142] Reference Figure 1 and Figures 6 to 9 In step S13, multiple character line structures 201 are formed in the substrate 101.

[0143] Reference Figure 6 and Figure 7 Multiple character line trenches 801 are formed in the substrate 101. Forming the character line trenches 801 includes forming a mask layer (e.g., a hard mask pattern) having multiple openings; then, using the mask layer as an etching mask, etching the exposed active regions 105 and the isolation layer 103. In a top view, the character line trenches 801 are parallel to each other and extend along a first axis X. The character line trenches 801 are arranged along a second axis Y. Each active region 105 intersects with two character line trenches 801. Two character line trenches 801 divide the corresponding active region 105 into three segments. It should be noted that in the description of this disclosure, the terms "segment" and "portion" are used interchangeably.

[0144] Reference Figure 8 and Figure 9 Each character line trench 801 contains a character line dielectric layer 203, a bottom conductive layer 205, a top conductive layer 207, and a capping layer 209. For example, the character line dielectric layer 203 is conformally formed within the character line trench 801. The character line dielectric layer 203 includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, and high dielectric constant dielectric materials.

[0145] The bottom conductive layer 205 of the character line is formed by filling the character line trench 801 with a conductive material, and a subsequent recess process lowers the top surface of the bottom conductive layer 205. The conductive material is polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, the like, or a combination thereof. In some embodiments, the bottom conductive layer 205 of the character line is doped with a dopant, such as phosphorus, arsenic, antimony, or boron.

[0146] The top conductive layer 207 of the character line is formed by filling the character line trench 801 with a conductive material, and a subsequent recessing process lowers the top surface of the top conductive layer 207 of the character line. The conductive material is tungsten, aluminum, titanium, copper, titanium nitride, the like, or a combination thereof.

[0147] A character line capping layer 209 is formed on the recessed top conductive layer 207 of the character line. The character line capping layer 209 has a top surface that is substantially coplanar with the substrate 101.

[0148] The character line dielectric layer 203, the bottom conductive layer 205, the top conductive layer 207, and the character line cover layer 209 together form the character line structure 201. In the top view, the character line structures 201 are parallel to each other and extend along the first axis X. The character line structures 201 are arranged along the second axis Y. Each active region 105 intersects with two character line structures 201.

[0149] Reference Figure 8 and Figure 9 An ion implantation process will be performed on the active region 105 to form source / drain regions 107-1 and 107-3 in the upper portion of the active region 105. For each active region 105 in the top view, the source region 107-1 is formed between two character line structures 201 intersecting with the active region 105. The drain region 107-3 is formed at both ends of the active region 105. The source / drain regions 107-1 and 107-3 are doped with a dopant, which may be phosphorus, arsenic, antimony, or boron.

[0150] Figure 10 For illustrative purposes, an enlarged top view is provided to illustrate the first test area 10 of a semiconductor device semi-finished product according to an embodiment of the present disclosure. Figure 11 and Figure 12 For illustration purposes, the diagrams show the following directions: Figure 10 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure. Figure 13 and Figure 14 For illustration purposes, the diagrams show the following directions: Figure 10 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0151] Figure 15 For illustrative purposes, an enlarged top view is provided to illustrate the first test area 10 of a semiconductor device semi-finished product according to an embodiment of the present disclosure. Figure 16 and Figure 17 For illustration purposes, the diagrams show the following directions: Figure 15 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0152] Reference Figure 1 and Figures 10 to 17 In step S15, an etch stop layer 109 is formed on the substrate 101, a plurality of bit line plugs 311 are formed along the etch stop layer 109 and extend to the substrate 101, and a plurality of bit line structures 301 are formed on the etch stop layer 109.

[0153] Reference Figures 10 to 12 An etch stop layer 109 is formed on a substrate 101 (e.g., the entire surface of substrate 101). The etch stop layer 109 is formed of silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. Next, the etch stop layer 109 is patterned (e.g., etched) to form multiple openings exposing the source region 107-1. A conductive material is deposited to fill the openings. The conductive material is tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. A planarization process, such as chemical mechanical polishing, is performed until the top surface of the etch stop layer 109 is exposed to remove excess filler, providing a flat surface for subsequent processes and simultaneously forming bitline plugs 311.

[0154] Reference Figure 13 and Figure 14 A layer of a first conductive material 805, a layer of a second conductive material 807, a layer of a third conductive material 809, a layer of a first insulating material 811, and a first masking layer 813 are sequentially formed on the etch stop layer 109.

[0155] The first conductive material 805 is, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, titanium, tantalum, tungsten, copper, aluminum, tungsten silicide, cobalt silicide, or titanium silicide. The second conductive material 807 is, for example, titanium nitride or tantalum nitride. The third conductive material 809 is, for example, tungsten, tantalum, titanium, copper, or aluminum. The layer of the second conductive material 807 reduces or prevents the diffusion of conductive material in the layer of the third conductive material 809 into the layer of the first conductive material 805. The first insulating material 811 is, for example, silicon nitride, silicon nitride oxide, silicon oxynitride, boron nitride, boron silicon nitride, boron nitride phosphide, or silicon boron carbon nitride. The first masking layer 813 has a pattern of bit line structure 301.

[0156] Reference Figures 15 to 17 An etching process, such as anisotropic dry etching, is performed to transfer the pattern of the bitline structure 301 to a layer beneath the first masking layer 813. After the etching process, the layers of the first conductive material 805, the second conductive material 807, the third conductive material 809, and the first insulating material 811 are respectively transformed into a bottom conductive layer 303, a middle conductive layer 305, a top conductive layer 307, and a cover layer 309 for the bitline. The aforementioned layers together form the bitline structure 301. The first masking layer 813 is removed after the bitline structure 301 is formed. In some embodiments, such as Figure 16 As shown, part of the bit line plug 311 will be removed during the etching process that forms the bit line structure 301.

[0157] Figure 18 and Figure 19 For illustration purposes, the diagrams show the following directions: Figure 15 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure. Figure 20 and Figure 21 For illustration purposes, the diagrams show the following directions: Figure 15 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0158] Reference Figure 1 and Figures 18 to 21 In step S17, multiple bit line gap walls 313 are formed on the sidewalls 301SW of the bit line structure 301.

[0159] Reference Figure 18 and Figure 19 A layer of spacer wall material 815 is conformally formed in Figure 16 and 17 The semiconductor device semi-finished product described. The spacer material 815 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

[0160] Reference Figure 20 and Figure 21 An etching process, such as anisotropic dry etching, is performed to remove a portion of the spacer wall material 815 layer and simultaneously form bit line spacer walls 313 attached to the sidewalls 301SW of the bit line structure 301. In some embodiments, such as Figure 20 As shown, the bottom surface 313BS of some bit line gap walls 313 is substantially coplanar with the bottom surface 311BS of bit line plugs 311.

[0161] Reference Figure 20 and Figure 21An insulating material layer is deposited to cover the etch stop layer 109, the bit line structure 301, and the bit line spacer 313. The insulating material is, for example, silicon oxide, undoped silicon glass, fluorinated silicon glass, borosilicate glass, a low-dielectric-constant dielectric material, or a combination thereof. The dielectric constant of the low-dielectric-constant dielectric material is less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-dielectric-constant dielectric material is less than 2.0. A planarization process, such as chemical mechanical polishing, is performed until the top surface 309TS of the bit line cover layer 309 is exposed to remove excess material, providing a substantially flat surface for subsequent processing steps, and simultaneously transforming the insulating material layer into the first insulating layer 111.

[0162] Figure 22 For illustrative purposes, an enlarged top view is provided to illustrate the first test area 10 of a semiconductor device semi-finished product according to an embodiment of the present disclosure. Figure 23 and Figure 24 For illustration purposes, the diagrams show the following directions: Figure 22 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0163] Reference Figure 1 and Figures 22 to 24 In step S19, a plurality of plug openings 803 are formed from a capacitor plug structure 401 extending to the substrate 101 and adjacent to the bit line structure 301.

[0164] Reference Figures 22 to 24 A photolithography process and a subsequent etching process are performed to form a plug opening 803 along the first insulating layer 111 and extending to the upper portion of the substrate 101. A portion of the drain region 107-3 will be exposed through the plug opening 803. In a top view, the plug opening 803 is located at the end of the active region 105.

[0165] Figure 25 For illustrative purposes, an enlarged top view is provided to illustrate the first test area 10 of a semiconductor device semi-finished product according to an embodiment of the present disclosure. Figure 26 and Figure 27 For illustration purposes, the diagrams show the following directions: Figure 25 The cross-sectional views along lines A-A' and B-B' illustrate a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0166] Reference Figure 1 and Figures 25 to 27 In step S21, multiple capacitor plug structures 401 are formed in the plug opening 803.

[0167] Reference Figures 25 to 27The bottom conductive layer 403 of the plug is formed in the plug opening 803. The bottom conductive layer 403 of the plug is formed of, for example, polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium. In some embodiments, the bottom conductive layer 403 of the plug is doped with a dopant, such as phosphorus, arsenic, antimony, or boron.

[0168] Reference Figures 25 to 27 A middle conductive layer 405 is formed on the bottom conductive layer 403 of the plug and is located in the plug opening 803. The middle conductive layer 405 is formed of, for example, cobalt silicide, titanium silicide, nickel silicide, nickel-platinum silicide, or tantalum silicide. The vertical height of the top surface of the middle conductive layer 405 is lower than the vertical height of the top surface 309TS of the bit line cover layer 309. The middle conductive layer 405 reduces the contact resistance between the bottom conductive layer 403 and the top conductive layer 407 of the plug.

[0169] Reference Figures 25 to 27 The top conductive layer 407 is correspondingly formed on the middle conductive layer 405 of the plug and completely fills the plug opening 803. The top surface 407TS of the top conductive layer 407 is substantially coplanar with the top surface 309TS of the bit line cover layer 309. The top conductive layer 407 is formed of, for example, titanium nitride or tantalum nitride.

[0170] The bottom conductive layer 403, the middle conductive layer 405, and the top conductive layer 407 of the plug together form the capacitor plug structure 401.

[0171] In the top view, the capacitor plug structures 401 are arranged in a grid dot pattern. The capacitor plug structures 401 located in the first test area 10 can be categorized into two groups, for example, the capacitor plug structures 401 of the first pillar C1 and the capacitor plug structures 401 of the second pillar C2. Each capacitor plug structure 401 of the first pillar C1 includes multiple capacitor plug structures 401 arranged along the second axis Y, and the capacitor plug structures 401 of each first pillar C1 are parallel to each other. Each capacitor plug structure 401 of the second pillar C2 includes multiple capacitor plug structures 401 arranged along the second axis Y, and the capacitor plug structures 401 of each second pillar C2 are parallel to each other. The capacitor plug structures 401 of the first pillar C1 and the capacitor plug structures 401 of the second pillar C2 are alternately arranged along the first axis X.

[0172] Figure 28 For illustrative purposes, an enlarged top view is provided to illustrate the first test area 10 of a semiconductor device semi-finished product according to an embodiment of the present disclosure. Figure 29 For illustration purposes, along Figure 28 The cross-sectional view along line A-A' illustrates a portion of the process for manufacturing a semiconductor device 1A according to an embodiment of this disclosure.

[0173] Reference Figure 1 , Figure 27 and Figure 28 In step S23, a first test structure 501 is formed on the capacitor plug structure 401.

[0174] Reference Figure 27 and Figure 28 A second insulating layer 113 is formed in Figures 25 to 27 On the semiconductor device semi-finished product described. The second insulating layer 113 and the first insulating layer 111 are formed of the same material, but are not limited thereto. The first test structure 501 is formed within the second insulating layer 113 using an embedded process.

[0175] Reference Figure 27 and Figure 28 The first test structure 501 includes a plurality of first drain portions 503, a connection portion 505, a plurality of first source portions 507, and a connection portion 509. The first drain portions 503, the connection portion 505, the first source portions 507, and the connection portion 509 are formed of copper, aluminum, the like, or a combination thereof.

[0176] In the top view, the first drain portion 503 extends along the second axis Y and is formed on the capacitor plug structure 401 of the first post C1. Each first drain portion 503 is formed on a corresponding post in the capacitor plug structure 401 of the first post C1. The first drain portions 503 are parallel to each other. The connecting portion 505 extends along the first axis X and connects to the upper end of the first drain portion 503. The first drain portion 503 and the connecting portion 505 together form a drain electrode of the first test structure 501. The drain electrode is comb-shaped.

[0177] In the top view, the first source portion 507 extends along the second axis Y and is formed on the capacitor plug structure 401 of the second pillar C2. Each first source portion 507 is formed on a corresponding pillar in the capacitor plug structure 401 of the second pillar C2. The first source portions 507 are parallel to each other. The first source portions 507 and the first drain portions 503 are arranged alternately along the first axis X. The connecting portion 509 extends along the first axis X and connects to the lower end of the first source portion 507. The first source portion 507 and the connecting portion 509 together form a source electrode of the first test structure 501. The source electrode is comb-shaped.

[0178] As the size of semiconductor devices continues to shrink, leakage current, which severely impacts the reliability and yield of semiconductor devices, will appear in adjacent capacitor plug structures 401. For example, a first type of leakage current may flow from one capacitor plug structure 401 along the first axis X and through the bit line structure 301 to an adjacent capacitor plug structure 401. As another example, a second type of leakage current may flow from one capacitor plug structure 401 along the first axis X and around the bottom surface of the isolation layer 103 to an adjacent capacitor plug structure 401. The first type of leakage current will be greater than the second type of leakage current.

[0179] The first test structure 501 is used to measure the leakage current of both the first and second types. In the illustrated embodiment, the first test structure 501 is adapted to detect leakage current flowing along the first axis X. When operating the first test structure 501, an external voltage is applied to the drain electrode, while the source electrode is grounded. If no leakage current is generated in the adjacent capacitor plug structure 401, the first test structure 501 will not detect any current signal. If leakage current exists in the adjacent capacitor plug structure 401, the leakage current will be induced by the external voltage, and a current path will be established between the drain and source electrodes; therefore, the first test structure 501 will be able to detect a current signal. The type of leakage current can be determined by the detected current value and the number of capacitor plug structures 401 connected to the first test structure 501.

[0180] With the assistance of the first test structure 501, defects such as leakage current can be monitored before capacitor formation. Since these defects can be monitored in advance, the monitoring results can be used to determine whether rework is required or the device should be scrapped. Therefore, the reliability and yield of the semiconductor device 1A will be improved.

[0181] Figure 30 For illustrative purposes, a top view is provided to illustrate a semiconductor device 1B disclosed in another embodiment.

[0182] Reference Figure 30 In the top view, the semiconductor device 1B includes multiple die regions 40 and multiple dicing tracks SL. The dicing tracks SL are located between the die regions 40. A first test region 10, a second test region 20, and a third test region 30 are each located within the dicing tracks SL. The first test region 10, the second test region 20, and the third test region 30 are adjacent to each other, but not limited thereto.

[0183] Figure 31 For illustrative purposes, an enlarged top view is used as an example. Figure 30 The first test area is 10. Figure 32 For illustration purposes, along Figure 31 A cross-sectional view along line A-A' illustrates a semiconductor device 1B in another embodiment of this disclosure.

[0184] Reference Figure 31 and Figure 32 The first test structure 501 is formed within the first test area 10. The structure of the first test structure 501 is similar to... Figure 28 and Figure 29 The first test structure 501 is suitable for detecting leakage current along the first axis X.

[0185] Figure 33 For illustrative purposes, an enlarged top view is used as an example. Figure 30 The second test area is 20. Figure 34 For illustration purposes, along Figure 33 A cross-sectional view along line C-C' illustrates a semiconductor device 1B in another embodiment of this disclosure.

[0186] Reference Figure 33 and Figure 34 The capacitor plug structures 401 located in the second test area 20 can be categorized into two groups, for example, the capacitor plug structures 401 in the first row R1 and the capacitor plug structures 401 in the second row R2. Each capacitor plug structure 401 in the first row R1 includes multiple capacitor plug structures 401 arranged along the first axis X, and the capacitor plug structures 401 in the first row R1 are parallel to each other. Each capacitor plug structure 401 in the second row R2 includes multiple capacitor plug structures 401 arranged along the first axis X, and the capacitor plug structures 401 in the first row R1 are parallel to each other. The capacitor plug structures 401 in the first row R1 and the capacitor plug structures 401 in the second row R2 are alternately arranged along the second axis Y.

[0187] Reference Figure 33 and Figure 34 A second test structure 601 is formed in the second test area 20 and includes multiple second drain portions 603, a connecting portion 605, multiple second source portions 607, and a connecting portion 609. In the top view, the second drain portions 603 extend along the first axis X and are formed on the capacitor plug structure 401 of the first row R1. Each second drain portion 603 is formed on a corresponding post in the capacitor plug structure 401 of the first row R1. The second drain portions 603 are parallel to each other. The connecting portion 605 extends along the second axis Y and connects to the left end of the second drain portion 603. The second drain portions 603 and the connecting portion 605 together form a drain electrode of the second test structure 601. The drain electrode is comb-shaped.

[0188] The second source portion 607 extends along the first axis X and is formed on the capacitor plug structure 401 of the second row R2. Each second source portion 607 is formed on a corresponding post in the capacitor plug structure 401 of the second row R2. The second source portions 607 are parallel to each other. The second source portions 607 and the second drain portions 603 are arranged alternately along the second axis Y. The connecting portion 609 extends along the second axis Y and connects to the right end of the second source portion 607. The second source portion 607 and the connecting portion 609 together form a source electrode of the second test structure 601. The source electrode is comb-shaped.

[0189] In addition to leakage current between adjacent capacitor plug structures 401 along the first axis X, leakage current also occurs between adjacent capacitor plug structures 401 along the second axis Y. For example, a third type of leakage current may flow from one capacitor plug structure 401, along the second axis Y, through the first insulating layer 111, to the adjacent capacitor plug structure 401. As another example, a fourth type of leakage current may flow from one capacitor plug structure 401, along the second axis Y, around the bottom surface of the character line structure 201 and the isolation layer 103, to the adjacent capacitor plug structure 401. The third type of leakage current will be greater than the fourth type of leakage current.

[0190] The second test structure 601 is used to measure the leakage current of types three and four. In the illustrated embodiment, the second test structure 601 is adapted to detect leakage current flowing along the second axis Y. When operating the second test structure 601, an external voltage is applied to the drain electrode, while the source electrode is grounded. If no leakage current is generated in the adjacent capacitor plug structure 401, the second test structure 601 will not detect any current signal. If leakage current exists in the adjacent capacitor plug structure 401, the leakage current will be induced by the external voltage, and a current path will be established between the drain electrode and the source electrode; therefore, the second test structure 601 will be able to detect a current signal. The type of leakage current can be determined by the detected current value and the number of capacitor plug structures 401 connected to the second test structure 601, whether or not a voltage is applied to the character line structure 201.

[0191] Figure 35 For illustrative purposes, an enlarged top view is used as an example. Figure 30 The third test area is 30. Figure 36 and Figure 37 For illustration purposes, the diagrams show the following directions: Figure 35 The cross-sectional view of lines A-A' and C-C' illustrates a semiconductor device 1B in another embodiment of this disclosure.

[0192] Reference Figures 35 to 37The capacitor plug structures 401 located in the third test area 30 can be classified into two groups, for example, the capacitor plug structures 401 of the first oblique column SR1 and the capacitor plug structures 401 of the second oblique column SR2. Each capacitor plug structure 401 in the first oblique column SR1 includes multiple capacitor plug structures 401 arranged along a first direction S1. The first direction S1 is inclined relative to the first axis X and the second axis Y, and the first direction S1 intersects with the inclination direction D1. The capacitor plug structures 401 in each first oblique column SR1 are parallel to each other. Each capacitor plug structure 401 in the second oblique column SR2 includes multiple capacitor plug structures 401 arranged along the first direction S1. The capacitor plug structures 401 in each second oblique column SR2 are parallel to each other. The capacitor plug structures 401 of the first oblique column SR1 and the capacitor plug structures 401 of the second oblique column SR2 are alternately arranged along a direction perpendicular to the first direction S1.

[0193] Reference Figures 35 to 37 A third test structure 701 is formed in a third test region 30 and includes a plurality of third drain portions 703, a connection portion 705, a plurality of third source portions 707, and a connection portion 709. In a top view, the third drain portions 703 extend along a first direction S1 and are formed on the capacitor plug structure 401 of the first oblique column SR1. Each third drain portion 703 is formed in a corresponding oblique column of the capacitor plug structure 401 of the first oblique column SR1. The third drain portions 703 are parallel to each other. The connection portion 705 includes a vertical portion extending along a second axis Y and a horizontal portion extending along a first axis X. In a top view, the connection portion 705 is L-shaped. In the illustrated embodiment, the connection portion 705 is connected to the left end of the third drain portion 703. The third drain portions 703 and the connection portion 705 together form a drain electrode of the third test structure 701.

[0194] The third source portion 707 extends along the first direction S1 and is formed on the capacitor plug structure 401 of the second oblique column SR2. Each third drain portion 703 is formed on a corresponding post in the capacitor plug structure 401 of the second oblique column SR2. The third source portions 707 are parallel to each other. The third source portions 707 and the third drain portions 703 are arranged alternately along a direction perpendicular to the first direction S1. The connection portion 709 includes a vertical portion extending along the second axis Y and a horizontal portion extending along the first axis X. In the top view, the connection portion 709 is L-shaped. In the illustrated embodiment, the right ends of the connection portion 709 and the third source portion 707 are connected. The third source portion 707 and the connection portion 709 together form a source electrode of the third test structure 701.

[0195] The third test structure 701 will be used to measure the leakage current of types 1, 2, 3, and 4. The first test structure 501, the second test structure 601, and the third test structure 701 will make the semiconductor device 1B suitable for detecting all types of leakage current.

[0196] In some embodiments, the semiconductor device may include only the second test structure 601. In some embodiments, the semiconductor device may include only the third test structure 701. In some embodiments, the semiconductor device may include only the first test structure 501 and the second test structure 601. In some embodiments, the semiconductor device may include only the first test structure 501 and the third test structure 701. In some embodiments, the semiconductor device may include only the second test structure 601 and the third test structure 701.

[0197] Figure 38 For illustrative purposes, an enlarged top view is shown illustrating the first test area 10 of the semiconductor device 1C in another embodiment of the present disclosure.

[0198] Reference Figure 38 The first test structure 501 is similar to Figure 28 The description is as follows. In some embodiments, in a top view, each first drain portion 503 and each first source portion 507 are formed on two pillars in the capacitor plug structure 401. The first test structure 501 is adapted to detect leakage current along the first axis X.

[0199] 39 and Figure 40 For illustration purposes, along Figure 25 A cross-sectional view along line A-A' is provided to illustrate a portion of the process for manufacturing the semiconductor device 1D disclosed in another embodiment.

[0200] Reference Figure 39 , in a similar way Figures 2 to 27 A semi-finished semiconductor device is prepared using a procedure. A recessing process is performed to recess the top surface 309TS of the bit line capping layer 309 and the top surface 313TS of the bit line spacer 313. The vertical height of the top surface 407TS of the plug top conductive layer 407 is higher than the vertical height of the top surface 309TS of the bit line capping layer 309 and the top surface 313TS of the bit line spacer 313.

[0201] Reference Figure 40 The second insulating layer 113 and the first test structure 501 are similar to Figure 28 and Figure 29The process is as follows: The first drain portion 503 and the first source portion 507 will cover the top surface 407TS and sidewall 407SW of the top conductive layer 407 of the plug. That is, the contact surface between the capacitor plug structure 401 and the first test structure 501 will be increased. Therefore, the sensitivity of the first test structure 501 will be increased.

[0202] Figure 41 For illustration purposes, along Figure 28 A cross-sectional view along line A-A' is provided to illustrate the manufacture of the semiconductor device 1E disclosed in another embodiment.

[0203] Reference Figure 41 The capacitor plug structure 401 is formed on the substrate 101, rather than as... Figure 26 As shown, it extends into the substrate 101.

[0204] Because of the design of the semiconductor device disclosed herein, the leakage current of the adjacent capacitor plug structure 401 can be detected, thereby improving the reliability and yield of the semiconductor device 1A.

[0205] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0206] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this application that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this application. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device comprising: a first test region in a scribe lane; a word line structure disposed in the first test region and arranged parallel to a first axis; a first column of capacitor plug structures disposed in the first test region and arranged parallel to a second axis, the second axis being perpendicular to the first axis; a second column of capacitor plug structures disposed adjacent to the first column of capacitor plug structures and arranged parallel to the first column of capacitor plug structures; and a first test structure comprising a first drain portion extending along the second axis and a first source portion extending along the second axis; wherein the first drain portion is disposed on the first column of capacitor plug structures and the first source portion is disposed on the second column of capacitor plug structures; a second test region in the scribe lane; a first row of capacitor plug structures disposed in the second test region and arranged parallel to the first axis; a second row of capacitor plug structures disposed adjacent to the first row of capacitor plug structures and arranged parallel to the first row of capacitor plug structures; and a second test structure comprising a second drain portion extending along the first axis and a second source portion extending along the first axis; wherein the second drain portion is disposed on the first row of capacitor plug structures and the second source portion is disposed on the second row of capacitor plug structures; a third test region in the scribe lane; a first diagonal column of capacitor plug structures disposed in the third test region and arranged parallel to a first direction, the first direction being oblique with respect to the first axis and the second axis; a second diagonal column of capacitor plug structures disposed adjacent to the first diagonal column of capacitor plug structures and arranged parallel to the first diagonal column of capacitor plug structures; and a third test structure comprising a third drain portion extending along the first direction and a third source portion extending along the first direction; wherein the third drain portion is disposed on the first diagonal column of capacitor plug structures and the third source portion is disposed on the second diagonal column of capacitor plug structures.

2. The semiconductor device of claim 1, further comprising a substrate; wherein the first column of capacitor plug structures is disposed on the substrate and the word line structure is disposed within the substrate.

3. The semiconductor device of claim 1, further comprising a substrate; wherein the first column of capacitor plug structures is disposed extending on an upper portion of the substrate and the word line structure is disposed within the substrate.

4. The semiconductor device of claim 3, further comprising a bit line structure disposed between the first column of capacitor plug structures and the second column of capacitor plug structures.

5. The semiconductor device of claim 4, further comprising an etch stop layer disposed between the bit line structure and the substrate.

6. The semiconductor device of claim 4, further comprising a plurality of bit line spacers disposed on sidewalls of the bit line structure. ​ 7. The semiconductor device of claim 6, wherein the bit line structure comprises a bit line bottom conductive layer, a bit line middle conductive layer, a bit line top conductive layer, and a bit line cap layer, the bit line bottom conductive layer disposed on the substrate, the bit line middle conductive layer disposed on the bit line bottom conductive layer, the bit line top conductive layer disposed on the bit line middle conductive layer, and the bit line cap layer disposed on the bit line top conductive layer.

8. The semiconductor device of claim 7, further comprising a bit line plug disposed under the bit line bottom conductive layer.

9. The semiconductor device of claim 8, wherein the word line structure comprises a word line dielectric layer, a word line bottom conductive layer, a word line top conductive layer, and a word line cap layer, the word line dielectric layer recessedly disposed in the substrate, the word line bottom conductive layer disposed on the word line dielectric layer, the word line top conductive layer disposed on the word line bottom conductive layer, and the word line cap layer disposed on the word line top conductive layer.

10. The semiconductor device of claim 9, further comprising a plurality of drain regions disposed under the first column of capacitor plug structures.

11. The semiconductor device of claim 10, wherein the first column of capacitor plug structures comprises polysilicon, polygermanium, polysilicon germanium, titanium nitride, tantalum nitride, cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or tantalum silicide.

12. A semiconductor device, comprising: a first test region located in a scribe lane; a word line structure disposed in the first test region and arranged parallel to a first axis; a bit line structure disposed in the first test region and arranged parallel to a second axis, the second axis perpendicular to the first axis; a first diagonal column of capacitor plug structures disposed in the first test region and arranged parallel to a first direction, the first direction oblique with respect to the first axis and the second axis; a second diagonal column of capacitor plug structures disposed adjacent to the first diagonal column of capacitor plug structures and arranged parallel to the first diagonal column of capacitor plug structures; and a first test structure comprising a first drain portion and a first source portion, the first drain portion extending along the first direction, the first source portion extending along the first direction; wherein the first drain portion is disposed on the first diagonal column of capacitor plug structures and the first source portion is disposed on the second diagonal column of capacitor plug structures.

13. The semiconductor device of claim 12, further comprising: a second test region located in the scribe lane; a first column of capacitor plug structures disposed in the second test region and arranged parallel to the second axis; a second column of capacitor plug structures disposed adjacent to the first column of capacitor plug structures and arranged parallel to the first column of capacitor plug structures; and a second test structure comprising a second drain portion and a second source portion, the second drain portion extending along the second axis, the second source portion extending along the second axis. ​ ​ wherein the second drain portion is disposed on the first pillar capacitor plug structure and the second source portion is disposed on the second pillar capacitor plug structure.

14. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a word line structure within the substrate and arranged parallel to a first axis; forming a first pillar capacitor plug structure on the substrate and arranged parallel to a second axis, the second axis being perpendicular to the first axis; and forming a second pillar capacitor plug structure adjacent to the first pillar capacitor plug structure and arranged parallel to the first pillar capacitor plug structure; and forming a first drain portion extending along the second axis and located on the first pillar capacitor plug structure; and forming a first source portion extending along the second axis and located on the second pillar capacitor plug structure; wherein the first drain portion and the first source portion collectively form a first test structure.

15. The method of fabricating a semiconductor device of claim 14, wherein the first drain portion and the first source portion comprise copper, aluminum, or a combination thereof.

16. The method of fabricating a semiconductor device of claim 14, wherein the first pillar capacitor plug structure comprises polysilicon, polygermanium, polysilicon germanium, titanium nitride, tantalum nitride, cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or tantalum silicide.

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